1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4declare i32 @llvm.r600.read.tidig.x() #1
5
6; SI-LABEL: {{^}}v_cnd_nan_nosgpr:
7; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
8; SI-DAG: v{{[0-9]}}
9; All nan values are converted to 0xffffffff
10; SI: s_endpgm
11define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
12  %idx = call i32 @llvm.r600.read.tidig.x() #1
13  %f.gep = getelementptr float addrspace(1)* %fptr, i32 %idx
14  %f = load float addrspace(1)* %fptr
15  %setcc = icmp ne i32 %c, 0
16  %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
17  store float %select, float addrspace(1)* %out
18  ret void
19}
20
21
22; This requires slightly trickier SGPR operand legalization since the
23; single constant bus SGPR usage is the last operand, and it should
24; never be moved.
25
26; SI-LABEL: {{^}}v_cnd_nan:
27; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
28; SI-DAG: v{{[0-9]}}
29; All nan values are converted to 0xffffffff
30; SI: s_endpgm
31define void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
32  %setcc = icmp ne i32 %c, 0
33  %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
34  store float %select, float addrspace(1)* %out
35  ret void
36}
37
38attributes #0 = { nounwind }
39attributes #1 = { nounwind readnone }
40