1; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
2
3define <4 x i3> @test1(<4 x i3>* %in) nounwind {
4  %ret = load <4 x i3>* %in, align 1
5  ret <4 x i3> %ret
6}
7; CHECK-LABEL: test1
8; CHECK: movzwl
9; CHECK: shrl $3
10; CHECK: andl $7
11; CHECK: andl $7
12; CHECK: vmovd
13; CHECK: pinsrd $1
14; CHECK: shrl $6
15; CHECK: andl $7
16; CHECK: pinsrd $2
17; CHECK: shrl $9
18; CHECK: andl $7
19; CHECK: pinsrd $3
20; CHECK: ret
21
22define <4 x i1> @test2(<4 x i1>* %in) nounwind {
23  %ret = load <4 x i1>* %in, align 1
24  ret <4 x i1> %ret
25}
26
27; CHECK-LABEL: test2
28; CHECK: movzbl
29; CHECK: shrl
30; CHECK: andl $1
31; CHECK: andl $1
32; CHECK: vmovd
33; CHECK: pinsrd $1
34; CHECK: shrl $2
35; CHECK: andl $1
36; CHECK: pinsrd $2
37; CHECK: shrl $3
38; CHECK: andl $1
39; CHECK: pinsrd $3
40; CHECK: ret
41
42define <4 x i64> @test3(<4 x i1>* %in) nounwind {
43  %wide.load35 = load <4 x i1>* %in, align 1
44  %sext = sext <4 x i1> %wide.load35 to <4 x i64>
45  ret <4 x i64> %sext
46}
47
48; CHECK-LABEL: test3
49; CHECK: movzbl
50; CHECK: movq
51; CHECK: shlq
52; CHECK: sarq
53; CHECK: vmovq
54; CHECK: movq
55; CHECK: shlq
56; CHECK: sarq
57; CHECK: vmovq
58; CHECK: vpunpcklqdq
59; CHECK: movq
60; CHECK: shlq
61; CHECK: sarq
62; CHECK: vmovq
63; CHECK: shlq
64; CHECK: sarq
65; CHECK: vmovq
66; CHECK: vpunpcklqdq
67; CHECK: vinsertf128
68; CHECK: ret
69
70define <16 x i4> @test4(<16 x i4>* %in) nounwind {
71  %ret = load <16 x i4>* %in, align 1
72  ret <16 x i4> %ret
73}
74
75; CHECK-LABEL: test4
76; CHECK: movl
77; CHECK-NEXT: shrl
78; CHECK-NEXT: andl
79; CHECK-NEXT: movl
80; CHECK-NEXT: andl
81; CHECK-NEXT: vmovd
82; CHECK-NEXT: vpinsrb
83; CHECK-NEXT: movl
84; CHECK-NEXT: shrl
85; CHECK-NEXT: andl
86; CHECK-NEXT: vpinsrb
87; CHECK-NEXT: movl
88; CHECK-NEXT: shrl
89; CHECK-NEXT: andl
90; CHECK-NEXT: vpinsrb
91; CHECK-NEXT: movl
92; CHECK-NEXT: shrl
93; CHECK-NEXT: andl
94; CHECK-NEXT: vpinsrb
95; CHECK-NEXT: movl
96; CHECK-NEXT: shrl
97; CHECK-NEXT: andl
98; CHECK-NEXT: vpinsrb
99; CHECK-NEXT: movl
100; CHECK-NEXT: shrl
101; CHECK-NEXT: andl
102; CHECK-NEXT: vpinsrb
103; CHECK-NEXT: movl
104; CHECK-NEXT: shrl
105; CHECK-NEXT: vpinsrb
106; CHECK-NEXT: movq
107; CHECK-NEXT: shrq
108; CHECK-NEXT: andl
109; CHECK-NEXT: vpinsrb
110; CHECK-NEXT: movq
111; CHECK-NEXT: shrq
112; CHECK-NEXT: andl
113; CHECK-NEXT: vpinsrb
114; CHECK-NEXT: movq
115; CHECK-NEXT: shrq
116; CHECK-NEXT: andl
117; CHECK-NEXT: vpinsrb
118; CHECK-NEXT: movq
119; CHECK-NEXT: shrq
120; CHECK-NEXT: andl
121; CHECK-NEXT: vpinsrb
122; CHECK-NEXT: movq
123; CHECK-NEXT: shrq
124; CHECK-NEXT: andl
125; CHECK-NEXT: vpinsrb
126; CHECK-NEXT: movq
127; CHECK-NEXT: shrq
128; CHECK-NEXT: andl
129; CHECK-NEXT: vpinsrb
130; CHECK-NEXT: movq
131; CHECK-NEXT: shrq
132; CHECK-NEXT: andl
133; CHECK-NEXT: vpinsrb
134; CHECK-NEXT: shrq
135; CHECK-NEXT: vpinsrb
136; CHECK-NEXT: retq
137