1 /* A device driver for Intel Pro/1000 Gigabit Ethernet Controllers. */ 2 3 #include <minix/drivers.h> 4 #include <minix/netdriver.h> 5 #include <machine/pci.h> 6 #include <sys/mman.h> 7 #include "assert.h" 8 #include "e1000.h" 9 #include "e1000_hw.h" 10 #include "e1000_reg.h" 11 #include "e1000_pci.h" 12 13 static int e1000_init(unsigned int instance, ether_addr_t *addr); 14 static void e1000_stop(void); 15 static int e1000_send(struct netdriver_data *data, size_t size); 16 static ssize_t e1000_recv(struct netdriver_data *data, size_t max); 17 static void e1000_stat(eth_stat_t *stat); 18 static void e1000_intr(unsigned int mask); 19 static int e1000_probe(e1000_t *e, int skip); 20 static void e1000_init_hw(e1000_t *e, ether_addr_t *addr); 21 static uint32_t e1000_reg_read(e1000_t *e, uint32_t reg); 22 static void e1000_reg_write(e1000_t *e, uint32_t reg, uint32_t value); 23 static void e1000_reg_set(e1000_t *e, uint32_t reg, uint32_t value); 24 static void e1000_reg_unset(e1000_t *e, uint32_t reg, uint32_t value); 25 static u16_t eeprom_eerd(e1000_t *e, int reg); 26 static u16_t eeprom_ich(e1000_t *e, int reg); 27 static int eeprom_ich_init(e1000_t *e); 28 static int eeprom_ich_cycle(e1000_t *e, u32_t timeout); 29 30 static int e1000_instance; 31 static e1000_t e1000_state; 32 33 static const struct netdriver e1000_table = { 34 .ndr_init = e1000_init, 35 .ndr_stop = e1000_stop, 36 .ndr_recv = e1000_recv, 37 .ndr_send = e1000_send, 38 .ndr_stat = e1000_stat, 39 .ndr_intr = e1000_intr, 40 }; 41 42 /* 43 * The e1000 driver. 44 */ 45 int 46 main(int argc, char * argv[]) 47 { 48 49 env_setargs(argc, argv); 50 51 /* Let the netdriver library take control. */ 52 netdriver_task(&e1000_table); 53 54 return 0; 55 } 56 57 /* 58 * Initialize the e1000 driver and device. 59 */ 60 static int 61 e1000_init(unsigned int instance, ether_addr_t * addr) 62 { 63 e1000_t *e; 64 int r; 65 66 e1000_instance = instance; 67 68 /* Clear state. */ 69 memset(&e1000_state, 0, sizeof(e1000_state)); 70 71 e = &e1000_state; 72 strlcpy(e->name, "e1000#0", sizeof(e->name)); 73 e->name[6] += instance; 74 75 /* Perform calibration. */ 76 if ((r = tsc_calibrate()) != OK) 77 panic("tsc_calibrate failed: %d", r); 78 79 /* See if we can find a matching device. */ 80 if (!e1000_probe(e, instance)) 81 return ENXIO; 82 83 /* Initialize the hardware, and return its ethernet address. */ 84 e1000_init_hw(e, addr); 85 86 return OK; 87 } 88 89 /* 90 * Map flash memory. This step is optional. 91 */ 92 static void 93 e1000_map_flash(e1000_t * e, int devind, int did) 94 { 95 u32_t flash_addr, gfpreg, sector_base_addr; 96 size_t flash_size; 97 98 /* The flash memory is pointed to by BAR2. It may not be present. */ 99 if ((flash_addr = pci_attr_r32(devind, PCI_BAR_2)) == 0) 100 return; 101 102 /* The default flash size. */ 103 flash_size = 0x10000; 104 105 switch (did) { 106 case E1000_DEV_ID_82540EM: 107 case E1000_DEV_ID_82545EM: 108 case E1000_DEV_ID_82540EP: 109 case E1000_DEV_ID_82540EP_LP: 110 return; /* don't even try */ 111 112 /* 82566/82567/82562V series support mapping 4kB of flash memory. */ 113 case E1000_DEV_ID_ICH10_D_BM_LM: 114 case E1000_DEV_ID_ICH10_R_BM_LF: 115 flash_size = 0x1000; 116 break; 117 } 118 119 e->flash = vm_map_phys(SELF, (void *)flash_addr, flash_size); 120 if (e->flash == MAP_FAILED) 121 panic("e1000: couldn't map in flash"); 122 123 /* sector_base_addr is a "sector"-aligned address (4096 bytes). */ 124 gfpreg = E1000_READ_FLASH_REG(e, ICH_FLASH_GFPREG); 125 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 126 127 /* flash_base_addr is byte-aligned. */ 128 e->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 129 } 130 131 /* 132 * Find a matching device. Return TRUE on success. 133 */ 134 static int 135 e1000_probe(e1000_t * e, int skip) 136 { 137 int r, devind, ioflag; 138 u16_t vid, did, cr; 139 u32_t status; 140 u32_t base, size; 141 char *dname; 142 143 E1000_DEBUG(3, ("%s: probe()\n", e->name)); 144 145 /* Initialize communication to the PCI driver. */ 146 pci_init(); 147 148 /* Attempt to iterate the PCI bus. Start at the beginning. */ 149 if ((r = pci_first_dev(&devind, &vid, &did)) == 0) 150 return FALSE; 151 152 /* Loop devices on the PCI bus. */ 153 while (skip--) { 154 E1000_DEBUG(3, ("%s: probe() devind %d vid 0x%x did 0x%x\n", 155 e->name, devind, vid, did)); 156 157 if (!(r = pci_next_dev(&devind, &vid, &did))) 158 return FALSE; 159 } 160 161 /* We found a matching card. Set card-specific properties. */ 162 e->eeprom_read = eeprom_eerd; 163 164 switch (did) { 165 case E1000_DEV_ID_ICH10_D_BM_LM: 166 case E1000_DEV_ID_ICH10_R_BM_LF: 167 e->eeprom_read = eeprom_ich; 168 break; 169 170 case E1000_DEV_ID_82540EM: 171 case E1000_DEV_ID_82545EM: 172 case E1000_DEV_ID_82540EP_LP: 173 e->eeprom_done_bit = (1 << 4); 174 e->eeprom_addr_off = 8; 175 break; 176 177 default: 178 e->eeprom_done_bit = (1 << 1); 179 e->eeprom_addr_off = 2; 180 break; 181 } 182 183 /* Inform the user about the new card. */ 184 if (!(dname = pci_dev_name(vid, did))) 185 dname = "Intel Pro/1000 Gigabit Ethernet Card"; 186 E1000_DEBUG(1, ("%s: %s (%04x/%04x) at %s\n", 187 e->name, dname, vid, did, pci_slot_name(devind))); 188 189 /* Reserve PCI resources found. */ 190 pci_reserve(devind); 191 192 /* Read PCI configuration. */ 193 e->irq = pci_attr_r8(devind, PCI_ILR); 194 195 if ((r = pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) != OK) 196 panic("failed to get PCI BAR: %d", r); 197 if (ioflag) 198 panic("PCI BAR is not for memory"); 199 200 if ((e->regs = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED) 201 panic("failed to map hardware registers from PCI"); 202 203 /* Enable DMA bus mastering if necessary. */ 204 cr = pci_attr_r16(devind, PCI_CR); 205 if (!(cr & PCI_CR_MAST_EN)) 206 pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN); 207 208 /* Optionally map flash memory. */ 209 e1000_map_flash(e, devind, did); 210 211 /* Output debug information. */ 212 status = e1000_reg_read(e, E1000_REG_STATUS); 213 E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n", e->name, e->regs, e->irq)); 214 E1000_DEBUG(3, ("%s: link %s, %s duplex\n", e->name, 215 status & 3 ? "up" : "down", status & 1 ? "full" : "half")); 216 217 return TRUE; 218 } 219 220 /* 221 * Reset the card. 222 */ 223 static void 224 e1000_reset_hw(e1000_t * e) 225 { 226 227 /* Assert a Device Reset signal. */ 228 e1000_reg_set(e, E1000_REG_CTRL, E1000_REG_CTRL_RST); 229 230 /* Wait one microsecond. */ 231 tickdelay(1); 232 } 233 234 /* 235 * Initialize and return the card's ethernet address. 236 */ 237 static void 238 e1000_init_addr(e1000_t * e, ether_addr_t * addr) 239 { 240 static char eakey[] = E1000_ENVVAR "#_EA"; 241 static char eafmt[] = "x:x:x:x:x:x"; 242 u16_t word; 243 int i; 244 long v; 245 246 /* Do we have a user defined ethernet address? */ 247 eakey[sizeof(E1000_ENVVAR)-1] = '0' + e1000_instance; 248 249 for (i = 0; i < 6; i++) { 250 if (env_parse(eakey, eafmt, i, &v, 0x00L, 0xFFL) != EP_SET) 251 break; 252 else 253 addr->ea_addr[i] = v; 254 } 255 256 /* If that fails, read Ethernet Address from EEPROM. */ 257 if (i != 6) { 258 for (i = 0; i < 3; i++) { 259 word = e->eeprom_read(e, i); 260 addr->ea_addr[i * 2] = (word & 0x00ff); 261 addr->ea_addr[i * 2 + 1] = (word & 0xff00) >> 8; 262 } 263 } 264 265 /* Set Receive Address. */ 266 e1000_reg_write(e, E1000_REG_RAL, *(u32_t *)(&addr->ea_addr[0])); 267 e1000_reg_write(e, E1000_REG_RAH, *(u16_t *)(&addr->ea_addr[4])); 268 e1000_reg_set(e, E1000_REG_RAH, E1000_REG_RAH_AV); 269 e1000_reg_set(e, E1000_REG_RCTL, E1000_REG_RCTL_MPE); 270 271 E1000_DEBUG(3, ("%s: Ethernet Address %x:%x:%x:%x:%x:%x\n", e->name, 272 addr->ea_addr[0], addr->ea_addr[1], addr->ea_addr[2], 273 addr->ea_addr[3], addr->ea_addr[4], addr->ea_addr[5])); 274 } 275 276 /* 277 * Initialize receive and transmit buffers. 278 */ 279 static void 280 e1000_init_buf(e1000_t * e) 281 { 282 phys_bytes rx_desc_p, rx_buff_p; 283 phys_bytes tx_desc_p, tx_buff_p; 284 int i; 285 286 /* Number of descriptors. */ 287 e->rx_desc_count = E1000_RXDESC_NR; 288 e->tx_desc_count = E1000_TXDESC_NR; 289 290 /* Allocate receive descriptors. */ 291 if ((e->rx_desc = alloc_contig(sizeof(e1000_rx_desc_t) * 292 e->rx_desc_count, AC_ALIGN4K, &rx_desc_p)) == NULL) 293 panic("failed to allocate RX descriptors"); 294 295 memset(e->rx_desc, 0, sizeof(e1000_rx_desc_t) * e->rx_desc_count); 296 297 /* Allocate receive buffers. */ 298 e->rx_buffer_size = E1000_RXDESC_NR * E1000_IOBUF_SIZE; 299 300 if ((e->rx_buffer = alloc_contig(e->rx_buffer_size, AC_ALIGN4K, 301 &rx_buff_p)) == NULL) 302 panic("failed to allocate RX buffers"); 303 304 /* Set up receive descriptors. */ 305 for (i = 0; i < E1000_RXDESC_NR; i++) 306 e->rx_desc[i].buffer = rx_buff_p + i * E1000_IOBUF_SIZE; 307 308 /* Allocate transmit descriptors. */ 309 if ((e->tx_desc = alloc_contig(sizeof(e1000_tx_desc_t) * 310 e->tx_desc_count, AC_ALIGN4K, &tx_desc_p)) == NULL) 311 panic("failed to allocate TX descriptors"); 312 313 memset(e->tx_desc, 0, sizeof(e1000_tx_desc_t) * e->tx_desc_count); 314 315 /* Allocate transmit buffers. */ 316 e->tx_buffer_size = E1000_TXDESC_NR * E1000_IOBUF_SIZE; 317 318 if ((e->tx_buffer = alloc_contig(e->tx_buffer_size, AC_ALIGN4K, 319 &tx_buff_p)) == NULL) 320 panic("failed to allocate TX buffers"); 321 322 /* Set up transmit descriptors. */ 323 for (i = 0; i < E1000_TXDESC_NR; i++) 324 e->tx_desc[i].buffer = tx_buff_p + i * E1000_IOBUF_SIZE; 325 326 /* Set up the receive ring registers. */ 327 e1000_reg_write(e, E1000_REG_RDBAL, rx_desc_p); 328 e1000_reg_write(e, E1000_REG_RDBAH, 0); 329 e1000_reg_write(e, E1000_REG_RDLEN, 330 e->rx_desc_count * sizeof(e1000_rx_desc_t)); 331 e1000_reg_write(e, E1000_REG_RDH, 0); 332 e1000_reg_write(e, E1000_REG_RDT, e->rx_desc_count - 1); 333 e1000_reg_unset(e, E1000_REG_RCTL, E1000_REG_RCTL_BSIZE); 334 e1000_reg_set(e, E1000_REG_RCTL, E1000_REG_RCTL_EN); 335 336 /* Set up the transmit ring registers. */ 337 e1000_reg_write(e, E1000_REG_TDBAL, tx_desc_p); 338 e1000_reg_write(e, E1000_REG_TDBAH, 0); 339 e1000_reg_write(e, E1000_REG_TDLEN, 340 e->tx_desc_count * sizeof(e1000_tx_desc_t)); 341 e1000_reg_write(e, E1000_REG_TDH, 0); 342 e1000_reg_write(e, E1000_REG_TDT, 0); 343 e1000_reg_set(e, E1000_REG_TCTL, 344 E1000_REG_TCTL_EN | E1000_REG_TCTL_PSP); 345 } 346 347 /* 348 * Initialize the hardware. Return the ethernet address. 349 */ 350 static void 351 e1000_init_hw(e1000_t * e, ether_addr_t * addr) 352 { 353 int r, i; 354 355 e->irq_hook = e->irq; 356 357 /* 358 * Set the interrupt handler and policy. Do not automatically 359 * reenable interrupts. Return the IRQ line number on interrupts. 360 */ 361 if ((r = sys_irqsetpolicy(e->irq, 0, &e->irq_hook)) != OK) 362 panic("sys_irqsetpolicy failed: %d", r); 363 if ((r = sys_irqenable(&e->irq_hook)) != OK) 364 panic("sys_irqenable failed: %d", r); 365 366 /* Reset hardware. */ 367 e1000_reset_hw(e); 368 369 /* 370 * Initialize appropriately, according to section 14.3 General 371 * Configuration of Intel's Gigabit Ethernet Controllers Software 372 * Developer's Manual. 373 */ 374 e1000_reg_set(e, E1000_REG_CTRL, 375 E1000_REG_CTRL_ASDE | E1000_REG_CTRL_SLU); 376 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_LRST); 377 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_PHY_RST); 378 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_ILOS); 379 e1000_reg_write(e, E1000_REG_FCAL, 0); 380 e1000_reg_write(e, E1000_REG_FCAH, 0); 381 e1000_reg_write(e, E1000_REG_FCT, 0); 382 e1000_reg_write(e, E1000_REG_FCTTV, 0); 383 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_VME); 384 385 /* Clear Multicast Table Array (MTA). */ 386 for (i = 0; i < 128; i++) 387 e1000_reg_write(e, E1000_REG_MTA + i * 4, 0); 388 389 /* Initialize statistics registers. */ 390 for (i = 0; i < 64; i++) 391 e1000_reg_write(e, E1000_REG_CRCERRS + i * 4, 0); 392 393 /* Acquire MAC address and set up RX/TX buffers. */ 394 e1000_init_addr(e, addr); 395 e1000_init_buf(e); 396 397 /* Enable interrupts. */ 398 e1000_reg_set(e, E1000_REG_IMS, E1000_REG_IMS_LSC | E1000_REG_IMS_RXO | 399 E1000_REG_IMS_RXT | E1000_REG_IMS_TXQE | E1000_REG_IMS_TXDW); 400 } 401 402 /* 403 * Try to send a packet. 404 */ 405 static int 406 e1000_send(struct netdriver_data * data, size_t size) 407 { 408 e1000_t *e; 409 e1000_tx_desc_t *desc; 410 unsigned int head, tail, next; 411 char *ptr; 412 413 e = &e1000_state; 414 415 if (size > E1000_IOBUF_SIZE) 416 panic("packet too large to send"); 417 418 /* 419 * The queue tail must not advance to the point that it is equal to the 420 * queue head, since this condition indicates that the queue is empty. 421 */ 422 head = e1000_reg_read(e, E1000_REG_TDH); 423 tail = e1000_reg_read(e, E1000_REG_TDT); 424 next = (tail + 1) % e->tx_desc_count; 425 426 if (next == head) 427 return SUSPEND; 428 429 /* The descriptor to use is the one pointed to by the current tail. */ 430 desc = &e->tx_desc[tail]; 431 432 /* Copy the packet from the caller. */ 433 ptr = e->tx_buffer + tail * E1000_IOBUF_SIZE; 434 435 netdriver_copyin(data, 0, ptr, size); 436 437 /* Mark this descriptor ready. */ 438 desc->status = 0; 439 desc->length = size; 440 desc->command = E1000_TX_CMD_EOP | E1000_TX_CMD_FCS | E1000_TX_CMD_RS; 441 442 /* Increment tail. Start transmission. */ 443 e1000_reg_write(e, E1000_REG_TDT, next); 444 445 return OK; 446 } 447 448 /* 449 * Try to receive a packet. 450 */ 451 static ssize_t 452 e1000_recv(struct netdriver_data * data, size_t max) 453 { 454 e1000_t *e; 455 e1000_rx_desc_t *desc; 456 unsigned int head, tail, cur; 457 char *ptr; 458 size_t size; 459 460 e = &e1000_state; 461 462 /* If the queue head and tail are equal, the queue is empty. */ 463 head = e1000_reg_read(e, E1000_REG_RDH); 464 tail = e1000_reg_read(e, E1000_REG_RDT); 465 466 E1000_DEBUG(4, ("%s: head=%u, tail=%u\n", e->name, head, tail)); 467 468 if (head == tail) 469 return SUSPEND; 470 471 /* Has a packet been received? */ 472 cur = (tail + 1) % e->rx_desc_count; 473 desc = &e->rx_desc[cur]; 474 475 if (!(desc->status & E1000_RX_STATUS_DONE)) 476 return SUSPEND; 477 478 /* 479 * HACK: we expect all packets to fit in a single receive buffer. 480 * Eventually, some sort of support to deal with packets spanning 481 * multiple receive descriptors should be added. For now, we panic, 482 * so that we can continue after the restart; this is already an 483 * improvement over freezing (the old behavior of this driver). 484 */ 485 size = desc->length; 486 487 if (!(desc->status & E1000_RX_STATUS_EOP)) 488 panic("received packet too large"); 489 490 /* Copy the packet to the caller. */ 491 ptr = e->rx_buffer + cur * E1000_IOBUF_SIZE; 492 493 if (size > max) 494 size = max; 495 496 netdriver_copyout(data, 0, ptr, size); 497 498 /* Reset the descriptor. */ 499 desc->status = 0; 500 501 /* Increment tail. */ 502 e1000_reg_write(e, E1000_REG_RDT, cur); 503 504 /* Return the size of the received packet. */ 505 return size; 506 } 507 508 /* 509 * Return statistics. 510 */ 511 static void 512 e1000_stat(eth_stat_t * stat) 513 { 514 e1000_t *e = &e1000_state; 515 516 E1000_DEBUG(3, ("e1000: stat()\n")); 517 518 stat->ets_recvErr = e1000_reg_read(e, E1000_REG_RXERRC); 519 stat->ets_sendErr = 0; 520 stat->ets_OVW = 0; 521 stat->ets_CRCerr = e1000_reg_read(e, E1000_REG_CRCERRS); 522 stat->ets_frameAll = 0; 523 stat->ets_missedP = e1000_reg_read(e, E1000_REG_MPC); 524 stat->ets_packetR = e1000_reg_read(e, E1000_REG_TPR); 525 stat->ets_packetT = e1000_reg_read(e, E1000_REG_TPT); 526 stat->ets_collision = e1000_reg_read(e, E1000_REG_COLC); 527 stat->ets_transAb = 0; 528 stat->ets_carrSense = 0; 529 stat->ets_fifoUnder = 0; 530 stat->ets_fifoOver = 0; 531 stat->ets_CDheartbeat = 0; 532 stat->ets_OWC = 0; 533 } 534 535 /* 536 * Link status has changed. Nothing to do for now. 537 */ 538 static void 539 e1000_link_changed(e1000_t * e) 540 { 541 542 E1000_DEBUG(4, ("%s: link_changed()\n", e->name)); 543 } 544 545 /* 546 * Handle an interrupt. 547 */ 548 static void 549 e1000_intr(unsigned int __unused mask) 550 { 551 e1000_t *e; 552 u32_t cause; 553 554 E1000_DEBUG(3, ("e1000: interrupt\n")); 555 556 e = &e1000_state; 557 558 /* Reenable interrupts. */ 559 if (sys_irqenable(&e->irq_hook) != OK) 560 panic("failed to re-enable IRQ"); 561 562 /* Read the Interrupt Cause Read register. */ 563 if ((cause = e1000_reg_read(e, E1000_REG_ICR)) != 0) { 564 if (cause & E1000_REG_ICR_LSC) 565 e1000_link_changed(e); 566 567 if (cause & (E1000_REG_ICR_RXO | E1000_REG_ICR_RXT)) 568 netdriver_recv(); 569 570 if (cause & (E1000_REG_ICR_TXQE | E1000_REG_ICR_TXDW)) 571 netdriver_send(); 572 } 573 } 574 575 /* 576 * Stop the card. 577 */ 578 static void 579 e1000_stop(void) 580 { 581 e1000_t *e; 582 583 e = &e1000_state; 584 585 E1000_DEBUG(3, ("%s: stop()\n", e->name)); 586 587 e1000_reset_hw(e); 588 } 589 590 /* 591 * Read from a register. 592 */ 593 static uint32_t 594 e1000_reg_read(e1000_t * e, uint32_t reg) 595 { 596 uint32_t value; 597 598 /* Assume a sane register. */ 599 assert(reg < 0x1ffff); 600 601 /* Read from memory mapped register. */ 602 value = *(volatile uint32_t *)(e->regs + reg); 603 604 /* Return the result. */ 605 return value; 606 } 607 608 /* 609 * Write to a register. 610 */ 611 static void 612 e1000_reg_write(e1000_t * e, uint32_t reg, uint32_t value) 613 { 614 615 /* Assume a sane register. */ 616 assert(reg < 0x1ffff); 617 618 /* Write to memory mapped register. */ 619 *(volatile u32_t *)(e->regs + reg) = value; 620 } 621 622 /* 623 * Set bits in a register. 624 */ 625 static void 626 e1000_reg_set(e1000_t * e, uint32_t reg, uint32_t value) 627 { 628 uint32_t data; 629 630 /* First read the current value. */ 631 data = e1000_reg_read(e, reg); 632 633 /* Set bits, and write back. */ 634 e1000_reg_write(e, reg, data | value); 635 } 636 637 /* 638 * Clear bits in a register. 639 */ 640 static void 641 e1000_reg_unset(e1000_t * e, uint32_t reg, uint32_t value) 642 { 643 uint32_t data; 644 645 /* First read the current value. */ 646 data = e1000_reg_read(e, reg); 647 648 /* Unset bits, and write back. */ 649 e1000_reg_write(e, reg, data & ~value); 650 } 651 652 /* 653 * Read from EEPROM. 654 */ 655 static u16_t 656 eeprom_eerd(e1000_t * e, int reg) 657 { 658 u32_t data; 659 660 /* Request EEPROM read. */ 661 e1000_reg_write(e, E1000_REG_EERD, 662 (reg << e->eeprom_addr_off) | (E1000_REG_EERD_START)); 663 664 /* Wait until ready. */ 665 while (!((data = (e1000_reg_read(e, E1000_REG_EERD))) & 666 e->eeprom_done_bit)); 667 668 return data >> 16; 669 } 670 671 /* 672 * Initialize ICH8 flash. 673 */ 674 static int 675 eeprom_ich_init(e1000_t * e) 676 { 677 union ich8_hws_flash_status hsfsts; 678 int ret_val = -1; 679 int i = 0; 680 681 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 682 683 /* Check if the flash descriptor is valid */ 684 if (hsfsts.hsf_status.fldesvalid == 0) { 685 E1000_DEBUG(3, ("Flash descriptor invalid. " 686 "SW Sequencing must be used.")); 687 return ret_val; 688 } 689 690 /* Clear FCERR and DAEL in hw status by writing 1 */ 691 hsfsts.hsf_status.flcerr = 1; 692 hsfsts.hsf_status.dael = 1; 693 694 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval); 695 696 /* 697 * Either we should have a hardware SPI cycle in progress bit to check 698 * against, in order to start a new cycle or FDONE bit should be 699 * changed in the hardware so that it is 1 after hardware reset, which 700 * can then be used as an indication whether a cycle is in progress or 701 * has been completed. 702 */ 703 if (hsfsts.hsf_status.flcinprog == 0) { 704 /* 705 * There is no cycle running at present, so we can start a 706 * cycle. Begin by setting Flash Cycle Done. 707 */ 708 hsfsts.hsf_status.flcdone = 1; 709 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval); 710 ret_val = 0; 711 } else { 712 /* 713 * Otherwise poll for sometime so the current cycle has a 714 * chance to end before giving up. 715 */ 716 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 717 hsfsts.regval = E1000_READ_FLASH_REG16(e, 718 ICH_FLASH_HSFSTS); 719 720 if (hsfsts.hsf_status.flcinprog == 0) { 721 ret_val = 0; 722 break; 723 } 724 tickdelay(1); 725 } 726 if (ret_val == 0) { 727 /* 728 * Successful in waiting for previous cycle to timeout, 729 * now set the Flash Cycle Done. 730 */ 731 hsfsts.hsf_status.flcdone = 1; 732 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, 733 hsfsts.regval); 734 } else { 735 E1000_DEBUG(3, 736 ("Flash controller busy, cannot get access")); 737 } 738 } 739 740 return ret_val; 741 } 742 743 /* 744 * Start ICH8 flash cycle. 745 */ 746 static int 747 eeprom_ich_cycle(e1000_t * e, u32_t timeout) 748 { 749 union ich8_hws_flash_ctrl hsflctl; 750 union ich8_hws_flash_status hsfsts; 751 int ret_val = -1; 752 u32_t i = 0; 753 754 E1000_DEBUG(3, ("e1000_flash_cycle_ich8lan")); 755 756 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 757 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL); 758 hsflctl.hsf_ctrl.flcgo = 1; 759 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval); 760 761 /* Wait till the FDONE bit is set to 1 */ 762 do { 763 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS); 764 if (hsfsts.hsf_status.flcdone == 1) 765 break; 766 tickdelay(1); 767 } while (i++ < timeout); 768 769 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 770 ret_val = 0; 771 772 return ret_val; 773 } 774 775 /* 776 * Read from ICH8 flash. 777 */ 778 static u16_t 779 eeprom_ich(e1000_t * e, int reg) 780 { 781 union ich8_hws_flash_status hsfsts; 782 union ich8_hws_flash_ctrl hsflctl; 783 u32_t flash_linear_addr; 784 u32_t flash_data = 0; 785 int ret_val = -1; 786 u8_t count = 0; 787 u16_t data = 0; 788 789 E1000_DEBUG(3, ("e1000_read_flash_data_ich8lan")); 790 791 if (reg > ICH_FLASH_LINEAR_ADDR_MASK) 792 return data; 793 794 reg *= sizeof(u16_t); 795 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & reg) + 796 e->flash_base_addr; 797 798 do { 799 tickdelay(1); 800 801 /* Steps */ 802 ret_val = eeprom_ich_init(e); 803 if (ret_val != 0) 804 break; 805 806 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL); 807 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 808 hsflctl.hsf_ctrl.fldbcount = 1; 809 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 810 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval); 811 E1000_WRITE_FLASH_REG(e, ICH_FLASH_FADDR, flash_linear_addr); 812 813 ret_val = eeprom_ich_cycle(e, ICH_FLASH_READ_COMMAND_TIMEOUT); 814 815 /* 816 * Check if FCERR is set to 1, if set to 1, clear it and try 817 * the whole sequence a few more times, else read in (shift in) 818 * the Flash Data0, the order is least significant byte first 819 * msb to lsb. 820 */ 821 if (ret_val == 0) { 822 flash_data = E1000_READ_FLASH_REG(e, ICH_FLASH_FDATA0); 823 data = (u16_t)(flash_data & 0x0000FFFF); 824 break; 825 } else { 826 /* 827 * If we've gotten here, then things are probably 828 * completely hosed, but if the error condition is 829 * detected, it won't hurt to give it another try... 830 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 831 */ 832 hsfsts.regval = E1000_READ_FLASH_REG16(e, 833 ICH_FLASH_HSFSTS); 834 835 if (hsfsts.hsf_status.flcerr == 1) { 836 /* Repeat for some time before giving up. */ 837 continue; 838 } else if (hsfsts.hsf_status.flcdone == 0) { 839 E1000_DEBUG(3, ("Timeout error - flash cycle " 840 "did not complete.")); 841 break; 842 } 843 } 844 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 845 846 return data; 847 } 848