1 #ifndef LAN8710A_REG_H_
2 #define LAN8710A_REG_H_
3 
4 /* How much memory we should map */
5 #define MEMORY_LIMIT		(0x5302000)
6 #define BEGINNING_DESC_MEM	(0x4A102000)
7 #define DESC_MEMORY_LIMIT	(0x2000)
8 #define BEGINNING_RX_DESC_MEM	(0x4A102000)
9 #define BEGINNING_TX_DESC_MEM	(0x4A103000)
10 
11 /* MDIO Registers */
12 #define MDIO_BASE_ADDR		(0x4A101000)
13 #define MDIOVER			((volatile u32_t *)( lan8710a_state.regs_mdio + 0x00))
14 #define MDIOCONTROL		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x04))
15 #define MDIOALIVE		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x08))
16 #define MDIOLINK		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x0C))
17 #define MDIOLINKINTRAW		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x10))
18 #define MDIOLINKINTMASKED	((volatile u32_t *)( lan8710a_state.regs_mdio + 0x14))
19 #define MDIOUSERINTRAW		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x20))
20 #define MDIOUSERINTMASKED	((volatile u32_t *)( lan8710a_state.regs_mdio + 0x24))
21 #define MDIOUSERINTMASKSET	((volatile u32_t *)( lan8710a_state.regs_mdio + 0x28))
22 #define MDIOUSERINTMASKCLR	((volatile u32_t *)( lan8710a_state.regs_mdio + 0x2C))
23 #define MDIOUSERACCESS0		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x80))
24 #define MDIOUSERPHYSEL0		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x84))
25 #define MDIOUSERACCESS1		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x88))
26 #define MDIOUSERPHYSEL1		((volatile u32_t *)( lan8710a_state.regs_mdio + 0x8C))
27 
28 #define MDIO_PREAMBLE		(1 << 20)
29 #define MDCLK_DIVIDER		(0x255)
30 #define MDIO_ENABLE		(1 << 30)
31 #define MDIO_GO			(1 << 31)
32 #define MDIO_WRITE		(1 << 30)
33 #define MDIO_ACK		(1 << 29)
34 
35 #define MDIO_REGADR		(21)
36 #define MDIO_PHYADR		(16)
37 #define MDIO_DATA		(0)
38 
39 /* CONTROL MODULE Registers */
40 #define CTRL_MOD_BASE_ADR	(0x44E10000)
41 #define CTRL_MAC_ID0_LO		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x630))
42 #define CTRL_MAC_ID0_HI		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x634))
43 #define GMII_SEL		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x650))
44 #define CONF_MII1_COL		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x908))
45 #define CONF_MII1_CRS		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x90C))
46 #define CONF_MII1_RX_ER		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x910))
47 #define CONF_MII1_TX_EN		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x914))
48 #define CONF_MII1_RX_DV		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x918))
49 #define CONF_MII1_TXD3		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x91C))
50 #define CONF_MII1_TXD2		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x920))
51 #define CONF_MII1_TXD1		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x924))
52 #define CONF_MII1_TXD0		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x928))
53 #define CONF_MII1_TX_CLK	((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x92C))
54 #define CONF_MII1_RX_CLK	((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x930))
55 #define CONF_MII1_RXD3		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x934))
56 #define CONF_MII1_RXD2		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x938))
57 #define CONF_MII1_RXD1		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x93C))
58 #define CONF_MII1_RXD0		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x940))
59 #define CONF_MDIO		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x948))
60 #define CONF_MDC		((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x94C))
61 
62 #define CONF_MOD_SLEW_CTRL	(1 << 6)
63 #define CONF_MOD_RX_ACTIVE	(1 << 5)
64 #define CONF_MOD_PU_TYPESEL	(1 << 4)
65 #define CONF_MOD_PUDEN		(1 << 3)
66 #define CONF_MOD_MMODE_MII	(7 << 0)
67 #define RMII1_IO_CLK_EN		(1 << 6)
68 #define RGMII1_IDMODE		(1 << 4)
69 #define GMII2_SEL_BIT1		(1 << 3)
70 #define GMII2_SEL_BIT0		(1 << 2)
71 #define GMII1_SEL_BIT1		(1 << 1)
72 #define GMII1_SEL_BIT0		(1 << 0)
73 
74 /* CLOCK MODULE Registers */
75 #define CM_PER_BASE_ADR		(0x44E00000)
76 #define CM_PER_CPSW_CLKSTCTRL	((volatile u32_t *)( lan8710a_state.regs_cp_per + 0x144))
77 
78 #define CM_PER_CPSW_CLKSTCTRL_BIT1	(1 << 1)
79 #define CM_PER_CPSW_CLKSTCTRL_BIT0	(1 << 0)
80 
81 /* CPSW_ALE Registers */
82 #define CPSW_ALE_BASE_ADR	(0x4A100D00)
83 #define CPSW_ALE_CONTROL	((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x08))
84 #define CPSW_ALE_PORTCTL0	((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x40))
85 #define CPSW_ALE_PORTCTL1	((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x44))
86 
87 #define CPSW_ALE_ENABLE		(1 << 31)
88 #define CPSW_ALE_BYPASS		(1 << 4)
89 #define CPSW_ALE_PORT_FWD	(3 << 0)
90 
91 /* CPSW_SL Registers */
92 #define CPSW_SL_BASE_ADR	(0x4A100D80)
93 #define CPSW_SL_MACCONTROL(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04))
94 #define CPSW_SL_SOFT_RESET(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C))
95 #define CPSW_SL_RX_MAXLEN(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10))
96 #define CPSW_SL_BOFFTEST(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14))
97 #define CPSW_SL_EMCONTROL(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20))
98 #define CPSW_SL_RX_PRI_MAP(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x24))
99 #define CPSW_SL_TX_GAP(x)	((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x28))
100 
101 #define CPSW_SL_GMII_EN		(1 << 5)
102 #define CPSW_SL_FULLDUPLEX	(1 << 0)
103 #define SOFT_RESET		(1 << 0)
104 
105 /* CPSW_STATS Registers */
106 #define CPSW_STATS_BASE_ADR	(0x4A100900)
107 #define CPSW_STATS_MEM_LIMIT	(0x90)
108 #define CPSW_STAT_RX_GOOD	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x00))
109 #define CPSW_STAT_RX_CRC_ERR	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x10))
110 #define CPSW_STAT_RX_AGNCD_ERR	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x14))
111 #define CPSW_STAT_RX_OVERSIZE	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x18))
112 #define CPSW_STAT_TX_GOOD	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x34))
113 #define CPSW_STAT_COLLISIONS	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x48))
114 #define CPSW_STAT_TX_UNDERRUN	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C))
115 #define CPSW_STAT_CARR_SENS_ERR	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x60))
116 #define CPSW_STAT_RX_OVERRUN	((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C))
117 
118 /* CPSW_CPDMA Registers */
119 #define CPSW_CPDMA_BASE_ADR	(0x4A100800)
120 #define CPDMA_SOFT_RESET	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x1C))
121 #define CPDMA_TX_CONTROL	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x04))
122 #define CPDMA_RX_CONTROL	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14))
123 #define CPDMA_CONTROL		((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20))
124 #define CPDMA_STATUS		((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24))
125 #define CPDMA_RX_BUFFER_OFFSET	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28))
126 #define CPDMA_EMCONTROL		((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C))
127 #define CPDMA_TX_INTMASK_SET	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88))
128 #define CPDMA_TX_INTMASK_CLEAR	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C))
129 #define CPDMA_EOI_VECTOR	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94))
130 #define CPDMA_RX_INTMASK_SET	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8))
131 #define CPDMA_RX_INTMASK_CLEAR	((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC))
132 
133 #define CPDMA_IDLE		(1 << 31)
134 #define CPDMA_TX_RLIM		(0xFF << 8)
135 #define CPDMA_NO_OFFSET		(0xFFFF << 0)
136 #define CPDMA_RX_CEF		(1 << 4)
137 #define CPDMA_CMD_IDLE		(1 << 3)
138 #define RX_OFFLEN_BLOCK		(1 << 2)
139 #define RX_OWNERSHIP		(1 << 1)
140 #define TX_PTYPE		(1 << 0)
141 #define CPDMA_TX_EN		(1 << 0)
142 #define CPDMA_RX_EN		(1 << 0)
143 #define CPDMA_FIRST_CHAN_INT	(1 << 0)
144 #define CPDMA_ALL_CHAN_INT	(0xFF << 0)
145 #define CPDMA_TX_PTYPE		(1 << 0)
146 #define CPDMA_ERROR		(0x00F7F700)
147 
148 /* CPSW_SS Registers */
149 #define CPSW_SS_BASE_ADR	(0x4A100000)
150 #define CPSW_SS_SOFT_RESET	((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x08))
151 #define CPSW_SS_STAT_PORT_EN	((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C))
152 #define CPSW_SS_TX_START_WDS	((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x20))
153 
154 #define CPSW_P2_STAT_EN		(1 << 2)
155 #define CPSW_P1_STAT_EN		(1 << 1)
156 #define CPSW_P0_STAT_EN		(1 << 0)
157 
158 /* CPSW_WR Registers */
159 #define CPSW_WR_BASE_ADR	(0x4A101200)
160 #define CPSW_WR_INT_CONTROL	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x0C))
161 #define CPSW_WR_C0_RX_EN	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x14))
162 #define CPSW_WR_C1_RX_EN	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x24))
163 #define CPSW_WR_C2_RX_EN	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x34))
164 #define CPSW_WR_C0_RX_STAT	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x44))
165 #define CPSW_WR_C0_TX_EN	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x18))
166 #define CPSW_WR_C0_TX_STAT	((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x48))
167 
168 #define CPSW_FIRST_CHAN_INT	(1 << 0)
169 #define CPSW_ALL_CHAN_INT	(0xFF << 0)
170 
171 /* INTERRUPTION CONTROLLER Registers */
172 #define INTC_BASE_ADR		(0x48200000)
173 #define INTC_SYSCONFIG		((volatile u32_t *)( lan8710a_state.regs_intc + 0x10))
174 #define INTC_IDLE		((volatile u32_t *)( lan8710a_state.regs_intc + 0x50))
175 #define INTC_MIR_CLEAR1		((volatile u32_t *)( lan8710a_state.regs_intc + 0xA8))
176 #define INTC_ILR(x)		((volatile u32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x)))
177 
178 #define INTC_AUTOIDLE		(1 << 0)
179 #define INTC_FUNCIDLE		(1 << 0)
180 #define INTC_TURBO		(1 << 1)
181 #define INTC_FIQnIRQ		(1 << 0)
182 #define INTC_RX_MASK		(1 << 9)
183 #define INTC_TX_MASK		(1 << 10)
184 
185 /* DMA STATERAM Registers */
186 #define CPDMA_STRAM_BASE_ADR	(0x4A100A00)
187 #define CPDMA_STRAM_TX_HDP(x)	((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 4*(x)))
188 #define CPDMA_STRAM_RX_HDP(x)	((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x20 + 4*(x)))
189 #define CPDMA_STRAM_TX_CP(x)	((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x40 + 4*(x)))
190 #define CPDMA_STRAM_RX_CP(x)	((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x60 + 4*(x)))
191 
192 #define ALL_BITS		(0xFFFFFFFF)
193 
194 /* LAN8710A Registers */
195 #define PHY_REGISTERS		(31)
196 #define LAN8710A_CTRL_REG	(0)
197 #define LAN8710A_STATUS_REG	(1)
198 
199 #define LAN8710A_SOFT_RESET	(1 << 15)
200 #define LAN8710A_AUTO_NEG	(1 << 12)
201 #define LAN8710A_AUTO_NEG_COMPL	(1 << 5)
202 
203 #endif /* LAN8710A_REG_H_ */
204