1 2 /* macros for 'flags' */ 3 #define ECF_PROMISC 0x01 4 #define ECF_MULTI 0x02 5 #define ECF_BROAD 0x04 6 7 /* ====== ethernet card info. ====== */ 8 typedef struct ether_card 9 { 10 /* ####### MINIX style ####### */ 11 char port_name[sizeof("lance#n")]; 12 int flags; 13 eth_stat_t eth_stat; 14 15 /* ######## device info. ####### */ 16 port_t ec_port; 17 int ec_irq; 18 int ec_hook; 19 } ether_card_t; 20 21 /* 22 * NOTE: Not all the CSRs are defined. Just the ones that were deemed 23 * necessary or potentially useful. 24 */ 25 26 /* Control and Status Register Addresses */ 27 #define LANCE_CSR0 0 /* Controller Status Register */ 28 #define LANCE_CSR1 1 /* Initialization Block Address (Lower) */ 29 #define LANCE_CSR2 2 /* Initialization Block Address (Upper) */ 30 #define LANCE_CSR3 3 /* Interrupt Masks and Deferral Control */ 31 #define LANCE_CSR4 4 /* Test and Features Control */ 32 #define LANCE_CSR5 5 /* Extended Control and Interrupt */ 33 #define LANCE_CSR8 8 /* Logical Address Filter 0 */ 34 #define LANCE_CSR9 9 /* Logical Address Filter 1 */ 35 #define LANCE_CSR10 10 /* Logical Address Filter 2 */ 36 #define LANCE_CSR11 11 /* Logical Address Filter 3 */ 37 #define LANCE_CSR15 15 /* Mode */ 38 #define LANCE_CSR88 88 /* Chip ID Register (Lower) */ 39 #define LANCE_CSR89 89 /* Chip ID Register (Upper) */ 40 41 /* Control and Status Register 0 (CSR0) */ 42 #define LANCE_CSR0_ERR 0x8000 /* Error Occurred */ 43 #define LANCE_CSR0_BABL 0x4000 /* Transmitter Timeout Error */ 44 #define LANCE_CSR0_CERR 0x2000 /* Collision Error */ 45 #define LANCE_CSR0_MISS 0x1000 /* Missed Frame */ 46 #define LANCE_CSR0_MERR 0x0800 /* Memory Error */ 47 #define LANCE_CSR0_RINT 0x0400 /* Receive Interrupt */ 48 #define LANCE_CSR0_TINT 0x0200 /* Transmit Interrupt */ 49 #define LANCE_CSR0_IDON 0x0100 /* Initialization Done */ 50 #define LANCE_CSR0_INTR 0x0080 /* Interrupt Flag */ 51 #define LANCE_CSR0_IENA 0x0040 /* Interrupt Enable */ 52 #define LANCE_CSR0_RXON 0x0020 /* Receive On */ 53 #define LANCE_CSR0_TXON 0x0010 /* Transmit On */ 54 #define LANCE_CSR0_TDMD 0x0008 /* Transmit Demand */ 55 #define LANCE_CSR0_STOP 0x0004 /* Stop */ 56 #define LANCE_CSR0_STRT 0x0002 /* Start */ 57 #define LANCE_CSR0_INIT 0x0001 /* Init */ 58 59 /* Control and Status Register 3 (CSR3) */ 60 /* 0x8000 Reserved */ 61 #define LANCE_CSR3_BABLM 0x4000 /* Babble Mask */ 62 /* 0x2000 Reserved */ 63 #define LANCE_CSR3_MISSM 0x1000 /* Missed Frame Mask */ 64 #define LANCE_CSR3_MERRM 0x0800 /* Memory Error Mask */ 65 #define LANCE_CSR3_RINTM 0x0400 /* Receive Interrupt Mask */ 66 #define LANCE_CSR3_TINTM 0x0200 /* Transmit Interrupt Mask */ 67 #define LANCE_CSR3_IDONM 0x0100 /* Initialization Done Mask */ 68 /* 0x0080 Reserved */ 69 #define LANCE_CSR3_DXSUFLO 0x0040 /* Disable Transmit Stop on Underflow */ 70 #define LANCE_CSR3_LAPPEN 0x0020 /* Look Ahead Packet Processing Enable */ 71 #define LANCE_CSR3_DXMT2PD 0x0010 /* Disable Transmit Two Part Deferral */ 72 #define LANCE_CSR3_EMBA 0x0008 /* Enable Modified Back-off Algorithm */ 73 #define LANCE_CSR3_BSWP 0x0004 /* Byte Swap */ 74 /* 0x0002 Reserved 75 * 0x0001 Reserved */ 76 77 /* Control and Status Register 4 (CSR4) */ 78 #define LANCE_CSR4_EN124 0x8000 /* Enable CSR124 Access */ 79 #define LANCE_CSR4_DMAPLUS 0x4000 /* Disable DMA Burst Transfer Counter */ 80 #define LANCE_CSR4_TIMER 0x2000 /* Enable Bus Activity Timer */ 81 #define LANCE_CSR4_DPOLL 0x1000 /* Disable Transmit Polling */ 82 #define LANCE_CSR4_APAD_XMT 0x0800 /* Auto Pad Transmit */ 83 #define LANCE_CSR4_ASTRP_RCV 0x0400 /* Auto Strip Receive */ 84 #define LANCE_CSR4_MFCO 0x0200 /* Missed Frame Counter Overflow */ 85 #define LANCE_CSR4_MFCOM 0x0100 /* Missed Frame Counter Overflow Mask */ 86 #define LANCE_CSR4_UINTCMD 0x0080 /* User Interrupt Command */ 87 #define LANCE_CSR4_UINT 0x0040 /* User Interrupt */ 88 #define LANCE_CSR4_RCVCCO 0x0020 /* Receive Collision Counter Overflow */ 89 #define LANCE_CSR4_RCVCCOM 0x0010 /* Receive Collision Counter Overflow 90 * Mask */ 91 #define LANCE_CSR4_TXSTRT 0x0008 /* Transmit Start */ 92 #define LANCE_CSR4_TXSTRTM 0x0004 /* Transmit Start Mask */ 93 #define LANCE_CSR4_JAB 0x0002 /* Jabber Error */ 94 #define LANCE_CSR4_JABM 0x0001 /* Jabber Error Mask */ 95 96 /* Control and Status Register 5 (CSR5) */ 97 #define LANCE_CSR5_TOKINTD 0x8000 /* Transmit OK Interrupt Disable */ 98 #define LANCE_CSR5_LINTEN 0x4000 /* Last Transmit Interrupt Enable */ 99 /* 0x2000 Reserved 100 * 0x1000 Reserved */ 101 #define LANCE_CSR5_SINT 0x0800 /* System Interrupt */ 102 #define LANCE_CSR5_SINTE 0x0400 /* System Interrupt Enable */ 103 #define LANCE_CSR5_SLPINT 0x0200 /* Sleep Interrupt */ 104 #define LANCE_CSR5_SLPINTE 0x0100 /* Sleep Interrupt Enable */ 105 #define LANCE_CSR5_EXDINT 0x0080 /* Excessive Deferral Interrupt */ 106 #define LANCE_CSR5_EXDINTE 0x0040 /* Excessive Deferral Interrupt Enable */ 107 #define LANCE_CSR5_MPPLBA 0x0020 /* Magic Packet Physical Logical Broadcast 108 * Accept */ 109 #define LANCE_CSR5_MPINT 0x0010 /* Magic Packet Interrupt */ 110 #define LANCE_CSR5_MPINTE 0x0008 /* Magic Packet Interrupt Enable */ 111 #define LANCE_CSR5_MPEN 0x0004 /* Magic Packet Enable */ 112 #define LANCE_CSR5_MPMODE 0x0002 /* Magic Packet Mode */ 113 #define LANCE_CSR5_SPND 0x0001 /* Suspend */ 114 115 /* Control and Status Register 15 (CSR15) */ 116 #define LANCE_CSR15_PROM 0x8000 /* Promiscuous Mode */ 117 #define LANCE_CSR15_DRCVBC 0x4000 /* Disable Receive Broadcast */ 118 #define LANCE_CSR15_DRCVPA 0x2000 /* Disable Receive Physical Address */ 119 #define LANCE_CSR15_DLNKTST 0x1000 /* Disable Link Status */ 120 #define LANCE_CSR15_DAPC 0x0800 /* Disable Automatic Polarity Correction */ 121 #define LANCE_CSR15_MENDECL 0x0400 /* MENDEC Loopback Mode */ 122 #define LANCE_CSR15_LRT 0x0200 /* Low Receive Threshold (T-MAU Mode) */ 123 #define LANCE_CSR15_TSEL 0x0200 /* Transmit Mode Select (AUI Mode) */ 124 /* 0x0100 Portsel[1] 125 * 0x0080 Portsel[0] */ 126 #define LANCE_CSR15_INTL 0x0040 /* Internal Loopback */ 127 #define LANCE_CSR15_DRTY 0x0020 /* Disable Retry */ 128 #define LANCE_CSR15_FCOLL 0x0010 /* Force Collision */ 129 #define LANCE_CSR15_DXMTFCS 0x0008 /* Disable Transmit CRC (FCS) */ 130 #define LANCE_CSR15_LOOP 0x0004 /* Loopback Enable */ 131 #define LANCE_CSR15_DTX 0x0002 /* Disable Transmit */ 132 #define LANCE_CSR15_DRX 0x0001 /* Disable Receiver */ 133