1 2 /* macros for 'mode' */ 3 #define EC_DISABLED 0x0 4 #define EC_SINK 0x1 5 #define EC_ENABLED 0x2 6 7 /* macros for 'flags' */ 8 #define ECF_EMPTY 0x000 9 #define ECF_PACK_SEND 0x001 10 #define ECF_PACK_RECV 0x002 11 #define ECF_SEND_AVAIL 0x004 12 #define ECF_READING 0x010 13 #define ECF_PROMISC 0x040 14 #define ECF_MULTI 0x080 15 #define ECF_BROAD 0x100 16 #define ECF_ENABLED 0x200 17 #define ECF_STOPPED 0x400 18 19 /* === macros for ether cards (our generalized version) === */ 20 #define EC_ISR_RINT 0x0001 21 #define EC_ISR_WINT 0x0002 22 #define EC_ISR_RERR 0x0010 23 #define EC_ISR_WERR 0x0020 24 #define EC_ISR_ERR 0x0040 25 #define EC_ISR_RST 0x0100 26 27 /* IOVEC */ 28 #define IOVEC_NR 16 29 typedef struct iovec_dat 30 { 31 iovec_s_t iod_iovec[IOVEC_NR]; 32 int iod_iovec_s; 33 endpoint_t iod_proc_nr; 34 cp_grant_id_t iod_grant; 35 vir_bytes iod_iovec_offset; 36 } iovec_dat_t; 37 38 /* ====== ethernet card info. ====== */ 39 typedef struct ether_card 40 { 41 /* ####### MINIX style ####### */ 42 char port_name[sizeof("lance#n")]; 43 int flags; 44 int mode; 45 int transfer_mode; 46 eth_stat_t eth_stat; 47 iovec_dat_t read_iovec; 48 iovec_dat_t write_iovec; 49 iovec_dat_t tmp_iovec; 50 vir_bytes write_s; 51 vir_bytes read_s; 52 int client; 53 message sendmsg; 54 55 /* ######## device info. ####### */ 56 port_t ec_port; 57 phys_bytes ec_linmem; 58 int ec_irq; 59 int ec_int_pending; 60 int ec_hook; 61 62 int ec_ramsize; 63 64 /* Addrassing */ 65 u16_t ec_memseg; 66 vir_bytes ec_memoff; 67 68 ether_addr_t mac_address; 69 } ether_card_t; 70 71 #define DEI_DEFAULT 0x8000 72 73 /* 74 * NOTE: Not all the CSRs are defined. Just the ones that were deemed 75 * necessary or potentially useful. 76 */ 77 78 /* Control and Status Register Addresses */ 79 #define LANCE_CSR0 0 /* Controller Status Register */ 80 #define LANCE_CSR1 1 /* Initialization Block Address (Lower) */ 81 #define LANCE_CSR2 2 /* Initialization Block Address (Upper) */ 82 #define LANCE_CSR3 3 /* Interrupt Masks and Deferral Control */ 83 #define LANCE_CSR4 4 /* Test and Features Control */ 84 #define LANCE_CSR5 5 /* Extended Control and Interrupt */ 85 #define LANCE_CSR8 8 /* Logical Address Filter 0 */ 86 #define LANCE_CSR9 9 /* Logical Address Filter 1 */ 87 #define LANCE_CSR10 10 /* Logical Address Filter 2 */ 88 #define LANCE_CSR11 11 /* Logical Address Filter 3 */ 89 #define LANCE_CSR15 15 /* Mode */ 90 #define LANCE_CSR88 88 /* Chip ID Register (Lower) */ 91 #define LANCE_CSR89 89 /* Chip ID Register (Upper) */ 92 93 /* Control and Status Register 0 (CSR0) */ 94 #define LANCE_CSR0_ERR 0x8000 /* Error Occurred */ 95 #define LANCE_CSR0_BABL 0x4000 /* Transmitter Timeout Error */ 96 #define LANCE_CSR0_CERR 0x2000 /* Collision Error */ 97 #define LANCE_CSR0_MISS 0x1000 /* Missed Frame */ 98 #define LANCE_CSR0_MERR 0x0800 /* Memory Error */ 99 #define LANCE_CSR0_RINT 0x0400 /* Receive Interrupt */ 100 #define LANCE_CSR0_TINT 0x0200 /* Transmit Interrupt */ 101 #define LANCE_CSR0_IDON 0x0100 /* Initialization Done */ 102 #define LANCE_CSR0_INTR 0x0080 /* Interrupt Flag */ 103 #define LANCE_CSR0_IENA 0x0040 /* Interrupt Enable */ 104 #define LANCE_CSR0_RXON 0x0020 /* Receive On */ 105 #define LANCE_CSR0_TXON 0x0010 /* Transmit On */ 106 #define LANCE_CSR0_TDMD 0x0008 /* Transmit Demand */ 107 #define LANCE_CSR0_STOP 0x0004 /* Stop */ 108 #define LANCE_CSR0_STRT 0x0002 /* Start */ 109 #define LANCE_CSR0_INIT 0x0001 /* Init */ 110 111 /* Control and Status Register 3 (CSR3) */ 112 /* 0x8000 Reserved */ 113 #define LANCE_CSR3_BABLM 0x4000 /* Babble Mask */ 114 /* 0x2000 Reserved */ 115 #define LANCE_CSR3_MISSM 0x1000 /* Missed Frame Mask */ 116 #define LANCE_CSR3_MERRM 0x0800 /* Memory Error Mask */ 117 #define LANCE_CSR3_RINTM 0x0400 /* Receive Interrupt Mask */ 118 #define LANCE_CSR3_TINTM 0x0200 /* Transmit Interrupt Mask */ 119 #define LANCE_CSR3_IDONM 0x0100 /* Initialization Done Mask */ 120 /* 0x0080 Reserved */ 121 #define LANCE_CSR3_DXSUFLO 0x0040 /* Disable Transmit Stop on Underflow */ 122 #define LANCE_CSR3_LAPPEN 0x0020 /* Look Ahead Packet Processing Enable */ 123 #define LANCE_CSR3_DXMT2PD 0x0010 /* Disable Transmit Two Part Deferral */ 124 #define LANCE_CSR3_EMBA 0x0008 /* Enable Modified Back-off Algorithm */ 125 #define LANCE_CSR3_BSWP 0x0004 /* Byte Swap */ 126 /* 0x0002 Reserved 127 * 0x0001 Reserved */ 128 129 /* Control and Status Register 4 (CSR4) */ 130 #define LANCE_CSR4_EN124 0x8000 /* Enable CSR124 Access */ 131 #define LANCE_CSR4_DMAPLUS 0x4000 /* Disable DMA Burst Transfer Counter */ 132 #define LANCE_CSR4_TIMER 0x2000 /* Enable Bus Activity Timer */ 133 #define LANCE_CSR4_DPOLL 0x1000 /* Disable Transmit Polling */ 134 #define LANCE_CSR4_APAD_XMT 0x0800 /* Auto Pad Transmit */ 135 #define LANCE_CSR4_ASTRP_RCV 0x0400 /* Auto Strip Receive */ 136 #define LANCE_CSR4_MFCO 0x0200 /* Missed Frame Counter Overflow */ 137 #define LANCE_CSR4_MFCOM 0x0100 /* Missed Frame Counter Overflow Mask */ 138 #define LANCE_CSR4_UINTCMD 0x0080 /* User Interrupt Command */ 139 #define LANCE_CSR4_UINT 0x0040 /* User Interrupt */ 140 #define LANCE_CSR4_RCVCCO 0x0020 /* Receive Collision Counter Overflow */ 141 #define LANCE_CSR4_RCVCCOM 0x0010 /* Receive Collision Counter Overflow 142 * Mask */ 143 #define LANCE_CSR4_TXSTRT 0x0008 /* Transmit Start */ 144 #define LANCE_CSR4_TXSTRTM 0x0004 /* Transmit Start Mask */ 145 #define LANCE_CSR4_JAB 0x0002 /* Jabber Error */ 146 #define LANCE_CSR4_JABM 0x0001 /* Jabber Error Mask */ 147 148 /* Control and Status Register 5 (CSR5) */ 149 #define LANCE_CSR5_TOKINTD 0x8000 /* Transmit OK Interrupt Disable */ 150 #define LANCE_CSR5_LINTEN 0x4000 /* Last Transmit Interrupt Enable */ 151 /* 0x2000 Reserved 152 * 0x1000 Reserved */ 153 #define LANCE_CSR5_SINT 0x0800 /* System Interrupt */ 154 #define LANCE_CSR5_SINTE 0x0400 /* System Interrupt Enable */ 155 #define LANCE_CSR5_SLPINT 0x0200 /* Sleep Interrupt */ 156 #define LANCE_CSR5_SLPINTE 0x0100 /* Sleep Interrupt Enable */ 157 #define LANCE_CSR5_EXDINT 0x0080 /* Excessive Deferral Interrupt */ 158 #define LANCE_CSR5_EXDINTE 0x0040 /* Excessive Deferral Interrupt Enable */ 159 #define LANCE_CSR5_MPPLBA 0x0020 /* Magic Packet Physical Logical Broadcast 160 * Accept */ 161 #define LANCE_CSR5_MPINT 0x0010 /* Magic Packet Interrupt */ 162 #define LANCE_CSR5_MPINTE 0x0008 /* Magic Packet Interrupt Enable */ 163 #define LANCE_CSR5_MPEN 0x0004 /* Magic Packet Enable */ 164 #define LANCE_CSR5_MPMODE 0x0002 /* Magic Packet Mode */ 165 #define LANCE_CSR5_SPND 0x0001 /* Suspend */ 166 167 /* Control and Status Register 15 (CSR15) */ 168 #define LANCE_CSR15_PROM 0x8000 /* Promiscuous Mode */ 169 #define LANCE_CSR15_DRCVBC 0x4000 /* Disable Receive Broadcast */ 170 #define LANCE_CSR15_DRCVPA 0x2000 /* Disable Receive Physical Address */ 171 #define LANCE_CSR15_DLNKTST 0x1000 /* Disable Link Status */ 172 #define LANCE_CSR15_DAPC 0x0800 /* Disable Automatic Polarity Correction */ 173 #define LANCE_CSR15_MENDECL 0x0400 /* MENDEC Loopback Mode */ 174 #define LANCE_CSR15_LRT 0x0200 /* Low Receive Threshold (T-MAU Mode) */ 175 #define LANCE_CSR15_TSEL 0x0200 /* Transmit Mode Select (AUI Mode) */ 176 /* 0x0100 Portsel[1] 177 * 0x0080 Portsel[0] */ 178 #define LANCE_CSR15_INTL 0x0040 /* Internal Loopback */ 179 #define LANCE_CSR15_DRTY 0x0020 /* Disable Retry */ 180 #define LANCE_CSR15_FCOLL 0x0010 /* Force Collision */ 181 #define LANCE_CSR15_DXMTFCS 0x0008 /* Disable Transmit CRC (FCS) */ 182 #define LANCE_CSR15_LOOP 0x0004 /* Loopback Enable */ 183 #define LANCE_CSR15_DTX 0x0002 /* Disable Transmit */ 184 #define LANCE_CSR15_DRX 0x0001 /* Disable Receiver */ 185