1 /* kernel headers */ 2 #include <minix/blockdriver.h> 3 #include <minix/com.h> 4 #include <minix/vm.h> 5 #include <minix/spin.h> 6 #include <minix/log.h> 7 #include <minix/mmio.h> 8 #include <minix/type.h> 9 #include <minix/board.h> 10 #include <sys/mman.h> 11 #include <sys/time.h> 12 13 /* usr headers */ 14 #include <assert.h> 15 #include <stdio.h> 16 #include <stdlib.h> 17 #include <stdarg.h> 18 #include <string.h> 19 #include <inttypes.h> 20 #include <limits.h> 21 #include <unistd.h> 22 23 /* local headers */ 24 #include "mmchost.h" 25 26 /* header imported from netbsd */ 27 #include "sdmmcreg.h" 28 #include "sdmmcreg.h" 29 #include "sdhcreg.h" 30 31 /* omap /hardware related */ 32 #include "omap_mmc.h" 33 34 #define USE_INTR 35 36 #ifdef USE_INTR 37 static int hook_id = 1; 38 #endif 39 40 #define USE_DMA 41 42 #define SANE_TIMEOUT 500000 /* 500 ms */ 43 44 struct omap_mmchs *mmchs; /* pointer to the current mmchs */ 45 46 struct omap_mmchs bone_sdcard = { 47 .io_base = 0, 48 .io_size = 0x2ff, 49 .hw_base = 0x48060000, 50 .irq_nr = 64, /* MMC/SD module 1 */ 51 .regs = ®s_v1, 52 }; 53 54 struct omap_mmchs bbxm_sdcard = { 55 .io_base = 0, 56 .io_size = 0x2ff, 57 .hw_base = 0x4809C000, 58 .irq_nr = 83, /* MMC/SD module 1 */ 59 .regs = ®s_v0, 60 }; 61 62 /* Integer divide x by y and ensure that the result z is 63 * such that x / z is smaller or equal y 64 */ 65 #define div_roundup(x, y) (((x)+((y)-1))/(y)) 66 67 /* 68 * Define a structure to be used for logging 69 */ 70 static struct log log = { 71 .name = "mmc_host_mmchs", 72 .log_level = LEVEL_INFO, 73 .log_func = default_log 74 }; 75 76 #define HSMMCSD_0_IN_FREQ 96000000 /* 96MHz */ 77 #define HSMMCSD_0_INIT_FREQ 400000 /* 400kHz */ 78 #define HSMMCSD_0_FREQ_25MHZ 25000000 /* 25MHz */ 79 #define HSMMCSD_0_FREQ_50MHZ 50000000 /* 50MHz */ 80 81 void 82 mmc_set32(vir_bytes reg, u32_t mask, u32_t value) 83 { 84 assert(reg >= 0 && reg <= mmchs->io_size); 85 set32(mmchs->io_base + reg, mask, value); 86 } 87 88 u32_t 89 mmc_read32(vir_bytes reg) 90 { 91 assert(reg >= 0 && reg <= mmchs->io_size); 92 return read32(mmchs->io_base + reg); 93 } 94 95 void 96 mmc_write32(vir_bytes reg, u32_t value) 97 { 98 assert(reg >= 0 && reg <= mmchs->io_size); 99 write32(mmchs->io_base + reg, value); 100 } 101 102 void 103 mmchs_set_bus_freq(u32_t freq) 104 { 105 u32_t freq_in = HSMMCSD_0_IN_FREQ; 106 u32_t freq_out = freq; 107 108 /* Calculate and program the divisor */ 109 u32_t clkd = div_roundup(freq_in, freq_out); 110 clkd = (clkd < 2) ? 2 : clkd; 111 clkd = (clkd > 1023) ? 1023 : clkd; 112 113 log_debug(&log, "Setting divider to %d\n", clkd); 114 mmc_set32(mmchs->regs->SYSCTL, MMCHS_SD_SYSCTL_CLKD, (clkd << 6)); 115 } 116 117 /* 118 * Initialize the MMC controller given a certain 119 * instance. this driver only handles a single 120 * mmchs controller at a given time. 121 */ 122 int 123 mmchs_init(uint32_t instance) 124 { 125 126 uint32_t value; 127 value = 0; 128 struct minix_mem_range mr; 129 spin_t spin; 130 assert(mmchs); 131 132 mr.mr_base = mmchs->hw_base; 133 mr.mr_limit = mmchs->hw_base + mmchs->io_size; 134 135 /* grant ourself rights to map the register memory */ 136 if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) { 137 panic("Unable to request permission to map memory"); 138 } 139 140 /* Set the base address to use */ 141 mmchs->io_base = 142 (uint32_t) vm_map_phys(SELF, (void *) mmchs->hw_base, 143 mmchs->io_size); 144 145 if (mmchs->io_base == (uint32_t) MAP_FAILED) 146 panic("Unable to map MMC memory"); 147 148 /* Soft reset of the controller. This section is documented in the TRM 149 */ 150 151 /* Write 1 to sysconfig[0] to trigger a reset */ 152 mmc_set32(mmchs->regs->SYSCONFIG, MMCHS_SD_SYSCONFIG_SOFTRESET, 153 MMCHS_SD_SYSCONFIG_SOFTRESET); 154 155 /* Read sysstatus to know when it's done */ 156 157 spin_init(&spin, SANE_TIMEOUT); 158 while (!(mmc_read32(mmchs->regs->SYSSTATUS) 159 & MMCHS_SD_SYSSTATUS_RESETDONE)) { 160 if (spin_check(&spin) == FALSE) { 161 log_warn(&log, "mmc init timeout\n"); 162 return 1; 163 } 164 } 165 166 /* Set SD default capabilities */ 167 mmc_set32(mmchs->regs->CAPA, MMCHS_SD_CAPA_VS_MASK, 168 MMCHS_SD_CAPA_VS18 | MMCHS_SD_CAPA_VS30); 169 170 /* TRM mentions MMCHS_SD_CUR_CAPA but does not describe how to limit 171 * the current */ 172 173 uint32_t mask = 174 MMCHS_SD_SYSCONFIG_AUTOIDLE | MMCHS_SD_SYSCONFIG_ENAWAKEUP | 175 MMCHS_SD_SYSCONFIG_STANDBYMODE | MMCHS_SD_SYSCONFIG_CLOCKACTIVITY | 176 MMCHS_SD_SYSCONFIG_SIDLEMODE; 177 178 /* Automatic clock gating strategy */ 179 value = MMCHS_SD_SYSCONFIG_AUTOIDLE_EN; 180 /* Enable wake-up capability */ 181 value |= MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN; 182 /* Smart-idle */ 183 value |= MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE; 184 /* Both the interface and functional can be switched off */ 185 value |= MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF; 186 /* Go into wake-up mode when possible */ 187 value |= MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL; 188 189 /* 190 * wake-up configuration 191 */ 192 mmc_set32(mmchs->regs->SYSCONFIG, mask, value); 193 194 /* Wake-up on sd interrupt for SDIO */ 195 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_IWE, MMCHS_SD_HCTL_IWE_EN); 196 197 /* 198 * MMC host and bus configuration 199 */ 200 201 /* Configure data and command transfer (1 bit mode) switching to 202 * higher bit modes happens after a card is detected */ 203 mmc_set32(mmchs->regs->CON, MMCHS_SD_CON_DW8, MMCHS_SD_CON_DW8_1BIT); 204 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_DTW, 205 MMCHS_SD_HCTL_DTW_1BIT); 206 207 /* Configure card voltage to 3.0 volt */ 208 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_SDVS, 209 MMCHS_SD_HCTL_SDVS_VS30); 210 211 /* Power on the host controller and wait for the 212 * MMCHS_SD_HCTL_SDBP_POWER_ON to be set */ 213 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_SDBP, 214 MMCHS_SD_HCTL_SDBP_ON); 215 216 spin_init(&spin, SANE_TIMEOUT); 217 while ((mmc_read32(mmchs->regs->HCTL) & MMCHS_SD_HCTL_SDBP) 218 != MMCHS_SD_HCTL_SDBP_ON) { 219 if (spin_check(&spin) == FALSE) { 220 log_warn(&log, "mmc init timeout SDBP not set\n"); 221 return 1; 222 } 223 } 224 225 /* Enable internal clock and clock to the card */ 226 mmc_set32(mmchs->regs->SYSCTL, MMCHS_SD_SYSCTL_ICE, 227 MMCHS_SD_SYSCTL_ICE_EN); 228 229 mmchs_set_bus_freq(HSMMCSD_0_INIT_FREQ); 230 231 mmc_set32(mmchs->regs->SYSCTL, MMCHS_SD_SYSCTL_CEN, 232 MMCHS_SD_SYSCTL_CEN_EN); 233 234 spin_init(&spin, SANE_TIMEOUT); 235 while ((mmc_read32(mmchs->regs->SYSCTL) & MMCHS_SD_SYSCTL_ICS) 236 != MMCHS_SD_SYSCTL_ICS_STABLE) { 237 if (spin_check(&spin) == FALSE) { 238 log_warn(&log, "clock not stable\n"); 239 return 1; 240 } 241 } 242 243 /* 244 * See spruh73e page 3576 Card Detection, Identification, and Selection 245 */ 246 247 /* Enable command interrupt */ 248 mmc_set32(mmchs->regs->IE, MMCHS_SD_IE_CC_ENABLE, 249 MMCHS_SD_IE_CC_ENABLE_ENABLE); 250 /* Enable transfer complete interrupt */ 251 mmc_set32(mmchs->regs->IE, MMCHS_SD_IE_TC_ENABLE, 252 MMCHS_SD_IE_TC_ENABLE_ENABLE); 253 254 /* enable error interrupts */ 255 mmc_set32(mmchs->regs->IE, MMCHS_SD_IE_ERROR_MASK, 0xffffffffu); 256 257 /* clear the error interrupts */ 258 mmc_set32(mmchs->regs->SD_STAT, MMCHS_SD_STAT_ERROR_MASK, 0xffffffffu); 259 260 /* send a init signal to the host controller. This does not actually 261 * send a command to a card manner */ 262 mmc_set32(mmchs->regs->CON, MMCHS_SD_CON_INIT, MMCHS_SD_CON_INIT_INIT); 263 /* command 0 , type other commands not response etc) */ 264 mmc_write32(mmchs->regs->CMD, 0x00); 265 266 spin_init(&spin, SANE_TIMEOUT); 267 while ((mmc_read32(mmchs->regs->SD_STAT) & MMCHS_SD_STAT_CC) 268 != MMCHS_SD_STAT_CC_RAISED) { 269 if (mmc_read32(mmchs->regs->SD_STAT) & 0x8000) { 270 log_warn(&log, "%s, error stat %x\n", 271 __FUNCTION__, mmc_read32(mmchs->regs->SD_STAT)); 272 return 1; 273 } 274 275 if (spin_check(&spin) == FALSE) { 276 log_warn(&log, "Interrupt not raised during init\n"); 277 return 1; 278 } 279 } 280 281 /* clear the cc interrupt status */ 282 mmc_set32(mmchs->regs->SD_STAT, MMCHS_SD_IE_CC_ENABLE, 283 MMCHS_SD_IE_CC_ENABLE_ENABLE); 284 285 /* 286 * Set Set SD_CON[1] INIT bit to 0x0 to end the initialization sequence 287 */ 288 mmc_set32(mmchs->regs->CON, MMCHS_SD_CON_INIT, 289 MMCHS_SD_CON_INIT_NOINIT); 290 291 /* Set timeout */ 292 mmc_set32(mmchs->regs->SYSCTL, MMCHS_SD_SYSCTL_DTO, 293 MMCHS_SD_SYSCTL_DTO_2POW27); 294 295 /* Clean the MMCHS_SD_STAT register */ 296 mmc_write32(mmchs->regs->SD_STAT, 0xffffffffu); 297 #ifdef USE_INTR 298 hook_id = 1; 299 if (sys_irqsetpolicy(mmchs->irq_nr, 0, &hook_id) != OK) { 300 log_warn(&log, "mmc: couldn't set IRQ policy %d\n", 301 mmchs->irq_nr); 302 return 1; 303 } 304 /* enable signaling from MMC controller towards interrupt controller */ 305 mmc_write32(mmchs->regs->ISE, 0xffffffffu); 306 #endif 307 308 return 0; 309 } 310 311 void 312 intr_deassert(int mask) 313 { 314 if (mmc_read32(mmchs->regs->SD_STAT) & 0x8000) { 315 log_warn(&log, "%s, error stat %08x\n", __FUNCTION__, 316 mmc_read32(mmchs->regs->SD_STAT)); 317 mmc_set32(mmchs->regs->SD_STAT, MMCHS_SD_STAT_ERROR_MASK, 318 0xffffffffu); 319 } else { 320 mmc_write32(mmchs->regs->SD_STAT, mask); 321 } 322 } 323 324 /* pointer to the data to transfer used in bwr and brr */ 325 unsigned char *io_data; 326 int io_len; 327 328 void 329 handle_bwr() 330 { 331 /* handle buffer write ready interrupts. These happen in a non 332 * predictable way (eg. we send a request but don't know if we are 333 * first doing to get a request completed before we are allowed to 334 * send the data to the hardware or not */ 335 uint32_t value; 336 uint32_t count; 337 assert(mmc_read32(mmchs->regs->PSTATE) & MMCHS_SD_PSTATE_BWE_EN); 338 assert(io_data != NULL); 339 340 for (count = 0; count < io_len; count += 4) { 341 while (!(mmc_read32(mmchs->regs-> 342 PSTATE) & MMCHS_SD_PSTATE_BWE_EN)) { 343 log_warn(&log, 344 "Error expected Buffer to be write enabled(%d)\n", 345 count); 346 } 347 *((char *) &value) = io_data[count]; 348 *((char *) &value + 1) = io_data[count + 1]; 349 *((char *) &value + 2) = io_data[count + 2]; 350 *((char *) &value + 3) = io_data[count + 3]; 351 mmc_write32(mmchs->regs->DATA, value); 352 } 353 intr_deassert(MMCHS_SD_IE_BWR_ENABLE); 354 /* expect buffer to be write enabled */ 355 io_data = NULL; 356 } 357 358 void 359 handle_brr() 360 { 361 /* handle buffer read ready interrupts. genrally these happen afther 362 * the data is read from the sd card. */ 363 364 uint32_t value; 365 uint32_t count; 366 367 /* Problem BRE should be true */ 368 assert(mmc_read32(mmchs->regs->PSTATE) & MMCHS_SD_PSTATE_BRE_EN); 369 370 assert(io_data != NULL); 371 372 for (count = 0; count < io_len; count += 4) { 373 value = mmc_read32(mmchs->regs->DATA); 374 io_data[count] = *((char *) &value); 375 io_data[count + 1] = *((char *) &value + 1); 376 io_data[count + 2] = *((char *) &value + 2); 377 io_data[count + 3] = *((char *) &value + 3); 378 } 379 /* clear bbr interrupt */ 380 intr_deassert(MMCHS_SD_IE_BRR_ENABLE_ENABLE); 381 io_data = NULL; 382 } 383 384 static void 385 mmchs_hw_intr(unsigned int irqs) 386 { 387 log_warn(&log, "Hardware interrupt left over (0x%08lx)\n", 388 mmc_read32(mmchs->regs->SD_STAT)); 389 390 #ifdef USE_INTR 391 if (sys_irqenable(&hook_id) != OK) 392 printf("couldn't re-enable interrupt \n"); 393 #endif 394 /* Leftover interrupt(s) received; ack it/them. */ 395 } 396 397 /*===========================================================================* 398 * w_intr_wait * 399 *===========================================================================*/ 400 static int 401 intr_wait(int mask) 402 { 403 long v; 404 #ifdef USE_INTR 405 if (sys_irqenable(&hook_id) != OK) 406 printf("Failed to enable irqenable irq\n"); 407 /* Wait for a task completion interrupt. */ 408 message m; 409 int ipc_status; 410 int ticks = SANE_TIMEOUT * sys_hz() / 1000000; 411 412 if (ticks <= 0) 413 ticks = 1; 414 while (1) { 415 int rr; 416 sys_setalarm(ticks, 0); 417 if ((rr = driver_receive(ANY, &m, &ipc_status)) != OK) { 418 panic("driver_receive failed: %d", rr); 419 }; 420 if (is_ipc_notify(ipc_status)) { 421 switch (_ENDPOINT_P(m.m_source)) { 422 case CLOCK: 423 /* Timeout. */ 424 log_warn(&log, "TIMEOUT\n"); 425 return 1; 426 break; 427 case HARDWARE: 428 while ((v = 429 mmc_read32(mmchs->regs->SD_STAT)) != 430 0) { 431 if (v & MMCHS_SD_IE_BWR_ENABLE) { 432 handle_bwr(); 433 continue; 434 } 435 if (v & MMCHS_SD_IE_BRR_ENABLE) { 436 handle_brr(); 437 continue; 438 } 439 440 if (v & mask) { 441 /* this is the normal return 442 * path, the mask given 443 * matches the pending 444 * interrupt. cancel the alarm 445 * and return */ 446 sys_setalarm(0, 0); 447 return 0; 448 } else if (v & (1 << 15)) { 449 return 1; /* error */ 450 } 451 452 log_warn(&log, 453 "unexpected HW interrupt 0x%08x mask 0X%08x\n", 454 v, mask); 455 if (sys_irqenable(&hook_id) != OK) 456 printf 457 ("Failed to re-enable irqenable irq\n"); 458 } 459 /* if we end up here re-enable interrupts for 460 * the next round */ 461 if (sys_irqenable(&hook_id) != OK) 462 printf 463 ("Failed to re-enable irqenable irq\n"); 464 break; 465 default: 466 /* 467 * unhandled notify message. Queue it and 468 * handle it in the blockdriver loop. 469 */ 470 blockdriver_mq_queue(&m, ipc_status); 471 } 472 } else { 473 /* 474 * unhandled message. Queue it and handle it in the 475 * blockdriver loop. 476 */ 477 blockdriver_mq_queue(&m, ipc_status); 478 } 479 } 480 sys_setalarm(0, 0); /* cancel the alarm */ 481 482 #else 483 spin_t spin; 484 spin_init(&spin, SANE_TIMEOUT); 485 /* Wait for completion */ 486 int counter = 0; 487 while (1 == 1) { 488 counter++; 489 v = mmc_read32(mmchs->regs->SD_STAT); 490 if (spin_check(&spin) == FALSE) { 491 log_warn(&log, 492 "Timeout waiting for interrupt (%d) value 0x%08x mask 0x%08x\n", 493 counter, v, mask); 494 return 1; 495 } 496 if (v & MMCHS_SD_IE_BWR_ENABLE) { 497 handle_bwr(); 498 continue; 499 } 500 if (v & MMCHS_SD_IE_BRR_ENABLE) { 501 handle_brr(); 502 continue; 503 } 504 if (v & mask) { 505 return 0; 506 } else if (v & 0xFF00) { 507 log_debug(&log, 508 "unexpected HW interrupt (%d) 0x%08x mask 0x%08x\n", 509 v, mask); 510 return 1; 511 } 512 } 513 return 1; /* unreached */ 514 #endif /* USE_INTR */ 515 } 516 517 int 518 mmchs_send_cmd(uint32_t command, uint32_t arg) 519 { 520 521 /* Read current interrupt status and fail it an interrupt is already 522 * asserted */ 523 assert(mmc_read32(mmchs->regs->SD_STAT) == 0); 524 525 /* Set arguments */ 526 mmc_write32(mmchs->regs->ARG, arg); 527 /* Set command */ 528 mmc_set32(mmchs->regs->CMD, MMCHS_SD_CMD_MASK, command); 529 530 if (intr_wait(MMCHS_SD_STAT_CC)) { 531 uint32_t v = mmc_read32(mmchs->regs->SD_STAT); 532 intr_deassert(MMCHS_SD_STAT_CC); 533 log_warn(&log, "Failure waiting for interrupt 0x%lx\n", v); 534 return 1; 535 } 536 intr_deassert(MMCHS_SD_STAT_CC); 537 538 if ((command & MMCHS_SD_CMD_RSP_TYPE) == 539 MMCHS_SD_CMD_RSP_TYPE_48B_BUSY) { 540 /* 541 * Command with busy response *CAN* also set the TC bit if they exit busy 542 */ 543 if ((mmc_read32(mmchs->regs->SD_STAT) 544 & MMCHS_SD_IE_TC_ENABLE_ENABLE) == 0) { 545 log_warn(&log, "TC should be raised\n"); 546 } 547 intr_deassert(MMCHS_SD_STAT_TC); 548 } 549 return 0; 550 } 551 552 int 553 mmc_send_cmd(struct mmc_command *c) 554 { 555 556 /* convert the command to a hsmmc command */ 557 int ret; 558 uint32_t cmd, arg; 559 cmd = MMCHS_SD_CMD_INDX_CMD(c->cmd); 560 arg = c->args; 561 assert(c->data_type == DATA_NONE || c->data_type == DATA_READ 562 || c->data_type == DATA_WRITE); 563 564 switch (c->resp_type) { 565 case RESP_LEN_48_CHK_BUSY: 566 cmd |= MMCHS_SD_CMD_RSP_TYPE_48B_BUSY; 567 break; 568 case RESP_LEN_48: 569 cmd |= MMCHS_SD_CMD_RSP_TYPE_48B; 570 break; 571 case RESP_LEN_136: 572 cmd |= MMCHS_SD_CMD_RSP_TYPE_136B; 573 break; 574 case RESP_NO_RESPONSE: 575 cmd |= MMCHS_SD_CMD_RSP_TYPE_NO_RESP; 576 break; 577 default: 578 return 1; 579 } 580 581 /* read single block */ 582 if (c->data_type == DATA_READ) { 583 cmd |= MMCHS_SD_CMD_DP_DATA; /* Command with data transfer */ 584 cmd |= MMCHS_SD_CMD_MSBS_SINGLE; /* single block */ 585 cmd |= MMCHS_SD_CMD_DDIR_READ; /* read data from card */ 586 } 587 588 /* write single block */ 589 if (c->data_type == DATA_WRITE) { 590 cmd |= MMCHS_SD_CMD_DP_DATA; /* Command with data transfer */ 591 cmd |= MMCHS_SD_CMD_MSBS_SINGLE; /* single block */ 592 cmd |= MMCHS_SD_CMD_DDIR_WRITE; /* write to the card */ 593 } 594 595 /* check we are in a sane state */ 596 if ((mmc_read32(mmchs->regs->SD_STAT) & 0xffffu)) { 597 log_warn(&log, "%s, interrupt already raised stat %08x\n", 598 __FUNCTION__, mmc_read32(mmchs->regs->SD_STAT)); 599 mmc_write32(mmchs->regs->SD_STAT, MMCHS_SD_IE_CC_ENABLE_CLEAR); 600 } 601 602 if (cmd & MMCHS_SD_CMD_DP_DATA) { 603 if (cmd & MMCHS_SD_CMD_DDIR_READ) { 604 /* if we are going to read enable the buffer ready 605 * interrupt */ 606 mmc_set32(mmchs->regs->IE, 607 MMCHS_SD_IE_BRR_ENABLE, 608 MMCHS_SD_IE_BRR_ENABLE_ENABLE); 609 } else { 610 mmc_set32(mmchs->regs->IE, 611 MMCHS_SD_IE_BWR_ENABLE, 612 MMCHS_SD_IE_BWR_ENABLE_ENABLE); 613 } 614 io_data = c->data; 615 io_len = c->data_len; 616 assert(io_len <= 0xFFF); /* only 12 bits */ 617 assert(io_data != NULL); 618 mmc_set32(mmchs->regs->BLK, MMCHS_SD_BLK_BLEN, io_len); 619 } 620 621 ret = mmchs_send_cmd(cmd, arg); 622 623 if (cmd & MMCHS_SD_CMD_DP_DATA) { 624 assert(c->data_len); 625 if (cmd & MMCHS_SD_CMD_DDIR_READ) { 626 /* Wait for TC */ 627 if (intr_wait(MMCHS_SD_IE_TC_ENABLE_ENABLE)) { 628 intr_deassert(MMCHS_SD_IE_TC_ENABLE_ENABLE); 629 log_warn(&log, 630 "(Read) Timeout waiting for interrupt\n"); 631 return 1; 632 } 633 634 mmc_write32(mmchs->regs->SD_STAT, 635 MMCHS_SD_IE_TC_ENABLE_CLEAR); 636 637 /* disable the bbr interrupt */ 638 mmc_set32(mmchs->regs->IE, 639 MMCHS_SD_IE_BRR_ENABLE, 640 MMCHS_SD_IE_BRR_ENABLE_DISABLE); 641 } else { 642 /* Wait for TC */ 643 if (intr_wait(MMCHS_SD_IE_TC_ENABLE_ENABLE)) { 644 intr_deassert(MMCHS_SD_IE_TC_ENABLE_CLEAR); 645 log_warn(&log, 646 "(Write) Timeout waiting for transfer complete\n"); 647 return 1; 648 } 649 intr_deassert(MMCHS_SD_IE_TC_ENABLE_CLEAR); 650 651 mmc_set32(mmchs->regs->IE, 652 MMCHS_SD_IE_BWR_ENABLE, 653 MMCHS_SD_IE_BWR_ENABLE_DISABLE); 654 655 } 656 } 657 658 /* copy response into cmd->resp */ 659 switch (c->resp_type) { 660 case RESP_LEN_48_CHK_BUSY: 661 case RESP_LEN_48: 662 c->resp[0] = mmc_read32(mmchs->regs->RSP10); 663 break; 664 case RESP_LEN_136: 665 c->resp[0] = mmc_read32(mmchs->regs->RSP10); 666 c->resp[1] = mmc_read32(mmchs->regs->RSP32); 667 c->resp[2] = mmc_read32(mmchs->regs->RSP54); 668 c->resp[3] = mmc_read32(mmchs->regs->RSP76); 669 break; 670 case RESP_NO_RESPONSE: 671 break; 672 default: 673 return 1; 674 } 675 676 return ret; 677 } 678 679 int 680 mmc_send_app_cmd(struct sd_card_regs *card, struct mmc_command *c) 681 { 682 struct mmc_command command; 683 command.cmd = MMC_APP_CMD; 684 command.resp_type = RESP_LEN_48; 685 command.data_type = DATA_NONE; 686 command.args = MMC_ARG_RCA(card->rca); 687 if (mmc_send_cmd(&command)) { 688 return 1; 689 } 690 return mmc_send_cmd(c); 691 } 692 693 int 694 card_goto_idle_state() 695 { 696 struct mmc_command command; 697 command.cmd = MMC_GO_IDLE_STATE; 698 command.resp_type = RESP_NO_RESPONSE; 699 command.data_type = DATA_NONE; 700 command.args = 0x00; 701 if (mmc_send_cmd(&command)) { 702 // Failure 703 return 1; 704 } 705 return 0; 706 } 707 708 int 709 card_identification() 710 { 711 struct mmc_command command; 712 command.cmd = SD_SEND_IF_COND; /* Send CMD8 */ 713 command.resp_type = RESP_LEN_48; 714 command.data_type = DATA_NONE; 715 command.args = MMCHS_SD_ARG_CMD8_VHS | MMCHS_SD_ARG_CMD8_CHECK_PATTERN; 716 717 if (mmc_send_cmd(&command)) { 718 /* We currently only support 2.0, and 1.0 won't respond to 719 * this request */ 720 log_warn(&log, "%s, non SDHC card inserted\n", __FUNCTION__); 721 return 1; 722 } 723 724 if (!(command.resp[0] 725 == (MMCHS_SD_ARG_CMD8_VHS | MMCHS_SD_ARG_CMD8_CHECK_PATTERN))) { 726 log_warn(&log, "%s, check pattern check failed %08x\n", 727 __FUNCTION__, command.resp[0]); 728 return 1; 729 } 730 return 0; 731 } 732 733 int 734 card_query_voltage_and_type(struct sd_card_regs *card) 735 { 736 struct mmc_command command; 737 spin_t spin; 738 739 command.cmd = SD_APP_OP_COND; 740 command.resp_type = RESP_LEN_48; 741 command.data_type = DATA_NONE; 742 743 /* 0x1 << 30 == send HCS (Host capacity support) and get OCR register */ 744 command.args = 745 MMC_OCR_3_3V_3_4V | MMC_OCR_3_2V_3_3V | MMC_OCR_3_1V_3_2V | 746 MMC_OCR_3_0V_3_1V | MMC_OCR_2_9V_3_0V | MMC_OCR_2_8V_2_9V | 747 MMC_OCR_2_7V_2_8V; 748 command.args |= MMC_OCR_HCS; /* RCA=0000 */ 749 750 if (mmc_send_app_cmd(card, &command)) { 751 return 1; 752 } 753 754 spin_init(&spin, SANE_TIMEOUT); 755 while (!(command.resp[0] & MMC_OCR_MEM_READY)) { 756 757 /* Send ADMD41 */ 758 /* 0x1 << 30 == send HCS (Host capacity support) and get OCR 759 * register */ 760 command.cmd = SD_APP_OP_COND; 761 command.resp_type = RESP_LEN_48; 762 command.data_type = DATA_NONE; 763 /* 0x1 << 30 == send HCS (Host capacity support) */ 764 command.args = MMC_OCR_3_3V_3_4V | MMC_OCR_3_2V_3_3V 765 | MMC_OCR_3_1V_3_2V | MMC_OCR_3_0V_3_1V | MMC_OCR_2_9V_3_0V 766 | MMC_OCR_2_8V_2_9V | MMC_OCR_2_7V_2_8V; 767 command.args |= MMC_OCR_HCS; /* RCA=0000 */ 768 769 if (mmc_send_app_cmd(card, &command)) { 770 return 1; 771 } 772 773 /* if bit 31 is set the response is valid */ 774 if ((command.resp[0] & MMC_OCR_MEM_READY)) { 775 break; 776 } 777 if (spin_check(&spin) == FALSE) { 778 log_warn(&log, "TIMEOUT waiting for the SD card\n"); 779 } 780 781 } 782 card->ocr = command.resp[3]; 783 return 0; 784 } 785 786 int 787 card_identify(struct sd_card_regs *card) 788 { 789 struct mmc_command command; 790 /* Send cmd 2 (all_send_cid) and expect 136 bits response */ 791 command.cmd = MMC_ALL_SEND_CID; 792 command.resp_type = RESP_LEN_136; 793 command.data_type = DATA_NONE; 794 command.args = MMC_ARG_RCA(0x0); /* RCA=0000 */ 795 796 if (mmc_send_cmd(&command)) { 797 return 1; 798 } 799 800 card->cid[0] = command.resp[0]; 801 card->cid[1] = command.resp[1]; 802 card->cid[2] = command.resp[2]; 803 card->cid[3] = command.resp[3]; 804 805 command.cmd = MMC_SET_RELATIVE_ADDR; 806 command.resp_type = RESP_LEN_48; 807 command.data_type = DATA_NONE; 808 command.args = 0x0; /* RCA=0000 */ 809 810 /* R6 response */ 811 if (mmc_send_cmd(&command)) { 812 return 1; 813 } 814 815 card->rca = SD_R6_RCA(command.resp); 816 /* MMHCS only supports a single card so sending MMCHS_SD_CMD_CMD2 is 817 * useless Still we should make it possible in the API to support 818 * multiple cards */ 819 820 return 0; 821 } 822 823 int 824 card_csd(struct sd_card_regs *card) 825 { 826 /* Read the Card Specific Data register */ 827 struct mmc_command command; 828 829 /* send_csd -> r2 response */ 830 command.cmd = MMC_SEND_CSD; 831 command.resp_type = RESP_LEN_136; 832 command.data_type = DATA_NONE; 833 command.args = MMC_ARG_RCA(card->rca); /* card rca */ 834 835 if (mmc_send_cmd(&command)) { 836 return 1; 837 } 838 839 card->csd[0] = command.resp[0]; 840 card->csd[1] = command.resp[1]; 841 card->csd[2] = command.resp[2]; 842 card->csd[3] = command.resp[3]; 843 844 log_trace(&log, "CSD version %d\n", SD_CSD_CSDVER(card->csd)); 845 if (SD_CSD_CSDVER(card->csd) != SD_CSD_CSDVER_2_0) { 846 log_warn(&log, "Version 2.0 of CSD register expected\n"); 847 return 1; 848 } 849 850 return 0; 851 } 852 853 int 854 select_card(struct sd_card_regs *card) 855 { 856 struct mmc_command command; 857 858 command.cmd = MMC_SELECT_CARD; 859 command.resp_type = RESP_LEN_48_CHK_BUSY; 860 command.data_type = DATA_NONE; 861 command.args = MMC_ARG_RCA(card->rca); /* card rca */ 862 863 if (mmc_send_cmd(&command)) { 864 return 1; 865 } 866 return 0; 867 } 868 869 int 870 card_scr(struct sd_card_regs *card) 871 { 872 uint8_t buffer[8]; /* 64 bits */ 873 uint8_t *p; 874 int c; 875 /* the SD CARD configuration register. This is an additional register 876 * next to the Card Specific register containing additional data we 877 * need */ 878 struct mmc_command command; 879 880 log_trace(&log, "Read card scr\n"); 881 /* send_csd -> r2 response */ 882 command.cmd = SD_APP_SEND_SCR; 883 command.resp_type = RESP_LEN_48; 884 command.data_type = DATA_READ; 885 command.args = 0xaaaaaaaa; 886 command.data = buffer; 887 command.data_len = 8; 888 889 if (mmc_send_app_cmd(card, &command)) { 890 return 1; 891 } 892 893 p = (uint8_t *) card->scr; 894 895 /* copy the data to card->scr */ 896 for (c = 7; c >= 0; c--) { 897 *p++ = buffer[c]; 898 } 899 900 if (!SCR_SD_BUS_WIDTHS(card->scr) & SCR_SD_BUS_WIDTHS_4BIT) { 901 /* it would be very weird not to support 4 bits access */ 902 log_warn(&log, "4 bit access not supported\n"); 903 } 904 905 log_trace(&log, "1 bit bus width %ssupported\n", 906 (SCR_SD_BUS_WIDTHS(card->scr) & SCR_SD_BUS_WIDTHS_1BIT) ? "" : 907 "un"); 908 log_trace(&log, "4 bit bus width %ssupported\n", 909 (SCR_SD_BUS_WIDTHS(card->scr) & SCR_SD_BUS_WIDTHS_4BIT) ? "" : 910 "un"); 911 912 return 0; 913 } 914 915 int 916 enable_4bit_mode(struct sd_card_regs *card) 917 { 918 struct mmc_command command; 919 920 if (SCR_SD_BUS_WIDTHS(card->scr) & SCR_SD_BUS_WIDTHS_4BIT) { 921 /* set transfer width */ 922 command.cmd = SD_APP_SET_BUS_WIDTH; 923 command.resp_type = RESP_LEN_48; 924 command.data_type = DATA_NONE; 925 command.args = 2; /* 4 bits */ 926 927 if (mmc_send_app_cmd(card, &command)) { 928 log_warn(&log, 929 "SD-card does not support 4 bit transfer\n"); 930 return 1; 931 } 932 /* now configure the controller to use 4 bit access */ 933 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_DTW, 934 MMCHS_SD_HCTL_DTW_4BIT); 935 return 0; 936 } 937 return 1; /* expect 4 bits mode to work so having a card 938 * that doesn't support 4 bits mode */ 939 } 940 941 void 942 dump_char(char *out, char in) 943 { 944 int i; 945 memset(out, 0, 9); 946 for (i = 0; i < 8; i++) { 947 out[i] = ((in >> i) & 0x1) ? '1' : '0'; 948 } 949 950 } 951 952 void 953 dump(uint8_t * data, int len) 954 { 955 int c; 956 char digit[4][9]; 957 char *p = data; 958 959 for (c = 0; c < len;) { 960 memset(digit, 0, sizeof(digit)); 961 if (c++ < len) 962 dump_char(digit[0], *data++); 963 if (c++ < len) 964 dump_char(digit[1], *data++); 965 if (c++ < len) 966 dump_char(digit[2], *data++); 967 if (c++ < len) 968 dump_char(digit[3], *data++); 969 printf("%x %s %s %s %s\n", c, digit[0], digit[1], digit[2], 970 digit[3]); 971 } 972 } 973 974 void 975 mmc_switch(int function, int value, uint8_t * data) 976 { 977 struct mmc_command command; 978 979 /* function index */ 980 int findex, fshift; 981 findex = function - 1; 982 fshift = findex << 2; /* bits used per function */ 983 984 command.cmd = MMC_SWITCH; 985 command.resp_type = RESP_LEN_48; 986 command.data_type = DATA_READ; 987 command.data = data; 988 command.data_len = 64; 989 command.args = (1 << 31) | (0x00ffffff & ~(0xf << fshift)); 990 command.args |= (value << fshift); 991 if (mmc_send_cmd(&command)) { 992 log_warn(&log, "Failed to set device in high speed mode\n"); 993 return; 994 } 995 // dump(data,64); 996 } 997 998 int 999 enable_high_speed_mode(struct sd_card_regs *card) 1000 { 1001 /* MMC cards using version 4.0 or higher of the specs can work at 1002 * higher bus rates. After setting the bus width one can send the 1003 * HS_TIMING command to set the card in high speed mode after witch 1004 * one can higher up the frequency */ 1005 1006 uint8_t buffer[64]; /* 512 bits */ 1007 log_info(&log, "Enabling high speed mode\n"); 1008 #if 0 1009 Doesnt currently work 1010 if (SCR_SD_SPEC(&card->scr[0]) >= SCR_SD_SPEC_VER_1_10) 1011 { 1012 mmc_switch(1, 1, buffer); 1013 } 1014 #endif 1015 1016 if (SD_CSD_SPEED(card->csd) == SD_CSD_SPEED_25_MHZ) { 1017 log_trace(&log, "Using 25MHz clock\n"); 1018 mmchs_set_bus_freq(HSMMCSD_0_FREQ_25MHZ); 1019 } else if (SD_CSD_SPEED(card->csd) == SD_CSD_SPEED_50_MHZ) { 1020 log_trace(&log, "Using 50MHz clock\n"); 1021 mmchs_set_bus_freq(HSMMCSD_0_FREQ_50MHZ); 1022 } else { 1023 log_warn(&log, "Unknown speed 0x%x in CSD register\n", 1024 SD_CSD_SPEED(card->csd)); 1025 } 1026 1027 return 0; 1028 } 1029 1030 int 1031 read_single_block(struct sd_card_regs *card, 1032 uint32_t blknr, unsigned char *buf) 1033 { 1034 struct mmc_command command; 1035 1036 command.cmd = MMC_READ_BLOCK_SINGLE; 1037 command.args = blknr; 1038 command.resp_type = RESP_LEN_48; 1039 command.data_type = DATA_READ; 1040 command.data = buf; 1041 command.data_len = 512; 1042 1043 if (mmc_send_cmd(&command)) { 1044 log_warn(&log, "Error sending command\n"); 1045 return 1; 1046 } 1047 1048 return 0; 1049 } 1050 1051 int 1052 write_single_block(struct sd_card_regs *card, 1053 uint32_t blknr, unsigned char *buf) 1054 { 1055 struct mmc_command command; 1056 1057 command.cmd = MMC_WRITE_BLOCK_SINGLE; 1058 command.args = blknr; 1059 command.resp_type = RESP_LEN_48; 1060 command.data_type = DATA_WRITE; 1061 command.data = buf; 1062 command.data_len = 512; 1063 1064 /* write single block */ 1065 if (mmc_send_cmd(&command)) { 1066 log_warn(&log, "Write single block command failed\n"); 1067 return 1; 1068 } 1069 1070 return 0; 1071 } 1072 1073 int 1074 mmchs_host_init(struct mmc_host *host) 1075 { 1076 mmchs_init(1); 1077 return 0; 1078 } 1079 1080 void 1081 mmchs_set_log_level(int level) 1082 { 1083 if (level >= 0 && level <= 4) { 1084 log.log_level = level; 1085 } 1086 } 1087 1088 int 1089 mmchs_host_set_instance(struct mmc_host *host, int instance) 1090 { 1091 log_info(&log, "Using instance number %d\n", instance); 1092 if (instance != 0) { 1093 return EIO; 1094 } 1095 return OK; 1096 } 1097 1098 int 1099 mmchs_host_reset(struct mmc_host *host) 1100 { 1101 // mmchs_init(1); 1102 return 0; 1103 } 1104 1105 int 1106 mmchs_card_detect(struct sd_slot *slot) 1107 { 1108 /* @TODO implement proper card detect */ 1109 return 1; 1110 } 1111 1112 struct sd_card * 1113 mmchs_card_initialize(struct sd_slot *slot) 1114 { 1115 // mmchs_init(1); 1116 1117 struct sd_card *card; 1118 card = &slot->card; 1119 memset(card, 0, sizeof(struct sd_card)); 1120 card->slot = slot; 1121 1122 if (card_goto_idle_state()) { 1123 log_warn(&log, "Failed to go idle state\n"); 1124 return NULL; 1125 } 1126 1127 if (card_identification()) { 1128 log_warn(&log, "Failed to do card_identification\n"); 1129 return NULL; 1130 } 1131 1132 if (card_query_voltage_and_type(&slot->card.regs)) { 1133 log_warn(&log, "Failed to do card_query_voltage_and_type\n"); 1134 return NULL; 1135 } 1136 1137 if (card_identify(&slot->card.regs)) { 1138 log_warn(&log, "Failed to identify card\n"); 1139 return NULL; 1140 } 1141 /* We have now initialized the hardware identified the card */ 1142 if (card_csd(&slot->card.regs)) { 1143 log_warn(&log, "failed to read csd (card specific data)\n"); 1144 return NULL; 1145 } 1146 1147 if (select_card(&slot->card.regs)) { 1148 log_warn(&log, "Failed to select card\n"); 1149 return NULL; 1150 } 1151 1152 if (card_scr(&slot->card.regs)) { 1153 log_warn(&log, 1154 "failed to read scr (card additional specific data)\n"); 1155 return NULL; 1156 } 1157 1158 if (enable_4bit_mode(&slot->card.regs)) { 1159 log_warn(&log, "failed to configure 4 bit access mode\n"); 1160 return NULL; 1161 } 1162 1163 if (enable_high_speed_mode(&slot->card.regs)) { 1164 log_warn(&log, "failed to configure high speed mode mode\n"); 1165 return NULL; 1166 } 1167 1168 if (SD_CSD_READ_BL_LEN(slot->card.regs.csd) != 0x09) { 1169 /* for CSD version 2.0 the value is fixed to 0x09 and means a 1170 * block size of 512 */ 1171 log_warn(&log, "Block size expect to be 512\n"); 1172 return NULL; 1173 } 1174 1175 slot->card.blk_size = 512; /* HARDCODED value */ 1176 slot->card.blk_count = SD_CSD_V2_CAPACITY(slot->card.regs.csd); 1177 slot->card.state = SD_MODE_DATA_TRANSFER_MODE; 1178 1179 /* MINIX related stuff to keep track of partitions */ 1180 memset(slot->card.part, 0, sizeof(slot->card.part)); 1181 memset(slot->card.subpart, 0, sizeof(slot->card.subpart)); 1182 slot->card.part[0].dv_base = 0; 1183 slot->card.part[0].dv_size = 1184 (unsigned long long) SD_CSD_V2_CAPACITY(slot->card.regs.csd) * 512; 1185 return &slot->card; 1186 } 1187 1188 /* read count blocks into existing buf */ 1189 static int 1190 mmchs_host_read(struct sd_card *card, 1191 uint32_t blknr, uint32_t count, unsigned char *buf) 1192 { 1193 uint32_t i; 1194 i = count; 1195 for (i = 0; i < count; i++) { 1196 read_single_block(&card->regs, blknr + i, 1197 buf + (i * card->blk_size)); 1198 } 1199 return OK; 1200 } 1201 1202 /* write count blocks */ 1203 static int 1204 mmchs_host_write(struct sd_card *card, 1205 uint32_t blknr, uint32_t count, unsigned char *buf) 1206 { 1207 uint32_t i; 1208 1209 i = count; 1210 for (i = 0; i < count; i++) { 1211 write_single_block(&card->regs, blknr + i, 1212 buf + (i * card->blk_size)); 1213 } 1214 1215 return OK; 1216 } 1217 1218 int 1219 mmchs_card_release(struct sd_card *card) 1220 { 1221 assert(card->open_ct == 1); 1222 card->open_ct--; 1223 card->state = SD_MODE_UNINITIALIZED; 1224 /* TODO:Set card state */ 1225 1226 /* now configure the controller to use 4 bit access */ 1227 mmc_set32(mmchs->regs->HCTL, MMCHS_SD_HCTL_DTW, 1228 MMCHS_SD_HCTL_DTW_1BIT); 1229 1230 return OK; 1231 } 1232 1233 void 1234 host_initialize_host_structure_mmchs(struct mmc_host *host) 1235 { 1236 /* Initialize the basic data structures host slots and cards */ 1237 int i; 1238 mmchs = NULL; 1239 1240 struct machine machine ; 1241 sys_getmachine(&machine); 1242 1243 if (BOARD_IS_BBXM(machine.board_id)){ 1244 mmchs = &bbxm_sdcard; 1245 } else if ( BOARD_IS_BB(machine.board_id)){ 1246 mmchs = &bone_sdcard; 1247 } 1248 1249 assert(mmchs); 1250 host->host_set_instance = mmchs_host_set_instance; 1251 host->host_init = mmchs_host_init; 1252 host->set_log_level = mmchs_set_log_level; 1253 host->host_reset = mmchs_host_reset; 1254 host->card_detect = mmchs_card_detect; 1255 host->card_initialize = mmchs_card_initialize; 1256 host->card_release = mmchs_card_release; 1257 host->hw_intr = mmchs_hw_intr; 1258 host->read = mmchs_host_read; 1259 host->write = mmchs_host_write; 1260 1261 /* initialize data structures */ 1262 for (i = 0; i < sizeof(host->slot) / sizeof(host->slot[0]); i++) { 1263 // @TODO set initial card and slot state 1264 host->slot[i].host = host; 1265 host->slot[i].card.slot = &host->slot[i]; 1266 } 1267 } 1268