xref: /minix/sys/arch/arm/include/cpufunc.h (revision 0a6a1f1d)
1 /*	cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp	*/
2 
3 /*
4  * Copyright (c) 1997 Mark Brinicombe.
5  * Copyright (c) 1997 Causality Limited
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Causality Limited.
19  * 4. The name of Causality Limited may not be used to endorse or promote
20  *    products derived from this software without specific prior written
21  *    permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * RiscBSD kernel project
36  *
37  * cpufunc.h
38  *
39  * Prototypes for cpu, mmu and tlb related functions.
40  */
41 
42 #ifndef _ARM_CPUFUNC_H_
43 #define _ARM_CPUFUNC_H_
44 
45 #ifdef _KERNEL
46 
47 #include <sys/types.h>
48 #include <arm/armreg.h>
49 #include <arm/cpuconf.h>
50 #include <arm/armreg.h>
51 #include <arm/cpufunc_proto.h>
52 
53 struct cpu_functions {
54 
55 	/* CPU functions */
56 
57 	u_int	(*cf_id)		(void);
58 	void	(*cf_cpwait)		(void);
59 
60 	/* MMU functions */
61 
62 	u_int	(*cf_control)		(u_int, u_int);
63 	void	(*cf_domains)		(u_int);
64 #if defined(ARM_MMU_EXTENDED)
65 	void	(*cf_setttb)		(u_int, tlb_asid_t);
66 #else
67 	void	(*cf_setttb)		(u_int, bool);
68 #endif
69 	u_int	(*cf_faultstatus)	(void);
70 	u_int	(*cf_faultaddress)	(void);
71 
72 	/* TLB functions */
73 
74 	void	(*cf_tlb_flushID)	(void);
75 	void	(*cf_tlb_flushID_SE)	(vaddr_t);
76 	void	(*cf_tlb_flushI)	(void);
77 	void	(*cf_tlb_flushI_SE)	(vaddr_t);
78 	void	(*cf_tlb_flushD)	(void);
79 	void	(*cf_tlb_flushD_SE)	(vaddr_t);
80 
81 	/*
82 	 * Cache operations:
83 	 *
84 	 * We define the following primitives:
85 	 *
86 	 *	icache_sync_all		Synchronize I-cache
87 	 *	icache_sync_range	Synchronize I-cache range
88 	 *
89 	 *	dcache_wbinv_all	Write-back and Invalidate D-cache
90 	 *	dcache_wbinv_range	Write-back and Invalidate D-cache range
91 	 *	dcache_inv_range	Invalidate D-cache range
92 	 *	dcache_wb_range		Write-back D-cache range
93 	 *
94 	 *	idcache_wbinv_all	Write-back and Invalidate D-cache,
95 	 *				Invalidate I-cache
96 	 *	idcache_wbinv_range	Write-back and Invalidate D-cache,
97 	 *				Invalidate I-cache range
98 	 *
99 	 * Note that the ARM term for "write-back" is "clean".  We use
100 	 * the term "write-back" since it's a more common way to describe
101 	 * the operation.
102 	 *
103 	 * There are some rules that must be followed:
104 	 *
105 	 *	I-cache Synch (all or range):
106 	 *		The goal is to synchronize the instruction stream,
107 	 *		so you may beed to write-back dirty D-cache blocks
108 	 *		first.  If a range is requested, and you can't
109 	 *		synchronize just a range, you have to hit the whole
110 	 *		thing.
111 	 *
112 	 *	D-cache Write-Back and Invalidate range:
113 	 *		If you can't WB-Inv a range, you must WB-Inv the
114 	 *		entire D-cache.
115 	 *
116 	 *	D-cache Invalidate:
117 	 *		If you can't Inv the D-cache, you must Write-Back
118 	 *		and Invalidate.  Code that uses this operation
119 	 *		MUST NOT assume that the D-cache will not be written
120 	 *		back to memory.
121 	 *
122 	 *	D-cache Write-Back:
123 	 *		If you can't Write-back without doing an Inv,
124 	 *		that's fine.  Then treat this as a WB-Inv.
125 	 *		Skipping the invalidate is merely an optimization.
126 	 *
127 	 *	All operations:
128 	 *		Valid virtual addresses must be passed to each
129 	 *		cache operation.
130 	 */
131 	void	(*cf_icache_sync_all)	(void);
132 	void	(*cf_icache_sync_range)	(vaddr_t, vsize_t);
133 
134 	void	(*cf_dcache_wbinv_all)	(void);
135 	void	(*cf_dcache_wbinv_range)(vaddr_t, vsize_t);
136 	void	(*cf_dcache_inv_range)	(vaddr_t, vsize_t);
137 	void	(*cf_dcache_wb_range)	(vaddr_t, vsize_t);
138 
139 	void	(*cf_sdcache_wbinv_range)(vaddr_t, paddr_t, psize_t);
140 	void	(*cf_sdcache_inv_range)	(vaddr_t, paddr_t, psize_t);
141 	void	(*cf_sdcache_wb_range)	(vaddr_t, paddr_t, psize_t);
142 
143 	void	(*cf_idcache_wbinv_all)	(void);
144 	void	(*cf_idcache_wbinv_range)(vaddr_t, vsize_t);
145 
146 	/* Other functions */
147 
148 	void	(*cf_flush_prefetchbuf)	(void);
149 	void	(*cf_drain_writebuf)	(void);
150 	void	(*cf_flush_brnchtgt_C)	(void);
151 	void	(*cf_flush_brnchtgt_E)	(u_int);
152 
153 	void	(*cf_sleep)		(int mode);
154 
155 	/* Soft functions */
156 
157 	int	(*cf_dataabt_fixup)	(void *);
158 	int	(*cf_prefetchabt_fixup)	(void *);
159 
160 #if defined(ARM_MMU_EXTENDED)
161 	void	(*cf_context_switch)	(u_int, tlb_asid_t);
162 #else
163 	void	(*cf_context_switch)	(u_int);
164 #endif
165 
166 	void	(*cf_setup)		(char *);
167 };
168 
169 extern struct cpu_functions cpufuncs;
170 extern u_int cputype;
171 
172 #define cpu_id()		cpufuncs.cf_id()
173 
174 #define cpu_control(c, e)	cpufuncs.cf_control(c, e)
175 #define cpu_domains(d)		cpufuncs.cf_domains(d)
176 #define cpu_setttb(t, f)	cpufuncs.cf_setttb(t, f)
177 #define cpu_faultstatus()	cpufuncs.cf_faultstatus()
178 #define cpu_faultaddress()	cpufuncs.cf_faultaddress()
179 
180 #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
181 #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
182 #define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
183 #define	cpu_tlb_flushI_SE(e)	cpufuncs.cf_tlb_flushI_SE(e)
184 #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
185 #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
186 
187 #define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
188 #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
189 
190 #define	cpu_dcache_wbinv_all()	cpufuncs.cf_dcache_wbinv_all()
191 #define	cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
192 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
193 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
194 
195 #define	cpu_sdcache_wbinv_range(a, b, s) cpufuncs.cf_sdcache_wbinv_range((a), (b), (s))
196 #define	cpu_sdcache_inv_range(a, b, s) cpufuncs.cf_sdcache_inv_range((a), (b), (s))
197 #define	cpu_sdcache_wb_range(a, b, s) cpufuncs.cf_sdcache_wb_range((a), (b), (s))
198 
199 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
200 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
201 
202 #define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
203 #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()
204 #define	cpu_flush_brnchtgt_C()	cpufuncs.cf_flush_brnchtgt_C()
205 #define	cpu_flush_brnchtgt_E(e)	cpufuncs.cf_flush_brnchtgt_E(e)
206 
207 #define cpu_sleep(m)		cpufuncs.cf_sleep(m)
208 
209 #define cpu_dataabt_fixup(a)		cpufuncs.cf_dataabt_fixup(a)
210 #define cpu_prefetchabt_fixup(a)	cpufuncs.cf_prefetchabt_fixup(a)
211 #define ABORT_FIXUP_OK		0	/* fixup succeeded */
212 #define ABORT_FIXUP_FAILED	1	/* fixup failed */
213 #define ABORT_FIXUP_RETURN	2	/* abort handler should return */
214 
215 #define cpu_context_switch(a)		cpufuncs.cf_context_switch(a)
216 #define cpu_setup(a)			cpufuncs.cf_setup(a)
217 
218 int	set_cpufuncs		(void);
219 int	set_cpufuncs_id		(u_int);
220 #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
221 #define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
222 
223 void	cpufunc_nullop		(void);
224 int	cpufunc_null_fixup	(void *);
225 int	early_abort_fixup	(void *);
226 int	late_abort_fixup	(void *);
227 u_int	cpufunc_id		(void);
228 u_int	cpufunc_control		(u_int, u_int);
229 void	cpufunc_domains		(u_int);
230 u_int	cpufunc_faultstatus	(void);
231 u_int	cpufunc_faultaddress	(void);
232 
233 #define tlb_flush	cpu_tlb_flushID
234 #define setttb		cpu_setttb
235 #define drain_writebuf	cpu_drain_writebuf
236 
237 
238 #if defined(CPU_XSCALE)
239 #define	cpu_cpwait()		cpufuncs.cf_cpwait()
240 #endif
241 
242 #ifndef cpu_cpwait
243 #define	cpu_cpwait()
244 #endif
245 
246 /*
247  * Macros for manipulating CPU interrupts
248  */
249 #ifdef __PROG32
250 static __inline uint32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__));
251 static __inline uint32_t disable_interrupts(uint32_t mask) __attribute__((__unused__));
252 static __inline uint32_t enable_interrupts(uint32_t mask) __attribute__((__unused__));
253 
254 static __inline uint32_t
__set_cpsr_c(uint32_t bic,uint32_t eor)255 __set_cpsr_c(uint32_t bic, uint32_t eor)
256 {
257 	uint32_t	tmp, ret;
258 
259 	__asm volatile(
260 		"mrs     %0, cpsr\n"	/* Get the CPSR */
261 		"bic	 %1, %0, %2\n"	/* Clear bits */
262 		"eor	 %1, %1, %3\n"	/* XOR bits */
263 		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
264 	: "=&r" (ret), "=&r" (tmp)
265 	: "r" (bic), "r" (eor) : "memory");
266 
267 	return ret;
268 }
269 
270 static __inline uint32_t
disable_interrupts(uint32_t mask)271 disable_interrupts(uint32_t mask)
272 {
273 	uint32_t	tmp, ret;
274 	mask &= (I32_bit | F32_bit);
275 
276 	__asm volatile(
277 		"mrs     %0, cpsr\n"	/* Get the CPSR */
278 		"orr	 %1, %0, %2\n"	/* set bits */
279 		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
280 	: "=&r" (ret), "=&r" (tmp)
281 	: "r" (mask)
282 	: "memory");
283 
284 	return ret;
285 }
286 
287 static __inline uint32_t
enable_interrupts(uint32_t mask)288 enable_interrupts(uint32_t mask)
289 {
290 	uint32_t	ret;
291 	mask &= (I32_bit | F32_bit);
292 
293 	/* Get the CPSR */
294 	__asm __volatile("mrs\t%0, cpsr\n" : "=r"(ret));
295 #ifdef _ARM_ARCH_6
296 	if (__builtin_constant_p(mask)) {
297 		switch (mask) {
298 		case I32_bit | F32_bit:
299 			__asm __volatile("cpsie\tif");
300 			break;
301 		case I32_bit:
302 			__asm __volatile("cpsie\ti");
303 			break;
304 		case F32_bit:
305 			__asm __volatile("cpsie\tf");
306 			break;
307 		default:
308 			break;
309 		}
310 		return ret;
311 	}
312 #endif /* _ARM_ARCH_6 */
313 
314 	/* Set the control field of CPSR */
315 	__asm volatile("msr\tcpsr_c, %0" :: "r"(ret & ~mask));
316 
317 	return ret;
318 }
319 
320 #define restore_interrupts(old_cpsr)					\
321 	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
322 
323 static inline void cpsie(register_t psw) __attribute__((__unused__));
324 static inline register_t cpsid(register_t psw) __attribute__((__unused__));
325 
326 static inline void
cpsie(register_t psw)327 cpsie(register_t psw)
328 {
329 #ifdef _ARM_ARCH_6
330 	if (!__builtin_constant_p(psw)) {
331 		enable_interrupts(psw);
332 		return;
333 	}
334 	switch (psw & (I32_bit|F32_bit)) {
335 	case I32_bit:		__asm("cpsie\ti"); break;
336 	case F32_bit:		__asm("cpsie\tf"); break;
337 	case I32_bit|F32_bit:	__asm("cpsie\tif"); break;
338 	}
339 #else
340 	enable_interrupts(psw);
341 #endif
342 }
343 
344 static inline register_t
cpsid(register_t psw)345 cpsid(register_t psw)
346 {
347 #ifdef _ARM_ARCH_6
348 	register_t oldpsw;
349 	if (!__builtin_constant_p(psw))
350 		return disable_interrupts(psw);
351 
352 	__asm("mrs	%0, cpsr" : "=r"(oldpsw));
353 	switch (psw & (I32_bit|F32_bit)) {
354 	case I32_bit:		__asm("cpsid\ti"); break;
355 	case F32_bit:		__asm("cpsid\tf"); break;
356 	case I32_bit|F32_bit:	__asm("cpsid\tif"); break;
357 	}
358 	return oldpsw;
359 #else
360 	return disable_interrupts(psw);
361 #endif
362 }
363 
364 #else /* ! __PROG32 */
365 #define	disable_interrupts(mask)					\
366 	(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE),		\
367 		 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
368 
369 #define	enable_interrupts(mask)						\
370 	(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
371 
372 #define	restore_interrupts(old_r15)					\
373 	(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE),			\
374 		 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
375 #endif /* __PROG32 */
376 
377 #ifdef __PROG32
378 /* Functions to manipulate the CPSR. */
379 u_int	SetCPSR(u_int, u_int);
380 u_int	GetCPSR(void);
381 #else
382 /* Functions to manipulate the processor control bits in r15. */
383 u_int	set_r15(u_int, u_int);
384 u_int	get_r15(void);
385 #endif /* __PROG32 */
386 
387 
388 /*
389  * CPU functions from locore.S
390  */
391 
392 void cpu_reset		(void) __dead;
393 
394 /*
395  * Cache info variables.
396  */
397 #define	CACHE_TYPE_VIVT		0
398 #define	CACHE_TYPE_xxPT		1
399 #define	CACHE_TYPE_VIPT		1
400 #define	CACHE_TYPE_PIxx		2
401 #define	CACHE_TYPE_PIPT		3
402 
403 /* PRIMARY CACHE VARIABLES */
404 struct arm_cache_info {
405 	u_int icache_size;
406 	u_int icache_line_size;
407 	u_int icache_ways;
408 	u_int icache_way_size;
409 	u_int icache_sets;
410 
411 	u_int dcache_size;
412 	u_int dcache_line_size;
413 	u_int dcache_ways;
414 	u_int dcache_way_size;
415 	u_int dcache_sets;
416 
417 	uint8_t cache_type;
418 	bool cache_unified;
419 	uint8_t icache_type;
420 	uint8_t dcache_type;
421 };
422 
423 extern u_int arm_cache_prefer_mask;
424 extern u_int arm_dcache_align;
425 extern u_int arm_dcache_align_mask;
426 
427 extern struct arm_cache_info arm_pcache;
428 extern struct arm_cache_info arm_scache;
429 #endif	/* _KERNEL */
430 
431 #if defined(_KERNEL) || defined(_KMEMUSER)
432 /*
433  * Miscellany
434  */
435 
436 int get_pc_str_offset	(void);
437 
438 /*
439  * Functions to manipulate cpu r13
440  * (in arm/arm32/setstack.S)
441  */
442 
443 void set_stackptr	(u_int, u_int);
444 u_int get_stackptr	(u_int);
445 
446 #endif /* _KERNEL || _KMEMUSER */
447 
448 #endif	/* _ARM_CPUFUNC_H_ */
449 
450 /* End of cpufunc.h */
451