1*06f32e7eSjoerg//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===// 2*06f32e7eSjoerg// 3*06f32e7eSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*06f32e7eSjoerg// See https://llvm.org/LICENSE.txt for license information. 5*06f32e7eSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*06f32e7eSjoerg// 7*06f32e7eSjoerg//===----------------------------------------------------------------------===// 8*06f32e7eSjoerg 9*06f32e7eSjoerg// Define TII for use in SchedVariant Predicates. 10*06f32e7eSjoerg// const MachineInstr *MI and const TargetSchedModel *SchedModel 11*06f32e7eSjoerg// are defined by default. 12*06f32e7eSjoergdef : PredicateProlog<[{ 13*06f32e7eSjoerg const AArch64InstrInfo *TII = 14*06f32e7eSjoerg static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo()); 15*06f32e7eSjoerg (void)TII; 16*06f32e7eSjoerg}]>; 17*06f32e7eSjoerg 18*06f32e7eSjoerg// AArch64 Scheduler Definitions 19*06f32e7eSjoerg 20*06f32e7eSjoergdef WriteImm : SchedWrite; // MOVN, MOVZ 21*06f32e7eSjoerg// TODO: Provide variants for MOV32/64imm Pseudos that dynamically 22*06f32e7eSjoerg// select the correct sequence of WriteImms. 23*06f32e7eSjoerg 24*06f32e7eSjoergdef WriteI : SchedWrite; // ALU 25*06f32e7eSjoergdef WriteISReg : SchedWrite; // ALU of Shifted-Reg 26*06f32e7eSjoergdef WriteIEReg : SchedWrite; // ALU of Extended-Reg 27*06f32e7eSjoergdef ReadI : SchedRead; // ALU 28*06f32e7eSjoergdef ReadISReg : SchedRead; // ALU of Shifted-Reg 29*06f32e7eSjoergdef ReadIEReg : SchedRead; // ALU of Extended-Reg 30*06f32e7eSjoergdef WriteExtr : SchedWrite; // EXTR shifts a reg pair 31*06f32e7eSjoergdef ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair 32*06f32e7eSjoergdef WriteIS : SchedWrite; // Shift/Scale 33*06f32e7eSjoergdef WriteID32 : SchedWrite; // 32-bit Divide 34*06f32e7eSjoergdef WriteID64 : SchedWrite; // 64-bit Divide 35*06f32e7eSjoergdef ReadID : SchedRead; // 32/64-bit Divide 36*06f32e7eSjoergdef WriteIM32 : SchedWrite; // 32-bit Multiply 37*06f32e7eSjoergdef WriteIM64 : SchedWrite; // 64-bit Multiply 38*06f32e7eSjoergdef ReadIM : SchedRead; // 32/64-bit Multiply 39*06f32e7eSjoergdef ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate 40*06f32e7eSjoergdef WriteBr : SchedWrite; // Branch 41*06f32e7eSjoergdef WriteBrReg : SchedWrite; // Indirect Branch 42*06f32e7eSjoerg 43*06f32e7eSjoergdef WriteLD : SchedWrite; // Load from base addr plus immediate offset 44*06f32e7eSjoergdef WriteST : SchedWrite; // Store to base addr plus immediate offset 45*06f32e7eSjoergdef WriteSTP : SchedWrite; // Store a register pair. 46*06f32e7eSjoergdef WriteAdr : SchedWrite; // Address pre/post increment. 47*06f32e7eSjoerg 48*06f32e7eSjoergdef WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). 49*06f32e7eSjoergdef WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). 50*06f32e7eSjoergdef ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. 51*06f32e7eSjoerg 52*06f32e7eSjoerg// Serialized two-level address load. 53*06f32e7eSjoerg// EXAMPLE: LOADGot 54*06f32e7eSjoergdef WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; 55*06f32e7eSjoerg 56*06f32e7eSjoerg// Serialized two-level address lookup. 57*06f32e7eSjoerg// EXAMPLE: MOVaddr... 58*06f32e7eSjoergdef WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>; 59*06f32e7eSjoerg 60*06f32e7eSjoerg// The second register of a load-pair. 61*06f32e7eSjoerg// LDP,LDPSW,LDNP,LDXP,LDAXP 62*06f32e7eSjoergdef WriteLDHi : SchedWrite; 63*06f32e7eSjoerg 64*06f32e7eSjoerg// Store-exclusive is a store followed by a dependent load. 65*06f32e7eSjoergdef WriteSTX : WriteSequence<[WriteST, WriteLD]>; 66*06f32e7eSjoerg 67*06f32e7eSjoergdef WriteSys : SchedWrite; // Long, variable latency system ops. 68*06f32e7eSjoergdef WriteBarrier : SchedWrite; // Memory barrier. 69*06f32e7eSjoergdef WriteHint : SchedWrite; // Hint instruction. 70*06f32e7eSjoerg 71*06f32e7eSjoergdef WriteF : SchedWrite; // General floating-point ops. 72*06f32e7eSjoergdef WriteFCmp : SchedWrite; // Floating-point compare. 73*06f32e7eSjoergdef WriteFCvt : SchedWrite; // Float conversion. 74*06f32e7eSjoergdef WriteFCopy : SchedWrite; // Float-int register copy. 75*06f32e7eSjoergdef WriteFImm : SchedWrite; // Floating-point immediate. 76*06f32e7eSjoergdef WriteFMul : SchedWrite; // Floating-point multiply. 77*06f32e7eSjoergdef WriteFDiv : SchedWrite; // Floating-point division. 78*06f32e7eSjoerg 79*06f32e7eSjoergdef WriteV : SchedWrite; // Vector ops. 80*06f32e7eSjoergdef WriteVLD : SchedWrite; // Vector loads. 81*06f32e7eSjoergdef WriteVST : SchedWrite; // Vector stores. 82*06f32e7eSjoerg 83*06f32e7eSjoergdef WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP) 84*06f32e7eSjoerg 85*06f32e7eSjoerg// Read the unwritten lanes of the VLD's destination registers. 86*06f32e7eSjoergdef ReadVLD : SchedRead; 87*06f32e7eSjoerg 88*06f32e7eSjoerg// Sequential vector load and shuffle. 89*06f32e7eSjoergdef WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>; 90*06f32e7eSjoergdef WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>; 91*06f32e7eSjoerg 92*06f32e7eSjoerg// Store a shuffled vector. 93*06f32e7eSjoergdef WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>; 94*06f32e7eSjoergdef WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>; 95