1*da58b97aSjoerg//===-- VEInstrInfo.td - Target Description for VE Target -----------------===// 2*da58b97aSjoerg// 3*da58b97aSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*da58b97aSjoerg// See https://llvm.org/LICENSE.txt for license information. 5*da58b97aSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*da58b97aSjoerg// 7*da58b97aSjoerg//===----------------------------------------------------------------------===// 8*da58b97aSjoerg// 9*da58b97aSjoerg// This file describes the VE instructions in TableGen format. 10*da58b97aSjoerg// 11*da58b97aSjoerg//===----------------------------------------------------------------------===// 12*da58b97aSjoerg 13*da58b97aSjoerg//===----------------------------------------------------------------------===// 14*da58b97aSjoerg// Instruction format superclass 15*da58b97aSjoerg//===----------------------------------------------------------------------===// 16*da58b97aSjoerg 17*da58b97aSjoerginclude "VEInstrFormats.td" 18*da58b97aSjoerg 19*da58b97aSjoerg//===----------------------------------------------------------------------===// 20*da58b97aSjoerg// Helper functions to retrieve target constants. 21*da58b97aSjoerg// 22*da58b97aSjoerg// VE instructions have a space to hold following immediates 23*da58b97aSjoerg// $sy has 7 bits to represent simm7, uimm7, simm7fp, or uimm7fp. 24*da58b97aSjoerg// $sz also has 7 bits to represent mimm or mimmfp. 25*da58b97aSjoerg// $disp has 32 bits to represent simm32. 26*da58b97aSjoerg// 27*da58b97aSjoerg// The mimm is a special immediate value of sequential bit stream of 0 or 1. 28*da58b97aSjoerg// `(m)0`: Represents 0 sequence then 1 sequence like 0b00...0011...11, 29*da58b97aSjoerg// where `m` is equal to the number of leading zeros. 30*da58b97aSjoerg// `(m)1`: Represents 1 sequence then 0 sequence like 0b11...1100...00, 31*da58b97aSjoerg// where `m` is equal to the number of leading ones. 32*da58b97aSjoerg// Each bit of mimm's 7 bits is used like below: 33*da58b97aSjoerg// bit 6 : If `(m)0`, this bit is 1. Otherwise, this bit is 0. 34*da58b97aSjoerg// bit 5-0: Represents the m (0-63). 35*da58b97aSjoerg// Use `!add(m, 64)` to generates an immediate value in pattern matchings. 36*da58b97aSjoerg// 37*da58b97aSjoerg// The floating point immediate value is not something like compacted value. 38*da58b97aSjoerg// It is simple integer representation, so it works rarely. 39*da58b97aSjoerg// e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1). 40*da58b97aSjoerg//===----------------------------------------------------------------------===// 41*da58b97aSjoerg 42*da58b97aSjoergdef ULO7 : SDNodeXForm<imm, [{ 43*da58b97aSjoerg return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f, 44*da58b97aSjoerg SDLoc(N), MVT::i32); 45*da58b97aSjoerg}]>; 46*da58b97aSjoergdef LO7 : SDNodeXForm<imm, [{ 47*da58b97aSjoerg return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7), 48*da58b97aSjoerg SDLoc(N), MVT::i32); 49*da58b97aSjoerg}]>; 50*da58b97aSjoergdef MIMM : SDNodeXForm<imm, [{ 51*da58b97aSjoerg return CurDAG->getTargetConstant(val2MImm(getImmVal(N)), 52*da58b97aSjoerg SDLoc(N), MVT::i32); 53*da58b97aSjoerg}]>; 54*da58b97aSjoergdef LO32 : SDNodeXForm<imm, [{ 55*da58b97aSjoerg return CurDAG->getTargetConstant(Lo_32(N->getZExtValue()), 56*da58b97aSjoerg SDLoc(N), MVT::i32); 57*da58b97aSjoerg}]>; 58*da58b97aSjoergdef HI32 : SDNodeXForm<imm, [{ 59*da58b97aSjoerg // Transformation function: shift the immediate value down into the low bits. 60*da58b97aSjoerg return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()), 61*da58b97aSjoerg SDLoc(N), MVT::i32); 62*da58b97aSjoerg}]>; 63*da58b97aSjoerg 64*da58b97aSjoergdef LO7FP : SDNodeXForm<fpimm, [{ 65*da58b97aSjoerg uint64_t Val = getFpImmVal(N); 66*da58b97aSjoerg return CurDAG->getTargetConstant(SignExtend32(Val, 7), SDLoc(N), MVT::i32); 67*da58b97aSjoerg}]>; 68*da58b97aSjoergdef MIMMFP : SDNodeXForm<fpimm, [{ 69*da58b97aSjoerg return CurDAG->getTargetConstant(val2MImm(getFpImmVal(N)), 70*da58b97aSjoerg SDLoc(N), MVT::i32); 71*da58b97aSjoerg}]>; 72*da58b97aSjoergdef LOFP32 : SDNodeXForm<fpimm, [{ 73*da58b97aSjoerg return CurDAG->getTargetConstant(Lo_32(getFpImmVal(N) & 0xffffffff), 74*da58b97aSjoerg SDLoc(N), MVT::i32); 75*da58b97aSjoerg}]>; 76*da58b97aSjoergdef HIFP32 : SDNodeXForm<fpimm, [{ 77*da58b97aSjoerg return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32); 78*da58b97aSjoerg}]>; 79*da58b97aSjoerg 80*da58b97aSjoergdef icond2cc : SDNodeXForm<cond, [{ 81*da58b97aSjoerg VECC::CondCode VECC = intCondCode2Icc(N->get()); 82*da58b97aSjoerg return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32); 83*da58b97aSjoerg}]>; 84*da58b97aSjoerg 85*da58b97aSjoergdef icond2ccSwap : SDNodeXForm<cond, [{ 86*da58b97aSjoerg ISD::CondCode CC = getSetCCSwappedOperands(N->get()); 87*da58b97aSjoerg VECC::CondCode VECC = intCondCode2Icc(CC); 88*da58b97aSjoerg return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32); 89*da58b97aSjoerg}]>; 90*da58b97aSjoerg 91*da58b97aSjoergdef fcond2cc : SDNodeXForm<cond, [{ 92*da58b97aSjoerg VECC::CondCode VECC = fpCondCode2Fcc(N->get()); 93*da58b97aSjoerg return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32); 94*da58b97aSjoerg}]>; 95*da58b97aSjoerg 96*da58b97aSjoergdef fcond2ccSwap : SDNodeXForm<cond, [{ 97*da58b97aSjoerg ISD::CondCode CC = getSetCCSwappedOperands(N->get()); 98*da58b97aSjoerg VECC::CondCode VECC = fpCondCode2Fcc(CC); 99*da58b97aSjoerg return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32); 100*da58b97aSjoerg}]>; 101*da58b97aSjoerg 102*da58b97aSjoergdef CCOP : SDNodeXForm<imm, [{ 103*da58b97aSjoerg return CurDAG->getTargetConstant(N->getZExtValue(), 104*da58b97aSjoerg SDLoc(N), MVT::i32); 105*da58b97aSjoerg}]>; 106*da58b97aSjoerg 107*da58b97aSjoerg//===----------------------------------------------------------------------===// 108*da58b97aSjoerg// Feature predicates. 109*da58b97aSjoerg//===----------------------------------------------------------------------===// 110*da58b97aSjoerg 111*da58b97aSjoerg//===----------------------------------------------------------------------===// 112*da58b97aSjoerg// Instruction Pattern Stuff 113*da58b97aSjoerg//===----------------------------------------------------------------------===// 114*da58b97aSjoerg 115*da58b97aSjoerg// zero 116*da58b97aSjoergdef ZeroAsmOperand : AsmOperandClass { 117*da58b97aSjoerg let Name = "Zero"; 118*da58b97aSjoerg} 119*da58b97aSjoergdef zero : Operand<i32>, PatLeaf<(imm), [{ 120*da58b97aSjoerg return N->getSExtValue() == 0; }]> { 121*da58b97aSjoerg let ParserMatchClass = ZeroAsmOperand; 122*da58b97aSjoerg} 123*da58b97aSjoerg 124*da58b97aSjoerg// uimm0to2 - Special immediate value represents 0, 1, and 2. 125*da58b97aSjoergdef UImm0to2AsmOperand : AsmOperandClass { 126*da58b97aSjoerg let Name = "UImm0to2"; 127*da58b97aSjoerg} 128*da58b97aSjoergdef uimm0to2 : Operand<i32>, PatLeaf<(imm), [{ 129*da58b97aSjoerg return N->getZExtValue() < 3; }], ULO7> { 130*da58b97aSjoerg let ParserMatchClass = UImm0to2AsmOperand; 131*da58b97aSjoerg} 132*da58b97aSjoerg 133*da58b97aSjoerg// uimm1 - Generic immediate value. 134*da58b97aSjoergdef UImm1AsmOperand : AsmOperandClass { 135*da58b97aSjoerg let Name = "UImm1"; 136*da58b97aSjoerg} 137*da58b97aSjoergdef uimm1 : Operand<i32>, PatLeaf<(imm), [{ 138*da58b97aSjoerg return isUInt<1>(N->getZExtValue()); }], ULO7> { 139*da58b97aSjoerg let ParserMatchClass = UImm1AsmOperand; 140*da58b97aSjoerg} 141*da58b97aSjoerg 142*da58b97aSjoerg// uimm2 - Generic immediate value. 143*da58b97aSjoergdef UImm2AsmOperand : AsmOperandClass { 144*da58b97aSjoerg let Name = "UImm2"; 145*da58b97aSjoerg} 146*da58b97aSjoergdef uimm2 : Operand<i32>, PatLeaf<(imm), [{ 147*da58b97aSjoerg return isUInt<2>(N->getZExtValue()); }], ULO7> { 148*da58b97aSjoerg let ParserMatchClass = UImm2AsmOperand; 149*da58b97aSjoerg} 150*da58b97aSjoerg 151*da58b97aSjoerg// uimm3 - Generic immediate value. 152*da58b97aSjoergdef UImm3AsmOperand : AsmOperandClass { 153*da58b97aSjoerg let Name = "UImm3"; 154*da58b97aSjoerg} 155*da58b97aSjoergdef uimm3 : Operand<i32>, PatLeaf<(imm), [{ 156*da58b97aSjoerg return isUInt<3>(N->getZExtValue()); }], ULO7> { 157*da58b97aSjoerg let ParserMatchClass = UImm3AsmOperand; 158*da58b97aSjoerg} 159*da58b97aSjoerg 160*da58b97aSjoerg// uimm4 - Generic immediate value. 161*da58b97aSjoergdef UImm4AsmOperand : AsmOperandClass { 162*da58b97aSjoerg let Name = "UImm4"; 163*da58b97aSjoerg} 164*da58b97aSjoergdef uimm4 : Operand<i32>, PatLeaf<(imm), [{ 165*da58b97aSjoerg return isUInt<4>(N->getZExtValue()); }], ULO7> { 166*da58b97aSjoerg let ParserMatchClass = UImm4AsmOperand; 167*da58b97aSjoerg} 168*da58b97aSjoerg 169*da58b97aSjoerg// uimm6 - Generic immediate value. 170*da58b97aSjoergdef UImm6AsmOperand : AsmOperandClass { 171*da58b97aSjoerg let Name = "UImm6"; 172*da58b97aSjoerg} 173*da58b97aSjoergdef uimm6 : Operand<i32>, PatLeaf<(imm), [{ 174*da58b97aSjoerg return isUInt<6>(N->getZExtValue()); }], ULO7> { 175*da58b97aSjoerg let ParserMatchClass = UImm6AsmOperand; 176*da58b97aSjoerg} 177*da58b97aSjoerg 178*da58b97aSjoerg// uimm7 - Generic immediate value. 179*da58b97aSjoergdef UImm7AsmOperand : AsmOperandClass { 180*da58b97aSjoerg let Name = "UImm7"; 181*da58b97aSjoerg} 182*da58b97aSjoergdef uimm7 : Operand<i32>, PatLeaf<(imm), [{ 183*da58b97aSjoerg return isUInt<7>(N->getZExtValue()); }], ULO7> { 184*da58b97aSjoerg let ParserMatchClass = UImm7AsmOperand; 185*da58b97aSjoerg} 186*da58b97aSjoerg 187*da58b97aSjoerg// simm7 - Generic immediate value. 188*da58b97aSjoergdef SImm7AsmOperand : AsmOperandClass { 189*da58b97aSjoerg let Name = "SImm7"; 190*da58b97aSjoerg} 191*da58b97aSjoergdef simm7 : Operand<i32>, PatLeaf<(imm), [{ 192*da58b97aSjoerg return isInt<7>(N->getSExtValue()); }], LO7> { 193*da58b97aSjoerg let ParserMatchClass = SImm7AsmOperand; 194*da58b97aSjoerg let DecoderMethod = "DecodeSIMM7"; 195*da58b97aSjoerg} 196*da58b97aSjoerg 197*da58b97aSjoerg// mimm - Special immediate value of sequential bit stream of 0 or 1. 198*da58b97aSjoergdef MImmAsmOperand : AsmOperandClass { 199*da58b97aSjoerg let Name = "MImm"; 200*da58b97aSjoerg let ParserMethod = "parseMImmOperand"; 201*da58b97aSjoerg} 202*da58b97aSjoergdef mimm : Operand<i32>, PatLeaf<(imm), [{ 203*da58b97aSjoerg return isMImmVal(getImmVal(N)); }], MIMM> { 204*da58b97aSjoerg let ParserMatchClass = MImmAsmOperand; 205*da58b97aSjoerg let PrintMethod = "printMImmOperand"; 206*da58b97aSjoerg} 207*da58b97aSjoerg 208*da58b97aSjoerg// zerofp - Generic fp immediate zero value. 209*da58b97aSjoergdef zerofp : Operand<i32>, PatLeaf<(fpimm), [{ 210*da58b97aSjoerg return getFpImmVal(N) == 0; }]> { 211*da58b97aSjoerg let ParserMatchClass = ZeroAsmOperand; 212*da58b97aSjoerg} 213*da58b97aSjoerg 214*da58b97aSjoerg// simm7fp - Generic fp immediate value. 215*da58b97aSjoergdef simm7fp : Operand<i32>, PatLeaf<(fpimm), [{ 216*da58b97aSjoerg return isInt<7>(getFpImmVal(N)); 217*da58b97aSjoerg }], LO7FP> { 218*da58b97aSjoerg let ParserMatchClass = SImm7AsmOperand; 219*da58b97aSjoerg let DecoderMethod = "DecodeSIMM7"; 220*da58b97aSjoerg} 221*da58b97aSjoerg 222*da58b97aSjoerg// mimmfp - Special fp immediate value of sequential bit stream of 0 or 1. 223*da58b97aSjoergdef mimmfp : Operand<i32>, PatLeaf<(fpimm), [{ 224*da58b97aSjoerg return isMImmVal(getFpImmVal(N)); }], MIMMFP> { 225*da58b97aSjoerg let ParserMatchClass = MImmAsmOperand; 226*da58b97aSjoerg let PrintMethod = "printMImmOperand"; 227*da58b97aSjoerg} 228*da58b97aSjoerg 229*da58b97aSjoerg// mimmfp32 - 32 bit width mimmfp 230*da58b97aSjoerg// Float value places at higher bits, so ignore lower 32 bits. 231*da58b97aSjoergdef mimmfp32 : Operand<i32>, PatLeaf<(fpimm), [{ 232*da58b97aSjoerg return isMImm32Val(getFpImmVal(N) >> 32); }], MIMMFP> { 233*da58b97aSjoerg let ParserMatchClass = MImmAsmOperand; 234*da58b97aSjoerg let PrintMethod = "printMImmOperand"; 235*da58b97aSjoerg} 236*da58b97aSjoerg 237*da58b97aSjoerg// other generic patterns to use in pattern matchings 238*da58b97aSjoergdef simm32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>; 239*da58b97aSjoergdef uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 240*da58b97aSjoergdef lomsbzero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0x80000000) 241*da58b97aSjoerg == 0; }]>; 242*da58b97aSjoergdef lozero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff) 243*da58b97aSjoerg == 0; }]>; 244*da58b97aSjoergdef fplomsbzero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0x80000000) 245*da58b97aSjoerg == 0; }]>; 246*da58b97aSjoergdef fplozero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0xffffffff) 247*da58b97aSjoerg == 0; }]>; 248*da58b97aSjoergdef nonzero : PatLeaf<(imm), [{ return N->getSExtValue() !=0 ; }]>; 249*da58b97aSjoerg 250*da58b97aSjoergdef CCSIOp : PatLeaf<(cond), [{ 251*da58b97aSjoerg switch (N->get()) { 252*da58b97aSjoerg default: return true; 253*da58b97aSjoerg case ISD::SETULT: 254*da58b97aSjoerg case ISD::SETULE: 255*da58b97aSjoerg case ISD::SETUGT: 256*da58b97aSjoerg case ISD::SETUGE: return false; 257*da58b97aSjoerg } 258*da58b97aSjoerg}]>; 259*da58b97aSjoerg 260*da58b97aSjoergdef CCUIOp : PatLeaf<(cond), [{ 261*da58b97aSjoerg switch (N->get()) { 262*da58b97aSjoerg default: return true; 263*da58b97aSjoerg case ISD::SETLT: 264*da58b97aSjoerg case ISD::SETLE: 265*da58b97aSjoerg case ISD::SETGT: 266*da58b97aSjoerg case ISD::SETGE: return false; 267*da58b97aSjoerg } 268*da58b97aSjoerg}]>; 269*da58b97aSjoerg 270*da58b97aSjoerg//===----------------------------------------------------------------------===// 271*da58b97aSjoerg// Addressing modes. 272*da58b97aSjoerg// SX-Aurora has following fields. 273*da58b97aSjoerg// sz: register or 0 274*da58b97aSjoerg// sy: register or immediate (-64 to 63) 275*da58b97aSjoerg// disp: immediate (-2147483648 to 2147483647) 276*da58b97aSjoerg// 277*da58b97aSjoerg// There are two kinds of instruction. 278*da58b97aSjoerg// ASX format uses sz + sy + disp. 279*da58b97aSjoerg// AS format uses sz + disp. 280*da58b97aSjoerg// 281*da58b97aSjoerg// Moreover, there are four kinds of assembly instruction format. 282*da58b97aSjoerg// ASX format uses "disp", "disp(, sz)", "disp(sy)", "disp(sy, sz)", 283*da58b97aSjoerg// "(, sz)", "(sy)", or "(sy, sz)". 284*da58b97aSjoerg// AS format uses "disp", "disp(, sz)", or "(, sz)" in general. 285*da58b97aSjoerg// AS format in RRM format uses "disp", "disp(sz)", or "(sz)". 286*da58b97aSjoerg// AS format in RRM format for host memory access uses "sz", "(sz)", 287*da58b97aSjoerg// or "disp(sz)". 288*da58b97aSjoerg// 289*da58b97aSjoerg// We defined them below. 290*da58b97aSjoerg// 291*da58b97aSjoerg// ASX format: 292*da58b97aSjoerg// MEMrri, MEMrii, MEMzri, MEMzii 293*da58b97aSjoerg// AS format: 294*da58b97aSjoerg// MEMriASX, MEMziASX : simple AS format 295*da58b97aSjoerg// MEMriRRM, MEMziRRM : AS format in RRM format 296*da58b97aSjoerg// MEMriHM, MEMziHM : AS format in RRM format for host memory access 297*da58b97aSjoerg//===----------------------------------------------------------------------===// 298*da58b97aSjoerg 299*da58b97aSjoerg// DAG selections for both ASX and AS formats. 300*da58b97aSjoergdef ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>; 301*da58b97aSjoergdef ADDRrii : ComplexPattern<iPTR, 3, "selectADDRrii", [frameindex], []>; 302*da58b97aSjoergdef ADDRzri : ComplexPattern<iPTR, 3, "selectADDRzri", [], []>; 303*da58b97aSjoergdef ADDRzii : ComplexPattern<iPTR, 3, "selectADDRzii", [], []>; 304*da58b97aSjoergdef ADDRri : ComplexPattern<iPTR, 2, "selectADDRri", [frameindex], []>; 305*da58b97aSjoergdef ADDRzi : ComplexPattern<iPTR, 2, "selectADDRzi", [], []>; 306*da58b97aSjoerg 307*da58b97aSjoerg// ASX format. 308*da58b97aSjoergdef VEMEMrriAsmOperand : AsmOperandClass { 309*da58b97aSjoerg let Name = "MEMrri"; 310*da58b97aSjoerg let ParserMethod = "parseMEMOperand"; 311*da58b97aSjoerg} 312*da58b97aSjoergdef VEMEMriiAsmOperand : AsmOperandClass { 313*da58b97aSjoerg let Name = "MEMrii"; 314*da58b97aSjoerg let ParserMethod = "parseMEMOperand"; 315*da58b97aSjoerg} 316*da58b97aSjoergdef VEMEMzriAsmOperand : AsmOperandClass { 317*da58b97aSjoerg let Name = "MEMzri"; 318*da58b97aSjoerg let ParserMethod = "parseMEMOperand"; 319*da58b97aSjoerg} 320*da58b97aSjoergdef VEMEMziiAsmOperand : AsmOperandClass { 321*da58b97aSjoerg let Name = "MEMzii"; 322*da58b97aSjoerg let ParserMethod = "parseMEMOperand"; 323*da58b97aSjoerg} 324*da58b97aSjoerg 325*da58b97aSjoerg// ASX format uses single assembly instruction format. 326*da58b97aSjoergdef MEMrri : Operand<iPTR> { 327*da58b97aSjoerg let PrintMethod = "printMemASXOperand"; 328*da58b97aSjoerg let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm); 329*da58b97aSjoerg let ParserMatchClass = VEMEMrriAsmOperand; 330*da58b97aSjoerg} 331*da58b97aSjoergdef MEMrii : Operand<iPTR> { 332*da58b97aSjoerg let PrintMethod = "printMemASXOperand"; 333*da58b97aSjoerg let MIOperandInfo = (ops ptr_rc, i32imm, i32imm); 334*da58b97aSjoerg let ParserMatchClass = VEMEMriiAsmOperand; 335*da58b97aSjoerg} 336*da58b97aSjoergdef MEMzri : Operand<iPTR> { 337*da58b97aSjoerg let PrintMethod = "printMemASXOperand"; 338*da58b97aSjoerg let MIOperandInfo = (ops i32imm /* = 0 */, ptr_rc, i32imm); 339*da58b97aSjoerg let ParserMatchClass = VEMEMzriAsmOperand; 340*da58b97aSjoerg} 341*da58b97aSjoergdef MEMzii : Operand<iPTR> { 342*da58b97aSjoerg let PrintMethod = "printMemASXOperand"; 343*da58b97aSjoerg let MIOperandInfo = (ops i32imm /* = 0 */, i32imm, i32imm); 344*da58b97aSjoerg let ParserMatchClass = VEMEMziiAsmOperand; 345*da58b97aSjoerg} 346*da58b97aSjoerg 347*da58b97aSjoerg// AS format. 348*da58b97aSjoergdef VEMEMriAsmOperand : AsmOperandClass { 349*da58b97aSjoerg let Name = "MEMri"; 350*da58b97aSjoerg let ParserMethod = "parseMEMAsOperand"; 351*da58b97aSjoerg} 352*da58b97aSjoergdef VEMEMziAsmOperand : AsmOperandClass { 353*da58b97aSjoerg let Name = "MEMzi"; 354*da58b97aSjoerg let ParserMethod = "parseMEMAsOperand"; 355*da58b97aSjoerg} 356*da58b97aSjoerg 357*da58b97aSjoerg// AS format uses multiple assembly instruction formats 358*da58b97aSjoerg// 1. AS generic assembly instruction format: 359*da58b97aSjoergdef MEMriASX : Operand<iPTR> { 360*da58b97aSjoerg let PrintMethod = "printMemASOperandASX"; 361*da58b97aSjoerg let MIOperandInfo = (ops ptr_rc, i32imm); 362*da58b97aSjoerg let ParserMatchClass = VEMEMriAsmOperand; 363*da58b97aSjoerg} 364*da58b97aSjoergdef MEMziASX : Operand<iPTR> { 365*da58b97aSjoerg let PrintMethod = "printMemASOperandASX"; 366*da58b97aSjoerg let MIOperandInfo = (ops i32imm /* = 0 */, i32imm); 367*da58b97aSjoerg let ParserMatchClass = VEMEMziAsmOperand; 368*da58b97aSjoerg} 369*da58b97aSjoerg 370*da58b97aSjoerg// 2. AS RRM style assembly instruction format: 371*da58b97aSjoergdef MEMriRRM : Operand<iPTR> { 372*da58b97aSjoerg let PrintMethod = "printMemASOperandRRM"; 373*da58b97aSjoerg let MIOperandInfo = (ops ptr_rc, i32imm); 374*da58b97aSjoerg let ParserMatchClass = VEMEMriAsmOperand; 375*da58b97aSjoerg} 376*da58b97aSjoergdef MEMziRRM : Operand<iPTR> { 377*da58b97aSjoerg let PrintMethod = "printMemASOperandRRM"; 378*da58b97aSjoerg let MIOperandInfo = (ops i32imm /* = 0 */, i32imm); 379*da58b97aSjoerg let ParserMatchClass = VEMEMziAsmOperand; 380*da58b97aSjoerg} 381*da58b97aSjoerg 382*da58b97aSjoerg// 3. AS HM style assembly instruction format: 383*da58b97aSjoergdef MEMriHM : Operand<iPTR> { 384*da58b97aSjoerg let PrintMethod = "printMemASOperandHM"; 385*da58b97aSjoerg let MIOperandInfo = (ops ptr_rc, i32imm); 386*da58b97aSjoerg let ParserMatchClass = VEMEMriAsmOperand; 387*da58b97aSjoerg} 388*da58b97aSjoergdef MEMziHM : Operand<iPTR> { 389*da58b97aSjoerg let PrintMethod = "printMemASOperandHM"; 390*da58b97aSjoerg let MIOperandInfo = (ops i32imm /* = 0 */, i32imm); 391*da58b97aSjoerg let ParserMatchClass = VEMEMziAsmOperand; 392*da58b97aSjoerg} 393*da58b97aSjoerg 394*da58b97aSjoerg//===----------------------------------------------------------------------===// 395*da58b97aSjoerg// Other operands. 396*da58b97aSjoerg//===----------------------------------------------------------------------===// 397*da58b97aSjoerg 398*da58b97aSjoerg// Branch targets have OtherVT type. 399*da58b97aSjoergdef brtarget32 : Operand<OtherVT> { 400*da58b97aSjoerg let EncoderMethod = "getBranchTargetOpValue"; 401*da58b97aSjoerg let DecoderMethod = "DecodeSIMM32"; 402*da58b97aSjoerg} 403*da58b97aSjoerg 404*da58b97aSjoerg// Operand for printing out a condition code. 405*da58b97aSjoergdef CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; } 406*da58b97aSjoergdef CCOp : Operand<i32>, ImmLeaf<i32, [{ 407*da58b97aSjoerg return Imm >= 0 && Imm < 22; }], CCOP> { 408*da58b97aSjoerg let PrintMethod = "printCCOperand"; 409*da58b97aSjoerg let DecoderMethod = "DecodeCCOperand"; 410*da58b97aSjoerg let EncoderMethod = "getCCOpValue"; 411*da58b97aSjoerg let ParserMatchClass = CCOpAsmOperand; 412*da58b97aSjoerg} 413*da58b97aSjoerg 414*da58b97aSjoerg// Operand for a rounding mode code. 415*da58b97aSjoergdef RDOpAsmOperand : AsmOperandClass { 416*da58b97aSjoerg let Name = "RDOp"; 417*da58b97aSjoerg} 418*da58b97aSjoergdef RDOp : Operand<i32> { 419*da58b97aSjoerg let PrintMethod = "printRDOperand"; 420*da58b97aSjoerg let DecoderMethod = "DecodeRDOperand"; 421*da58b97aSjoerg let EncoderMethod = "getRDOpValue"; 422*da58b97aSjoerg let ParserMatchClass = RDOpAsmOperand; 423*da58b97aSjoerg} 424*da58b97aSjoerg 425*da58b97aSjoergdef VEhi : SDNode<"VEISD::Hi", SDTIntUnaryOp>; 426*da58b97aSjoergdef VElo : SDNode<"VEISD::Lo", SDTIntUnaryOp>; 427*da58b97aSjoerg 428*da58b97aSjoerg// These are target-independent nodes, but have target-specific formats. 429*da58b97aSjoergdef SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64>, 430*da58b97aSjoerg SDTCisVT<1, i64> ]>; 431*da58b97aSjoergdef SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i64>, 432*da58b97aSjoerg SDTCisVT<1, i64> ]>; 433*da58b97aSjoerg 434*da58b97aSjoergdef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 435*da58b97aSjoerg [SDNPHasChain, SDNPOutGlue]>; 436*da58b97aSjoergdef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 437*da58b97aSjoerg [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 438*da58b97aSjoerg 439*da58b97aSjoergdef SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i64>]>; 440*da58b97aSjoergdef call : SDNode<"VEISD::CALL", SDT_SPCall, 441*da58b97aSjoerg [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 442*da58b97aSjoerg SDNPVariadic]>; 443*da58b97aSjoerg 444*da58b97aSjoergdef retflag : SDNode<"VEISD::RET_FLAG", SDTNone, 445*da58b97aSjoerg [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 446*da58b97aSjoerg 447*da58b97aSjoergdef getGOT : Operand<iPTR>; 448*da58b97aSjoerg 449*da58b97aSjoergdef VEeh_sjlj_setjmp: SDNode<"VEISD::EH_SJLJ_SETJMP", 450*da58b97aSjoerg SDTypeProfile<1, 1, [SDTCisInt<0>, 451*da58b97aSjoerg SDTCisPtrTy<1>]>, 452*da58b97aSjoerg [SDNPHasChain, SDNPSideEffect]>; 453*da58b97aSjoergdef VEeh_sjlj_longjmp: SDNode<"VEISD::EH_SJLJ_LONGJMP", 454*da58b97aSjoerg SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 455*da58b97aSjoerg [SDNPHasChain, SDNPSideEffect]>; 456*da58b97aSjoergdef VEeh_sjlj_setup_dispatch: SDNode<"VEISD::EH_SJLJ_SETUP_DISPATCH", 457*da58b97aSjoerg SDTypeProfile<0, 0, []>, 458*da58b97aSjoerg [SDNPHasChain, SDNPSideEffect]>; 459*da58b97aSjoerg 460*da58b97aSjoerg// GETFUNPLT for PIC 461*da58b97aSjoergdef GetFunPLT : SDNode<"VEISD::GETFUNPLT", SDTIntUnaryOp>; 462*da58b97aSjoerg 463*da58b97aSjoerg// GETTLSADDR for TLS 464*da58b97aSjoergdef GetTLSAddr : SDNode<"VEISD::GETTLSADDR", SDT_SPCall, 465*da58b97aSjoerg [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 466*da58b97aSjoerg SDNPVariadic]>; 467*da58b97aSjoerg 468*da58b97aSjoerg// GETSTACKTOP 469*da58b97aSjoergdef GetStackTop : SDNode<"VEISD::GETSTACKTOP", SDTNone, 470*da58b97aSjoerg [SDNPHasChain, SDNPSideEffect]>; 471*da58b97aSjoerg 472*da58b97aSjoerg// MEMBARRIER 473*da58b97aSjoergdef MemBarrier : SDNode<"VEISD::MEMBARRIER", SDTNone, 474*da58b97aSjoerg [SDNPHasChain, SDNPSideEffect]>; 475*da58b97aSjoerg 476*da58b97aSjoerg// TS1AM 477*da58b97aSjoergdef SDT_TS1AM : SDTypeProfile<1, 3, [SDTCisSameAs<0, 3>, SDTCisPtrTy<1>, 478*da58b97aSjoerg SDTCisVT<2, i32>, SDTCisInt<3>]>; 479*da58b97aSjoergdef ts1am : SDNode<"VEISD::TS1AM", SDT_TS1AM, 480*da58b97aSjoerg [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 481*da58b97aSjoerg SDNPMemOperand]>; 482*da58b97aSjoerg 483*da58b97aSjoerg//===----------------------------------------------------------------------===// 484*da58b97aSjoerg// VE Flag Conditions 485*da58b97aSjoerg//===----------------------------------------------------------------------===// 486*da58b97aSjoerg 487*da58b97aSjoerg// Note that these values must be kept in sync with the CCOp::CondCode enum 488*da58b97aSjoerg// values. 489*da58b97aSjoergclass CC_VAL<int N> : PatLeaf<(i32 N)>; 490*da58b97aSjoergdef CC_IG : CC_VAL< 0>; // Greater 491*da58b97aSjoergdef CC_IL : CC_VAL< 1>; // Less 492*da58b97aSjoergdef CC_INE : CC_VAL< 2>; // Not Equal 493*da58b97aSjoergdef CC_IEQ : CC_VAL< 3>; // Equal 494*da58b97aSjoergdef CC_IGE : CC_VAL< 4>; // Greater or Equal 495*da58b97aSjoergdef CC_ILE : CC_VAL< 5>; // Less or Equal 496*da58b97aSjoergdef CC_AF : CC_VAL< 6>; // Always false 497*da58b97aSjoergdef CC_G : CC_VAL< 7>; // Greater 498*da58b97aSjoergdef CC_L : CC_VAL< 8>; // Less 499*da58b97aSjoergdef CC_NE : CC_VAL< 9>; // Not Equal 500*da58b97aSjoergdef CC_EQ : CC_VAL<10>; // Equal 501*da58b97aSjoergdef CC_GE : CC_VAL<11>; // Greater or Equal 502*da58b97aSjoergdef CC_LE : CC_VAL<12>; // Less or Equal 503*da58b97aSjoergdef CC_NUM : CC_VAL<13>; // Number 504*da58b97aSjoergdef CC_NAN : CC_VAL<14>; // NaN 505*da58b97aSjoergdef CC_GNAN : CC_VAL<15>; // Greater or NaN 506*da58b97aSjoergdef CC_LNAN : CC_VAL<16>; // Less or NaN 507*da58b97aSjoergdef CC_NENAN : CC_VAL<17>; // Not Equal or NaN 508*da58b97aSjoergdef CC_EQNAN : CC_VAL<18>; // Equal or NaN 509*da58b97aSjoergdef CC_GENAN : CC_VAL<19>; // Greater or Equal or NaN 510*da58b97aSjoergdef CC_LENAN : CC_VAL<20>; // Less or Equal or NaN 511*da58b97aSjoergdef CC_AT : CC_VAL<21>; // Always true 512*da58b97aSjoerg 513*da58b97aSjoerg//===----------------------------------------------------------------------===// 514*da58b97aSjoerg// VE Rounding Mode 515*da58b97aSjoerg//===----------------------------------------------------------------------===// 516*da58b97aSjoerg 517*da58b97aSjoerg// Note that these values must be kept in sync with the VERD::RoundingMode enum 518*da58b97aSjoerg// values. 519*da58b97aSjoergclass RD_VAL<int N> : PatLeaf<(i32 N)>; 520*da58b97aSjoergdef RD_NONE : RD_VAL< 0>; // According to PSW 521*da58b97aSjoergdef RD_RZ : RD_VAL< 8>; // Round toward Zero 522*da58b97aSjoergdef RD_RP : RD_VAL< 9>; // Round toward Plus infinity 523*da58b97aSjoergdef RD_RM : RD_VAL<10>; // Round toward Minus infinity 524*da58b97aSjoergdef RD_RN : RD_VAL<11>; // Round to Nearest (ties to Even) 525*da58b97aSjoergdef RD_RA : RD_VAL<12>; // Round to Nearest (ties to Away) 526*da58b97aSjoerg 527*da58b97aSjoerg//===----------------------------------------------------------------------===// 528*da58b97aSjoerg// VE Multiclasses for common instruction formats 529*da58b97aSjoerg//===----------------------------------------------------------------------===// 530*da58b97aSjoerg 531*da58b97aSjoerg// Multiclass for generic RR type instructions 532*da58b97aSjoerglet hasSideEffects = 0 in 533*da58b97aSjoergmulticlass RRbm<string opcStr, bits<8>opc, 534*da58b97aSjoerg RegisterClass RCo, ValueType Tyo, 535*da58b97aSjoerg RegisterClass RCi, ValueType Tyi, 536*da58b97aSjoerg SDPatternOperator OpNode = null_frag, 537*da58b97aSjoerg Operand immOp = simm7, Operand mOp = mimm, 538*da58b97aSjoerg bit MoveImm = 0> { 539*da58b97aSjoerg def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz), 540*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 541*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>; 542*da58b97aSjoerg // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate 543*da58b97aSjoerg // in RHS, so we use following definition. 544*da58b97aSjoerg let cy = 0 in 545*da58b97aSjoerg def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy), 546*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 547*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>; 548*da58b97aSjoerg let cz = 0 in 549*da58b97aSjoerg def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz), 550*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 551*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>; 552*da58b97aSjoerg let cy = 0, cz = 0 in 553*da58b97aSjoerg def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz), 554*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 555*da58b97aSjoerg [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> { 556*da58b97aSjoerg // VE uses ORim as a move immediate instruction, so declare it here. 557*da58b97aSjoerg // An instruction declared as MoveImm will be optimized in FoldImmediate 558*da58b97aSjoerg // later. 559*da58b97aSjoerg let isMoveImm = MoveImm; 560*da58b97aSjoerg } 561*da58b97aSjoerg} 562*da58b97aSjoerg 563*da58b97aSjoerg// Multiclass for non-commutative RR type instructions 564*da58b97aSjoerglet hasSideEffects = 0 in 565*da58b97aSjoergmulticlass RRNCbm<string opcStr, bits<8>opc, 566*da58b97aSjoerg RegisterClass RCo, ValueType Tyo, 567*da58b97aSjoerg RegisterClass RCi, ValueType Tyi, 568*da58b97aSjoerg SDPatternOperator OpNode = null_frag, 569*da58b97aSjoerg Operand immOp = simm7, Operand mOp = mimm> { 570*da58b97aSjoerg def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz), 571*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 572*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>; 573*da58b97aSjoerg let cy = 0 in 574*da58b97aSjoerg def ir : RR<opc, (outs RCo:$sx), (ins immOp:$sy, RCi:$sz), 575*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 576*da58b97aSjoerg [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), Tyi:$sz))]>; 577*da58b97aSjoerg let cz = 0 in 578*da58b97aSjoerg def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz), 579*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 580*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>; 581*da58b97aSjoerg let cy = 0, cz = 0 in 582*da58b97aSjoerg def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz), 583*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz"), 584*da58b97aSjoerg [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]>; 585*da58b97aSjoerg} 586*da58b97aSjoerg 587*da58b97aSjoerg// Generic RR multiclass with 2 arguments. 588*da58b97aSjoerg// e.g. ADDUL, ADDSWSX, ADDSWZX, and etc. 589*da58b97aSjoergmulticlass RRm<string opcStr, bits<8>opc, 590*da58b97aSjoerg RegisterClass RC, ValueType Ty, 591*da58b97aSjoerg SDPatternOperator OpNode = null_frag, 592*da58b97aSjoerg Operand immOp = simm7, Operand mOp = mimm, bit MoveImm = 0> : 593*da58b97aSjoerg RRbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp, MoveImm>; 594*da58b97aSjoerg 595*da58b97aSjoerg// Generic RR multiclass for non-commutative instructions with 2 arguments. 596*da58b97aSjoerg// e.g. SUBUL, SUBUW, SUBSWSX, and etc. 597*da58b97aSjoergmulticlass RRNCm<string opcStr, bits<8>opc, 598*da58b97aSjoerg RegisterClass RC, ValueType Ty, 599*da58b97aSjoerg SDPatternOperator OpNode = null_frag, 600*da58b97aSjoerg Operand immOp = simm7, Operand mOp = mimm> : 601*da58b97aSjoerg RRNCbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>; 602*da58b97aSjoerg 603*da58b97aSjoerg// Generic RR multiclass for floating point instructions with 2 arguments. 604*da58b97aSjoerg// e.g. FADDD, FADDS, FSUBD, and etc. 605*da58b97aSjoergmulticlass RRFm<string opcStr, bits<8>opc, 606*da58b97aSjoerg RegisterClass RC, ValueType Ty, 607*da58b97aSjoerg SDPatternOperator OpNode = null_frag, 608*da58b97aSjoerg Operand immOp = simm7fp, Operand mOp = mimmfp> : 609*da58b97aSjoerg RRNCbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>; 610*da58b97aSjoerg 611*da58b97aSjoerg// Generic RR multiclass for shift instructions with 2 arguments. 612*da58b97aSjoerg// e.g. SLL, SRL, SLAWSX, and etc. 613*da58b97aSjoerglet hasSideEffects = 0 in 614*da58b97aSjoergmulticlass RRIm<string opcStr, bits<8>opc, 615*da58b97aSjoerg RegisterClass RC, ValueType Ty, 616*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 617*da58b97aSjoerg def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, I32:$sy), 618*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 619*da58b97aSjoerg [(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]>; 620*da58b97aSjoerg let cz = 0 in 621*da58b97aSjoerg def mr : RR<opc, (outs RC:$sx), (ins mimm:$sz, I32:$sy), 622*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 623*da58b97aSjoerg [(set Ty:$sx, (OpNode (Ty mimm:$sz), i32:$sy))]>; 624*da58b97aSjoerg let cy = 0 in 625*da58b97aSjoerg def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy), 626*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 627*da58b97aSjoerg [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>; 628*da58b97aSjoerg let cy = 0, cz = 0 in 629*da58b97aSjoerg def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy), 630*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 631*da58b97aSjoerg [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>; 632*da58b97aSjoerg} 633*da58b97aSjoerg 634*da58b97aSjoerg// Special RR multiclass for 128 bits shift left instruction. 635*da58b97aSjoerg// e.g. SLD 636*da58b97aSjoerglet Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in 637*da58b97aSjoergmulticlass RRILDm<string opcStr, bits<8>opc, 638*da58b97aSjoerg RegisterClass RC, ValueType Ty, 639*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 640*da58b97aSjoerg def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy), 641*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 642*da58b97aSjoerg let cz = 0 in 643*da58b97aSjoerg def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy), 644*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 645*da58b97aSjoerg let cy = 0 in 646*da58b97aSjoerg def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy), 647*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 648*da58b97aSjoerg let cy = 0, cz = 0 in 649*da58b97aSjoerg def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy), 650*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 651*da58b97aSjoerg} 652*da58b97aSjoerg 653*da58b97aSjoerg// Special RR multiclass for 128 bits shift right instruction. 654*da58b97aSjoerg// e.g. SRD 655*da58b97aSjoerglet Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in 656*da58b97aSjoergmulticlass RRIRDm<string opcStr, bits<8>opc, 657*da58b97aSjoerg RegisterClass RC, ValueType Ty, 658*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 659*da58b97aSjoerg def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy), 660*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 661*da58b97aSjoerg let cz = 0 in 662*da58b97aSjoerg def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy), 663*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 664*da58b97aSjoerg let cy = 0 in 665*da58b97aSjoerg def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy), 666*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 667*da58b97aSjoerg let cy = 0, cz = 0 in 668*da58b97aSjoerg def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy), 669*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 670*da58b97aSjoerg} 671*da58b97aSjoerg 672*da58b97aSjoerg// Generic RR multiclass with an argument. 673*da58b97aSjoerg// e.g. LDZ, PCNT, and BRV 674*da58b97aSjoerglet cy = 0, sy = 0, hasSideEffects = 0 in 675*da58b97aSjoergmulticlass RRI1m<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty, 676*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 677*da58b97aSjoerg def r : RR<opc, (outs RC:$sx), (ins RC:$sz), !strconcat(opcStr, " $sx, $sz"), 678*da58b97aSjoerg [(set Ty:$sx, (OpNode Ty:$sz))]>; 679*da58b97aSjoerg let cz = 0 in 680*da58b97aSjoerg def m : RR<opc, (outs RC:$sx), (ins mimm:$sz), 681*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz"), 682*da58b97aSjoerg [(set Ty:$sx, (OpNode (Ty mimm:$sz)))]>; 683*da58b97aSjoerg} 684*da58b97aSjoerg 685*da58b97aSjoerg// Special RR multiclass for MRG instruction. 686*da58b97aSjoerg// e.g. MRG 687*da58b97aSjoerglet Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0 in 688*da58b97aSjoergmulticlass RRMRGm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty> { 689*da58b97aSjoerg def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sd), 690*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 691*da58b97aSjoerg let cy = 0 in 692*da58b97aSjoerg def ir : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz, RC:$sd), 693*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 694*da58b97aSjoerg let cz = 0 in 695*da58b97aSjoerg def rm : RR<opc, (outs RC:$sx), (ins RC:$sy, mimm:$sz, RC:$sd), 696*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 697*da58b97aSjoerg let cy = 0, cz = 0 in 698*da58b97aSjoerg def im : RR<opc, (outs RC:$sx), (ins simm7:$sy, mimm:$sz, RC:$sd), 699*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 700*da58b97aSjoerg} 701*da58b97aSjoerg 702*da58b97aSjoerg// Special RR multiclass for BSWP instruction. 703*da58b97aSjoerg// e.g. BSWP 704*da58b97aSjoerglet hasSideEffects = 0 in 705*da58b97aSjoergmulticlass RRSWPm<string opcStr, bits<8>opc, 706*da58b97aSjoerg RegisterClass RC, ValueType Ty, 707*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 708*da58b97aSjoerg let cy = 0 in 709*da58b97aSjoerg def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm1:$sy), 710*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 711*da58b97aSjoerg [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm1:$sy)))]>; 712*da58b97aSjoerg let cy = 0, cz = 0 in 713*da58b97aSjoerg def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm1:$sy), 714*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy"), 715*da58b97aSjoerg [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm1:$sy)))]>; 716*da58b97aSjoerg} 717*da58b97aSjoerg 718*da58b97aSjoerg// Multiclass for CMOV instructions. 719*da58b97aSjoerg// e.g. CMOVL, CMOVW, CMOVD, and etc. 720*da58b97aSjoerglet Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0, 721*da58b97aSjoerg cfw = ? in 722*da58b97aSjoergmulticlass RRCMOVm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty> { 723*da58b97aSjoerg def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd), 724*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 725*da58b97aSjoerg let cy = 0 in 726*da58b97aSjoerg def ir : RR<opc, (outs I64:$sx), 727*da58b97aSjoerg (ins CCOp:$cfw, simm7:$sy, I64:$sz, I64:$sd), 728*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 729*da58b97aSjoerg let cz = 0 in 730*da58b97aSjoerg def rm : RR<opc, (outs I64:$sx), 731*da58b97aSjoerg (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd), 732*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 733*da58b97aSjoerg let cy = 0, cz = 0 in 734*da58b97aSjoerg def im : RR<opc, (outs I64:$sx), 735*da58b97aSjoerg (ins CCOp:$cfw, simm7:$sy, mimm:$sz, I64:$sd), 736*da58b97aSjoerg !strconcat(opcStr, " $sx, $sz, $sy")>; 737*da58b97aSjoerg} 738*da58b97aSjoerg 739*da58b97aSjoerg// Multiclass for floating point conversion instructions. 740*da58b97aSjoerg// e.g. CVTWDSX, CVTWDZX, CVTWSSX, and etc. 741*da58b97aSjoerg// sz{3-0} = rounding mode 742*da58b97aSjoerglet cz = 0, hasSideEffects = 0 in 743*da58b97aSjoergmulticlass CVTRDm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo, 744*da58b97aSjoerg RegisterClass RCi, ValueType Tyi> { 745*da58b97aSjoerg def r : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, RCi:$sy), 746*da58b97aSjoerg !strconcat(opcStr, "${rd} $sx, $sy")> { 747*da58b97aSjoerg bits<4> rd; 748*da58b97aSjoerg let sz{5-4} = 0; 749*da58b97aSjoerg let sz{3-0} = rd; 750*da58b97aSjoerg } 751*da58b97aSjoerg let cy = 0 in 752*da58b97aSjoerg def i : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, simm7:$sy), 753*da58b97aSjoerg !strconcat(opcStr, "${rd} $sx, $sy")> { 754*da58b97aSjoerg bits<4> rd; 755*da58b97aSjoerg let sz{5-4} = 0; 756*da58b97aSjoerg let sz{3-0} = rd; 757*da58b97aSjoerg } 758*da58b97aSjoerg} 759*da58b97aSjoerg 760*da58b97aSjoerg// Multiclass for floating point conversion instructions. 761*da58b97aSjoerg// e.g. CVTDW, CVTSW, CVTDL, and etc. 762*da58b97aSjoerglet cz = 0, sz = 0, hasSideEffects = 0 in 763*da58b97aSjoergmulticlass CVTm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo, 764*da58b97aSjoerg RegisterClass RCi, ValueType Tyi, 765*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 766*da58b97aSjoerg def r : RR<opc, (outs RCo:$sx), (ins RCi:$sy), 767*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy"), 768*da58b97aSjoerg [(set Tyo:$sx, (OpNode Tyi:$sy))]>; 769*da58b97aSjoerg let cy = 0 in 770*da58b97aSjoerg def i : RR<opc, (outs RCo:$sx), (ins simm7:$sy), 771*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy")>; 772*da58b97aSjoerg} 773*da58b97aSjoerg 774*da58b97aSjoerg// Multiclass for PFCH instructions. 775*da58b97aSjoerg// e.g. PFCH 776*da58b97aSjoerglet sx = 0, hasSideEffects = 0 in 777*da58b97aSjoergmulticlass PFCHm<string opcStr, bits<8>opc> { 778*da58b97aSjoerg def rri : RM<opc, (outs), (ins MEMrri:$addr), !strconcat(opcStr, " $addr"), 779*da58b97aSjoerg [(prefetch ADDRrri:$addr, imm, imm, (i32 1))]>; 780*da58b97aSjoerg let cy = 0 in 781*da58b97aSjoerg def rii : RM<opc, (outs), (ins MEMrii:$addr), !strconcat(opcStr, " $addr"), 782*da58b97aSjoerg [(prefetch ADDRrii:$addr, imm, imm, (i32 1))]>; 783*da58b97aSjoerg let cz = 0 in 784*da58b97aSjoerg def zri : RM<opc, (outs), (ins MEMzri:$addr), !strconcat(opcStr, " $addr"), 785*da58b97aSjoerg [(prefetch ADDRzri:$addr, imm, imm, (i32 1))]>; 786*da58b97aSjoerg let cy = 0, cz = 0 in 787*da58b97aSjoerg def zii : RM<opc, (outs), (ins MEMzii:$addr), !strconcat(opcStr, " $addr"), 788*da58b97aSjoerg [(prefetch ADDRzii:$addr, imm, imm, (i32 1))]>; 789*da58b97aSjoerg} 790*da58b97aSjoerg 791*da58b97aSjoerg// Multiclass for CAS instructions. 792*da58b97aSjoerg// e.g. TS1AML, TS1AMW, TS2AM, and etc. 793*da58b97aSjoerglet Constraints = "$dest = $sd", DisableEncoding = "$sd", 794*da58b97aSjoerg mayStore=1, mayLoad = 1, hasSideEffects = 0 in 795*da58b97aSjoergmulticlass RRCAStgm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty, 796*da58b97aSjoerg Operand immOp, Operand MEM, ComplexPattern ADDR, 797*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 798*da58b97aSjoerg def r : RRM<opc, (outs RC:$dest), (ins MEM:$addr, RC:$sy, RC:$sd), 799*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr, $sy"), 800*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>; 801*da58b97aSjoerg let cy = 0 in 802*da58b97aSjoerg def i : RRM<opc, (outs RC:$dest), (ins MEM:$addr, immOp:$sy, RC:$sd), 803*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr, $sy"), 804*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>; 805*da58b97aSjoerg} 806*da58b97aSjoergmulticlass RRCASm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty, 807*da58b97aSjoerg Operand immOp, SDPatternOperator OpNode = null_frag> { 808*da58b97aSjoerg defm ri : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMriRRM, ADDRri, OpNode>; 809*da58b97aSjoerg let cz = 0 in 810*da58b97aSjoerg defm zi : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMziRRM, ADDRzi, OpNode>; 811*da58b97aSjoerg} 812*da58b97aSjoerg 813*da58b97aSjoerg// Multiclass for branch instructions 814*da58b97aSjoerg// e.g. BCFL, BCFW, BCFD, and etc. 815*da58b97aSjoerglet isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in 816*da58b97aSjoergmulticlass BCbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond, 817*da58b97aSjoerg Operand ADDR> { 818*da58b97aSjoerg let bpf = 0 /* NONE */ in 819*da58b97aSjoerg def "" : CF<opc, (outs), !con(cond, (ins ADDR:$addr)), 820*da58b97aSjoerg !strconcat(opcStr, " ", cmpStr, "$addr")>; 821*da58b97aSjoerg let bpf = 2 /* NOT TAKEN */ in 822*da58b97aSjoerg def _nt : CF<opc, (outs), !con(cond, (ins ADDR:$addr)), 823*da58b97aSjoerg !strconcat(opcStr, ".nt ", cmpStr, "$addr")>; 824*da58b97aSjoerg let bpf = 3 /* TAKEN */ in 825*da58b97aSjoerg def _t : CF<opc, (outs), !con(cond, (ins ADDR:$addr)), 826*da58b97aSjoerg !strconcat(opcStr, ".t ", cmpStr, "$addr")>; 827*da58b97aSjoerg} 828*da58b97aSjoergmulticlass BCtgm<string opcStr, string cmpStr, bits<8> opc, dag cond> { 829*da58b97aSjoerg defm ri : BCbpfm<opcStr, cmpStr, opc, cond, MEMriASX>; 830*da58b97aSjoerg let cz = 0 in defm zi : BCbpfm<opcStr, cmpStr, opc, cond, MEMziASX>; 831*da58b97aSjoerg} 832*da58b97aSjoergmulticlass BCm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc, 833*da58b97aSjoerg RegisterClass RC, Operand immOp> { 834*da58b97aSjoerg let DecoderMethod = "DecodeBranchCondition" in 835*da58b97aSjoerg defm r : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, RC:$comp)>; 836*da58b97aSjoerg let DecoderMethod = "DecodeBranchCondition", cy = 0 in 837*da58b97aSjoerg defm i : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, immOp:$comp)>; 838*da58b97aSjoerg let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, 839*da58b97aSjoerg cf = 15 /* AT */, isBarrier = 1 in 840*da58b97aSjoerg defm a : BCtgm<opcStrAt, "", opc, (ins)>; 841*da58b97aSjoerg let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, 842*da58b97aSjoerg cf = 0 /* AF */ in 843*da58b97aSjoerg defm na : BCtgm<opcStrAf, "", opc, (ins)>; 844*da58b97aSjoerg} 845*da58b97aSjoerg 846*da58b97aSjoerg// Multiclass for relative branch instructions 847*da58b97aSjoerg// e.g. BRCFL, BRCFW, BRCFD, and etc. 848*da58b97aSjoerglet isBranch = 1, isTerminator = 1, hasSideEffects = 0 in 849*da58b97aSjoergmulticlass BCRbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond> { 850*da58b97aSjoerg let bpf = 0 /* NONE */ in 851*da58b97aSjoerg def "" : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)), 852*da58b97aSjoerg !strconcat(opcStr, " ", cmpStr, "$imm32")>; 853*da58b97aSjoerg let bpf = 2 /* NOT TAKEN */ in 854*da58b97aSjoerg def _nt : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)), 855*da58b97aSjoerg !strconcat(opcStr, ".nt ", cmpStr, "$imm32")>; 856*da58b97aSjoerg let bpf = 3 /* TAKEN */ in 857*da58b97aSjoerg def _t : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)), 858*da58b97aSjoerg !strconcat(opcStr, ".t ", cmpStr, "$imm32")>; 859*da58b97aSjoerg} 860*da58b97aSjoergmulticlass BCRm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc, 861*da58b97aSjoerg RegisterClass RC, Operand immOp, Operand zeroOp> { 862*da58b97aSjoerg defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, RC:$sz)>; 863*da58b97aSjoerg let cy = 0 in 864*da58b97aSjoerg defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy, 865*da58b97aSjoerg RC:$sz)>; 866*da58b97aSjoerg let cz = 0 in 867*da58b97aSjoerg defm rz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, 868*da58b97aSjoerg zeroOp:$sz)>; 869*da58b97aSjoerg let cy = 0, cz = 0 in 870*da58b97aSjoerg defm iz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy, 871*da58b97aSjoerg zeroOp:$sz)>; 872*da58b97aSjoerg let cy = 0, sy = 0, cz = 0, sz = 0, cf = 15 /* AT */, isBarrier = 1 in 873*da58b97aSjoerg defm a : BCRbpfm<opcStrAt, "", opc, (ins)>; 874*da58b97aSjoerg let cy = 0, sy = 0, cz = 0, sz = 0, cf = 0 /* AF */ in 875*da58b97aSjoerg defm na : BCRbpfm<opcStrAf, "", opc, (ins)>; 876*da58b97aSjoerg} 877*da58b97aSjoerg 878*da58b97aSjoerg// Multiclass for communication register instructions. 879*da58b97aSjoerg// e.g. LCR 880*da58b97aSjoerglet hasSideEffects = 1 in 881*da58b97aSjoergmulticlass LOADCRm<string opcStr, bits<8>opc, RegisterClass RC> { 882*da58b97aSjoerg def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$sy), 883*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 884*da58b97aSjoerg let cy = 0 in def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, simm7:$sy), 885*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 886*da58b97aSjoerg let cz = 0 in def zr : RR<opc, (outs RC:$sx), (ins zero:$sz, RC:$sy), 887*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 888*da58b97aSjoerg let cy = 0, cz = 0 in 889*da58b97aSjoerg def zi : RR<opc, (outs RC:$sx), (ins zero:$sz, simm7:$sy), 890*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 891*da58b97aSjoerg} 892*da58b97aSjoerg 893*da58b97aSjoerg// Multiclass for communication register instructions. 894*da58b97aSjoerg// e.g. SCR 895*da58b97aSjoerglet hasSideEffects = 1 in 896*da58b97aSjoergmulticlass STORECRm<string opcStr, bits<8>opc, RegisterClass RC> { 897*da58b97aSjoerg def rr : RR<opc, (outs), (ins RC:$sz, RC:$sy, RC:$sx), 898*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 899*da58b97aSjoerg let cy = 0 in def ri : RR<opc, (outs), (ins RC:$sz, simm7:$sy, RC:$sx), 900*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 901*da58b97aSjoerg let cz = 0 in def zr : RR<opc, (outs), (ins zero:$sz, RC:$sy, RC:$sx), 902*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 903*da58b97aSjoerg let cy = 0, cz = 0 in 904*da58b97aSjoerg def zi : RR<opc, (outs), (ins zero:$sz, simm7:$sy, RC:$sx), 905*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 906*da58b97aSjoerg} 907*da58b97aSjoerg 908*da58b97aSjoerg// Multiclass for communication register instructions. 909*da58b97aSjoerg// e.g. FIDCR 910*da58b97aSjoerglet cz = 0, hasSideEffects = 1 in 911*da58b97aSjoergmulticlass FIDCRm<string opcStr, bits<8>opc, RegisterClass RC> { 912*da58b97aSjoerg def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz), 913*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 914*da58b97aSjoerg let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz), 915*da58b97aSjoerg !strconcat(opcStr, " $sx, $sy, $sz")>; 916*da58b97aSjoerg} 917*da58b97aSjoerg 918*da58b97aSjoerg// Multiclass for LHM instruction. 919*da58b97aSjoerglet mayLoad = 1, hasSideEffects = 0 in 920*da58b97aSjoergmulticlass LHMm<string opcStr, bits<8> opc, RegisterClass RC> { 921*da58b97aSjoerg def ri : RRMHM<opc, (outs RC:$dest), (ins MEMriHM:$addr), 922*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr")>; 923*da58b97aSjoerg let cz = 0 in 924*da58b97aSjoerg def zi : RRMHM<opc, (outs RC:$dest), (ins MEMziHM:$addr), 925*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr")>; 926*da58b97aSjoerg} 927*da58b97aSjoerg 928*da58b97aSjoerg// Multiclass for SHM instruction. 929*da58b97aSjoerglet mayStore = 1, hasSideEffects = 0 in 930*da58b97aSjoergmulticlass SHMm<string opcStr, bits<8> opc, RegisterClass RC> { 931*da58b97aSjoerg def ri : RRMHM<opc, (outs), (ins MEMriHM:$addr, RC:$sx), 932*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr")>; 933*da58b97aSjoerg let cz = 0 in 934*da58b97aSjoerg def zi : RRMHM<opc, (outs), (ins MEMziHM:$addr, RC:$sx), 935*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr")>; 936*da58b97aSjoerg} 937*da58b97aSjoerg 938*da58b97aSjoerg//===----------------------------------------------------------------------===// 939*da58b97aSjoerg// Instructions 940*da58b97aSjoerg// 941*da58b97aSjoerg// Define all scalar instructions defined in SX-Aurora TSUBASA Architecture 942*da58b97aSjoerg// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine 943*da58b97aSjoerg// Assembly Language Reference Manual. 944*da58b97aSjoerg//===----------------------------------------------------------------------===// 945*da58b97aSjoerg 946*da58b97aSjoerg//----------------------------------------------------------------------------- 947*da58b97aSjoerg// Section 8.2 - Load/Store instructions 948*da58b97aSjoerg//----------------------------------------------------------------------------- 949*da58b97aSjoerg 950*da58b97aSjoerg// Multiclass for generic RM instructions 951*da58b97aSjoergmulticlass RMm<string opcStr, bits<8>opc, RegisterClass RC, bit MoveImm = 0> { 952*da58b97aSjoerg def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr), 953*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), []>; 954*da58b97aSjoerg let cy = 0 in 955*da58b97aSjoerg def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr), 956*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), []>; 957*da58b97aSjoerg let cz = 0 in 958*da58b97aSjoerg def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr), 959*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), []>; 960*da58b97aSjoerg let cy = 0, cz = 0 in 961*da58b97aSjoerg def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr), 962*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), []> { 963*da58b97aSjoerg // VE uses LEAzii and LEASLzii as a move immediate instruction, so declare 964*da58b97aSjoerg // it here. An instruction declared as MoveImm will be optimized in 965*da58b97aSjoerg // FoldImmediate later. 966*da58b97aSjoerg let isMoveImm = MoveImm; 967*da58b97aSjoerg } 968*da58b97aSjoerg} 969*da58b97aSjoerg 970*da58b97aSjoerg// Section 8.2.1 - LEA 971*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1, 972*da58b97aSjoerg DecoderMethod = "DecodeLoadI64" in { 973*da58b97aSjoerg let cx = 0 in defm LEA : RMm<"lea", 0x06, I64, /* MoveImm */ 1>; 974*da58b97aSjoerg let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64, /* MoveImm */ 1>; 975*da58b97aSjoerg} 976*da58b97aSjoerg 977*da58b97aSjoerg// LEA basic patterns. 978*da58b97aSjoerg// Need to be defined here to prioritize LEA over ADX. 979*da58b97aSjoergdef : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>; 980*da58b97aSjoergdef : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>; 981*da58b97aSjoergdef : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>; 982*da58b97aSjoergdef : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>; 983*da58b97aSjoerg 984*da58b97aSjoerg// Multiclass for load instructions. 985*da58b97aSjoerglet mayLoad = 1, hasSideEffects = 0 in 986*da58b97aSjoergmulticlass LOADm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty, 987*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 988*da58b97aSjoerg def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr), 989*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), 990*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDRrri:$addr))]>; 991*da58b97aSjoerg let cy = 0 in 992*da58b97aSjoerg def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr), 993*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), 994*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDRrii:$addr))]>; 995*da58b97aSjoerg let cz = 0 in 996*da58b97aSjoerg def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr), 997*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), 998*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDRzri:$addr))]>; 999*da58b97aSjoerg let cy = 0, cz = 0 in 1000*da58b97aSjoerg def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr), 1001*da58b97aSjoerg !strconcat(opcStr, " $dest, $addr"), 1002*da58b97aSjoerg [(set Ty:$dest, (OpNode ADDRzii:$addr))]>; 1003*da58b97aSjoerg} 1004*da58b97aSjoerg 1005*da58b97aSjoerg// Section 8.2.2 - LDS 1006*da58b97aSjoerglet DecoderMethod = "DecodeLoadI64" in 1007*da58b97aSjoergdefm LD : LOADm<"ld", 0x01, I64, i64, load>; 1008*da58b97aSjoergdef : Pat<(f64 (load ADDRrri:$addr)), (LDrri MEMrri:$addr)>; 1009*da58b97aSjoergdef : Pat<(f64 (load ADDRrii:$addr)), (LDrii MEMrii:$addr)>; 1010*da58b97aSjoergdef : Pat<(f64 (load ADDRzri:$addr)), (LDzri MEMzri:$addr)>; 1011*da58b97aSjoergdef : Pat<(f64 (load ADDRzii:$addr)), (LDzii MEMzii:$addr)>; 1012*da58b97aSjoerg 1013*da58b97aSjoerg// Section 8.2.3 - LDU 1014*da58b97aSjoerglet DecoderMethod = "DecodeLoadF32" in 1015*da58b97aSjoergdefm LDU : LOADm<"ldu", 0x02, F32, f32, load>; 1016*da58b97aSjoerg 1017*da58b97aSjoerg// Section 8.2.4 - LDL 1018*da58b97aSjoerglet DecoderMethod = "DecodeLoadI32" in 1019*da58b97aSjoergdefm LDLSX : LOADm<"ldl.sx", 0x03, I32, i32, load>; 1020*da58b97aSjoerglet cx = 1, DecoderMethod = "DecodeLoadI32" in 1021*da58b97aSjoergdefm LDLZX : LOADm<"ldl.zx", 0x03, I32, i32, load>; 1022*da58b97aSjoerg 1023*da58b97aSjoerg// Section 8.2.5 - LD2B 1024*da58b97aSjoerglet DecoderMethod = "DecodeLoadI32" in 1025*da58b97aSjoergdefm LD2BSX : LOADm<"ld2b.sx", 0x04, I32, i32, sextloadi16>; 1026*da58b97aSjoerglet cx = 1, DecoderMethod = "DecodeLoadI32" in 1027*da58b97aSjoergdefm LD2BZX : LOADm<"ld2b.zx", 0x04, I32, i32, zextloadi16>; 1028*da58b97aSjoerg 1029*da58b97aSjoerg// Section 8.2.6 - LD1B 1030*da58b97aSjoerglet DecoderMethod = "DecodeLoadI32" in 1031*da58b97aSjoergdefm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>; 1032*da58b97aSjoerglet cx = 1, DecoderMethod = "DecodeLoadI32" in 1033*da58b97aSjoergdefm LD1BZX : LOADm<"ld1b.zx", 0x05, I32, i32, zextloadi8>; 1034*da58b97aSjoerg 1035*da58b97aSjoerg// LDQ pseudo instructions 1036*da58b97aSjoerglet mayLoad = 1, hasSideEffects = 0 in { 1037*da58b97aSjoerg def LDQrii : Pseudo<(outs F128:$dest), (ins MEMrii:$addr), 1038*da58b97aSjoerg "# pseudo ldq $dest, $addr", 1039*da58b97aSjoerg [(set f128:$dest, (load ADDRrii:$addr))]>; 1040*da58b97aSjoerg} 1041*da58b97aSjoerg 1042*da58b97aSjoerg// Multiclass for store instructions. 1043*da58b97aSjoerglet mayStore = 1 in 1044*da58b97aSjoergmulticlass STOREm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty, 1045*da58b97aSjoerg SDPatternOperator OpNode = null_frag> { 1046*da58b97aSjoerg def rri : RM<opc, (outs), (ins MEMrri:$addr, RC:$sx), 1047*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr"), 1048*da58b97aSjoerg [(OpNode Ty:$sx, ADDRrri:$addr)]>; 1049*da58b97aSjoerg let cy = 0 in 1050*da58b97aSjoerg def rii : RM<opc, (outs), (ins MEMrii:$addr, RC:$sx), 1051*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr"), 1052*da58b97aSjoerg [(OpNode Ty:$sx, ADDRrii:$addr)]>; 1053*da58b97aSjoerg let cz = 0 in 1054*da58b97aSjoerg def zri : RM<opc, (outs), (ins MEMzri:$addr, RC:$sx), 1055*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr"), 1056*da58b97aSjoerg [(OpNode Ty:$sx, ADDRzri:$addr)]>; 1057*da58b97aSjoerg let cy = 0, cz = 0 in 1058*da58b97aSjoerg def zii : RM<opc, (outs), (ins MEMzii:$addr, RC:$sx), 1059*da58b97aSjoerg !strconcat(opcStr, " $sx, $addr"), 1060*da58b97aSjoerg [(OpNode Ty:$sx, ADDRzii:$addr)]>; 1061*da58b97aSjoerg} 1062*da58b97aSjoerg 1063*da58b97aSjoerg// Section 8.2.7 - STS 1064*da58b97aSjoerglet DecoderMethod = "DecodeStoreI64" in 1065*da58b97aSjoergdefm ST : STOREm<"st", 0x11, I64, i64, store>; 1066*da58b97aSjoergdef : Pat<(store f64:$src, ADDRrri:$addr), (STrri MEMrri:$addr, $src)>; 1067*da58b97aSjoergdef : Pat<(store f64:$src, ADDRrii:$addr), (STrii MEMrii:$addr, $src)>; 1068*da58b97aSjoergdef : Pat<(store f64:$src, ADDRzri:$addr), (STzri MEMzri:$addr, $src)>; 1069*da58b97aSjoergdef : Pat<(store f64:$src, ADDRzii:$addr), (STzii MEMzii:$addr, $src)>; 1070*da58b97aSjoerg 1071*da58b97aSjoerg// Section 8.2.8 - STU 1072*da58b97aSjoerglet DecoderMethod = "DecodeStoreF32" in 1073*da58b97aSjoergdefm STU : STOREm<"stu", 0x12, F32, f32, store>; 1074*da58b97aSjoerg 1075*da58b97aSjoerg// Section 8.2.9 - STL 1076*da58b97aSjoerglet DecoderMethod = "DecodeStoreI32" in 1077*da58b97aSjoergdefm STL : STOREm<"stl", 0x13, I32, i32, store>; 1078*da58b97aSjoerg 1079*da58b97aSjoerg// Section 8.2.10 - ST2B 1080*da58b97aSjoerglet DecoderMethod = "DecodeStoreI32" in 1081*da58b97aSjoergdefm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>; 1082*da58b97aSjoerg 1083*da58b97aSjoerg// Section 8.2.11 - ST1B 1084*da58b97aSjoerglet DecoderMethod = "DecodeStoreI32" in 1085*da58b97aSjoergdefm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>; 1086*da58b97aSjoerg 1087*da58b97aSjoerg// STQ pseudo instructions 1088*da58b97aSjoerglet mayStore = 1, hasSideEffects = 0 in { 1089*da58b97aSjoerg def STQrii : Pseudo<(outs), (ins MEMrii:$addr, F128:$sx), 1090*da58b97aSjoerg "# pseudo stq $sx, $addr", 1091*da58b97aSjoerg [(store f128:$sx, ADDRrii:$addr)]>; 1092*da58b97aSjoerg} 1093*da58b97aSjoerg 1094*da58b97aSjoerg// Section 8.2.12 - DLDS 1095*da58b97aSjoerglet DecoderMethod = "DecodeLoadI64" in 1096*da58b97aSjoergdefm DLD : LOADm<"dld", 0x09, I64, i64, load>; 1097*da58b97aSjoerg 1098*da58b97aSjoerg// Section 8.2.13 - DLDU 1099*da58b97aSjoerglet DecoderMethod = "DecodeLoadF32" in 1100*da58b97aSjoergdefm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>; 1101*da58b97aSjoerg 1102*da58b97aSjoerg// Section 8.2.14 - DLDL 1103*da58b97aSjoerglet DecoderMethod = "DecodeLoadI32" in 1104*da58b97aSjoergdefm DLDLSX : LOADm<"dldl.sx", 0x0b, I32, i32, load>; 1105*da58b97aSjoerglet cx = 1, DecoderMethod = "DecodeLoadI32" in 1106*da58b97aSjoergdefm DLDLZX : LOADm<"dldl.zx", 0x0b, I32, i32, load>; 1107*da58b97aSjoerg 1108*da58b97aSjoerg// Section 8.2.15 - PFCH 1109*da58b97aSjoerglet DecoderMethod = "DecodeASX" in 1110*da58b97aSjoergdefm PFCH : PFCHm<"pfch", 0x0c>; 1111*da58b97aSjoerg 1112*da58b97aSjoerg// Section 8.2.16 - TS1AM (Test and Set 1 AM) 1113*da58b97aSjoerglet DecoderMethod = "DecodeTS1AMI64" in 1114*da58b97aSjoergdefm TS1AML : RRCASm<"ts1am.l", 0x42, I64, i64, uimm7>; 1115*da58b97aSjoerglet DecoderMethod = "DecodeTS1AMI32", cx = 1 in 1116*da58b97aSjoergdefm TS1AMW : RRCASm<"ts1am.w", 0x42, I32, i32, uimm7>; 1117*da58b97aSjoerg 1118*da58b97aSjoerg// Section 8.2.17 - TS2AM (Test and Set 2 AM) 1119*da58b97aSjoerglet DecoderMethod = "DecodeTS1AMI64" in 1120*da58b97aSjoergdefm TS2AM : RRCASm<"ts2am", 0x43, I64, i64, uimm7>; 1121*da58b97aSjoerg 1122*da58b97aSjoerg// Section 8.2.18 - TS3AM (Test and Set 3 AM) 1123*da58b97aSjoerglet DecoderMethod = "DecodeTS1AMI64" in 1124*da58b97aSjoergdefm TS3AM : RRCASm<"ts3am", 0x52, I64, i64, uimm1>; 1125*da58b97aSjoerg 1126*da58b97aSjoerg// Section 8.2.19 - ATMAM (Atomic AM) 1127*da58b97aSjoerglet DecoderMethod = "DecodeTS1AMI64" in 1128*da58b97aSjoergdefm ATMAM : RRCASm<"atmam", 0x53, I64, i64, uimm0to2>; 1129*da58b97aSjoerg 1130*da58b97aSjoerg// Section 8.2.20 - CAS (Compare and Swap) 1131*da58b97aSjoerglet DecoderMethod = "DecodeCASI64" in 1132*da58b97aSjoergdefm CASL : RRCASm<"cas.l", 0x62, I64, i64, simm7, atomic_cmp_swap_64>; 1133*da58b97aSjoerglet DecoderMethod = "DecodeCASI32", cx = 1 in 1134*da58b97aSjoergdefm CASW : RRCASm<"cas.w", 0x62, I32, i32, simm7, atomic_cmp_swap_32>; 1135*da58b97aSjoerg 1136*da58b97aSjoerg//----------------------------------------------------------------------------- 1137*da58b97aSjoerg// Section 8.3 - Transfer Control Instructions 1138*da58b97aSjoerg//----------------------------------------------------------------------------- 1139*da58b97aSjoerg 1140*da58b97aSjoerg// Section 8.3.1 - FENCE (Fence) 1141*da58b97aSjoerglet hasSideEffects = 1 in { 1142*da58b97aSjoerg let avo = 1 in def FENCEI : RRFENCE<0x20, (outs), (ins), "fencei">; 1143*da58b97aSjoerg def FENCEM : RRFENCE<0x20, (outs), (ins uimm2:$kind), "fencem $kind"> { 1144*da58b97aSjoerg bits<2> kind; 1145*da58b97aSjoerg let lf = kind{1}; 1146*da58b97aSjoerg let sf = kind{0}; 1147*da58b97aSjoerg } 1148*da58b97aSjoerg def FENCEC : RRFENCE<0x20, (outs), (ins uimm3:$kind), "fencec $kind"> { 1149*da58b97aSjoerg bits<3> kind; 1150*da58b97aSjoerg let c2 = kind{2}; 1151*da58b97aSjoerg let c1 = kind{1}; 1152*da58b97aSjoerg let c0 = kind{0}; 1153*da58b97aSjoerg } 1154*da58b97aSjoerg} 1155*da58b97aSjoerg 1156*da58b97aSjoerg// Section 8.3.2 - SVOB (Set Vector Out-of-order memory access Boundary) 1157*da58b97aSjoerglet sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in 1158*da58b97aSjoergdef SVOB : RR<0x30, (outs), (ins), "svob">; 1159*da58b97aSjoerg 1160*da58b97aSjoerg//----------------------------------------------------------------------------- 1161*da58b97aSjoerg// Section 8.4 - Fixed-point Operation Instructions 1162*da58b97aSjoerg//----------------------------------------------------------------------------- 1163*da58b97aSjoerg 1164*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1165*da58b97aSjoerg 1166*da58b97aSjoerg// Section 8.4.1 - ADD (Add) 1167*da58b97aSjoergdefm ADDUL : RRm<"addu.l", 0x48, I64, i64>; 1168*da58b97aSjoerglet cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>; 1169*da58b97aSjoerg 1170*da58b97aSjoerg// Section 8.4.2 - ADS (Add Single) 1171*da58b97aSjoergdefm ADDSWSX : RRm<"adds.w.sx", 0x4A, I32, i32, add>; 1172*da58b97aSjoerglet cx = 1 in defm ADDSWZX : RRm<"adds.w.zx", 0x4A, I32, i32>; 1173*da58b97aSjoerg 1174*da58b97aSjoerg// Section 8.4.3 - ADX (Add) 1175*da58b97aSjoergdefm ADDSL : RRm<"adds.l", 0x59, I64, i64, add>; 1176*da58b97aSjoerg 1177*da58b97aSjoerg// Section 8.4.4 - SUB (Subtract) 1178*da58b97aSjoergdefm SUBUL : RRNCm<"subu.l", 0x58, I64, i64>; 1179*da58b97aSjoerglet cx = 1 in defm SUBUW : RRNCm<"subu.w", 0x58, I32, i32>; 1180*da58b97aSjoerg 1181*da58b97aSjoerg// Section 8.4.5 - SBS (Subtract Single) 1182*da58b97aSjoergdefm SUBSWSX : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>; 1183*da58b97aSjoerglet cx = 1 in defm SUBSWZX : RRNCm<"subs.w.zx", 0x5A, I32, i32>; 1184*da58b97aSjoerg 1185*da58b97aSjoerg// Section 8.4.6 - SBX (Subtract) 1186*da58b97aSjoergdefm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>; 1187*da58b97aSjoerg 1188*da58b97aSjoerg} // isReMaterializable, isAsCheapAsAMove 1189*da58b97aSjoerg 1190*da58b97aSjoerg// Section 8.4.7 - MPY (Multiply) 1191*da58b97aSjoergdefm MULUL : RRm<"mulu.l", 0x49, I64, i64>; 1192*da58b97aSjoerglet cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>; 1193*da58b97aSjoerg 1194*da58b97aSjoerg// Section 8.4.8 - MPS (Multiply Single) 1195*da58b97aSjoergdefm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>; 1196*da58b97aSjoerglet cx = 1 in defm MULSWZX : RRm<"muls.w.zx", 0x4B, I32, i32>; 1197*da58b97aSjoerg 1198*da58b97aSjoerg// Section 8.4.9 - MPX (Multiply) 1199*da58b97aSjoergdefm MULSL : RRm<"muls.l", 0x6E, I64, i64, mul>; 1200*da58b97aSjoerg 1201*da58b97aSjoerg// Section 8.4.10 - MPD (Multiply) 1202*da58b97aSjoergdefm MULSLW : RRbm<"muls.l.w", 0x6B, I64, i64, I32, i32>; 1203*da58b97aSjoerg 1204*da58b97aSjoerg// Section 8.4.11 - DIV (Divide) 1205*da58b97aSjoergdefm DIVUL : RRNCm<"divu.l", 0x6F, I64, i64, udiv>; 1206*da58b97aSjoerglet cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>; 1207*da58b97aSjoerg 1208*da58b97aSjoerg// Section 8.4.12 - DVS (Divide Single) 1209*da58b97aSjoergdefm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>; 1210*da58b97aSjoerglet cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>; 1211*da58b97aSjoerg 1212*da58b97aSjoerg// Section 8.4.13 - DVX (Divide) 1213*da58b97aSjoergdefm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>; 1214*da58b97aSjoerg 1215*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1216*da58b97aSjoerg 1217*da58b97aSjoerg// Section 8.4.14 - CMP (Compare) 1218*da58b97aSjoergdefm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>; 1219*da58b97aSjoerglet cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>; 1220*da58b97aSjoerg 1221*da58b97aSjoerg// Section 8.4.15 - CPS (Compare Single) 1222*da58b97aSjoergdefm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>; 1223*da58b97aSjoerglet cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32>; 1224*da58b97aSjoerg 1225*da58b97aSjoerg// Section 8.4.16 - CPX (Compare) 1226*da58b97aSjoergdefm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64>; 1227*da58b97aSjoerg 1228*da58b97aSjoerg// Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single) 1229*da58b97aSjoerg// cx: sx/zx, cw: max/min 1230*da58b97aSjoergdefm MAXSWSX : RRm<"maxs.w.sx", 0x78, I32, i32>; 1231*da58b97aSjoerglet cx = 1 in defm MAXSWZX : RRm<"maxs.w.zx", 0x78, I32, i32>; 1232*da58b97aSjoerglet cw = 1 in defm MINSWSX : RRm<"mins.w.sx", 0x78, I32, i32>; 1233*da58b97aSjoerglet cx = 1, cw = 1 in defm MINSWZX : RRm<"mins.w.zx", 0x78, I32, i32>; 1234*da58b97aSjoerg 1235*da58b97aSjoerg// Section 8.4.18 - CMX (Compare and Select Maximum/Minimum) 1236*da58b97aSjoergdefm MAXSL : RRm<"maxs.l", 0x68, I64, i64>; 1237*da58b97aSjoerglet cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>; 1238*da58b97aSjoerg 1239*da58b97aSjoerg} // isReMaterializable, isAsCheapAsAMove 1240*da58b97aSjoerg 1241*da58b97aSjoerg//----------------------------------------------------------------------------- 1242*da58b97aSjoerg// Section 8.5 - Logical Operation Instructions 1243*da58b97aSjoerg//----------------------------------------------------------------------------- 1244*da58b97aSjoerg 1245*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1246*da58b97aSjoerg 1247*da58b97aSjoerg// Section 8.5.1 - AND (AND) 1248*da58b97aSjoergdefm AND : RRm<"and", 0x44, I64, i64, and>; 1249*da58b97aSjoerg 1250*da58b97aSjoerg// Section 8.5.2 - OR (OR) 1251*da58b97aSjoergdefm OR : RRm<"or", 0x45, I64, i64, or, simm7, mimm, /* MoveImm */ 1>; 1252*da58b97aSjoerg 1253*da58b97aSjoerg// Section 8.5.3 - XOR (Exclusive OR) 1254*da58b97aSjoergdefm XOR : RRm<"xor", 0x46, I64, i64, xor>; 1255*da58b97aSjoerg 1256*da58b97aSjoerg// Section 8.5.4 - EQV (Equivalence) 1257*da58b97aSjoergdefm EQV : RRm<"eqv", 0x47, I64, i64>; 1258*da58b97aSjoerg 1259*da58b97aSjoerg} // isReMaterializable, isAsCheapAsAMove 1260*da58b97aSjoerg 1261*da58b97aSjoerg// Section 8.5.5 - NND (Negate AND) 1262*da58b97aSjoergdef and_not : PatFrags<(ops node:$x, node:$y), 1263*da58b97aSjoerg [(and (not node:$x), node:$y)]>; 1264*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1265*da58b97aSjoergdefm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>; 1266*da58b97aSjoerg 1267*da58b97aSjoerg// Section 8.5.6 - MRG (Merge) 1268*da58b97aSjoergdefm MRG : RRMRGm<"mrg", 0x56, I64, i64>; 1269*da58b97aSjoerg 1270*da58b97aSjoerg// Section 8.5.7 - LDZ (Leading Zero Count) 1271*da58b97aSjoergdef ctlz_pat : PatFrags<(ops node:$src), 1272*da58b97aSjoerg [(ctlz node:$src), 1273*da58b97aSjoerg (ctlz_zero_undef node:$src)]>; 1274*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1275*da58b97aSjoergdefm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>; 1276*da58b97aSjoerg 1277*da58b97aSjoerg// Section 8.5.8 - PCNT (Population Count) 1278*da58b97aSjoergdefm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>; 1279*da58b97aSjoerg 1280*da58b97aSjoerg// Section 8.5.9 - BRV (Bit Reverse) 1281*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1282*da58b97aSjoergdefm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>; 1283*da58b97aSjoerg 1284*da58b97aSjoerg// Section 8.5.10 - BSWP (Byte Swap) 1285*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1286*da58b97aSjoergdefm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>; 1287*da58b97aSjoerg 1288*da58b97aSjoergdef : Pat<(i64 (bswap i64:$src)), 1289*da58b97aSjoerg (BSWPri $src, 0)>; 1290*da58b97aSjoergdef : Pat<(i64 (bswap (i64 mimm:$src))), 1291*da58b97aSjoerg (BSWPmi (MIMM $src), 0)>; 1292*da58b97aSjoergdef : Pat<(i32 (bswap i32:$src)), 1293*da58b97aSjoerg (EXTRACT_SUBREG 1294*da58b97aSjoerg (BSWPri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub_i32), 1), 1295*da58b97aSjoerg sub_i32)>; 1296*da58b97aSjoergdef : Pat<(i32 (bswap (i32 mimm:$src))), 1297*da58b97aSjoerg (EXTRACT_SUBREG (BSWPmi (MIMM $src), 1), sub_i32)>; 1298*da58b97aSjoerg 1299*da58b97aSjoerg// Section 8.5.11 - CMOV (Conditional Move) 1300*da58b97aSjoerglet cw = 0, cw2 = 0 in defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64, i64>; 1301*da58b97aSjoerglet cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>; 1302*da58b97aSjoerglet cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>; 1303*da58b97aSjoerglet cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>; 1304*da58b97aSjoergdef : MnemonicAlias<"cmov.l", "cmov.l.at">; 1305*da58b97aSjoergdef : MnemonicAlias<"cmov.w", "cmov.w.at">; 1306*da58b97aSjoergdef : MnemonicAlias<"cmov.d", "cmov.d.at">; 1307*da58b97aSjoergdef : MnemonicAlias<"cmov.s", "cmov.s.at">; 1308*da58b97aSjoerg 1309*da58b97aSjoerg//----------------------------------------------------------------------------- 1310*da58b97aSjoerg// Section 8.6 - Shift Operation Instructions 1311*da58b97aSjoerg//----------------------------------------------------------------------------- 1312*da58b97aSjoerg 1313*da58b97aSjoerg// Section 8.6.1 - SLL (Shift Left Logical) 1314*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1315*da58b97aSjoergdefm SLL : RRIm<"sll", 0x65, I64, i64, shl>; 1316*da58b97aSjoerg 1317*da58b97aSjoerg// Section 8.6.2 - SLD (Shift Left Double) 1318*da58b97aSjoergdefm SLD : RRILDm<"sld", 0x64, I64, i64>; 1319*da58b97aSjoerg 1320*da58b97aSjoerg// Section 8.6.3 - SRL (Shift Right Logical) 1321*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in 1322*da58b97aSjoergdefm SRL : RRIm<"srl", 0x75, I64, i64, srl>; 1323*da58b97aSjoerg 1324*da58b97aSjoerg// Section 8.6.4 - SRD (Shift Right Double) 1325*da58b97aSjoergdefm SRD : RRIRDm<"srd", 0x74, I64, i64>; 1326*da58b97aSjoerg 1327*da58b97aSjoerglet isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1328*da58b97aSjoerg 1329*da58b97aSjoerg// Section 8.6.5 - SLA (Shift Left Arithmetic) 1330*da58b97aSjoergdefm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>; 1331*da58b97aSjoerglet cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>; 1332*da58b97aSjoerg 1333*da58b97aSjoerg// Section 8.6.6 - SLAX (Shift Left Arithmetic) 1334*da58b97aSjoergdefm SLAL : RRIm<"sla.l", 0x57, I64, i64>; 1335*da58b97aSjoerg 1336*da58b97aSjoerg// Section 8.6.7 - SRA (Shift Right Arithmetic) 1337*da58b97aSjoergdefm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>; 1338*da58b97aSjoerglet cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>; 1339*da58b97aSjoerg 1340*da58b97aSjoerg// Section 8.6.8 - SRAX (Shift Right Arithmetic) 1341*da58b97aSjoergdefm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>; 1342*da58b97aSjoerg 1343*da58b97aSjoerg} // isReMaterializable, isAsCheapAsAMove 1344*da58b97aSjoerg 1345*da58b97aSjoergdef : Pat<(i32 (srl i32:$src, (i32 simm7:$val))), 1346*da58b97aSjoerg (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1347*da58b97aSjoerg $src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>; 1348*da58b97aSjoergdef : Pat<(i32 (srl i32:$src, i32:$val)), 1349*da58b97aSjoerg (EXTRACT_SUBREG (SRLrr (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1350*da58b97aSjoerg $src, sub_i32), !add(32, 64)), $val), sub_i32)>; 1351*da58b97aSjoerg 1352*da58b97aSjoerg//----------------------------------------------------------------------------- 1353*da58b97aSjoerg// Section 8.7 - Floating-point Arithmetic Instructions 1354*da58b97aSjoerg//----------------------------------------------------------------------------- 1355*da58b97aSjoerg 1356*da58b97aSjoerg// Section 8.7.1 - FAD (Floating Add) 1357*da58b97aSjoergdefm FADDD : RRFm<"fadd.d", 0x4C, I64, f64, fadd>; 1358*da58b97aSjoerglet cx = 1 in 1359*da58b97aSjoergdefm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>; 1360*da58b97aSjoerg 1361*da58b97aSjoerg// Section 8.7.2 - FSB (Floating Subtract) 1362*da58b97aSjoergdefm FSUBD : RRFm<"fsub.d", 0x5C, I64, f64, fsub>; 1363*da58b97aSjoerglet cx = 1 in 1364*da58b97aSjoergdefm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>; 1365*da58b97aSjoerg 1366*da58b97aSjoerg// Section 8.7.3 - FMP (Floating Multiply) 1367*da58b97aSjoergdefm FMULD : RRFm<"fmul.d", 0x4D, I64, f64, fmul>; 1368*da58b97aSjoerglet cx = 1 in 1369*da58b97aSjoergdefm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>; 1370*da58b97aSjoerg 1371*da58b97aSjoerg// Section 8.7.4 - FDV (Floating Divide) 1372*da58b97aSjoergdefm FDIVD : RRFm<"fdiv.d", 0x5D, I64, f64, fdiv>; 1373*da58b97aSjoerglet cx = 1 in 1374*da58b97aSjoergdefm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>; 1375*da58b97aSjoerg 1376*da58b97aSjoerg// Section 8.7.5 - FCP (Floating Compare) 1377*da58b97aSjoergdefm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64>; 1378*da58b97aSjoerglet cx = 1 in 1379*da58b97aSjoergdefm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, null_frag, simm7fp, mimmfp32>; 1380*da58b97aSjoerg 1381*da58b97aSjoerg// Section 8.7.6 - CMS (Compare and Select Maximum/Minimum Single) 1382*da58b97aSjoerg// cx: double/float, cw: max/min 1383*da58b97aSjoerglet cw = 0, cx = 0 in 1384*da58b97aSjoergdefm FMAXD : RRFm<"fmax.d", 0x3E, I64, f64, fmaxnum>; 1385*da58b97aSjoerglet cw = 0, cx = 1 in 1386*da58b97aSjoergdefm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>; 1387*da58b97aSjoerglet cw = 1, cx = 0 in 1388*da58b97aSjoergdefm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>; 1389*da58b97aSjoerglet cw = 1, cx = 1 in 1390*da58b97aSjoergdefm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>; 1391*da58b97aSjoerg 1392*da58b97aSjoerg// Section 8.7.7 - FAQ (Floating Add Quadruple) 1393*da58b97aSjoergdefm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128, fadd>; 1394*da58b97aSjoerg 1395*da58b97aSjoerg// Section 8.7.8 - FSQ (Floating Subtract Quadruple) 1396*da58b97aSjoergdefm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128, fsub>; 1397*da58b97aSjoerg 1398*da58b97aSjoerg// Section 8.7.9 - FMQ (Floating Subtract Quadruple) 1399*da58b97aSjoergdefm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128, fmul>; 1400*da58b97aSjoerg 1401*da58b97aSjoerg// Section 8.7.10 - FCQ (Floating Compare Quadruple) 1402*da58b97aSjoergdefm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp, 1403*da58b97aSjoerg mimmfp>; 1404*da58b97aSjoerg 1405*da58b97aSjoerg// Section 8.7.11 - FIX (Convert to Fixed Point) 1406*da58b97aSjoerg// cx: double/float, cw: sx/zx, sz{0-3} = round 1407*da58b97aSjoerglet cx = 0, cw = 0 /* sign extend */ in 1408*da58b97aSjoergdefm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, i32, I64, f64>; 1409*da58b97aSjoerglet cx = 0, cw = 1 /* zero extend */ in 1410*da58b97aSjoergdefm CVTWDZX : CVTRDm<"cvt.w.d.zx", 0x4E, I32, i32, I64, f64>; 1411*da58b97aSjoerglet cx = 1, cw = 0 /* sign extend */ in 1412*da58b97aSjoergdefm CVTWSSX : CVTRDm<"cvt.w.s.sx", 0x4E, I32, i32, F32, f32>; 1413*da58b97aSjoerglet cx = 1, cw = 1 /* zero extend */ in 1414*da58b97aSjoergdefm CVTWSZX : CVTRDm<"cvt.w.s.zx", 0x4E, I32, i32, F32, f32>; 1415*da58b97aSjoerg 1416*da58b97aSjoerg// Section 8.7.12 - FIXX (Convert to Fixed Point) 1417*da58b97aSjoergdefm CVTLD : CVTRDm<"cvt.l.d", 0x4F, I64, i64, I64, f64>; 1418*da58b97aSjoerg 1419*da58b97aSjoerg// Section 8.7.13 - FLT (Convert to Floating Point) 1420*da58b97aSjoergdefm CVTDW : CVTm<"cvt.d.w", 0x5E, I64, f64, I32, i32, sint_to_fp>; 1421*da58b97aSjoerglet cx = 1 in 1422*da58b97aSjoergdefm CVTSW : CVTm<"cvt.s.w", 0x5E, F32, f32, I32, i32, sint_to_fp>; 1423*da58b97aSjoerg 1424*da58b97aSjoerg// Section 8.7.14 - FLTX (Convert to Floating Point) 1425*da58b97aSjoergdefm CVTDL : CVTm<"cvt.d.l", 0x5F, I64, f64, I64, i64, sint_to_fp>; 1426*da58b97aSjoerg 1427*da58b97aSjoerg// Section 8.7.15 - CVS (Convert to Single-format) 1428*da58b97aSjoergdefm CVTSD : CVTm<"cvt.s.d", 0x1F, F32, f32, I64, f64, fpround>; 1429*da58b97aSjoerglet cx = 1 in 1430*da58b97aSjoergdefm CVTSQ : CVTm<"cvt.s.q", 0x1F, F32, f32, F128, f128, fpround>; 1431*da58b97aSjoerg 1432*da58b97aSjoerg// Section 8.7.16 - CVD (Convert to Double-format) 1433*da58b97aSjoergdefm CVTDS : CVTm<"cvt.d.s", 0x0F, I64, f64, F32, f32, fpextend>; 1434*da58b97aSjoerglet cx = 1 in 1435*da58b97aSjoergdefm CVTDQ : CVTm<"cvt.d.q", 0x0F, I64, f64, F128, f128, fpround>; 1436*da58b97aSjoerg 1437*da58b97aSjoerg// Section 8.7.17 - CVQ (Convert to Single-format) 1438*da58b97aSjoergdefm CVTQD : CVTm<"cvt.q.d", 0x2D, F128, f128, I64, f64, fpextend>; 1439*da58b97aSjoerglet cx = 1 in 1440*da58b97aSjoergdefm CVTQS : CVTm<"cvt.q.s", 0x2D, F128, f128, F32, f32, fpextend>; 1441*da58b97aSjoerg 1442*da58b97aSjoerg//----------------------------------------------------------------------------- 1443*da58b97aSjoerg// Section 8.8 - Branch instructions 1444*da58b97aSjoerg//----------------------------------------------------------------------------- 1445*da58b97aSjoerg 1446*da58b97aSjoerg// Section 8.8.1 - BC (Branch on Codition) 1447*da58b97aSjoergdefm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>; 1448*da58b97aSjoerg 1449*da58b97aSjoerg// Indirect branch aliases 1450*da58b97aSjoergdef : Pat<(brind I64:$reg), (BCFLari_t $reg, 0)>; 1451*da58b97aSjoergdef : Pat<(brind tblockaddress:$imm), (BCFLazi_t 0, $imm)>; 1452*da58b97aSjoerg 1453*da58b97aSjoerg// Return instruction is a special case of jump. 1454*da58b97aSjoerglet Uses = [SX10], bpf = 3 /* TAKEN */, cf = 15 /* AT */, cy = 0, sy = 0, 1455*da58b97aSjoerg sz = 10 /* SX10 */, imm32 = 0, isReturn = 1, isTerminator = 1, 1456*da58b97aSjoerg isBarrier = 1, isCodeGenOnly = 1, hasSideEffects = 0 in 1457*da58b97aSjoergdef RET : CF<0x19, (outs), (ins), "b.l.t (, %s10)", [(retflag)]>; 1458*da58b97aSjoerg 1459*da58b97aSjoerg// Section 8.8.2 - BCS (Branch on Condition Single) 1460*da58b97aSjoergdefm BCFW : BCm<"b${cond}.w", "b.w", "baf.w", 0x1B, I32, simm7>; 1461*da58b97aSjoerg 1462*da58b97aSjoerg// Section 8.8.3 - BCF (Branch on Condition Floating Point) 1463*da58b97aSjoergdefm BCFD : BCm<"b${cond}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>; 1464*da58b97aSjoerglet cx = 1 in 1465*da58b97aSjoergdefm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>; 1466*da58b97aSjoerg 1467*da58b97aSjoerg// Section 8.8.4 - BCR (Branch on Condition Relative) 1468*da58b97aSjoerglet cx = 0, cx2 = 0 in 1469*da58b97aSjoergdefm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7, zero>; 1470*da58b97aSjoerglet cx = 1, cx2 = 0 in 1471*da58b97aSjoergdefm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7, zero>; 1472*da58b97aSjoerglet cx = 0, cx2 = 1 in 1473*da58b97aSjoergdefm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp, zerofp>; 1474*da58b97aSjoerglet cx = 1, cx2 = 1 in 1475*da58b97aSjoergdefm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp, zerofp>; 1476*da58b97aSjoerg 1477*da58b97aSjoerg// Section 8.8.5 - BSIC (Branch and Save IC) 1478*da58b97aSjoerglet isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in 1479*da58b97aSjoergdefm BSIC : RMm<"bsic", 0x08, I64>; 1480*da58b97aSjoerg 1481*da58b97aSjoerg// Call instruction is a special case of BSIC. 1482*da58b97aSjoerglet Defs = [SX10], sx = 10 /* SX10 */, cy = 0, sy = 0, imm32 = 0, 1483*da58b97aSjoerg isCall = 1, isCodeGenOnly = 1, hasSideEffects = 0 in 1484*da58b97aSjoergdef CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops), 1485*da58b97aSjoerg "bsic %s10, (, $sz)", [(call i64:$sz)]>; 1486*da58b97aSjoerg 1487*da58b97aSjoerg//----------------------------------------------------------------------------- 1488*da58b97aSjoerg// Section 8.19 - Control Instructions 1489*da58b97aSjoerg//----------------------------------------------------------------------------- 1490*da58b97aSjoerg 1491*da58b97aSjoerg// Section 8.19.1 - SIC (Save Instruction Counter) 1492*da58b97aSjoerglet cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [IC] in 1493*da58b97aSjoergdef SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">; 1494*da58b97aSjoerg 1495*da58b97aSjoerg// Section 8.19.2 - LPM (Load Program Mode Flags) 1496*da58b97aSjoerglet sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in 1497*da58b97aSjoergdef LPM : RR<0x3a, (outs), (ins I64:$sy), "lpm $sy">; 1498*da58b97aSjoerg 1499*da58b97aSjoerg// Section 8.19.3 - SPM (Save Program Mode Flags) 1500*da58b97aSjoerglet cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in 1501*da58b97aSjoergdef SPM : RR<0x2a, (outs I64:$sx), (ins), "spm $sx">; 1502*da58b97aSjoerg 1503*da58b97aSjoerg// Section 8.19.4 - LFR (Load Flag Register) 1504*da58b97aSjoerglet sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in { 1505*da58b97aSjoerg def LFRr : RR<0x69, (outs), (ins I64:$sy), "lfr $sy">; 1506*da58b97aSjoerg let cy = 0 in def LFRi : RR<0x69, (outs), (ins uimm6:$sy), "lfr $sy">; 1507*da58b97aSjoerg} 1508*da58b97aSjoerg 1509*da58b97aSjoerg// Section 8.19.5 - SFR (Save Flag Register) 1510*da58b97aSjoerglet cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in 1511*da58b97aSjoergdef SFR : RR<0x29, (outs I64:$sx), (ins), "sfr $sx">; 1512*da58b97aSjoerg 1513*da58b97aSjoerg// Section 8.19.6 - SMIR (Save Miscellaneous Register) 1514*da58b97aSjoerglet cy = 0, cz = 0, sz = 0, hasSideEffects = 1 in { 1515*da58b97aSjoerg def SMIR : RR<0x22, (outs I64:$sx), (ins MISC:$sy), "smir $sx, $sy">; 1516*da58b97aSjoerg} 1517*da58b97aSjoerg 1518*da58b97aSjoerg// Section 8.19.7 - NOP (No Operation) 1519*da58b97aSjoerglet sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in 1520*da58b97aSjoergdef NOP : RR<0x79, (outs), (ins), "nop">; 1521*da58b97aSjoerg 1522*da58b97aSjoerg// Section 8.19.8 - MONC (Monitor Call) 1523*da58b97aSjoerglet sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in { 1524*da58b97aSjoerg def MONC : RR<0x3F, (outs), (ins), "monc">; 1525*da58b97aSjoerg let cx = 1, isTrap = 1 in def MONCHDB : RR<0x3F, (outs), (ins), "monc.hdb">; 1526*da58b97aSjoerg} 1527*da58b97aSjoerg 1528*da58b97aSjoerg// Section 8.19.9 - LCR (Load Communication Register) 1529*da58b97aSjoergdefm LCR : LOADCRm<"lcr", 0x40, I64>; 1530*da58b97aSjoerg 1531*da58b97aSjoerg// Section 8.19.10 - SCR (Save Communication Register) 1532*da58b97aSjoergdefm SCR : STORECRm<"scr", 0x50, I64>; 1533*da58b97aSjoerg 1534*da58b97aSjoerg// Section 8.19.11 - TSCR (Test & Set Communication Register) 1535*da58b97aSjoergdefm TSCR : LOADCRm<"tscr", 0x41, I64>; 1536*da58b97aSjoerg 1537*da58b97aSjoerg// Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR) 1538*da58b97aSjoergdefm FIDCR : FIDCRm<"fidcr", 0x51, I64>; 1539*da58b97aSjoerg 1540*da58b97aSjoerg//----------------------------------------------------------------------------- 1541*da58b97aSjoerg// Section 8.20 - Host Memory Access Instructions 1542*da58b97aSjoerg//----------------------------------------------------------------------------- 1543*da58b97aSjoerg 1544*da58b97aSjoerg// Section 8.20.1 - LHM (Load Host Memory) 1545*da58b97aSjoerglet ry = 3, DecoderMethod = "DecodeLoadASI64" in 1546*da58b97aSjoergdefm LHML : LHMm<"lhm.l", 0x21, I64>; 1547*da58b97aSjoerglet ry = 2, DecoderMethod = "DecodeLoadASI64" in 1548*da58b97aSjoergdefm LHMW : LHMm<"lhm.w", 0x21, I64>; 1549*da58b97aSjoerglet ry = 1, DecoderMethod = "DecodeLoadASI64" in 1550*da58b97aSjoergdefm LHMH : LHMm<"lhm.h", 0x21, I64>; 1551*da58b97aSjoerglet ry = 0, DecoderMethod = "DecodeLoadASI64" in 1552*da58b97aSjoergdefm LHMB : LHMm<"lhm.b", 0x21, I64>; 1553*da58b97aSjoerg 1554*da58b97aSjoerg// Section 8.20.2 - SHM (Store Host Memory) 1555*da58b97aSjoerglet ry = 3, DecoderMethod = "DecodeStoreASI64" in 1556*da58b97aSjoergdefm SHML : SHMm<"shm.l", 0x31, I64>; 1557*da58b97aSjoerglet ry = 2, DecoderMethod = "DecodeStoreASI64" in 1558*da58b97aSjoergdefm SHMW : SHMm<"shm.w", 0x31, I64>; 1559*da58b97aSjoerglet ry = 1, DecoderMethod = "DecodeStoreASI64" in 1560*da58b97aSjoergdefm SHMH : SHMm<"shm.h", 0x31, I64>; 1561*da58b97aSjoerglet ry = 0, DecoderMethod = "DecodeStoreASI64" in 1562*da58b97aSjoergdefm SHMB : SHMm<"shm.b", 0x31, I64>; 1563*da58b97aSjoerg 1564*da58b97aSjoerg//===----------------------------------------------------------------------===// 1565*da58b97aSjoerg// Instructions for CodeGenOnly 1566*da58b97aSjoerg//===----------------------------------------------------------------------===// 1567*da58b97aSjoerg 1568*da58b97aSjoerg//===----------------------------------------------------------------------===// 1569*da58b97aSjoerg// Pattern Matchings 1570*da58b97aSjoerg//===----------------------------------------------------------------------===// 1571*da58b97aSjoerg 1572*da58b97aSjoerg// Basic cast between registers. This is often used in ISel patterns, so make 1573*da58b97aSjoerg// them as OutPatFrag. 1574*da58b97aSjoergdef i2l : OutPatFrag<(ops node:$exp), 1575*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $exp, sub_i32)>; 1576*da58b97aSjoergdef l2i : OutPatFrag<(ops node:$exp), 1577*da58b97aSjoerg (EXTRACT_SUBREG $exp, sub_i32)>; 1578*da58b97aSjoergdef f2l : OutPatFrag<(ops node:$exp), 1579*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $exp, sub_f32)>; 1580*da58b97aSjoergdef l2f : OutPatFrag<(ops node:$exp), 1581*da58b97aSjoerg (EXTRACT_SUBREG $exp, sub_f32)>; 1582*da58b97aSjoerg 1583*da58b97aSjoerg// Small immediates. 1584*da58b97aSjoergdef : Pat<(i32 simm7:$val), (EXTRACT_SUBREG (ORim (LO7 $val), 0), sub_i32)>; 1585*da58b97aSjoergdef : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>; 1586*da58b97aSjoerg// Medium immediates. 1587*da58b97aSjoergdef : Pat<(i32 simm32:$val), 1588*da58b97aSjoerg (EXTRACT_SUBREG (LEAzii 0, 0, (LO32 $val)), sub_i32)>; 1589*da58b97aSjoergdef : Pat<(i64 simm32:$val), (LEAzii 0, 0, (LO32 $val))>; 1590*da58b97aSjoergdef : Pat<(i64 uimm32:$val), (ANDrm (LEAzii 0, 0, (LO32 $val)), !add(32, 64))>; 1591*da58b97aSjoerg// Arbitrary immediates. 1592*da58b97aSjoergdef : Pat<(i64 lozero:$val), 1593*da58b97aSjoerg (LEASLzii 0, 0, (HI32 imm:$val))>; 1594*da58b97aSjoergdef : Pat<(i64 lomsbzero:$val), 1595*da58b97aSjoerg (LEASLrii (LEAzii 0, 0, (LO32 imm:$val)), 0, (HI32 imm:$val))>; 1596*da58b97aSjoergdef : Pat<(i64 imm:$val), 1597*da58b97aSjoerg (LEASLrii (ANDrm (LEAzii 0, 0, (LO32 imm:$val)), !add(32, 64)), 0, 1598*da58b97aSjoerg (HI32 imm:$val))>; 1599*da58b97aSjoerg 1600*da58b97aSjoerg// LEA patterns 1601*da58b97aSjoergdef lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp), 1602*da58b97aSjoerg [(add (add node:$base, node:$idx), node:$disp), 1603*da58b97aSjoerg (add (add node:$base, node:$disp), node:$idx), 1604*da58b97aSjoerg (add node:$base, (add $idx, $disp))]>; 1605*da58b97aSjoergdef : Pat<(lea_add I64:$base, simm7:$idx, simm32:$disp), 1606*da58b97aSjoerg (LEArii $base, (LO7 $idx), (LO32 $disp))>; 1607*da58b97aSjoergdef : Pat<(lea_add I64:$base, I64:$idx, simm32:$disp), 1608*da58b97aSjoerg (LEArri $base, $idx, (LO32 $disp))>; 1609*da58b97aSjoergdef : Pat<(lea_add I64:$base, simm7:$idx, lozero:$disp), 1610*da58b97aSjoerg (LEASLrii $base, (LO7 $idx), (HI32 $disp))>; 1611*da58b97aSjoergdef : Pat<(lea_add I64:$base, I64:$idx, lozero:$disp), 1612*da58b97aSjoerg (LEASLrri $base, $idx, (HI32 $disp))>; 1613*da58b97aSjoerg 1614*da58b97aSjoerg// Address calculation patterns and optimizations 1615*da58b97aSjoerg// 1616*da58b97aSjoerg// Generate following instructions: 1617*da58b97aSjoerg// 1. LEA %reg, label@LO32 1618*da58b97aSjoerg// AND %reg, %reg, (32)0 1619*da58b97aSjoerg// 2. LEASL %reg, label@HI32 1620*da58b97aSjoerg// 3. (LEA %reg, label@LO32) 1621*da58b97aSjoerg// (AND %reg, %reg, (32)0) 1622*da58b97aSjoerg// LEASL %reg, label@HI32(, %reg) 1623*da58b97aSjoerg// 4. (LEA %reg, label@LO32) 1624*da58b97aSjoerg// (AND %reg, %reg, (32)0) 1625*da58b97aSjoerg// LEASL %reg, label@HI32(%reg, %got) 1626*da58b97aSjoerg// 1627*da58b97aSjoergdef velo_only : OutPatFrag<(ops node:$lo), 1628*da58b97aSjoerg (ANDrm (LEAzii 0, 0, $lo), !add(32, 64))>; 1629*da58b97aSjoergdef vehi_only : OutPatFrag<(ops node:$hi), 1630*da58b97aSjoerg (LEASLzii 0, 0, $hi)>; 1631*da58b97aSjoergdef vehi_lo : OutPatFrag<(ops node:$hi, node:$lo), 1632*da58b97aSjoerg (LEASLrii $lo, 0, $hi)>; 1633*da58b97aSjoergdef vehi_lo_imm : OutPatFrag<(ops node:$hi, node:$lo, node:$idx), 1634*da58b97aSjoerg (LEASLrii $lo, $idx, $hi)>; 1635*da58b97aSjoergdef vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo), 1636*da58b97aSjoerg (LEASLrri $base, $lo, $hi)>; 1637*da58b97aSjoergforeach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr", 1638*da58b97aSjoerg "tglobaltlsaddr", "tjumptable" ] in { 1639*da58b97aSjoerg def : Pat<(VElo !cast<SDNode>(type):$lo), (velo_only $lo)>; 1640*da58b97aSjoerg def : Pat<(VEhi !cast<SDNode>(type):$hi), (vehi_only $hi)>; 1641*da58b97aSjoerg def : Pat<(add (VEhi !cast<SDNode>(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>; 1642*da58b97aSjoerg def : Pat<(add (add (VEhi !cast<SDNode>(type):$hi), I64:$lo), simm7:$val), 1643*da58b97aSjoerg (vehi_lo_imm $hi, $lo, (LO7 $val))>; 1644*da58b97aSjoerg def : Pat<(add I64:$base, (add (VEhi !cast<SDNode>(type):$hi), I64:$lo)), 1645*da58b97aSjoerg (vehi_baselo $base, $hi, $lo)>; 1646*da58b97aSjoerg} 1647*da58b97aSjoerg 1648*da58b97aSjoerg// floating point 1649*da58b97aSjoergdef : Pat<(f32 fpimm:$val), 1650*da58b97aSjoerg (EXTRACT_SUBREG (LEASLzii 0, 0, (HIFP32 $val)), sub_f32)>; 1651*da58b97aSjoergdef : Pat<(f64 fplozero:$val), 1652*da58b97aSjoerg (LEASLzii 0, 0, (HIFP32 $val))>; 1653*da58b97aSjoergdef : Pat<(f64 fplomsbzero:$val), 1654*da58b97aSjoerg (LEASLrii (LEAzii 0, 0, (LOFP32 $val)), 0, (HIFP32 $val))>; 1655*da58b97aSjoergdef : Pat<(f64 fpimm:$val), 1656*da58b97aSjoerg (LEASLrii (ANDrm (LEAzii 0, 0, (LOFP32 $val)), !add(32, 64)), 0, 1657*da58b97aSjoerg (HIFP32 $val))>; 1658*da58b97aSjoerg 1659*da58b97aSjoerg// The same integer registers are used for i32 and i64 values. 1660*da58b97aSjoerg// When registers hold i32 values, the high bits are unused. 1661*da58b97aSjoerg 1662*da58b97aSjoerg// TODO Use standard expansion for shift-based lowering of sext_inreg 1663*da58b97aSjoerg 1664*da58b97aSjoerg// Cast to i1 1665*da58b97aSjoergdef : Pat<(sext_inreg I32:$src, i1), 1666*da58b97aSjoerg (SRAWSXri (SLAWSXri $src, 31), 31)>; 1667*da58b97aSjoergdef : Pat<(sext_inreg I64:$src, i1), 1668*da58b97aSjoerg (SRALri (SLLri $src, 63), 63)>; 1669*da58b97aSjoerg 1670*da58b97aSjoerg// Cast to i8 1671*da58b97aSjoergdef : Pat<(sext_inreg I32:$src, i8), 1672*da58b97aSjoerg (SRAWSXri (SLAWSXri $src, 24), 24)>; 1673*da58b97aSjoergdef : Pat<(sext_inreg I64:$src, i8), 1674*da58b97aSjoerg (SRALri (SLLri $src, 56), 56)>; 1675*da58b97aSjoergdef : Pat<(sext_inreg (i32 (trunc i64:$src)), i8), 1676*da58b97aSjoerg (EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>; 1677*da58b97aSjoergdef : Pat<(i32 (and (trunc i64:$src), 0xff)), 1678*da58b97aSjoerg (EXTRACT_SUBREG (ANDrm $src, !add(56, 64)), sub_i32)>; 1679*da58b97aSjoerg 1680*da58b97aSjoerg// Cast to i16 1681*da58b97aSjoergdef : Pat<(sext_inreg I32:$src, i16), 1682*da58b97aSjoerg (SRAWSXri (SLAWSXri $src, 16), 16)>; 1683*da58b97aSjoergdef : Pat<(sext_inreg I64:$src, i16), 1684*da58b97aSjoerg (SRALri (SLLri $src, 48), 48)>; 1685*da58b97aSjoergdef : Pat<(sext_inreg (i32 (trunc i64:$src)), i16), 1686*da58b97aSjoerg (EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>; 1687*da58b97aSjoergdef : Pat<(i32 (and (trunc i64:$src), 0xffff)), 1688*da58b97aSjoerg (EXTRACT_SUBREG (ANDrm $src, !add(48, 64)), sub_i32)>; 1689*da58b97aSjoerg 1690*da58b97aSjoerg// Cast to i32 1691*da58b97aSjoergdef : Pat<(i32 (trunc i64:$src)), 1692*da58b97aSjoerg (EXTRACT_SUBREG (ANDrm $src, !add(32, 64)), sub_i32)>; 1693*da58b97aSjoergdef : Pat<(i32 (fp_to_sint f32:$src)), (CVTWSSXr RD_RZ, $src)>; 1694*da58b97aSjoergdef : Pat<(i32 (fp_to_sint f64:$src)), (CVTWDSXr RD_RZ, $src)>; 1695*da58b97aSjoergdef : Pat<(i32 (fp_to_sint f128:$src)), (CVTWDSXr RD_RZ, (CVTDQr $src))>; 1696*da58b97aSjoerg 1697*da58b97aSjoerg// Cast to i64 1698*da58b97aSjoergdef : Pat<(sext_inreg i64:$src, i32), 1699*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1700*da58b97aSjoerg (ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0), sub_i32)>; 1701*da58b97aSjoergdef : Pat<(i64 (sext i32:$src)), 1702*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADDSWSXrm $src, 0), sub_i32)>; 1703*da58b97aSjoergdef : Pat<(i64 (zext i32:$src)), 1704*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADDSWZXrm $src, 0), sub_i32)>; 1705*da58b97aSjoergdef : Pat<(i64 (fp_to_sint f32:$src)), (CVTLDr RD_RZ, (CVTDSr $src))>; 1706*da58b97aSjoergdef : Pat<(i64 (fp_to_sint f64:$src)), (CVTLDr RD_RZ, $src)>; 1707*da58b97aSjoergdef : Pat<(i64 (fp_to_sint f128:$src)), (CVTLDr RD_RZ, (CVTDQr $src))>; 1708*da58b97aSjoerg 1709*da58b97aSjoerg// Cast to f32 1710*da58b97aSjoergdef : Pat<(f32 (sint_to_fp i64:$src)), (CVTSDr (CVTDLr i64:$src))>; 1711*da58b97aSjoerg 1712*da58b97aSjoerg// Cast to f128 1713*da58b97aSjoergdef : Pat<(f128 (sint_to_fp i32:$src)), (CVTQDr (CVTDWr $src))>; 1714*da58b97aSjoergdef : Pat<(f128 (sint_to_fp i64:$src)), (CVTQDr (CVTDLr $src))>; 1715*da58b97aSjoerg 1716*da58b97aSjoergdef : Pat<(i64 (anyext i32:$sy)), 1717*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, sub_i32)>; 1718*da58b97aSjoerg 1719*da58b97aSjoerg 1720*da58b97aSjoerg// extload, sextload and zextload stuff 1721*da58b97aSjoergmulticlass EXT64m<SDPatternOperator from, 1722*da58b97aSjoerg RM torri, 1723*da58b97aSjoerg RM torii, 1724*da58b97aSjoerg RM tozri, 1725*da58b97aSjoerg RM tozii> { 1726*da58b97aSjoerg def : Pat<(i64 (from ADDRrri:$addr)), 1727*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (torri MEMrri:$addr), 1728*da58b97aSjoerg sub_i32)>; 1729*da58b97aSjoerg def : Pat<(i64 (from ADDRrii:$addr)), 1730*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (torii MEMrii:$addr), 1731*da58b97aSjoerg sub_i32)>; 1732*da58b97aSjoerg def : Pat<(i64 (from ADDRzri:$addr)), 1733*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (tozri MEMzri:$addr), 1734*da58b97aSjoerg sub_i32)>; 1735*da58b97aSjoerg def : Pat<(i64 (from ADDRzii:$addr)), 1736*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (tozii MEMzii:$addr), 1737*da58b97aSjoerg sub_i32)>; 1738*da58b97aSjoerg} 1739*da58b97aSjoergdefm : EXT64m<sextloadi8, LD1BSXrri, LD1BSXrii, LD1BSXzri, LD1BSXzii>; 1740*da58b97aSjoergdefm : EXT64m<zextloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>; 1741*da58b97aSjoergdefm : EXT64m<extloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>; 1742*da58b97aSjoergdefm : EXT64m<sextloadi16, LD2BSXrri, LD2BSXrii, LD2BSXzri, LD2BSXzii>; 1743*da58b97aSjoergdefm : EXT64m<zextloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>; 1744*da58b97aSjoergdefm : EXT64m<extloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>; 1745*da58b97aSjoergdefm : EXT64m<sextloadi32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>; 1746*da58b97aSjoergdefm : EXT64m<zextloadi32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>; 1747*da58b97aSjoergdefm : EXT64m<extloadi32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>; 1748*da58b97aSjoerg 1749*da58b97aSjoerg// anyextload 1750*da58b97aSjoergmulticlass EXT32m<SDPatternOperator from, 1751*da58b97aSjoerg RM torri, 1752*da58b97aSjoerg RM torii, 1753*da58b97aSjoerg RM tozri, 1754*da58b97aSjoerg RM tozii> { 1755*da58b97aSjoerg def : Pat<(from ADDRrri:$addr), (torri MEMrri:$addr)>; 1756*da58b97aSjoerg def : Pat<(from ADDRrii:$addr), (torii MEMrii:$addr)>; 1757*da58b97aSjoerg def : Pat<(from ADDRzri:$addr), (tozri MEMzri:$addr)>; 1758*da58b97aSjoerg def : Pat<(from ADDRzii:$addr), (tozii MEMzii:$addr)>; 1759*da58b97aSjoerg} 1760*da58b97aSjoergdefm : EXT32m<extloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>; 1761*da58b97aSjoergdefm : EXT32m<extloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>; 1762*da58b97aSjoerg 1763*da58b97aSjoerg// truncstore 1764*da58b97aSjoergmulticlass TRUNC64m<SDPatternOperator from, 1765*da58b97aSjoerg RM torri, 1766*da58b97aSjoerg RM torii, 1767*da58b97aSjoerg RM tozri, 1768*da58b97aSjoerg RM tozii> { 1769*da58b97aSjoerg def : Pat<(from i64:$src, ADDRrri:$addr), 1770*da58b97aSjoerg (torri MEMrri:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1771*da58b97aSjoerg def : Pat<(from i64:$src, ADDRrii:$addr), 1772*da58b97aSjoerg (torii MEMrii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1773*da58b97aSjoerg def : Pat<(from i64:$src, ADDRzri:$addr), 1774*da58b97aSjoerg (tozri MEMzri:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1775*da58b97aSjoerg def : Pat<(from i64:$src, ADDRzii:$addr), 1776*da58b97aSjoerg (tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1777*da58b97aSjoerg} 1778*da58b97aSjoergdefm : TRUNC64m<truncstorei8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>; 1779*da58b97aSjoergdefm : TRUNC64m<truncstorei16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>; 1780*da58b97aSjoergdefm : TRUNC64m<truncstorei32, STLrri, STLrii, STLzri, ST1Bzii>; 1781*da58b97aSjoerg 1782*da58b97aSjoerg// Atomic loads 1783*da58b97aSjoergmulticlass ATMLDm<SDPatternOperator from, 1784*da58b97aSjoerg RM torri, RM torii, 1785*da58b97aSjoerg RM tozri, RM tozii> { 1786*da58b97aSjoerg def : Pat<(from ADDRrri:$addr), (torri MEMrri:$addr)>; 1787*da58b97aSjoerg def : Pat<(from ADDRrii:$addr), (torii MEMrii:$addr)>; 1788*da58b97aSjoerg def : Pat<(from ADDRzri:$addr), (tozri MEMzri:$addr)>; 1789*da58b97aSjoerg def : Pat<(from ADDRzii:$addr), (tozii MEMzii:$addr)>; 1790*da58b97aSjoerg} 1791*da58b97aSjoergdefm : ATMLDm<atomic_load_8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>; 1792*da58b97aSjoergdefm : ATMLDm<atomic_load_16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>; 1793*da58b97aSjoergdefm : ATMLDm<atomic_load_32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>; 1794*da58b97aSjoergdefm : ATMLDm<atomic_load_64, LDrri, LDrii, LDzri, LDzii>; 1795*da58b97aSjoerg 1796*da58b97aSjoerg// Optimized atomic loads with sext 1797*da58b97aSjoergmulticlass SXATMLDm<SDPatternOperator from, ValueType TY, 1798*da58b97aSjoerg RM torri, RM torii, 1799*da58b97aSjoerg RM tozri, RM tozii> { 1800*da58b97aSjoerg def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrri:$addr))), TY)), 1801*da58b97aSjoerg (i2l (torri MEMrri:$addr))>; 1802*da58b97aSjoerg def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrii:$addr))), TY)), 1803*da58b97aSjoerg (i2l (torii MEMrii:$addr))>; 1804*da58b97aSjoerg def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzri:$addr))), TY)), 1805*da58b97aSjoerg (i2l (tozri MEMzri:$addr))>; 1806*da58b97aSjoerg def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzii:$addr))), TY)), 1807*da58b97aSjoerg (i2l (tozii MEMzii:$addr))>; 1808*da58b97aSjoerg} 1809*da58b97aSjoergmulticlass SXATMLD32m<SDPatternOperator from, 1810*da58b97aSjoerg RM torri, RM torii, 1811*da58b97aSjoerg RM tozri, RM tozii> { 1812*da58b97aSjoerg def : Pat<(i64 (sext (from ADDRrri:$addr))), 1813*da58b97aSjoerg (i2l (torri MEMrri:$addr))>; 1814*da58b97aSjoerg def : Pat<(i64 (sext (from ADDRrii:$addr))), 1815*da58b97aSjoerg (i2l (torii MEMrii:$addr))>; 1816*da58b97aSjoerg def : Pat<(i64 (sext (from ADDRzri:$addr))), 1817*da58b97aSjoerg (i2l (tozri MEMzri:$addr))>; 1818*da58b97aSjoerg def : Pat<(i64 (sext (from ADDRzii:$addr))), 1819*da58b97aSjoerg (i2l (tozii MEMzii:$addr))>; 1820*da58b97aSjoerg} 1821*da58b97aSjoergdefm : SXATMLDm<atomic_load_8, i8, LD1BSXrri, LD1BSXrii, LD1BSXzri, LD1BSXzii>; 1822*da58b97aSjoergdefm : SXATMLDm<atomic_load_16, i16, LD2BSXrri, LD2BSXrii, LD2BSXzri, 1823*da58b97aSjoerg LD2BSXzii>; 1824*da58b97aSjoergdefm : SXATMLD32m<atomic_load_32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>; 1825*da58b97aSjoerg 1826*da58b97aSjoerg// Optimized atomic loads with zext 1827*da58b97aSjoergmulticlass ZXATMLDm<SDPatternOperator from, int VAL, 1828*da58b97aSjoerg RM torri, RM torii, 1829*da58b97aSjoerg RM tozri, RM tozii> { 1830*da58b97aSjoerg def : Pat<(i64 (and (anyext (from ADDRrri:$addr)), VAL)), 1831*da58b97aSjoerg (i2l (torri MEMrri:$addr))>; 1832*da58b97aSjoerg def : Pat<(i64 (and (anyext (from ADDRrii:$addr)), VAL)), 1833*da58b97aSjoerg (i2l (torii MEMrii:$addr))>; 1834*da58b97aSjoerg def : Pat<(i64 (and (anyext (from ADDRzri:$addr)), VAL)), 1835*da58b97aSjoerg (i2l (tozri MEMzri:$addr))>; 1836*da58b97aSjoerg def : Pat<(i64 (and (anyext (from ADDRzii:$addr)), VAL)), 1837*da58b97aSjoerg (i2l (tozii MEMzii:$addr))>; 1838*da58b97aSjoerg} 1839*da58b97aSjoergmulticlass ZXATMLD32m<SDPatternOperator from, int VAL, 1840*da58b97aSjoerg RM torri, RM torii, 1841*da58b97aSjoerg RM tozri, RM tozii> { 1842*da58b97aSjoerg def : Pat<(i64 (zext (from ADDRrri:$addr))), 1843*da58b97aSjoerg (i2l (torri MEMrri:$addr))>; 1844*da58b97aSjoerg def : Pat<(i64 (zext (from ADDRrii:$addr))), 1845*da58b97aSjoerg (i2l (torii MEMrii:$addr))>; 1846*da58b97aSjoerg def : Pat<(i64 (zext (from ADDRzri:$addr))), 1847*da58b97aSjoerg (i2l (tozri MEMzri:$addr))>; 1848*da58b97aSjoerg def : Pat<(i64 (zext (from ADDRzii:$addr))), 1849*da58b97aSjoerg (i2l (tozii MEMzii:$addr))>; 1850*da58b97aSjoerg} 1851*da58b97aSjoergdefm : ZXATMLDm<atomic_load_8, 0xFF, LD1BZXrri, LD1BZXrii, LD1BZXzri, 1852*da58b97aSjoerg LD1BZXzii>; 1853*da58b97aSjoergdefm : ZXATMLDm<atomic_load_16, 0xFFFF, LD2BZXrri, LD2BZXrii, LD2BZXzri, 1854*da58b97aSjoerg LD2BZXzii>; 1855*da58b97aSjoergdefm : ZXATMLD32m<atomic_load_32, 0xFFFFFFFF, LDLZXrri, LDLZXrii, LDLZXzri, 1856*da58b97aSjoerg LDLZXzii>; 1857*da58b97aSjoerg 1858*da58b97aSjoerg// Atomic stores 1859*da58b97aSjoergmulticlass ATMSTm<SDPatternOperator from, ValueType ty, 1860*da58b97aSjoerg RM torri, RM torii, 1861*da58b97aSjoerg RM tozri, RM tozii> { 1862*da58b97aSjoerg def : Pat<(from ADDRrri:$addr, ty:$src), (torri MEMrri:$addr, $src)>; 1863*da58b97aSjoerg def : Pat<(from ADDRrii:$addr, ty:$src), (torii MEMrii:$addr, $src)>; 1864*da58b97aSjoerg def : Pat<(from ADDRzri:$addr, ty:$src), (tozri MEMzri:$addr, $src)>; 1865*da58b97aSjoerg def : Pat<(from ADDRzii:$addr, ty:$src), (tozii MEMzii:$addr, $src)>; 1866*da58b97aSjoerg} 1867*da58b97aSjoergdefm : ATMSTm<atomic_store_8, i32, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>; 1868*da58b97aSjoergdefm : ATMSTm<atomic_store_16, i32, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>; 1869*da58b97aSjoergdefm : ATMSTm<atomic_store_32, i32, STLrri, STLrii, STLzri, STLzii>; 1870*da58b97aSjoergdefm : ATMSTm<atomic_store_64, i64, STrri, STrii, STzri, STzii>; 1871*da58b97aSjoerg 1872*da58b97aSjoerg// Optimized atomic stores with truncate 1873*da58b97aSjoergmulticlass TRATMSTm<SDPatternOperator from, 1874*da58b97aSjoerg ValueType ty, 1875*da58b97aSjoerg RM torri, 1876*da58b97aSjoerg RM torii, 1877*da58b97aSjoerg RM tozri, 1878*da58b97aSjoerg RM tozii> { 1879*da58b97aSjoerg def : Pat<(from ADDRrri:$addr, (i32 (trunc i64:$src))), 1880*da58b97aSjoerg (torri MEMrri:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1881*da58b97aSjoerg def : Pat<(from ADDRrii:$addr, (i32 (trunc i64:$src))), 1882*da58b97aSjoerg (torii MEMrii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1883*da58b97aSjoerg def : Pat<(from ADDRzri:$addr, (i32 (trunc i64:$src))), 1884*da58b97aSjoerg (tozri MEMzri:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1885*da58b97aSjoerg def : Pat<(from ADDRzii:$addr, (i32 (trunc i64:$src))), 1886*da58b97aSjoerg (tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; 1887*da58b97aSjoerg} 1888*da58b97aSjoergdefm : TRATMSTm<atomic_store_8, i32, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>; 1889*da58b97aSjoergdefm : TRATMSTm<atomic_store_16, i32, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>; 1890*da58b97aSjoergdefm : TRATMSTm<atomic_store_32, i32, STLrri, STLrii, STLzri, STLzii>; 1891*da58b97aSjoerg 1892*da58b97aSjoerg// Atomic swaps 1893*da58b97aSjoergdef : Pat<(i32 (ts1am i64:$src, i32:$flag, i32:$new)), 1894*da58b97aSjoerg (TS1AMWrir $src, 0, $flag, $new)>; 1895*da58b97aSjoergdef : Pat<(i32 (atomic_swap_32 ADDRri:$src, i32:$new)), 1896*da58b97aSjoerg (TS1AMWrii MEMriRRM:$src, 15, $new)>; 1897*da58b97aSjoergdef : Pat<(i64 (atomic_swap_64 ADDRri:$src, i64:$new)), 1898*da58b97aSjoerg (TS1AMLrir MEMriRRM:$src, (LEAzii 0, 0, 255), i64:$new)>; 1899*da58b97aSjoerg 1900*da58b97aSjoerg//===----------------------------------------------------------------------===// 1901*da58b97aSjoerg// SJLJ Exception handling patterns 1902*da58b97aSjoerg//===----------------------------------------------------------------------===// 1903*da58b97aSjoerg 1904*da58b97aSjoerglet hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1905*da58b97aSjoerg usesCustomInserter = 1 in { 1906*da58b97aSjoerg let isTerminator = 1 in 1907*da58b97aSjoerg def EH_SjLj_LongJmp : Pseudo<(outs), (ins I64:$buf), 1908*da58b97aSjoerg "# EH_SJLJ_LONGJMP", 1909*da58b97aSjoerg [(VEeh_sjlj_longjmp I64:$buf)]>; 1910*da58b97aSjoerg 1911*da58b97aSjoerg def EH_SjLj_SetJmp : Pseudo<(outs I32:$dst), (ins I64:$buf), 1912*da58b97aSjoerg "# EH_SJLJ_SETJMP", 1913*da58b97aSjoerg [(set I32:$dst, (VEeh_sjlj_setjmp I64:$buf))]>; 1914*da58b97aSjoerg 1915*da58b97aSjoerg def EH_SjLj_Setup_Dispatch : Pseudo<(outs), (ins), "# EH_SJLJ_SETUP_DISPATCH", 1916*da58b97aSjoerg [(VEeh_sjlj_setup_dispatch)]>; 1917*da58b97aSjoerg} 1918*da58b97aSjoerg 1919*da58b97aSjoerglet isTerminator = 1, isBranch = 1, isCodeGenOnly = 1 in 1920*da58b97aSjoerg def EH_SjLj_Setup : Pseudo<(outs), (ins brtarget32:$dst), 1921*da58b97aSjoerg "# EH_SJlJ_SETUP $dst">; 1922*da58b97aSjoerg 1923*da58b97aSjoerg//===----------------------------------------------------------------------===// 1924*da58b97aSjoerg// Branch related patterns 1925*da58b97aSjoerg//===----------------------------------------------------------------------===// 1926*da58b97aSjoerg 1927*da58b97aSjoerg// Branches 1928*da58b97aSjoergdef : Pat<(br bb:$addr), (BRCFLa bb:$addr)>; 1929*da58b97aSjoerg 1930*da58b97aSjoerg// brcc 1931*da58b97aSjoerg// integer brcc 1932*da58b97aSjoergmulticlass BRCCIm<ValueType ty, CF BrOpNode1, 1933*da58b97aSjoerg CF BrOpNode2, 1934*da58b97aSjoerg RR CmpOpNode1, 1935*da58b97aSjoerg RR CmpOpNode2> { 1936*da58b97aSjoerg def : Pat<(brcc CCSIOp:$cond, ty:$l, simm7:$r, bb:$addr), 1937*da58b97aSjoerg (BrOpNode2 (icond2ccSwap $cond), (LO7 $r), $l, bb:$addr)>; 1938*da58b97aSjoerg def : Pat<(brcc CCSIOp:$cond, ty:$l, ty:$r, bb:$addr), 1939*da58b97aSjoerg (BrOpNode1 (icond2cc $cond), $l, $r, bb:$addr)>; 1940*da58b97aSjoerg def : Pat<(brcc CCUIOp:$cond, ty:$l, simm7:$r, bb:$addr), 1941*da58b97aSjoerg (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode2 (LO7 $r), $l), 1942*da58b97aSjoerg bb:$addr)>; 1943*da58b97aSjoerg def : Pat<(brcc CCUIOp:$cond, ty:$l, ty:$r, bb:$addr), 1944*da58b97aSjoerg (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode1 $r, $l), bb:$addr)>; 1945*da58b97aSjoerg} 1946*da58b97aSjoergdefm : BRCCIm<i32, BRCFWrr, BRCFWir, CMPUWrr, CMPUWir>; 1947*da58b97aSjoergdefm : BRCCIm<i64, BRCFLrr, BRCFLir, CMPULrr, CMPULir>; 1948*da58b97aSjoerg 1949*da58b97aSjoerg// floating point brcc 1950*da58b97aSjoergmulticlass BRCCFm<ValueType ty, CF BrOpNode1, CF BrOpNode2> { 1951*da58b97aSjoerg def : Pat<(brcc cond:$cond, ty:$l, simm7fp:$r, bb:$addr), 1952*da58b97aSjoerg (BrOpNode2 (fcond2ccSwap $cond), (LO7FP $r), $l, bb:$addr)>; 1953*da58b97aSjoerg def : Pat<(brcc cond:$cond, ty:$l, ty:$r, bb:$addr), 1954*da58b97aSjoerg (BrOpNode1 (fcond2cc $cond), $l, $r, bb:$addr)>; 1955*da58b97aSjoerg} 1956*da58b97aSjoergdefm : BRCCFm<f32, BRCFSrr, BRCFSir>; 1957*da58b97aSjoergdefm : BRCCFm<f64, BRCFDrr, BRCFDir>; 1958*da58b97aSjoergdef : Pat<(brcc cond:$cond, f128:$l, f128:$r, bb:$addr), 1959*da58b97aSjoerg (BRCFDir (fcond2cc $cond), 0, (FCMPQrr $r, $l), bb:$addr)>; 1960*da58b97aSjoerg 1961*da58b97aSjoerg//===----------------------------------------------------------------------===// 1962*da58b97aSjoerg// Pseudo Instructions 1963*da58b97aSjoerg//===----------------------------------------------------------------------===// 1964*da58b97aSjoerg 1965*da58b97aSjoerg// GETGOT for PIC 1966*da58b97aSjoerglet Defs = [SX15 /* %got */, SX16 /* %plt */], hasSideEffects = 0 in { 1967*da58b97aSjoerg def GETGOT : Pseudo<(outs getGOT:$getpcseq), (ins), "$getpcseq">; 1968*da58b97aSjoerg} 1969*da58b97aSjoerg 1970*da58b97aSjoerg// GETFUNPLT for PIC 1971*da58b97aSjoerglet hasSideEffects = 0 in 1972*da58b97aSjoergdef GETFUNPLT : Pseudo<(outs I64:$dst), (ins i64imm:$addr), 1973*da58b97aSjoerg "$dst, $addr", 1974*da58b97aSjoerg [(set iPTR:$dst, (GetFunPLT tglobaladdr:$addr))] >; 1975*da58b97aSjoerg 1976*da58b97aSjoergdef : Pat<(GetFunPLT tglobaladdr:$dst), 1977*da58b97aSjoerg (GETFUNPLT tglobaladdr:$dst)>; 1978*da58b97aSjoergdef : Pat<(GetFunPLT texternalsym:$dst), 1979*da58b97aSjoerg (GETFUNPLT texternalsym:$dst)>; 1980*da58b97aSjoerg 1981*da58b97aSjoerg// GETTLSADDR for TLS 1982*da58b97aSjoerglet Defs = [SX0, SX10, SX12], hasSideEffects = 0 in 1983*da58b97aSjoergdef GETTLSADDR : Pseudo<(outs), (ins i64imm:$addr), 1984*da58b97aSjoerg "# GETTLSADDR $addr", 1985*da58b97aSjoerg [(GetTLSAddr tglobaltlsaddr:$addr)] >; 1986*da58b97aSjoerg 1987*da58b97aSjoergdef : Pat<(GetTLSAddr tglobaltlsaddr:$dst), 1988*da58b97aSjoerg (GETTLSADDR tglobaltlsaddr:$dst)>; 1989*da58b97aSjoerg 1990*da58b97aSjoerglet Defs = [SX11], Uses = [SX11], hasSideEffects = 0 in { 1991*da58b97aSjoergdef ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt, i64imm:$amt2), 1992*da58b97aSjoerg "# ADJCALLSTACKDOWN $amt, $amt2", 1993*da58b97aSjoerg [(callseq_start timm:$amt, timm:$amt2)]>; 1994*da58b97aSjoergdef ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 1995*da58b97aSjoerg "# ADJCALLSTACKUP $amt1", 1996*da58b97aSjoerg [(callseq_end timm:$amt1, timm:$amt2)]>; 1997*da58b97aSjoerg} 1998*da58b97aSjoerg 1999*da58b97aSjoerglet Defs = [SX8], Uses = [SX8, SX11], hasSideEffects = 0 in 2000*da58b97aSjoergdef EXTEND_STACK : Pseudo<(outs), (ins), 2001*da58b97aSjoerg "# EXTEND STACK", 2002*da58b97aSjoerg []>; 2003*da58b97aSjoerglet hasSideEffects = 0 in 2004*da58b97aSjoergdef EXTEND_STACK_GUARD : Pseudo<(outs), (ins), 2005*da58b97aSjoerg "# EXTEND STACK GUARD", 2006*da58b97aSjoerg []>; 2007*da58b97aSjoerg 2008*da58b97aSjoerg// Dynamic stack allocation yields a __llvm_grow_stack for VE targets. 2009*da58b97aSjoerg// These calls are needed to probe the stack when allocating more over 2010*da58b97aSjoerg// %s8 (%sl - stack limit). 2011*da58b97aSjoerg 2012*da58b97aSjoerglet Uses = [SX11], hasSideEffects = 1 in 2013*da58b97aSjoergdef GETSTACKTOP : Pseudo<(outs I64:$dst), (ins), 2014*da58b97aSjoerg "# GET STACK TOP", 2015*da58b97aSjoerg [(set iPTR:$dst, (GetStackTop))]>; 2016*da58b97aSjoerg 2017*da58b97aSjoerg// MEMBARRIER 2018*da58b97aSjoerglet hasSideEffects = 1 in 2019*da58b97aSjoergdef MEMBARRIER : Pseudo<(outs), (ins), "# MEMBARRIER", [(MemBarrier)] >; 2020*da58b97aSjoerg 2021*da58b97aSjoerg//===----------------------------------------------------------------------===// 2022*da58b97aSjoerg// Other patterns 2023*da58b97aSjoerg//===----------------------------------------------------------------------===// 2024*da58b97aSjoerg 2025*da58b97aSjoerg// SETCC pattern matches 2026*da58b97aSjoerg// 2027*da58b97aSjoerg// CMP %tmp, lhs, rhs ; compare lhs and rhs 2028*da58b97aSjoerg// or %res, 0, (0)1 ; initialize by 0 2029*da58b97aSjoerg// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true 2030*da58b97aSjoerg 2031*da58b97aSjoergclass setccrr<Instruction INSN> : 2032*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp), 2033*da58b97aSjoerg (EXTRACT_SUBREG 2034*da58b97aSjoerg (INSN $cond, $comp, 2035*da58b97aSjoerg !add(63, 64), // means (63)0 == 1 2036*da58b97aSjoerg (ORim 0, 0)), sub_i32)>; 2037*da58b97aSjoerg 2038*da58b97aSjoergdef : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)), 2039*da58b97aSjoerg (setccrr<CMOVWrm> (icond2cc $cond), (CMPSWSXrr $l, $r))>; 2040*da58b97aSjoergdef : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)), 2041*da58b97aSjoerg (setccrr<CMOVWrm> (icond2cc $cond), (CMPUWrr $l, $r))>; 2042*da58b97aSjoergdef : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)), 2043*da58b97aSjoerg (setccrr<CMOVLrm> (icond2cc $cond), (CMPSLrr $l, $r))>; 2044*da58b97aSjoergdef : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)), 2045*da58b97aSjoerg (setccrr<CMOVLrm> (icond2cc $cond), (CMPULrr $l, $r))>; 2046*da58b97aSjoergdef : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)), 2047*da58b97aSjoerg (setccrr<CMOVSrm> (fcond2cc $cond), (FCMPSrr $l, $r))>; 2048*da58b97aSjoergdef : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)), 2049*da58b97aSjoerg (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPDrr $l, $r))>; 2050*da58b97aSjoergdef : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)), 2051*da58b97aSjoerg (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>; 2052*da58b97aSjoerg 2053*da58b97aSjoerg// Special SELECTCC pattern matches 2054*da58b97aSjoerg// Use min/max for better performance. 2055*da58b97aSjoerg// 2056*da58b97aSjoerg// MAX/MIN %res, %lhs, %rhs 2057*da58b97aSjoerg 2058*da58b97aSjoergdef : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)), 2059*da58b97aSjoerg (FMAXDrr $LHS, $RHS)>; 2060*da58b97aSjoergdef : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGT)), 2061*da58b97aSjoerg (FMAXSrr $LHS, $RHS)>; 2062*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGT)), 2063*da58b97aSjoerg (MAXSLrr $LHS, $RHS)>; 2064*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGT)), 2065*da58b97aSjoerg (MAXSWSXrr $LHS, $RHS)>; 2066*da58b97aSjoergdef : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGE)), 2067*da58b97aSjoerg (FMAXDrr $LHS, $RHS)>; 2068*da58b97aSjoergdef : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGE)), 2069*da58b97aSjoerg (FMAXSrr $LHS, $RHS)>; 2070*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGE)), 2071*da58b97aSjoerg (MAXSLrr $LHS, $RHS)>; 2072*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGE)), 2073*da58b97aSjoerg (MAXSWSXrr $LHS, $RHS)>; 2074*da58b97aSjoerg 2075*da58b97aSjoergdef : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLT)), 2076*da58b97aSjoerg (FMINDrr $LHS, $RHS)>; 2077*da58b97aSjoergdef : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLT)), 2078*da58b97aSjoerg (FMINSrr $LHS, $RHS)>; 2079*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLT)), 2080*da58b97aSjoerg (MINSLrr $LHS, $RHS)>; 2081*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLT)), 2082*da58b97aSjoerg (MINSWSXrr $LHS, $RHS)>; 2083*da58b97aSjoergdef : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLE)), 2084*da58b97aSjoerg (FMINDrr $LHS, $RHS)>; 2085*da58b97aSjoergdef : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLE)), 2086*da58b97aSjoerg (FMINSrr $LHS, $RHS)>; 2087*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLE)), 2088*da58b97aSjoerg (MINSLrr $LHS, $RHS)>; 2089*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLE)), 2090*da58b97aSjoerg (MINSWSXrr $LHS, $RHS)>; 2091*da58b97aSjoerg 2092*da58b97aSjoerg// Helper classes to construct cmov patterns for the ease. 2093*da58b97aSjoerg// 2094*da58b97aSjoerg// Hiding INSERT_SUBREG/EXTRACT_SUBREG patterns. 2095*da58b97aSjoerg 2096*da58b97aSjoergclass cmovrr<Instruction INSN> : 2097*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), 2098*da58b97aSjoerg (INSN $cond, $comp, $t, $f)>; 2099*da58b97aSjoergclass cmovrm<Instruction INSN, SDNodeXForm MOP = MIMM> : 2100*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), 2101*da58b97aSjoerg (INSN $cond, $comp, (MOP $t), $f)>; 2102*da58b97aSjoergclass cmov32rr<Instruction INSN, SubRegIndex sub_oty> : 2103*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), 2104*da58b97aSjoerg (EXTRACT_SUBREG 2105*da58b97aSjoerg (INSN $cond, $comp, 2106*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_oty), 2107*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)), 2108*da58b97aSjoerg sub_oty)>; 2109*da58b97aSjoergclass cmov32rm<Instruction INSN, SubRegIndex sub_oty, SDNodeXForm MOP = MIMM> : 2110*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), 2111*da58b97aSjoerg (EXTRACT_SUBREG 2112*da58b97aSjoerg (INSN $cond, $comp, 2113*da58b97aSjoerg (MOP $t), 2114*da58b97aSjoerg (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)), 2115*da58b97aSjoerg sub_oty)>; 2116*da58b97aSjoergclass cmov128rr<Instruction INSN> : 2117*da58b97aSjoerg OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f), 2118*da58b97aSjoerg (INSERT_SUBREG 2119*da58b97aSjoerg (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 2120*da58b97aSjoerg (INSN $cond, $comp, 2121*da58b97aSjoerg (EXTRACT_SUBREG $t, sub_odd), 2122*da58b97aSjoerg (EXTRACT_SUBREG $f, sub_odd)), sub_odd), 2123*da58b97aSjoerg (INSN $cond, $comp, 2124*da58b97aSjoerg (EXTRACT_SUBREG $t, sub_even), 2125*da58b97aSjoerg (EXTRACT_SUBREG $f, sub_even)), sub_even)>; 2126*da58b97aSjoerg 2127*da58b97aSjoerg// Generic SELECTCC pattern matches 2128*da58b97aSjoerg// 2129*da58b97aSjoerg// CMP %tmp, %l, %r ; compare %l and %r 2130*da58b97aSjoerg// or %res, %f, (0)1 ; initialize by %f 2131*da58b97aSjoerg// CMOV %res, %t, %tmp ; set %t if %tmp is true 2132*da58b97aSjoerg 2133*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCSIOp:$cond)), 2134*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_i32> (icond2cc $cond), (CMPSWSXrr $l, $r), 2135*da58b97aSjoerg $t, $f)>; 2136*da58b97aSjoergdef : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCUIOp:$cond)), 2137*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_i32> (icond2cc $cond), (CMPUWrr $l, $r), 2138*da58b97aSjoerg $t, $f)>; 2139*da58b97aSjoergdef : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCSIOp:$cond)), 2140*da58b97aSjoerg (cmov32rr<CMOVLrr, sub_i32> (icond2cc $cond), (CMPSLrr $l, $r), 2141*da58b97aSjoerg $t, $f)>; 2142*da58b97aSjoergdef : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCUIOp:$cond)), 2143*da58b97aSjoerg (cmov32rr<CMOVLrr, sub_i32> (icond2cc $cond), (CMPULrr $l, $r), 2144*da58b97aSjoerg $t, $f)>; 2145*da58b97aSjoergdef : Pat<(i32 (selectcc f32:$l, f32:$r, i32:$t, i32:$f, cond:$cond)), 2146*da58b97aSjoerg (cmov32rr<CMOVSrr, sub_i32> (fcond2cc $cond), (FCMPSrr $l, $r), 2147*da58b97aSjoerg $t, $f)>; 2148*da58b97aSjoergdef : Pat<(i32 (selectcc f64:$l, f64:$r, i32:$t, i32:$f, cond:$cond)), 2149*da58b97aSjoerg (cmov32rr<CMOVDrr, sub_i32> (fcond2cc $cond), (FCMPDrr $l, $r), 2150*da58b97aSjoerg $t, $f)>; 2151*da58b97aSjoergdef : Pat<(i32 (selectcc f128:$l, f128:$r, i32:$t, i32:$f, cond:$cond)), 2152*da58b97aSjoerg (cmov32rr<CMOVDrr, sub_i32> (fcond2cc $cond), (FCMPQrr $l, $r), 2153*da58b97aSjoerg $t, $f)>; 2154*da58b97aSjoerg 2155*da58b97aSjoergdef : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCSIOp:$cond)), 2156*da58b97aSjoerg (cmovrr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; 2157*da58b97aSjoergdef : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCUIOp:$cond)), 2158*da58b97aSjoerg (cmovrr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; 2159*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCSIOp:$cond)), 2160*da58b97aSjoerg (cmovrr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; 2161*da58b97aSjoergdef : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCUIOp:$cond)), 2162*da58b97aSjoerg (cmovrr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; 2163*da58b97aSjoergdef : Pat<(i64 (selectcc f32:$l, f32:$r, i64:$t, i64:$f, cond:$cond)), 2164*da58b97aSjoerg (cmovrr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; 2165*da58b97aSjoergdef : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)), 2166*da58b97aSjoerg (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; 2167*da58b97aSjoergdef : Pat<(i64 (selectcc f128:$l, f128:$r, i64:$t, i64:$f, cond:$cond)), 2168*da58b97aSjoerg (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; 2169*da58b97aSjoerg 2170*da58b97aSjoergdef : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCSIOp:$cond)), 2171*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_f32> (icond2cc $cond), (CMPSWSXrr $l, $r), 2172*da58b97aSjoerg $t, $f)>; 2173*da58b97aSjoergdef : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCUIOp:$cond)), 2174*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_f32> (icond2cc $cond), (CMPUWrr $l, $r), 2175*da58b97aSjoerg $t, $f)>; 2176*da58b97aSjoergdef : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCSIOp:$cond)), 2177*da58b97aSjoerg (cmov32rr<CMOVLrr, sub_f32> (icond2cc $cond), (CMPSLrr $l, $r), 2178*da58b97aSjoerg $t, $f)>; 2179*da58b97aSjoergdef : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCUIOp:$cond)), 2180*da58b97aSjoerg (cmov32rr<CMOVLrr, sub_f32> (icond2cc $cond), (CMPULrr $l, $r), 2181*da58b97aSjoerg $t, $f)>; 2182*da58b97aSjoergdef : Pat<(f32 (selectcc f32:$l, f32:$r, f32:$t, f32:$f, cond:$cond)), 2183*da58b97aSjoerg (cmov32rr<CMOVSrr, sub_f32> (fcond2cc $cond), (FCMPSrr $l, $r), 2184*da58b97aSjoerg $t, $f)>; 2185*da58b97aSjoergdef : Pat<(f32 (selectcc f64:$l, f64:$r, f32:$t, f32:$f, cond:$cond)), 2186*da58b97aSjoerg (cmov32rr<CMOVDrr, sub_f32> (fcond2cc $cond), (FCMPDrr $l, $r), 2187*da58b97aSjoerg $t, $f)>; 2188*da58b97aSjoergdef : Pat<(f32 (selectcc f128:$l, f128:$r, f32:$t, f32:$f, cond:$cond)), 2189*da58b97aSjoerg (cmov32rr<CMOVDrr, sub_f32> (fcond2cc $cond), (FCMPQrr $l, $r), 2190*da58b97aSjoerg $t, $f)>; 2191*da58b97aSjoerg 2192*da58b97aSjoergdef : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCSIOp:$cond)), 2193*da58b97aSjoerg (cmovrr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; 2194*da58b97aSjoergdef : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCUIOp:$cond)), 2195*da58b97aSjoerg (cmovrr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; 2196*da58b97aSjoergdef : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCSIOp:$cond)), 2197*da58b97aSjoerg (cmovrr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; 2198*da58b97aSjoergdef : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCUIOp:$cond)), 2199*da58b97aSjoerg (cmovrr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; 2200*da58b97aSjoergdef : Pat<(f64 (selectcc f32:$l, f32:$r, f64:$t, f64:$f, cond:$cond)), 2201*da58b97aSjoerg (cmovrr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; 2202*da58b97aSjoergdef : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)), 2203*da58b97aSjoerg (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; 2204*da58b97aSjoergdef : Pat<(f64 (selectcc f128:$l, f128:$r, f64:$t, f64:$f, cond:$cond)), 2205*da58b97aSjoerg (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; 2206*da58b97aSjoerg 2207*da58b97aSjoergdef : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCSIOp:$cond)), 2208*da58b97aSjoerg (cmov128rr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>; 2209*da58b97aSjoergdef : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCUIOp:$cond)), 2210*da58b97aSjoerg (cmov128rr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; 2211*da58b97aSjoergdef : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCSIOp:$cond)), 2212*da58b97aSjoerg (cmov128rr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>; 2213*da58b97aSjoergdef : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCUIOp:$cond)), 2214*da58b97aSjoerg (cmov128rr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>; 2215*da58b97aSjoergdef : Pat<(f128 (selectcc f32:$l, f32:$r, f128:$t, f128:$f, cond:$cond)), 2216*da58b97aSjoerg (cmov128rr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>; 2217*da58b97aSjoergdef : Pat<(f128 (selectcc f64:$l, f64:$r, f128:$t, f128:$f, cond:$cond)), 2218*da58b97aSjoerg (cmov128rr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>; 2219*da58b97aSjoergdef : Pat<(f128 (selectcc f128:$l, f128:$r, f128:$t, f128:$f, cond:$cond)), 2220*da58b97aSjoerg (cmov128rr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>; 2221*da58b97aSjoerg 2222*da58b97aSjoerg// Generic SELECT pattern matches 2223*da58b97aSjoerg// Use cmov.w for all cases since %pred holds i32. 2224*da58b97aSjoerg// 2225*da58b97aSjoerg// CMOV.w.ne %res, %tval, %tmp ; set tval if %tmp is true 2226*da58b97aSjoerg 2227*da58b97aSjoergdef : Pat<(i32 (select i32:$pred, i32:$t, i32:$f)), 2228*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_i32> CC_INE, $pred, $t, $f)>; 2229*da58b97aSjoergdef : Pat<(i32 (select i32:$pred, (i32 mimm:$t), i32:$f)), 2230*da58b97aSjoerg (cmov32rm<CMOVWrm, sub_i32> CC_INE, $pred, $t, $f)>; 2231*da58b97aSjoergdef : Pat<(i32 (select i32:$pred, i32:$t, (i32 mimm:$f))), 2232*da58b97aSjoerg (cmov32rm<CMOVWrm, sub_i32> CC_IEQ, $pred, $f, $t)>; 2233*da58b97aSjoerg 2234*da58b97aSjoergdef : Pat<(i64 (select i32:$pred, i64:$t, i64:$f)), 2235*da58b97aSjoerg (cmovrr<CMOVWrr> CC_INE, $pred, $t, $f)>; 2236*da58b97aSjoergdef : Pat<(i64 (select i32:$pred, (i64 mimm:$t), i64:$f)), 2237*da58b97aSjoerg (cmovrm<CMOVWrm, MIMM> CC_INE, $pred, $t, $f)>; 2238*da58b97aSjoergdef : Pat<(i64 (select i32:$pred, i64:$t, (i64 mimm:$f))), 2239*da58b97aSjoerg (cmovrm<CMOVWrm, MIMM> CC_IEQ, $pred, $f, $t)>; 2240*da58b97aSjoerg 2241*da58b97aSjoergdef : Pat<(f32 (select i32:$pred, f32:$t, f32:$f)), 2242*da58b97aSjoerg (cmov32rr<CMOVWrr, sub_f32> CC_INE, $pred, $t, $f)>; 2243*da58b97aSjoergdef : Pat<(f32 (select i32:$pred, (f32 mimmfp:$t), f32:$f)), 2244*da58b97aSjoerg (cmov32rm<CMOVWrm, sub_f32, MIMMFP> CC_INE, $pred, $t, $f)>; 2245*da58b97aSjoergdef : Pat<(f32 (select i32:$pred, f32:$t, (f32 mimmfp:$f))), 2246*da58b97aSjoerg (cmov32rm<CMOVWrm, sub_f32, MIMMFP> CC_IEQ, $pred, $f, $t)>; 2247*da58b97aSjoerg 2248*da58b97aSjoergdef : Pat<(f64 (select i32:$pred, f64:$t, f64:$f)), 2249*da58b97aSjoerg (cmovrr<CMOVWrr> CC_INE, $pred, $t, $f)>; 2250*da58b97aSjoergdef : Pat<(f64 (select i32:$pred, (f64 mimmfp:$t), f64:$f)), 2251*da58b97aSjoerg (cmovrm<CMOVWrm, MIMMFP> CC_INE, $pred, $t, $f)>; 2252*da58b97aSjoergdef : Pat<(f64 (select i32:$pred, f64:$t, (f64 mimmfp:$f))), 2253*da58b97aSjoerg (cmovrm<CMOVWrm, MIMMFP> CC_IEQ, $pred, $f, $t)>; 2254*da58b97aSjoerg 2255*da58b97aSjoergdef : Pat<(f128 (select i32:$pred, f128:$t, f128:$f)), 2256*da58b97aSjoerg (cmov128rr<CMOVWrr> CC_INE, $pred, $t, $f)>; 2257*da58b97aSjoerg 2258*da58b97aSjoerg// bitconvert 2259*da58b97aSjoergdef : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>; 2260*da58b97aSjoergdef : Pat<(i64 (bitconvert f64:$src)), (COPY_TO_REGCLASS $src, I64)>; 2261*da58b97aSjoerg 2262*da58b97aSjoergdef : Pat<(i32 (bitconvert f32:$op)), 2263*da58b97aSjoerg (EXTRACT_SUBREG (SRALri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2264*da58b97aSjoerg $op, sub_f32), 32), sub_i32)>; 2265*da58b97aSjoergdef : Pat<(f32 (bitconvert i32:$op)), 2266*da58b97aSjoerg (EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2267*da58b97aSjoerg $op, sub_i32), 32), sub_f32)>; 2268*da58b97aSjoerg 2269*da58b97aSjoerg// Optimize code A generated by `(unsigned char)c << 5` to B. 2270*da58b97aSjoerg// A) sla.w.sx %s0, %s0, 5 2271*da58b97aSjoerg// lea %s1, 224 ; 0xE0 2272*da58b97aSjoerg// and %s0, %s0, %s1 2273*da58b97aSjoerg// B) sla.w.sx %s0, %s0, 5 2274*da58b97aSjoerg// and %s0, %s0, (56)0 2275*da58b97aSjoerg 2276*da58b97aSjoergdef : Pat<(i32 (and i32:$val, 0xff)), 2277*da58b97aSjoerg (EXTRACT_SUBREG 2278*da58b97aSjoerg (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32), 2279*da58b97aSjoerg !add(56, 64)), sub_i32)>; 2280*da58b97aSjoergdef : Pat<(i32 (and i32:$val, 0xffff)), 2281*da58b97aSjoerg (EXTRACT_SUBREG 2282*da58b97aSjoerg (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32), 2283*da58b97aSjoerg !add(48, 64)), sub_i32)>; 2284*da58b97aSjoergdef : Pat<(i64 (and i64:$val, 0xffffffff)), 2285*da58b97aSjoerg (ANDrm $val, !add(32, 64))>; 2286*da58b97aSjoerg 2287*da58b97aSjoerg//===----------------------------------------------------------------------===// 2288*da58b97aSjoerg// Vector Instruction Pattern Stuff 2289*da58b97aSjoerg//===----------------------------------------------------------------------===// 2290*da58b97aSjoerg 2291*da58b97aSjoerg// Custom intermediate ISDs. 2292*da58b97aSjoergclass IsVLVT<int OpIdx> : SDTCisVT<OpIdx,i32>; 2293*da58b97aSjoergdef vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, 2294*da58b97aSjoerg [SDTCisVec<0>, IsVLVT<2>]>>; 2295*da58b97aSjoerg 2296*da58b97aSjoerg// Whether this is an all-true mask (assuming undef-bits above VL are all-true). 2297*da58b97aSjoergdef true_mask : PatLeaf< 2298*da58b97aSjoerg (vec_broadcast (i32 nonzero), (i32 srcvalue))>; 2299*da58b97aSjoerg// Match any broadcast (ignoring VL). 2300*da58b97aSjoergdef any_broadcast : PatFrag<(ops node:$sx), 2301*da58b97aSjoerg (vec_broadcast node:$sx, (i32 srcvalue))>; 2302*da58b97aSjoerg 2303*da58b97aSjoerg// Vector instructions. 2304*da58b97aSjoerginclude "VEInstrVec.td" 2305*da58b97aSjoerg 2306*da58b97aSjoerg// The vevlintrin 2307*da58b97aSjoerginclude "VEInstrIntrinsicVL.td" 2308*da58b97aSjoerg 2309*da58b97aSjoerg// Patterns and intermediate SD nodes (VEC_*). 2310*da58b97aSjoerginclude "VEInstrPatternsVec.td" 2311*da58b97aSjoerg 2312*da58b97aSjoerg// Patterns and intermediate SD nodes (VVP_*). 2313*da58b97aSjoerginclude "VVPInstrPatternsVec.td" 2314