1ed0d50c3Schristos /* Assemble Matsushita MN10200 instructions. 2*b88e3e88Schristos Copyright (C) 1996-2020 Free Software Foundation, Inc. 3ed0d50c3Schristos 4ed0d50c3Schristos This file is part of the GNU opcodes library. 5ed0d50c3Schristos 6ed0d50c3Schristos This library is free software; you can redistribute it and/or modify 7ed0d50c3Schristos it under the terms of the GNU General Public License as published by 8ed0d50c3Schristos the Free Software Foundation; either version 3, or (at your option) 9ed0d50c3Schristos any later version. 10ed0d50c3Schristos 11ed0d50c3Schristos It is distributed in the hope that it will be useful, but WITHOUT 12ed0d50c3Schristos ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13ed0d50c3Schristos or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14ed0d50c3Schristos License for more details. 15ed0d50c3Schristos 16ed0d50c3Schristos You should have received a copy of the GNU General Public License 17ed0d50c3Schristos along with this program; if not, write to the Free Software 18ed0d50c3Schristos Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19ed0d50c3Schristos MA 02110-1301, USA. */ 20ed0d50c3Schristos 21ed0d50c3Schristos #include "sysdep.h" 22ed0d50c3Schristos #include "opcode/mn10200.h" 23ed0d50c3Schristos 24ed0d50c3Schristos 25ed0d50c3Schristos const struct mn10200_operand mn10200_operands[] = { 26ed0d50c3Schristos #define UNUSED 0 27ed0d50c3Schristos {0, 0, 0}, 28ed0d50c3Schristos 29ed0d50c3Schristos /* dn register in the first register operand position. */ 30ed0d50c3Schristos #define DN0 (UNUSED+1) 31ed0d50c3Schristos {2, 0, MN10200_OPERAND_DREG}, 32ed0d50c3Schristos 33ed0d50c3Schristos /* dn register in the second register operand position. */ 34ed0d50c3Schristos #define DN1 (DN0+1) 35ed0d50c3Schristos {2, 2, MN10200_OPERAND_DREG}, 36ed0d50c3Schristos 37ed0d50c3Schristos /* dm register in the first register operand position. */ 38ed0d50c3Schristos #define DM0 (DN1+1) 39ed0d50c3Schristos {2, 0, MN10200_OPERAND_DREG}, 40ed0d50c3Schristos 41ed0d50c3Schristos /* dm register in the second register operand position. */ 42ed0d50c3Schristos #define DM1 (DM0+1) 43ed0d50c3Schristos {2, 2, MN10200_OPERAND_DREG}, 44ed0d50c3Schristos 45ed0d50c3Schristos /* an register in the first register operand position. */ 46ed0d50c3Schristos #define AN0 (DM1+1) 47ed0d50c3Schristos {2, 0, MN10200_OPERAND_AREG}, 48ed0d50c3Schristos 49ed0d50c3Schristos /* an register in the second register operand position. */ 50ed0d50c3Schristos #define AN1 (AN0+1) 51ed0d50c3Schristos {2, 2, MN10200_OPERAND_AREG}, 52ed0d50c3Schristos 53ed0d50c3Schristos /* am register in the first register operand position. */ 54ed0d50c3Schristos #define AM0 (AN1+1) 55ed0d50c3Schristos {2, 0, MN10200_OPERAND_AREG}, 56ed0d50c3Schristos 57ed0d50c3Schristos /* am register in the second register operand position. */ 58ed0d50c3Schristos #define AM1 (AM0+1) 59ed0d50c3Schristos {2, 2, MN10200_OPERAND_AREG}, 60ed0d50c3Schristos 61ed0d50c3Schristos /* 8 bit unsigned immediate which may promote to a 16bit 62ed0d50c3Schristos unsigned immediate. */ 63ed0d50c3Schristos #define IMM8 (AM1+1) 64ed0d50c3Schristos {8, 0, MN10200_OPERAND_PROMOTE}, 65ed0d50c3Schristos 66ed0d50c3Schristos /* 16 bit unsigned immediate which may promote to a 32bit 67ed0d50c3Schristos unsigned immediate. */ 68ed0d50c3Schristos #define IMM16 (IMM8+1) 69ed0d50c3Schristos {16, 0, MN10200_OPERAND_PROMOTE}, 70ed0d50c3Schristos 71ed0d50c3Schristos /* 16 bit pc-relative immediate which may promote to a 16bit 72ed0d50c3Schristos pc-relative immediate. */ 73ed0d50c3Schristos #define IMM16_PCREL (IMM16+1) 74ed0d50c3Schristos {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, 75ed0d50c3Schristos 76ed0d50c3Schristos /* 16bit unsigned dispacement in a memory operation which 77ed0d50c3Schristos may promote to a 32bit displacement. */ 78ed0d50c3Schristos #define IMM16_MEM (IMM16_PCREL+1) 79ed0d50c3Schristos {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, 80ed0d50c3Schristos 81ed0d50c3Schristos /* 24 immediate, low 16 bits in the main instruction 82ed0d50c3Schristos word, 8 in the extension word. */ 83ed0d50c3Schristos 84ed0d50c3Schristos #define IMM24 (IMM16_MEM+1) 85ed0d50c3Schristos {24, 0, MN10200_OPERAND_EXTENDED}, 86ed0d50c3Schristos 87ed0d50c3Schristos /* 32bit pc-relative offset. */ 88ed0d50c3Schristos #define IMM24_PCREL (IMM24+1) 89ed0d50c3Schristos {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, 90ed0d50c3Schristos 91ed0d50c3Schristos /* 32bit memory offset. */ 92ed0d50c3Schristos #define IMM24_MEM (IMM24_PCREL+1) 93ed0d50c3Schristos {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, 94ed0d50c3Schristos 95ed0d50c3Schristos /* Processor status word. */ 96ed0d50c3Schristos #define PSW (IMM24_MEM+1) 97ed0d50c3Schristos {0, 0, MN10200_OPERAND_PSW}, 98ed0d50c3Schristos 99ed0d50c3Schristos /* MDR register. */ 100ed0d50c3Schristos #define MDR (PSW+1) 101ed0d50c3Schristos {0, 0, MN10200_OPERAND_MDR}, 102ed0d50c3Schristos 103ed0d50c3Schristos /* Index register. */ 104ed0d50c3Schristos #define DI (MDR+1) 105ed0d50c3Schristos {2, 4, MN10200_OPERAND_DREG}, 106ed0d50c3Schristos 107ed0d50c3Schristos /* 8 bit signed displacement, may promote to 16bit signed dispacement. */ 108ed0d50c3Schristos #define SD8 (DI+1) 109ed0d50c3Schristos {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 110ed0d50c3Schristos 111ed0d50c3Schristos /* 16 bit signed displacement, may promote to 32bit dispacement. */ 112ed0d50c3Schristos #define SD16 (SD8+1) 113ed0d50c3Schristos {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 114ed0d50c3Schristos 115ed0d50c3Schristos /* 8 bit pc-relative displacement. */ 116ed0d50c3Schristos #define SD8N_PCREL (SD16+1) 117ed0d50c3Schristos {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, 118ed0d50c3Schristos 119ed0d50c3Schristos /* 8 bit signed immediate which may promote to 16bit signed immediate. */ 120ed0d50c3Schristos #define SIMM8 (SD8N_PCREL+1) 121ed0d50c3Schristos {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 122ed0d50c3Schristos 123ed0d50c3Schristos /* 16 bit signed immediate which may promote to 32bit immediate. */ 124ed0d50c3Schristos #define SIMM16 (SIMM8+1) 125ed0d50c3Schristos {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 126ed0d50c3Schristos 127ed0d50c3Schristos /* 16 bit signed immediate which may not promote. */ 128ed0d50c3Schristos #define SIMM16N (SIMM16+1) 129ed0d50c3Schristos {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, 130ed0d50c3Schristos 131ed0d50c3Schristos /* Either an open paren or close paren. */ 132ed0d50c3Schristos #define PAREN (SIMM16N+1) 133ed0d50c3Schristos {0, 0, MN10200_OPERAND_PAREN}, 134ed0d50c3Schristos 135ed0d50c3Schristos /* dn register that appears in the first and second register positions. */ 136ed0d50c3Schristos #define DN01 (PAREN+1) 137ed0d50c3Schristos {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, 138ed0d50c3Schristos 139ed0d50c3Schristos /* an register that appears in the first and second register positions. */ 140ed0d50c3Schristos #define AN01 (DN01+1) 141ed0d50c3Schristos {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, 142ed0d50c3Schristos } ; 143ed0d50c3Schristos 144ed0d50c3Schristos #define MEM(ADDR) PAREN, ADDR, PAREN 145ed0d50c3Schristos #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 146ed0d50c3Schristos 147ed0d50c3Schristos /* The opcode table. 148ed0d50c3Schristos 149ed0d50c3Schristos The format of the opcode table is: 150ed0d50c3Schristos 151ed0d50c3Schristos NAME OPCODE MASK { OPERANDS } 152ed0d50c3Schristos 153ed0d50c3Schristos NAME is the name of the instruction. 154ed0d50c3Schristos OPCODE is the instruction opcode. 155ed0d50c3Schristos MASK is the opcode mask; this is used to tell the disassembler 156ed0d50c3Schristos which bits in the actual opcode must match OPCODE. 157ed0d50c3Schristos OPERANDS is the list of operands. 158ed0d50c3Schristos 159ed0d50c3Schristos The disassembler reads the table in order and prints the first 160ed0d50c3Schristos instruction which matches, so this table is sorted to put more 161ed0d50c3Schristos specific instructions before more general instructions. It is also 162ed0d50c3Schristos sorted by major opcode. */ 163ed0d50c3Schristos 164ed0d50c3Schristos const struct mn10200_opcode mn10200_opcodes[] = { 165ed0d50c3Schristos { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 166ed0d50c3Schristos { "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, 167ed0d50c3Schristos { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, 168ed0d50c3Schristos { "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, 169ed0d50c3Schristos { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, 170ed0d50c3Schristos { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, 171ed0d50c3Schristos { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, 172ed0d50c3Schristos { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, 173ed0d50c3Schristos { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, 174ed0d50c3Schristos { "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, 175ed0d50c3Schristos { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, 176ed0d50c3Schristos { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 177ed0d50c3Schristos { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 178ed0d50c3Schristos { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 179ed0d50c3Schristos { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 180ed0d50c3Schristos { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 181ed0d50c3Schristos { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, 182ed0d50c3Schristos { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, 183ed0d50c3Schristos { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, 184ed0d50c3Schristos { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, 185ed0d50c3Schristos { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, 186ed0d50c3Schristos { "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, 187ed0d50c3Schristos { "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, 188ed0d50c3Schristos { "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 189ed0d50c3Schristos { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, 190ed0d50c3Schristos { "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 191ed0d50c3Schristos { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 192ed0d50c3Schristos { "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 193ed0d50c3Schristos { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 194ed0d50c3Schristos { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 195ed0d50c3Schristos { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, 196ed0d50c3Schristos { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, 197ed0d50c3Schristos { "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, 198ed0d50c3Schristos { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, 199ed0d50c3Schristos { "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, 200ed0d50c3Schristos { "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, 201ed0d50c3Schristos { "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, 202ed0d50c3Schristos { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, 203ed0d50c3Schristos { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 204ed0d50c3Schristos { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 205ed0d50c3Schristos { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 206ed0d50c3Schristos 207ed0d50c3Schristos { "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 208ed0d50c3Schristos { "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 209ed0d50c3Schristos { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 210ed0d50c3Schristos { "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 211ed0d50c3Schristos { "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 212ed0d50c3Schristos { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 213ed0d50c3Schristos 214ed0d50c3Schristos { "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 215ed0d50c3Schristos { "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 216ed0d50c3Schristos { "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 217ed0d50c3Schristos { "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 218ed0d50c3Schristos { "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 219ed0d50c3Schristos { "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 220ed0d50c3Schristos { "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 221ed0d50c3Schristos { "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 222ed0d50c3Schristos { "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 223ed0d50c3Schristos { "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 224ed0d50c3Schristos { "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 225ed0d50c3Schristos { "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 226ed0d50c3Schristos 227ed0d50c3Schristos { "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, 228ed0d50c3Schristos { "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 229ed0d50c3Schristos { "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 230ed0d50c3Schristos { "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 231ed0d50c3Schristos { "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 232ed0d50c3Schristos { "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 233ed0d50c3Schristos { "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 234ed0d50c3Schristos 235ed0d50c3Schristos { "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, 236ed0d50c3Schristos { "extx", 0xb0, 0xfc, FMT_1, {DN0}}, 237ed0d50c3Schristos { "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, 238ed0d50c3Schristos { "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, 239ed0d50c3Schristos { "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, 240ed0d50c3Schristos 241ed0d50c3Schristos { "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, 242ed0d50c3Schristos { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, 243ed0d50c3Schristos { "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, 244ed0d50c3Schristos { "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, 245ed0d50c3Schristos { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 246ed0d50c3Schristos { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 247ed0d50c3Schristos { "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 248ed0d50c3Schristos { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 249ed0d50c3Schristos { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, 250ed0d50c3Schristos { "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 251ed0d50c3Schristos { "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, 252ed0d50c3Schristos { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 253ed0d50c3Schristos 254ed0d50c3Schristos { "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, 255ed0d50c3Schristos { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, 256ed0d50c3Schristos { "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, 257ed0d50c3Schristos { "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, 258ed0d50c3Schristos { "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, 259ed0d50c3Schristos { "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 260ed0d50c3Schristos { "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, 261ed0d50c3Schristos { "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 262ed0d50c3Schristos { "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, 263ed0d50c3Schristos 264ed0d50c3Schristos { "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, 265ed0d50c3Schristos { "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, 266ed0d50c3Schristos 267ed0d50c3Schristos { "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, 268ed0d50c3Schristos 269ed0d50c3Schristos { "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, 270ed0d50c3Schristos { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, 271ed0d50c3Schristos { "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, 272ed0d50c3Schristos { "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, 273ed0d50c3Schristos { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 274ed0d50c3Schristos { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 275ed0d50c3Schristos { "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 276ed0d50c3Schristos { "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 277ed0d50c3Schristos { "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 278ed0d50c3Schristos 279ed0d50c3Schristos { "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, 280ed0d50c3Schristos { "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, 281ed0d50c3Schristos { "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 282ed0d50c3Schristos { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 283ed0d50c3Schristos { "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, 284ed0d50c3Schristos { "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, 285ed0d50c3Schristos { "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 286ed0d50c3Schristos { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 287ed0d50c3Schristos { "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, 288ed0d50c3Schristos { "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 289ed0d50c3Schristos { "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, 290ed0d50c3Schristos 291ed0d50c3Schristos { "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, 292ed0d50c3Schristos { "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, 293ed0d50c3Schristos { "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, 294ed0d50c3Schristos { "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, 295ed0d50c3Schristos 296ed0d50c3Schristos { "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, 297ed0d50c3Schristos { "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 298ed0d50c3Schristos { "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 299ed0d50c3Schristos { "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 300ed0d50c3Schristos 301ed0d50c3Schristos { "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, 302ed0d50c3Schristos { "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, 303ed0d50c3Schristos { "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, 304ed0d50c3Schristos { "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, 305ed0d50c3Schristos { "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, 306ed0d50c3Schristos { "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, 307ed0d50c3Schristos { "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, 308ed0d50c3Schristos { "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, 309ed0d50c3Schristos { "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, 310ed0d50c3Schristos { "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, 311ed0d50c3Schristos { "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, 312ed0d50c3Schristos { "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, 313ed0d50c3Schristos { "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, 314ed0d50c3Schristos { "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, 315ed0d50c3Schristos { "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, 316ed0d50c3Schristos 317ed0d50c3Schristos { "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, 318ed0d50c3Schristos { "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, 319ed0d50c3Schristos { "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, 320ed0d50c3Schristos { "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, 321ed0d50c3Schristos { "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, 322ed0d50c3Schristos { "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, 323ed0d50c3Schristos { "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, 324ed0d50c3Schristos { "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, 325ed0d50c3Schristos { "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, 326ed0d50c3Schristos { "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, 327ed0d50c3Schristos { "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, 328ed0d50c3Schristos { "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, 329ed0d50c3Schristos { "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, 330ed0d50c3Schristos { "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, 331ed0d50c3Schristos 332ed0d50c3Schristos { "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 333ed0d50c3Schristos { "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 334ed0d50c3Schristos { "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 335ed0d50c3Schristos { "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 336ed0d50c3Schristos { "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 337ed0d50c3Schristos { "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 338ed0d50c3Schristos 339ed0d50c3Schristos { "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, 340ed0d50c3Schristos 341ed0d50c3Schristos { "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, 342ed0d50c3Schristos { "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, 343ed0d50c3Schristos 344ed0d50c3Schristos /* Extension. We need some instruction to trigger "emulated syscalls" 345ed0d50c3Schristos for our simulator. */ 346ed0d50c3Schristos { "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, 347ed0d50c3Schristos 348ed0d50c3Schristos /* Extension. When talking to the simulator, gdb requires some instruction 349ed0d50c3Schristos that will trigger a "breakpoint" (really just an instruction that isn't 350ed0d50c3Schristos otherwise used by the tools. This instruction must be the same size 351ed0d50c3Schristos as the smallest instruction on the target machine. In the case of the 352ed0d50c3Schristos mn10x00 the "break" instruction must be one byte. 0xff is available on 353ed0d50c3Schristos both mn10x00 architectures. */ 354ed0d50c3Schristos { "break", 0xff, 0xff, FMT_1, {UNUSED}}, 355ed0d50c3Schristos 356ed0d50c3Schristos { 0, 0, 0, 0, {0}}, 357ed0d50c3Schristos 358ed0d50c3Schristos } ; 359ed0d50c3Schristos 360ed0d50c3Schristos const int mn10200_num_opcodes = 361ed0d50c3Schristos sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); 362ed0d50c3Schristos 363ed0d50c3Schristos 364