1; Renesas M32C CPU description. -*- Scheme -*- 2; 3; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc. 4; 5; Contributed by Red Hat Inc; developed under contract from Renesas. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 3 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22; MA 02110-1301, USA. 23 24(include "simplify.inc") 25 26(define-arch 27 (name m32c) 28 (comment "Renesas M32C") 29 (default-alignment forced) 30 (insn-lsb0? #f) 31 (machs m16c m32c) 32 (isas m16c m32c) 33) 34 35(define-isa 36 (name m16c) 37 38 (default-insn-bitsize 32) 39 40 ; Number of bytes of insn we can initially fetch. 41 (base-insn-bitsize 32) 42 43 ; Used in computing bit numbers. 44 (default-insn-word-bitsize 32) 45 46 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. 47 48 ; fetches 1 insn at a time. 49 (liw-insns 1) 50 51 ; executes 1 insn at a time. 52 (parallel-insns 1) 53 ) 54 55(define-isa 56 (name m32c) 57 58 (default-insn-bitsize 32) 59 60 ; Number of bytes of insn we can initially fetch. 61 (base-insn-bitsize 32) 62 63 ; Used in computing bit numbers. 64 (default-insn-word-bitsize 32) 65 66 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. 67 68 ; fetches 1 insn at a time. 69 (liw-insns 1) 70 71 ; executes 1 insn at a time. 72 (parallel-insns 1) 73 ) 74 75(define-cpu 76 ; cpu names must be distinct from the architecture name and machine names. 77 ; The "b" suffix stands for "base" and is the convention. 78 ; The "f" suffix stands for "family" and is the convention. 79 (name m16cbf) 80 (comment "Renesas M16C base family") 81 (insn-endian big) 82 (data-endian little) 83 (word-bitsize 16) 84) 85 86(define-cpu 87 ; cpu names must be distinct from the architecture name and machine names. 88 ; The "b" suffix stands for "base" and is the convention. 89 ; The "f" suffix stands for "family" and is the convention. 90 (name m32cbf) 91 (comment "Renesas M32C base family") 92 (insn-endian big) 93 (data-endian little) 94 (word-bitsize 16) 95) 96 97(define-mach 98 (name m16c) 99 (comment "Generic M16C cpu") 100 (cpu m32cbf) 101) 102 103(define-mach 104 (name m32c) 105 (comment "Generic M32C cpu") 106 (cpu m32cbf) 107) 108 109; Model descriptions. 110 111(define-model 112 (name m16c) 113 (comment "m16c") (attrs) 114 (mach m16c) 115 116 ; `state' is a list of variables for recording model state 117 ; (state) 118 (unit u-exec "Execution Unit" () 119 1 1 ; issue done 120 () ; state 121 () ; inputs 122 () ; outputs 123 () ; profile action (default) 124 ) 125) 126 127(define-model 128 (name m32c) 129 (comment "m32c") (attrs) 130 (mach m32c) 131 132 ; `state' is a list of variables for recording model state 133 ; (state) 134 (unit u-exec "Execution Unit" () 135 1 1 ; issue done 136 () ; state 137 () ; inputs 138 () ; outputs 139 () ; profile action (default) 140 ) 141) 142 143(define-attr 144 (type enum) 145 (name RL_TYPE) 146 (values NONE JUMP 1ADDR 2ADDR) 147 (default NONE) 148 ) 149 150; Macros to simplify MACH attribute specification. 151 152(define-pmacro all-isas () (ISA m16c,m32c)) 153(define-pmacro m16c-isa () (ISA m16c)) 154(define-pmacro m32c-isa () (ISA m32c)) 155 156(define-pmacro MACH16 (MACH m16c)) 157(define-pmacro MACH32 (MACH m32c)) 158 159(define-pmacro (machine size) 160 (MACH (.sym m size c)) (ISA (.sym m size c))) 161 162(define-pmacro RL_JUMP (RL_TYPE JUMP)) 163(define-pmacro RL_1ADDR (RL_TYPE 1ADDR)) 164(define-pmacro RL_2ADDR (RL_TYPE 2ADDR)) 165 166 167;============================================================= 168; Fields 169;------------------------------------------------------------- 170; Main opcodes 171; 172(dnf f-0-1 "opcode" (all-isas) 0 1) 173(dnf f-0-2 "opcode" (all-isas) 0 2) 174(dnf f-0-3 "opcode" (all-isas) 0 3) 175(dnf f-0-4 "opcode" (all-isas) 0 4) 176(dnf f-1-3 "opcode" (all-isas) 1 3) 177(dnf f-2-2 "opcode" (all-isas) 2 2) 178(dnf f-3-4 "opcode" (all-isas) 3 4) 179(dnf f-3-1 "opcode" (all-isas) 3 1) 180(dnf f-4-1 "opcode" (all-isas) 4 1) 181(dnf f-4-3 "opcode" (all-isas) 4 3) 182(dnf f-4-4 "opcode" (all-isas) 4 4) 183(dnf f-4-6 "opcode" (all-isas) 4 6) 184(dnf f-5-1 "opcode" (all-isas) 5 1) 185(dnf f-5-3 "opcode" (all-isas) 5 3) 186(dnf f-6-2 "opcode" (all-isas) 6 2) 187(dnf f-7-1 "opcode" (all-isas) 7 1) 188(dnf f-8-1 "opcode" (all-isas) 8 1) 189(dnf f-8-2 "opcode" (all-isas) 8 2) 190(dnf f-8-3 "opcode" (all-isas) 8 3) 191(dnf f-8-4 "opcode" (all-isas) 8 4) 192(dnf f-8-8 "opcode" (all-isas) 8 8) 193(dnf f-9-3 "opcode" (all-isas) 9 3) 194(dnf f-9-1 "opcode" (all-isas) 9 1) 195(dnf f-10-1 "opcode" (all-isas) 10 1) 196(dnf f-10-2 "opcode" (all-isas) 10 2) 197(dnf f-10-3 "opcode" (all-isas) 10 3) 198(dnf f-11-1 "opcode" (all-isas) 11 1) 199(dnf f-12-1 "opcode" (all-isas) 12 1) 200(dnf f-12-2 "opcode" (all-isas) 12 2) 201(dnf f-12-3 "opcode" (all-isas) 12 3) 202(dnf f-12-4 "opcode" (all-isas) 12 4) 203(dnf f-12-6 "opcode" (all-isas) 12 6) 204(dnf f-13-3 "opcode" (all-isas) 13 3) 205(dnf f-14-1 "opcode" (all-isas) 14 1) 206(dnf f-14-2 "opcode" (all-isas) 14 2) 207(dnf f-15-1 "opcode" (all-isas) 15 1) 208(dnf f-16-1 "opcode" (all-isas) 16 1) 209(dnf f-16-2 "opcode" (all-isas) 16 2) 210(dnf f-16-4 "opcode" (all-isas) 16 4) 211(dnf f-16-8 "opcode" (all-isas) 16 8) 212(dnf f-18-1 "opcode" (all-isas) 18 1) 213(dnf f-18-2 "opcode" (all-isas) 18 2) 214(dnf f-18-3 "opcode" (all-isas) 18 3) 215(dnf f-20-1 "opcode" (all-isas) 20 1) 216(dnf f-20-3 "opcode" (all-isas) 20 3) 217(dnf f-20-2 "opcode" (all-isas) 20 2) 218(dnf f-20-4 "opcode" (all-isas) 20 4) 219(dnf f-21-3 "opcode" (all-isas) 21 3) 220(dnf f-24-2 "opcode" (all-isas) 24 2) 221(dnf f-24-8 "opcode" (all-isas) 24 8) 222(dnf f-32-16 "opcode" (all-isas) 32 16) 223 224;------------------------------------------------------------- 225; Registers 226;------------------------------------------------------------- 227 228(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2) 229(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1) 230 231(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1) 232(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1) 233 234; QI mode gr encoding for m32c is different than for m16c. The hardware 235; is indexed using the m16c encoding, so perform the transformation here. 236; register m16c m32c 237; ---------------------- 238; r0l 00'b 10'b 239; r0h 01'b 00'b 240; r1l 10'b 11'b 241; r1h 11'b 01'b 242(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT 243 ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert 244 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 245) 246; QI mode gr encoding for m32c is different than for m16c. The hardware 247; is indexed using the m16c encoding, so perform the transformation here. 248; register m16c m32c 249; ---------------------- 250; r0l 00'b 10'b 251; r0h 01'b 00'b 252; r1l 10'b 11'b 253; r1h 11'b 01'b 254(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT 255 ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert 256 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 257) 258; HI mode gr encoding for m32c is different than for m16c. The hardware 259; is indexed using the m16c encoding, so perform the transformation here. 260; register m16c m32c 261; ---------------------- 262; r0 00'b 10'b 263; r1 01'b 11'b 264; r2 10'b 00'b 265; r3 11'b 01'b 266(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT 267 ((value pc) (mod USI (add value 2) 4)) ; insert 268 ((value pc) (mod USI (add value 2) 4)) ; extract 269) 270 271; HI mode gr encoding for m32c is different than for m16c. The hardware 272; is indexed using the m16c encoding, so perform the transformation here. 273; register m16c m32c 274; ---------------------- 275; r0 00'b 10'b 276; r1 01'b 11'b 277; r2 10'b 00'b 278; r3 11'b 01'b 279(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT 280 ((value pc) (mod USI (add value 2) 4)) ; insert 281 ((value pc) (mod USI (add value 2) 4)) ; extract 282) 283 284; SI mode gr encoding for m32c is as follows: 285; register encoding index 286; ------------------------- 287; r2r0 10'b 0 288; r3r1 11'b 1 289(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT 290 ((value pc) (add USI value 2)) ; insert 291 ((value pc) (sub USI value 2)) ; extract 292) 293(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT 294 ((value pc) (add USI value 2)) ; insert 295 ((value pc) (sub USI value 2)) ; extract 296) 297 298(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1) 299 300(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2) 301(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1) 302(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1) 303 304(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1) 305(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1) 306 307(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1) 308(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1) 309 310; QI mode gr encoding for m32c is different than for m16c. The hardware 311; is indexed using the m16c encoding, so perform the transformation here. 312; register m16c m32c 313; ---------------------- 314; r0l 00'b 10'b 315; r0h 01'b 00'b 316; r1l 10'b 11'b 317; r1h 11'b 01'b 318(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT 319 ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert 320 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 321) 322(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT 323 ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert 324 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 325) 326; HI mode gr encoding for m32c is different than for m16c. The hardware 327; is indexed using the m16c encoding, so perform the transformation here. 328; register m16c m32c 329; ---------------------- 330; r0 00'b 10'b 331; r1 01'b 11'b 332; r2 10'b 00'b 333; r3 11'b 01'b 334(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT 335 ((value pc) (mod USI (add value 2) 4)) ; insert 336 ((value pc) (mod USI (add value 2) 4)) ; extract 337) 338(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT 339 ((value pc) (mod USI (add value 2) 4)) ; insert 340 ((value pc) (mod USI (add value 2) 4)) ; extract 341) 342; SI mode gr encoding for m32c is as follows: 343; register encoding index 344; ------------------------- 345; r2r0 10'b 0 346; r3r1 11'b 1 347(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT 348 ((value pc) (add USI value 2)) ; insert 349 ((value pc) (sub USI value 2)) ; extract 350) 351(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT 352 ((value pc) (add USI value 2)) ; insert 353 ((value pc) (sub USI value 2)) ; extract 354) 355 356(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1) 357 358;------------------------------------------------------------- 359; Immediates embedded in the base insn 360;------------------------------------------------------------- 361 362(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f) 363(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f) 364(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f) 365(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f) 366 367(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT 368 ((value pc) (sub USI value 1)) ; insert 369 ((value pc) (add USI value 1)) ; extract 370) 371 372(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT 373 (f-2-2 f-7-1) 374 (sequence () ; insert 375 (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1)) 376 (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3)) 377 ) 378 (sequence () ; extract 379 (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1) 380 (ifield f-7-1)) 381 1)) 382 ) 383) 384 385;------------------------------------------------------------- 386; Immediates and displacements beyond the base insn 387;------------------------------------------------------------- 388 389(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f) 390(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f) 391(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f) 392(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f) 393(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f) 394(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f) 395(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f) 396(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f) 397(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f) 398(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f) 399(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f) 400(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f) 401(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f) 402(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f) 403(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f) 404(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f) 405(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f) 406(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f) 407 408; Insn opcode endianness is big, but the immediate fields are stored 409; in little endian. Handle this here at the field level for all immediate 410; fields longer that 1 byte. 411; 412; CGEN can't handle a field which spans a 32 bit word boundary, so 413; handle those as multi ifields. 414; 415; Take care in expressions using 'srl' or 'sll' as part of some larger 416; expression meant to yield sign-extended values. CGEN translates 417; uses of those operators into C expressions whose type is 'unsigned 418; int', which tends to make the whole expression 'unsigned int'. 419; Expressions like (set (ifield foo) X), however, just take X and 420; store it in some member of 'struct cgen_fields', all of whose 421; members are 'long'. On machines where 'long' is larger than 422; 'unsigned int', assigning a "sign-extended" unsigned int to a long 423; just produces a very large positive value. insert_normal will 424; range-check the field's value and produce odd error messages like 425; this: 426; 427; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]' 428; 429; Annoyingly, the code will work fine on machines where 'long' and 430; 'unsigned int' are the same size: the assignment will produce a 431; negative number. 432; 433; Just tell yourself over and over: overflow detection is expensive, 434; and you're glad C doesn't do it, because it never happens in real 435; life. 436 437(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT 438 ((value pc) (or UHI 439 (and (srl value 8) #xff) 440 (sll (and value #xff) 8))) ; insert 441 ((value pc) (or UHI 442 (and UHI (srl UHI value 8) #xff) 443 (sll UHI (and UHI value #xff) 8))) ; extract 444) 445 446(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT 447 ((value pc) (ext INT 448 (trunc HI 449 (or (and (srl value 8) #xff) 450 (sll (and value #xff) 8))))) ; insert 451 ((value pc) (ext INT 452 (trunc HI 453 (or (and (srl value 8) #xff) 454 (sll (and value #xff) 8))))) ; extract 455) 456 457(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT 458 ((value pc) (or UHI 459 (and (srl value 8) #xff) 460 (sll (and value #xff) 8))) ; insert 461 ((value pc) (or UHI 462 (and UHI (srl UHI value 8) #xff) 463 (sll UHI (and UHI value #xff) 8))) ; extract 464) 465 466(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT 467 ((value pc) (ext INT 468 (trunc HI 469 (or (and (srl value 8) #xff) 470 (sll (and value #xff) 8))))) ; insert 471 ((value pc) (ext INT 472 (trunc HI 473 (or (and (srl value 8) #xff) 474 (sll (and value #xff) 8))))) ; extract 475) 476 477(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT 478 (f-dsp-24-u8 f-dsp-32-u8) 479 (sequence () ; insert 480 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff)) 481 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff)) 482 ) 483 (sequence () ; extract 484 (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8) 485 (ifield f-dsp-24-u8))) 486 ) 487) 488 489(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT 490 (f-dsp-24-u8 f-dsp-32-u8) 491 (sequence () ; insert 492 (set (ifield f-dsp-24-u8) 493 (and (ifield f-dsp-24-s16) #xff)) 494 (set (ifield f-dsp-32-u8) 495 (and (srl (ifield f-dsp-24-s16) 8) #xff)) 496 ) 497 (sequence () ; extract 498 (set (ifield f-dsp-24-s16) 499 (ext INT 500 (trunc HI (or (sll (ifield f-dsp-32-u8) 8) 501 (ifield f-dsp-24-u8))))) 502 ) 503) 504 505(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT 506 ((value pc) (or UHI 507 (and (srl value 8) #xff) 508 (sll (and value #xff) 8))) ; insert 509 ((value pc) (or UHI 510 (and UHI (srl UHI value 8) #xff) 511 (sll UHI (and UHI value #xff) 8))) ; extract 512) 513 514(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT 515 ((value pc) (ext INT 516 (trunc HI 517 (or (and (srl value 8) #xff) 518 (sll (and value #xff) 8))))) ; insert 519 ((value pc) (ext INT 520 (trunc HI 521 (or (and (srl value 8) #xff) 522 (sll (and value #xff) 8))))) ; extract 523) 524 525(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT 526 ((value pc) (or UHI 527 (and (srl value 8) #xff) 528 (sll (and value #xff) 8))) ; insert 529 ((value pc) (or UHI 530 (and UHI (srl UHI value 8) #xff) 531 (sll UHI (and UHI value #xff) 8))) ; extract 532) 533 534(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT 535 ((value pc) (ext INT 536 (trunc HI 537 (or (and (srl value 8) #xff) 538 (sll (and value #xff) 8))))) ; insert 539 ((value pc) (ext INT 540 (trunc HI 541 (or (and (srl value 8) #xff) 542 (sll (and value #xff) 8))))) ; extract 543) 544 545(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT 546 ((value pc) (or UHI 547 (and (srl value 8) #xff) 548 (sll (and value #xff) 8))) ; insert 549 ((value pc) (or UHI 550 (and UHI (srl UHI value 8) #xff) 551 (sll UHI (and UHI value #xff) 8))) ; extract 552) 553 554(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT 555 ((value pc) (ext INT 556 (trunc HI 557 (or (and (srl value 8) #xff) 558 (sll (and value #xff) 8))))) ; insert 559 ((value pc) (ext INT 560 (trunc HI 561 (or (and (srl value 8) #xff) 562 (sll (and value #xff) 8))))) ; extract 563) 564 565(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT 566 ((value pc) (or UHI 567 (and (srl value 8) #xff) 568 (sll (and value #xff) 8))) ; insert 569 ((value pc) (or UHI 570 (and UHI (srl UHI value 8) #xff) 571 (sll UHI (and UHI value #xff) 8))) ; extract 572) 573(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT 574 ((value pc) (sub SI (xor (or SI (or (and (srl value 16) #xff) 575 (and value #xff00)) 576 (sll (and value #xff) 16)) 577 #x800000) #x800000)) 578 ((value pc) (sub SI (xor (or SI 579 (or (and (srl value 16) #xff) 580 (and value #xff00)) 581 (sll (and value #xff) 16)) 582 #x800000) #x800000)) 583 ) 584 585(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT 586 ((value pc) (or SI 587 (or (srl value 16) (and value #xff00)) 588 (sll (and value #xff) 16))) 589 ((value pc) (or SI 590 (or (srl value 16) (and value #xff00)) 591 (sll (and value #xff) 16))) 592 ) 593 594(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT 595 (f-dsp-16-u16 f-dsp-32-u8) 596 (sequence () ; insert 597 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff)) 598 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff)) 599 ) 600 (sequence () ; extract 601 (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16) 602 (ifield f-dsp-16-u16))) 603 ) 604) 605 606(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT 607 (f-dsp-24-u8 f-dsp-32-u16) 608 (sequence () ; insert 609 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff)) 610 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff)) 611 ) 612 (sequence () ; extract 613 (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8) 614 (ifield f-dsp-24-u8))) 615 ) 616) 617 618(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT 619 ((value pc) (or USI 620 (or USI 621 (and (srl value 16) #x0000ff) 622 (and value #x00ff00)) 623 (and (sll value 16) #xff0000))) ; insert 624 ((value pc) (or USI 625 (or USI 626 (and USI (srl value 16) #x0000ff) 627 (and USI value #x00ff00)) 628 (and USI (sll value 16) #xff0000))) ; extract 629) 630 631(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT 632 ((value pc) (or USI 633 (or USI 634 (and (srl value 16) #x0000ff) 635 (and value #x00ff00)) 636 (and (sll value 16) #x0f0000))) ; insert 637 ((value pc) (or USI 638 (or USI 639 (and USI (srl value 16) #x0000ff) 640 (and USI value #x00ff00)) 641 (and USI (sll value 16) #x0f0000))) ; extract 642) 643 644(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT 645 ((value pc) (or USI 646 (or USI 647 (and (srl value 16) #x0000ff) 648 (and value #x00ff00)) 649 (and (sll value 16) #xff0000))) ; insert 650 ((value pc) (or USI 651 (or USI 652 (and USI (srl value 16) #x0000ff) 653 (and USI value #x00ff00)) 654 (and USI (sll value 16) #xff0000))) ; extract 655) 656 657(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT 658 (f-dsp-40-u24 f-dsp-64-u8) 659 (sequence () ; insert 660 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff)) 661 (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff)) 662 ) 663 (sequence () ; extract 664 (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff) 665 (and (sll (ifield f-dsp-64-u8) 24) #xff000000))) 666 ) 667) 668 669(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT 670 (f-dsp-48-u16 f-dsp-64-u8) 671 (sequence () ; insert 672 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) 673 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) 674 ) 675 (sequence () ; extract 676 (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) 677 (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) 678 ) 679) 680(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT 681 (f-dsp-48-u16 f-dsp-64-u8) 682 (sequence () ; insert 683 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff)) 684 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff)) 685 ) 686 (sequence () ; extract 687 (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff) 688 (and (sll (ifield f-dsp-64-u8) 16) #xff0000))) 689 ) 690) 691 692(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT 693 (f-dsp-16-u16 f-dsp-32-u16) 694 (sequence () ; insert 695 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff)) 696 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff)) 697 ) 698 (sequence () ; extract 699 (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff) 700 (and (sll (ifield f-dsp-32-u16) 16) #xffff0000))) 701 ) 702) 703 704(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT 705 (f-dsp-24-u8 f-dsp-32-u24) 706 (sequence () ; insert 707 (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff)) 708 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff)) 709 ) 710 (sequence () ; extract 711 (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff) 712 (and (sll (ifield f-dsp-32-u24) 8) #xffffff00))) 713 ) 714) 715 716(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT 717 ((value pc) 718 719 ;; insert 720 (ext INT 721 (or SI 722 (or SI 723 (and (srl value 24) #x00ff) 724 (and (srl value 8) #xff00)) 725 (or SI 726 (sll (and value #xff00) 8) 727 (sll (and value #x00ff) 24))))) 728 729 ;; extract 730 ((value pc) 731 (ext INT 732 (or SI 733 (or SI 734 (and (srl value 24) #x00ff) 735 (and (srl value 8) #xff00)) 736 (or SI 737 (sll (and value #xff00) 8) 738 (sll (and value #x00ff) 24))))) 739) 740 741(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT 742 (f-dsp-48-u16 f-dsp-64-u16) 743 (sequence () ; insert 744 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff)) 745 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff)) 746 ) 747 (sequence () ; extract 748 (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) 749 (sll (and (ifield f-dsp-64-u16) #xffff) 16))) 750 ) 751) 752 753(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT 754 (f-dsp-48-u16 f-dsp-64-u16) 755 (sequence () ; insert 756 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff)) 757 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff)) 758 ) 759 (sequence () ; extract 760 (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) 761 (sll (and (ifield f-dsp-64-u16) #xffff) 16))) 762 ) 763) 764 765(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT 766 (f-dsp-56-u8 f-dsp-64-u8) 767 (sequence () ; insert 768 (set (ifield f-dsp-56-u8) 769 (and (ifield f-dsp-56-s16) #xff)) 770 (set (ifield f-dsp-64-u8) 771 (and (srl (ifield f-dsp-56-s16) 8) #xff)) 772 ) 773 (sequence () ; extract 774 (set (ifield f-dsp-56-s16) 775 (ext INT 776 (trunc HI (or (sll (ifield f-dsp-64-u8) 8) 777 (ifield f-dsp-56-u8))))) 778 ) 779) 780 781(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT 782 ((value pc) (ext INT 783 (trunc HI 784 (or (and (srl value 8) #xff) 785 (sll (and value #xff) 8))))) ; insert 786 ((value pc) (ext INT 787 (trunc HI 788 (or (and (srl value 8) #xff) 789 (sll (and value #xff) 8))))) ; extract 790) 791 792;------------------------------------------------------------- 793; Bit indices 794;------------------------------------------------------------- 795 796(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3) 797(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3) 798(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3) 799 800(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT 801 (f-bitno16-S f-dsp-8-u8) 802 (sequence () ; insert 803 (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7)) 804 (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff)) 805 ) 806 (sequence () ; extract 807 (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3) 808 (ifield f-bitno16-S))) 809 ) 810) 811 812(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT 813 (f-bitno32-unprefixed f-dsp-16-u8) 814 (sequence () ; insert 815 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7)) 816 (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff)) 817 ) 818 (sequence () ; extract 819 (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3) 820 (ifield f-bitno32-unprefixed))) 821 ) 822) 823(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT 824 (f-bitno32-unprefixed f-dsp-16-s8) 825 (sequence () ; insert 826 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7)) 827 (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) 828 ) 829 (sequence () ; extract 830 (set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8) 831 (ifield f-bitno32-unprefixed))) 832 ) 833) 834(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT 835 (f-bitno32-unprefixed f-dsp-16-u16) 836 (sequence () ; insert 837 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7)) 838 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff)) 839 ) 840 (sequence () ; extract 841 (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) 842 (ifield f-bitno32-unprefixed))) 843 ) 844) 845(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT 846 (f-bitno32-unprefixed f-dsp-16-s16) 847 (sequence () ; insert 848 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7)) 849 (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) 850 ) 851 (sequence () ; extract 852 (set (ifield f-bitbase32-16-s19-unprefixed) (or (mul (ifield f-dsp-16-s16) 8) 853 (ifield f-bitno32-unprefixed))) 854 ) 855) 856; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 857(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT 858 (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8) 859 (sequence () ; insert 860 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7)) 861 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff)) 862 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff)) 863 ) 864 (sequence () ; extract 865 (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) 866 (or (sll (ifield f-dsp-32-u8) 19) 867 (ifield f-bitno32-unprefixed)))) 868 ) 869) 870(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT 871 (f-bitno32-prefixed f-dsp-24-u8) 872 (sequence () ; insert 873 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7)) 874 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff)) 875 ) 876 (sequence () ; extract 877 (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 878 (ifield f-bitno32-prefixed))) 879 ) 880) 881(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT 882 (f-bitno32-prefixed f-dsp-24-s8) 883 (sequence () ; insert 884 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7)) 885 (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) 886 ) 887 (sequence () ; extract 888 (set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8) 889 (ifield f-bitno32-prefixed))) 890 ) 891) 892; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 893(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT 894 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8) 895 (sequence () ; insert 896 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7)) 897 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff)) 898 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff)) 899 ) 900 (sequence () ; extract 901 (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 902 (or (sll (ifield f-dsp-32-u8) 11) 903 (ifield f-bitno32-prefixed)))) 904 ) 905) 906; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 907(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT 908 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8) 909 (sequence () ; insert 910 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7)) 911 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff)) 912 (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11)) 913 ) 914 (sequence () ; extract 915 (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 916 (or (mul (ifield f-dsp-32-s8) 2048) 917 (ifield f-bitno32-prefixed)))) 918 ) 919) 920; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 921(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT 922 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16) 923 (sequence () ; insert 924 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7)) 925 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff)) 926 (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff)) 927 ) 928 (sequence () ; extract 929 (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 930 (or (sll (ifield f-dsp-32-u16) 11) 931 (ifield f-bitno32-prefixed)))) 932 ) 933) 934 935;------------------------------------------------------------- 936; Labels 937;------------------------------------------------------------- 938 939(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT 940 ((value pc) (sub SI value (add SI pc 2))) ; insert 941 ((value pc) (add SI value (add SI pc 2))) ; extract 942) 943(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT 944 (f-2-2 f-7-1) 945 (sequence ((SI val)) ; insert 946 (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2)) 947 (set (ifield f-7-1) (and val #x1)) 948 (set (ifield f-2-2) (srl val 1)) 949 ) 950 (sequence () ; extract 951 (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1) 952 (ifield f-7-1)) 953 2))) 954 ) 955) 956(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT 957 ((value pc) (sub SI value (add SI pc 1))) ; insert 958 ((value pc) (add SI value (add SI pc 1))) ; extract 959) 960(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT 961 ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) 962 (srl (and (sub value (add pc 1)) #xff00) 8))) 963 ((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8) 964 (sll (and value #xff) 8)) 965 #x8000) 966 #x8000) 967 (add pc 1))) 968 ) 969(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT 970 ((value pc) (or SI 971 (or (srl value 16) (and value #xff00)) 972 (sll (and value #xff) 16))) 973 ((value pc) (or SI 974 (or (srl value 16) (and value #xff00)) 975 (sll (and value #xff) 16))) 976 ) 977(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT 978 ((value pc) (sub SI value (add SI pc 2))) ; insert 979 ((value pc) (add SI value (add SI pc 2))) ; extract 980) 981(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT 982 ((value pc) (sub SI value (add SI pc 2))) ; insert 983 ((value pc) (add SI value (add SI pc 2))) ; extract 984) 985(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT 986 ((value pc) (sub SI value (add SI pc 2))) ; insert 987 ((value pc) (add SI value (add SI pc 2))) ; extract 988) 989(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT 990 ((value pc) (sub SI value (add SI pc 2))) ; insert 991 ((value pc) (add SI value (add SI pc 2))) ; extract 992) 993 994;------------------------------------------------------------- 995; Condition codes 996;------------------------------------------------------------- 997 998(dnf f-cond16 "condition code" (all-isas) 12 4) 999(dnf f-cond16j-5 "condition code" (all-isas) 5 3) 1000 1001(dnmf f-cond32 "condition code" (all-isas) UINT 1002 (f-9-1 f-13-3) 1003 (sequence () ; insert 1004 (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1)) 1005 (set (ifield f-13-3) (and (ifield f-cond32) #x7)) 1006 ) 1007 (sequence () ; extract 1008 (set (ifield f-cond32) (or (sll (ifield f-9-1) 3) 1009 (ifield f-13-3))) 1010 ) 1011) 1012 1013(dnmf f-cond32j "condition code" (all-isas) UINT 1014 (f-1-3 f-7-1) 1015 (sequence () ; insert 1016 (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7)) 1017 (set (ifield f-7-1) (and (ifield f-cond32j) #x1)) 1018 ) 1019 (sequence () ; extract 1020 (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1) 1021 (ifield f-7-1))) 1022 ) 1023) 1024 1025;============================================================= 1026; Hardware 1027; 1028(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ()) 1029 1030;------------------------------------------------------------- 1031; General registers 1032; The actual registers are 16 bits 1033;------------------------------------------------------------- 1034 1035(define-hardware 1036 (name h-gr) 1037 (comment "general 16 bit registers") 1038 (attrs all-isas CACHE-ADDR) 1039 (type register HI (4)) 1040 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))) 1041 1042; Define different views of the grs as VIRTUAL with getter/setter specs 1043; 1044(define-hardware 1045 (name h-gr-QI) 1046 (comment "general 8 bit registers") 1047 (attrs all-isas VIRTUAL) 1048 (type register QI (4)) 1049 (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3))) 1050 (get (index) (and (if SI (mod index 2) 1051 (srl (reg h-gr (div index 2)) 8) 1052 (reg h-gr (div index 2))) 1053 #xff)) 1054 (set (index newval) (set (reg h-gr (div index 2)) 1055 (if SI (mod index 2) 1056 (or (and (reg h-gr (div index 2)) #xff) 1057 (sll (and newval #xff) 8)) 1058 (or (and (reg h-gr (div index 2)) #xff00) 1059 (and newval #xff)))))) 1060 1061(define-hardware 1062 (name h-gr-HI) 1063 (comment "general 16 bit registers") 1064 (attrs all-isas VIRTUAL) 1065 (type register HI (4)) 1066 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))) 1067 (get (index) (reg h-gr index)) 1068 (set (index newval) (set (reg h-gr index) newval))) 1069 1070(define-hardware 1071 (name h-gr-SI) 1072 (comment "general 32 bit registers") 1073 (attrs all-isas VIRTUAL) 1074 (type register SI (2)) 1075 (indices keyword "" (("r2r0" 0) ("r3r1" 1))) 1076 (get (index) (or SI 1077 (and (reg h-gr index) #xffff) 1078 (sll (and (reg h-gr (add index 2)) #xffff) 16))) 1079 (set (index newval) (sequence () 1080 (set (reg h-gr index) (and newval #xffff)) 1081 (set (reg h-gr (add index 2)) (srl newval 16))))) 1082 1083(define-hardware 1084 (name h-gr-ext-QI) 1085 (comment "general 16 bit registers") 1086 (attrs all-isas VIRTUAL) 1087 (type register HI (2)) 1088 (indices keyword "" (("r0l" 0) ("r1l" 1))) 1089 (get (index) (reg h-gr-QI (mul index 2))) 1090 (set (index newval) (set (reg h-gr (mul index 2)) newval))) 1091 1092(define-hardware 1093 (name h-gr-ext-HI) 1094 (comment "general 16 bit registers") 1095 (attrs all-isas VIRTUAL) 1096 (type register SI (2)) 1097 (indices keyword "" (("r0" 0) ("r1" 1))) 1098 (get (index) (reg h-gr (mul index 2))) 1099 (set (index newval) (set (reg h-gr-SI index) newval))) 1100 1101(define-hardware 1102 (name h-r0l) 1103 (comment "r0l register") 1104 (attrs all-isas VIRTUAL) 1105 (type register QI) 1106 (indices keyword "" (("r0l" 0))) 1107 (get () (reg h-gr-QI 0)) 1108 (set (newval) (set (reg h-gr-QI 0) newval))) 1109 1110(define-hardware 1111 (name h-r0h) 1112 (comment "r0h register") 1113 (attrs all-isas VIRTUAL) 1114 (type register QI) 1115 (indices keyword "" (("r0h" 0))) 1116 (get () (reg h-gr-QI 1)) 1117 (set (newval) (set (reg h-gr-QI 1) newval))) 1118 1119(define-hardware 1120 (name h-r1l) 1121 (comment "r1l register") 1122 (attrs all-isas VIRTUAL) 1123 (type register QI) 1124 (indices keyword "" (("r1l" 0))) 1125 (get () (reg h-gr-QI 2)) 1126 (set (newval) (set (reg h-gr-QI 2) newval))) 1127 1128(define-hardware 1129 (name h-r1h) 1130 (comment "r1h register") 1131 (attrs all-isas VIRTUAL) 1132 (type register QI) 1133 (indices keyword "" (("r1h" 0))) 1134 (get () (reg h-gr-QI 3)) 1135 (set (newval) (set (reg h-gr-QI 3) newval))) 1136 1137(define-hardware 1138 (name h-r0) 1139 (comment "r0 register") 1140 (attrs all-isas VIRTUAL) 1141 (type register HI) 1142 (indices keyword "" (("r0" 0))) 1143 (get () (reg h-gr 0)) 1144 (set (newval) (set (reg h-gr 0) newval))) 1145 1146(define-hardware 1147 (name h-r1) 1148 (comment "r1 register") 1149 (attrs all-isas VIRTUAL) 1150 (type register HI) 1151 (indices keyword "" (("r1" 0))) 1152 (get () (reg h-gr 1)) 1153 (set (newval) (set (reg h-gr 1) newval))) 1154 1155(define-hardware 1156 (name h-r2) 1157 (comment "r2 register") 1158 (attrs all-isas VIRTUAL) 1159 (type register HI) 1160 (indices keyword "" (("r2" 0))) 1161 (get () (reg h-gr 2)) 1162 (set (newval) (set (reg h-gr 2) newval))) 1163 1164(define-hardware 1165 (name h-r3) 1166 (comment "r3 register") 1167 (attrs all-isas VIRTUAL) 1168 (type register HI) 1169 (indices keyword "" (("r3" 0))) 1170 (get () (reg h-gr 3)) 1171 (set (newval) (set (reg h-gr 3) newval))) 1172 1173(define-hardware 1174 (name h-r0l-r0h) 1175 (comment "r0l or r0h") 1176 (attrs all-isas VIRTUAL) 1177 (type register QI (2)) 1178 (indices keyword "" (("r0l" 0) ("r0h" 1))) 1179 (get (index) (reg h-gr-QI index)) 1180 (set (index newval) (set (reg h-gr-QI index) newval))) 1181 1182(define-hardware 1183 (name h-r2r0) 1184 (comment "r2r0 register") 1185 (attrs all-isas VIRTUAL) 1186 (type register SI) 1187 (indices keyword "" (("r2r0" 0))) 1188 (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0))) 1189 (set (newval) 1190 (sequence () 1191 (set (reg h-gr 0) newval) 1192 (set (reg h-gr 2) (sra newval 16))))) 1193 1194(define-hardware 1195 (name h-r3r1) 1196 (comment "r3r1 register") 1197 (attrs all-isas VIRTUAL) 1198 (type register SI) 1199 (indices keyword "" (("r3r1" 0))) 1200 (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1))) 1201 (set (newval) 1202 (sequence () 1203 (set (reg h-gr 1) newval) 1204 (set (reg h-gr 3) (sra newval 16))))) 1205 1206(define-hardware 1207 (name h-r1r2r0) 1208 (comment "r1r2r0 register") 1209 (attrs all-isas VIRTUAL) 1210 (type register DI) 1211 (indices keyword "" (("r1r2r0" 0))) 1212 (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0)))) 1213 (set (newval) 1214 (sequence () 1215 (set (reg h-gr 0) newval) 1216 (set (reg h-gr 2) (sra newval 16)) 1217 (set (reg h-gr 1) (sra newval 32))))) 1218 1219;------------------------------------------------------------- 1220; Address registers 1221;------------------------------------------------------------- 1222 1223(define-hardware 1224 (name h-ar) 1225 (comment "address registers") 1226 (attrs all-isas) 1227 (type register USI (2)) 1228 (indices keyword "" (("a0" 0) ("a1" 1))) 1229 (get (index) (c-call USI "h_ar_get_handler" index)) 1230 (set (index newval) (c-call VOID "h_ar_set_handler" index newval))) 1231 1232; Define different views of the ars as VIRTUAL with getter/setter specs 1233(define-hardware 1234 (name h-ar-QI) 1235 (comment "8 bit view of address register") 1236 (attrs all-isas VIRTUAL) 1237 (type register QI (2)) 1238 (indices keyword "" (("a0" 0) ("a1" 1))) 1239 (get (index) (reg h-ar index)) 1240 (set (index newval) (set (reg h-ar index) newval))) 1241 1242(define-hardware 1243 (name h-ar-HI) 1244 (comment "16 bit view of address register") 1245 (attrs all-isas VIRTUAL) 1246 (type register HI (2)) 1247 (indices keyword "" (("a0" 0) ("a1" 1))) 1248 (get (index) (reg h-ar index)) 1249 (set (index newval) (set (reg h-ar index) newval))) 1250 1251(define-hardware 1252 (name h-ar-SI) 1253 (comment "32 bit view of address register") 1254 (attrs all-isas VIRTUAL) 1255 (type register SI) 1256 (indices keyword "" (("a1a0" 0))) 1257 (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0)))) 1258 (set (newval) (sequence () 1259 (set (reg h-ar 0) (and newval #xffff)) 1260 (set (reg h-ar 1) (and (srl newval 16) #xffff))))) 1261 1262(define-hardware 1263 (name h-a0) 1264 (comment "16 bit view of address register") 1265 (attrs all-isas VIRTUAL) 1266 (type register HI) 1267 (indices keyword "" (("a0" 0))) 1268 (get () (reg h-ar 0)) 1269 (set (newval) (set (reg h-ar 0) newval))) 1270 1271(define-hardware 1272 (name h-a1) 1273 (comment "16 bit view of address register") 1274 (attrs all-isas VIRTUAL) 1275 (type register HI) 1276 (indices keyword "" (("a1" 1))) 1277 (get () (reg h-ar 1)) 1278 (set (newval) (set (reg h-ar 1) newval))) 1279 1280; SB Register 1281(define-hardware 1282 (name h-sb) 1283 (comment "SB register") 1284 (attrs all-isas) 1285 (type register USI) 1286 (get () (c-call USI "h_sb_get_handler")) 1287 (set (newval) (c-call VOID "h_sb_set_handler" newval)) 1288) 1289 1290; FB Register 1291(define-hardware 1292 (name h-fb) 1293 (comment "FB register") 1294 (attrs all-isas) 1295 (type register USI) 1296 (get () (c-call USI "h_fb_get_handler")) 1297 (set (newval) (c-call VOID "h_fb_set_handler" newval)) 1298) 1299 1300; SP Register 1301(define-hardware 1302 (name h-sp) 1303 (comment "SP register") 1304 (attrs all-isas) 1305 (type register USI) 1306 (get () (c-call USI "h_sp_get_handler")) 1307 (set (newval) (c-call VOID "h_sp_set_handler" newval)) 1308) 1309 1310;------------------------------------------------------------- 1311; condition-code bits 1312;------------------------------------------------------------- 1313 1314(define-hardware 1315 (name h-sbit) 1316 (comment "sign bit") 1317 (attrs all-isas) 1318 (type register BI) 1319) 1320 1321(define-hardware 1322 (name h-zbit) 1323 (comment "zero bit") 1324 (attrs all-isas) 1325 (type register BI) 1326) 1327 1328(define-hardware 1329 (name h-obit) 1330 (comment "overflow bit") 1331 (attrs all-isas) 1332 (type register BI) 1333) 1334 1335(define-hardware 1336 (name h-cbit) 1337 (comment "carry bit") 1338 (attrs all-isas) 1339 (type register BI) 1340) 1341 1342(define-hardware 1343 (name h-ubit) 1344 (comment "stack pointer select bit") 1345 (attrs all-isas) 1346 (type register BI) 1347) 1348 1349(define-hardware 1350 (name h-ibit) 1351 (comment "interrupt enable bit") 1352 (attrs all-isas) 1353 (type register BI) 1354) 1355 1356(define-hardware 1357 (name h-bbit) 1358 (comment "register bank select bit") 1359 (attrs all-isas) 1360 (type register BI) 1361) 1362 1363(define-hardware 1364 (name h-dbit) 1365 (comment "debug bit") 1366 (attrs all-isas) 1367 (type register BI) 1368) 1369 1370(define-hardware 1371 (name h-dct0) 1372 (comment "dma transfer count 000") 1373 (attrs all-isas) 1374 (type register UHI) 1375) 1376(define-hardware 1377 (name h-dct1) 1378 (comment "dma transfer count 001") 1379 (attrs all-isas) 1380 (type register UHI) 1381) 1382(define-hardware 1383 (name h-svf) 1384 (comment "save flag 011") 1385 (attrs all-isas) 1386 (type register UHI) 1387) 1388(define-hardware 1389 (name h-drc0) 1390 (comment "dma transfer count reload 100") 1391 (attrs all-isas) 1392 (type register UHI) 1393) 1394(define-hardware 1395 (name h-drc1) 1396 (comment "dma transfer count reload 101") 1397 (attrs all-isas) 1398 (type register UHI) 1399) 1400(define-hardware 1401 (name h-dmd0) 1402 (comment "dma mode 110") 1403 (attrs all-isas) 1404 (type register UQI) 1405) 1406(define-hardware 1407 (name h-dmd1) 1408 (comment "dma mode 111") 1409 (attrs all-isas) 1410 (type register UQI) 1411) 1412(define-hardware 1413 (name h-intb) 1414 (comment "interrupt table 000") 1415 (attrs all-isas) 1416 (type register USI) 1417) 1418(define-hardware 1419 (name h-svp) 1420 (comment "save pc 100") 1421 (attrs all-isas) 1422 (type register UHI) 1423) 1424(define-hardware 1425 (name h-vct) 1426 (comment "vector 101") 1427 (attrs all-isas) 1428 (type register USI) 1429) 1430(define-hardware 1431 (name h-isp) 1432 (comment "interrupt stack ptr 111") 1433 (attrs all-isas) 1434 (type register USI) 1435) 1436(define-hardware 1437 (name h-dma0) 1438 (comment "dma mem addr 010") 1439 (attrs all-isas) 1440 (type register USI) 1441) 1442(define-hardware 1443 (name h-dma1) 1444 (comment "dma mem addr 011") 1445 (attrs all-isas) 1446 (type register USI) 1447) 1448(define-hardware 1449 (name h-dra0) 1450 (comment "dma mem addr reload 100") 1451 (attrs all-isas) 1452 (type register USI) 1453) 1454(define-hardware 1455 (name h-dra1) 1456 (comment "dma mem addr reload 101") 1457 (attrs all-isas) 1458 (type register USI) 1459) 1460(define-hardware 1461 (name h-dsa0) 1462 (comment "dma sfr addr 110") 1463 (attrs all-isas) 1464 (type register USI) 1465) 1466(define-hardware 1467 (name h-dsa1) 1468 (comment "dma sfr addr 111") 1469 (attrs all-isas) 1470 (type register USI) 1471) 1472 1473;------------------------------------------------------------- 1474; Condition code operand hardware 1475;------------------------------------------------------------- 1476 1477(define-hardware 1478 (name h-cond16) 1479 (comment "condition code hardware for m16c") 1480 (attrs m16c-isa MACH16) 1481 (type immediate UQI) 1482 (values keyword "" 1483 (("geu" #x00) ("c" #x00) 1484 ("gtu" #x01) 1485 ("eq" #x02) ("z" #x02) 1486 ("n" #x03) 1487 ("le" #x04) 1488 ("o" #x05) 1489 ("ge" #x06) 1490 ("ltu" #xf8) ("nc" #xf8) 1491 ("leu" #xf9) 1492 ("ne" #xfa) ("nz" #xfa) 1493 ("pz" #xfb) 1494 ("gt" #xfc) 1495 ("no" #xfd) 1496 ("lt" #xfe) 1497 ) 1498 ) 1499) 1500(define-hardware 1501 (name h-cond16c) 1502 (comment "condition code hardware for m16c") 1503 (attrs m16c-isa MACH16) 1504 (type immediate UQI) 1505 (values keyword "" 1506 (("geu" #x00) ("c" #x00) 1507 ("gtu" #x01) 1508 ("eq" #x02) ("z" #x02) 1509 ("n" #x03) 1510 ("ltu" #x04) ("nc" #x04) 1511 ("leu" #x05) 1512 ("ne" #x06) ("nz" #x06) 1513 ("pz" #x07) 1514 ("le" #x08) 1515 ("o" #x09) 1516 ("ge" #x0a) 1517 ("gt" #x0c) 1518 ("no" #x0d) 1519 ("lt" #x0e) 1520 ) 1521 ) 1522) 1523(define-hardware 1524 (name h-cond16j) 1525 (comment "condition code hardware for m16c") 1526 (attrs m16c-isa MACH16) 1527 (type immediate UQI) 1528 (values keyword "" 1529 (("le" #x08) 1530 ("o" #x09) 1531 ("ge" #x0a) 1532 ("gt" #x0c) 1533 ("no" #x0d) 1534 ("lt" #x0e) 1535 ) 1536 ) 1537) 1538(define-hardware 1539 (name h-cond16j-5) 1540 (comment "condition code hardware for m16c") 1541 (attrs m16c-isa MACH16) 1542 (type immediate UQI) 1543 (values keyword "" 1544 (("geu" #x00) ("c" #x00) 1545 ("gtu" #x01) 1546 ("eq" #x02) ("z" #x02) 1547 ("n" #x03) 1548 ("ltu" #x04) ("nc" #x04) 1549 ("leu" #x05) 1550 ("ne" #x06) ("nz" #x06) 1551 ("pz" #x07) 1552 ) 1553 ) 1554) 1555 1556(define-hardware 1557 (name h-cond32) 1558 (comment "condition code hardware for m32c") 1559 (attrs m32c-isa MACH32) 1560 (type immediate UQI) 1561 (values keyword "" 1562 (("ltu" #x00) ("nc" #x00) 1563 ("leu" #x01) 1564 ("ne" #x02) ("nz" #x02) 1565 ("pz" #x03) 1566 ("no" #x04) 1567 ("gt" #x05) 1568 ("ge" #x06) 1569 ("geu" #x08) ("c" #x08) 1570 ("gtu" #x09) 1571 ("eq" #x0a) ("z" #x0a) 1572 ("n" #x0b) 1573 ("o" #x0c) 1574 ("le" #x0d) 1575 ("lt" #x0e) 1576 ) 1577 ) 1578) 1579 1580(define-hardware 1581 (name h-cr1-32) 1582 (comment "control registers") 1583 (attrs m32c-isa MACH32) 1584 (type immediate UQI) 1585 (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4) 1586 ("drc1" 5) ("dmd0" 6) ("dmd1" 7)))) 1587(define-hardware 1588 (name h-cr2-32) 1589 (comment "control registers") 1590 (attrs m32c-isa MACH32) 1591 (type immediate UQI) 1592 (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4) 1593 ("vct" 5) ("isp" 7)))) 1594 1595(define-hardware 1596 (name h-cr3-32) 1597 (comment "control registers") 1598 (attrs m32c-isa MACH32) 1599 (type immediate UQI) 1600 (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4) 1601 ("dra1" 5) ("dsa0" 6) ("dsa1" 7)))) 1602(define-hardware 1603 (name h-cr-16) 1604 (comment "control registers") 1605 (attrs m16c-isa MACH16) 1606 (type immediate UQI) 1607 (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4) 1608 ("sp" 5) ("sb" 6) ("fb" 7)))) 1609 1610(define-hardware 1611 (name h-flags) 1612 (comment "flag hardware for m32c") 1613 (attrs all-isas) 1614 (type immediate UQI) 1615 (values keyword "" 1616 (("c" #x0) 1617 ("d" #x1) 1618 ("z" #x2) 1619 ("s" #x3) 1620 ("b" #x4) 1621 ("o" #x5) 1622 ("i" #x6) 1623 ("u" #x7) 1624 ) 1625 ) 1626) 1627 1628;------------------------------------------------------------- 1629; Misc helper hardware 1630;------------------------------------------------------------- 1631 1632(define-hardware 1633 (name h-shimm) 1634 (comment "shift immediate") 1635 (attrs all-isas) 1636 (type immediate (INT 4)) 1637 (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6) 1638 ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4) 1639 ("-6" -3) ("-7" -2) ("-8" -1) 1640 ))) 1641(define-hardware 1642 (name h-bit-index) 1643 (comment "bit index for the next insn") 1644 (attrs m32c-isa MACH32) 1645 (type register UHI) 1646) 1647(define-hardware 1648 (name h-src-index) 1649 (comment "source index for the next insn") 1650 (attrs m32c-isa MACH32) 1651 (type register UHI) 1652) 1653(define-hardware 1654 (name h-dst-index) 1655 (comment "destination index for the next insn") 1656 (attrs m32c-isa MACH32) 1657 (type register UHI) 1658) 1659(define-hardware 1660 (name h-src-indirect) 1661 (comment "indirect src for the next insn") 1662 (attrs all-isas) 1663 (type register UHI) 1664) 1665(define-hardware 1666 (name h-dst-indirect) 1667 (comment "indirect dst for the next insn") 1668 (attrs all-isas) 1669 (type register UHI) 1670) 1671(define-hardware 1672 (name h-none) 1673 (comment "for storing unused values") 1674 (attrs m32c-isa MACH32) 1675 (type register SI) 1676) 1677 1678;============================================================= 1679; Operands 1680;------------------------------------------------------------- 1681; Source Registers 1682;------------------------------------------------------------- 1683 1684(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn) 1685(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn) 1686 1687(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI) 1688(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI) 1689(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI) 1690 1691(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI) 1692(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI) 1693(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI) 1694 1695(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an) 1696(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an) 1697(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an) 1698 1699(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) 1700(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed) 1701(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed) 1702(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) 1703 1704(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) 1705(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed) 1706(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed) 1707(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) 1708 1709; Destination Registers 1710; 1711(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn) 1712(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) 1713(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn) 1714(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext) 1715 1716(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil) 1717(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil) 1718 1719(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) 1720(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI) 1721(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI) 1722(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed) 1723(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed) 1724 1725(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) 1726(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI) 1727(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI) 1728 1729(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s) 1730 1731(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s) 1732 1733(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) 1734 1735(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) 1736(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) 1737 1738(dnop R0 "r0" (all-isas) h-r0 f-nil) 1739(dnop R1 "r1" (all-isas) h-r1 f-nil) 1740(dnop R2 "r2" (all-isas) h-r2 f-nil) 1741(dnop R3 "r3" (all-isas) h-r3 f-nil) 1742(dnop R0l "r0l" (all-isas) h-r0l f-nil) 1743(dnop R0h "r0h" (all-isas) h-r0h f-nil) 1744(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil) 1745(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil) 1746(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil) 1747 1748(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an) 1749(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an) 1750(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an) 1751(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an) 1752(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s) 1753 1754(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1755(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed) 1756(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed) 1757(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1758 1759(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1760 1761(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1762(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed) 1763(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed) 1764(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1765 1766(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an) 1767 1768(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1769(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1770 1771(dnop A0 "a0" (all-isas) h-a0 f-nil) 1772(dnop A1 "a1" (all-isas) h-a1 f-nil) 1773 1774(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil) 1775(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil) 1776(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil) 1777 1778(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa) 1779 h-sint DFLT f-5-1 1780 ((parse "r0l_r0h") (print "r0l_r0h")) () () 1781) 1782 1783(define-full-operand Regsetpop "popm regset" (all-isas) h-uint 1784 DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ()) 1785(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint 1786 DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ()) 1787 1788(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1) 1789(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1) 1790 1791;------------------------------------------------------------- 1792; Offsets and absolutes 1793;------------------------------------------------------------- 1794 1795(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas) 1796 h-uint DFLT f-dsp-8-u6 1797 ((parse "unsigned6")) () () 1798) 1799(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas) 1800 h-uint DFLT f-dsp-8-u8 1801 ((parse "unsigned8")) () () 1802) 1803(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas) 1804 h-uint DFLT f-dsp-8-u16 1805 ((parse "unsigned16")) () () 1806) 1807(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas) 1808 h-sint DFLT f-dsp-8-s8 1809 ((parse "signed8")) () () 1810) 1811(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas) 1812 h-sint DFLT f-dsp-8-s24 1813 ((parse "signed24")) () () 1814) 1815(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) 1816 h-uint DFLT f-dsp-8-u24 1817 ((parse "unsigned24")) () () 1818) 1819(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas) 1820 h-uint DFLT f-dsp-10-u6 1821 ((parse "unsigned6")) () () 1822) 1823(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas) 1824 h-uint DFLT f-dsp-16-u8 1825 ((parse "unsigned8")) () () 1826) 1827(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas) 1828 h-uint DFLT f-dsp-16-u16 1829 ((parse "unsigned16")) () () 1830) 1831(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas) 1832 h-uint DFLT f-dsp-16-u24 1833 ((parse "unsigned20")) () () 1834) 1835(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas) 1836 h-uint DFLT f-dsp-16-u24 1837 ((parse "unsigned24")) () () 1838) 1839(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas) 1840 h-sint DFLT f-dsp-16-s8 1841 ((parse "signed8")) () () 1842) 1843(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas) 1844 h-sint DFLT f-dsp-16-s16 1845 ((parse "signed16")) () () 1846) 1847(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas) 1848 h-uint DFLT f-dsp-24-u8 1849 ((parse "unsigned8")) () () 1850) 1851(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas) 1852 h-uint DFLT f-dsp-24-u16 1853 ((parse "unsigned16")) () () 1854) 1855(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas) 1856 h-uint DFLT f-dsp-24-u24 1857 ((parse "unsigned20")) () () 1858) 1859(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas) 1860 h-uint DFLT f-dsp-24-u24 1861 ((parse "unsigned24")) () () 1862) 1863(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas) 1864 h-sint DFLT f-dsp-24-s8 1865 ((parse "signed8")) () () 1866) 1867(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas) 1868 h-sint DFLT f-dsp-24-s16 1869 ((parse "signed16")) () () 1870) 1871(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas) 1872 h-uint DFLT f-dsp-32-u8 1873 ((parse "unsigned8")) () () 1874) 1875(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas) 1876 h-uint DFLT f-dsp-32-u16 1877 ((parse "unsigned16")) () () 1878) 1879(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas) 1880 h-uint DFLT f-dsp-32-u24 1881 ((parse "unsigned24")) () () 1882) 1883(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas) 1884 h-uint DFLT f-dsp-32-u24 1885 ((parse "unsigned20")) () () 1886) 1887(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas) 1888 h-sint DFLT f-dsp-32-s8 1889 ((parse "signed8")) () () 1890) 1891(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas) 1892 h-sint DFLT f-dsp-32-s16 1893 ((parse "signed16")) () () 1894) 1895(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas) 1896 h-uint DFLT f-dsp-40-u8 1897 ((parse "unsigned8")) () () 1898) 1899(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas) 1900 h-sint DFLT f-dsp-40-s8 1901 ((parse "signed8")) () () 1902) 1903(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas) 1904 h-uint DFLT f-dsp-40-u16 1905 ((parse "unsigned16")) () () 1906) 1907(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas) 1908 h-sint DFLT f-dsp-40-s16 1909 ((parse "signed16")) () () 1910) 1911(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) 1912 h-uint DFLT f-dsp-40-u20 1913 ((parse "unsigned20")) () () 1914) 1915(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) 1916 h-uint DFLT f-dsp-40-u24 1917 ((parse "unsigned24")) () () 1918) 1919(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas) 1920 h-uint DFLT f-dsp-48-u8 1921 ((parse "unsigned8")) () () 1922) 1923(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas) 1924 h-sint DFLT f-dsp-48-s8 1925 ((parse "signed8")) () () 1926) 1927(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas) 1928 h-uint DFLT f-dsp-48-u16 1929 ((parse "unsigned16")) () () 1930) 1931(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas) 1932 h-sint DFLT f-dsp-48-s16 1933 ((parse "signed16")) () () 1934) 1935(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) 1936 h-uint DFLT f-dsp-48-u20 1937 ((parse "unsigned24")) () () 1938) 1939(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) 1940 h-uint DFLT f-dsp-48-u24 1941 ((parse "unsigned24")) () () 1942) 1943 1944(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas) 1945 h-sint DFLT f-imm-8-s4 1946 ((parse "signed4")) () () 1947) 1948(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) 1949 h-sint DFLT f-imm-8-s4 1950 ((parse "signed4n") (print "signed4n")) () () 1951) 1952(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) 1953 h-shimm DFLT f-imm-8-s4 1954 () () () 1955) 1956(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas) 1957 h-sint DFLT f-dsp-8-s8 1958 ((parse "signed8")) () () 1959) 1960(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas) 1961 h-sint DFLT f-dsp-8-s16 1962 ((parse "signed16")) () () 1963) 1964(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas) 1965 h-sint DFLT f-imm-12-s4 1966 ((parse "signed4")) () () 1967) 1968(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas) 1969 h-sint DFLT f-imm-12-s4 1970 ((parse "signed4n") (print "signed4n")) () () 1971) 1972(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) 1973 h-shimm DFLT f-imm-12-s4 1974 () () () 1975) 1976(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas) 1977 h-sint DFLT f-imm-13-u3 1978 ((parse "signed4")) () () 1979) 1980(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas) 1981 h-sint DFLT f-imm-20-s4 1982 ((parse "signed4")) () () 1983) 1984(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) 1985 h-shimm DFLT f-imm-20-s4 1986 () () () 1987) 1988(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas) 1989 h-sint DFLT f-dsp-16-s8 1990 ((parse "signed8")) () () 1991) 1992(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas) 1993 h-sint DFLT f-dsp-16-s16 1994 ((parse "signed16")) () () 1995) 1996(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas) 1997 h-sint DFLT f-dsp-16-s32 1998 ((parse "signed32")) () () 1999) 2000(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas) 2001 h-sint DFLT f-dsp-24-s8 2002 ((parse "signed8")) () () 2003) 2004(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas) 2005 h-sint DFLT f-dsp-24-s16 2006 ((parse "signed16")) () () 2007) 2008(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas) 2009 h-sint DFLT f-dsp-24-s32 2010 ((parse "signed32")) () () 2011) 2012(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas) 2013 h-sint DFLT f-dsp-32-s8 2014 ((parse "signed8")) () () 2015) 2016(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas) 2017 h-sint DFLT f-dsp-32-s32 2018 ((parse "signed32")) () () 2019) 2020(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas) 2021 h-sint DFLT f-dsp-32-s16 2022 ((parse "signed16")) () () 2023) 2024(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas) 2025 h-sint DFLT f-dsp-40-s8 2026 ((parse "signed8")) () () 2027) 2028(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas) 2029 h-sint DFLT f-dsp-40-s16 2030 ((parse "signed16")) () () 2031) 2032(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas) 2033 h-sint DFLT f-dsp-40-s32 2034 ((parse "signed32")) () () 2035) 2036(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas) 2037 h-sint DFLT f-dsp-48-s8 2038 ((parse "signed8")) () () 2039) 2040(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas) 2041 h-sint DFLT f-dsp-48-s16 2042 ((parse "signed16")) () () 2043) 2044(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas) 2045 h-sint DFLT f-dsp-48-s32 2046 ((parse "signed32")) () () 2047) 2048(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas) 2049 h-sint DFLT f-dsp-56-s8 2050 ((parse "signed8")) () () 2051) 2052(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas) 2053 h-sint DFLT f-dsp-56-s16 2054 ((parse "signed16")) () () 2055) 2056(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas) 2057 h-sint DFLT f-dsp-64-s16 2058 ((parse "signed16")) () () 2059) 2060(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa) 2061 h-sint DFLT f-imm1-S 2062 ((parse "imm1_S")) () () 2063) 2064(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa) 2065 h-sint DFLT f-imm3-S 2066 ((parse "imm3_S")) () () 2067) 2068(define-full-operand Bit3-S "3 bit bit number" (m32c-isa) 2069 h-sint DFLT f-imm3-S 2070 ((parse "bit3_S")) () () 2071) 2072 2073;------------------------------------------------------------- 2074; Bit numbers 2075;------------------------------------------------------------- 2076 2077(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa) 2078 h-uint DFLT f-dsp-16-u8 2079 ((parse "Bitno16R")) () () 2080) 2081(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed) 2082(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed) 2083 2084(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa) 2085 h-uint DFLT f-dsp-16-u8 2086 ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () () 2087) 2088(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa) 2089 h-sint DFLT f-dsp-16-s8 2090 ((parse "signed_bitbase8") (print "signed_bitbase")) () () 2091) 2092(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa) 2093 h-uint DFLT f-dsp-16-u16 2094 ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () () 2095) 2096(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa) 2097 h-uint DFLT f-bitbase16-u11-S 2098 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2099) 2100 2101(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa) 2102 h-uint DFLT f-bitbase32-16-u11-unprefixed 2103 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2104) 2105(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa) 2106 h-sint DFLT f-bitbase32-16-s11-unprefixed 2107 ((parse "signed_bitbase11") (print "signed_bitbase")) () () 2108) 2109(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa) 2110 h-uint DFLT f-bitbase32-16-u19-unprefixed 2111 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () 2112) 2113(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa) 2114 h-sint DFLT f-bitbase32-16-s19-unprefixed 2115 ((parse "signed_bitbase19") (print "signed_bitbase")) () () 2116) 2117(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa) 2118 h-uint DFLT f-bitbase32-16-u27-unprefixed 2119 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () 2120) 2121(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa) 2122 h-uint DFLT f-bitbase32-24-u11-prefixed 2123 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2124) 2125(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa) 2126 h-sint DFLT f-bitbase32-24-s11-prefixed 2127 ((parse "signed_bitbase11") (print "signed_bitbase")) () () 2128) 2129(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa) 2130 h-uint DFLT f-bitbase32-24-u19-prefixed 2131 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () 2132) 2133(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa) 2134 h-sint DFLT f-bitbase32-24-s19-prefixed 2135 ((parse "signed_bitbase19") (print "signed_bitbase")) () () 2136) 2137(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa) 2138 h-uint DFLT f-bitbase32-24-u27-prefixed 2139 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () 2140) 2141;------------------------------------------------------------- 2142; Labels 2143;------------------------------------------------------------- 2144 2145(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX) 2146 h-iaddr DFLT f-lab-5-3 2147 ((parse "lab_5_3")) () () ) 2148 2149(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX) 2150 h-iaddr DFLT f-lab32-jmp-s 2151 ((parse "lab_5_3")) () () ) 2152 2153(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) 2154(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) 2155(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) 2156(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) 2157(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) 2158(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) 2159(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) 2160 2161;------------------------------------------------------------- 2162; Condition code bits 2163;------------------------------------------------------------- 2164 2165(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil) 2166(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil) 2167(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil) 2168(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil) 2169(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil) 2170(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil) 2171(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil) 2172(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil) 2173 2174;------------------------------------------------------------- 2175; Condition operands 2176;------------------------------------------------------------- 2177 2178(define-pmacro (cond-operand mach offset) 2179 (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8)) 2180) 2181 2182(cond-operand 16 16) 2183(cond-operand 16 24) 2184(cond-operand 16 32) 2185(cond-operand 32 16) 2186(cond-operand 32 24) 2187(cond-operand 32 32) 2188(cond-operand 32 40) 2189 2190(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16) 2191(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16) 2192(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5) 2193(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32) 2194(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j) 2195(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16) 2196(dnop flags16 "flags" (m16c-isa) h-flags f-9-3) 2197(dnop flags32 "flags" (m32c-isa) h-flags f-13-3) 2198(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3) 2199(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3) 2200(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3) 2201(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3) 2202(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3) 2203(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3) 2204 2205;------------------------------------------------------------- 2206; Suffixes 2207;------------------------------------------------------------- 2208 2209(define-full-operand Z "Suffix for zero format insns" (all-isas) 2210 h-sint DFLT f-nil 2211 ((parse "Z") (print "Z")) () () 2212) 2213(define-full-operand S "Suffix for short format insns" (all-isas) 2214 h-sint DFLT f-nil 2215 ((parse "S") (print "S")) () () 2216) 2217(define-full-operand Q "Suffix for quick format insns" (all-isas) 2218 h-sint DFLT f-nil 2219 ((parse "Q") (print "Q")) () () 2220) 2221(define-full-operand G "Suffix for general format insns" (all-isas) 2222 h-sint DFLT f-nil 2223 ((parse "G") (print "G")) () () 2224) 2225(define-full-operand X "Empty suffix" (all-isas) 2226 h-sint DFLT f-nil 2227 ((parse "X") (print "X")) () () 2228) 2229(define-full-operand size "any size specifier" (all-isas) 2230 h-sint DFLT f-nil 2231 ((parse "size") (print "size")) () () 2232) 2233;------------------------------------------------------------- 2234; Misc 2235;------------------------------------------------------------- 2236 2237(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil) 2238(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil) 2239(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil) 2240(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil) 2241 2242;============================================================= 2243; Derived Operands 2244 2245; Memory reference macros that clip addresses appropriately. Refer to 2246; memory at ADDRESS in MODE, clipped appropriately for either the m16c 2247; or m32c. 2248(define-pmacro (mem16 mode address) 2249 (mem mode (and #xffff address))) 2250 2251(define-pmacro (mem20 mode address) 2252 (mem mode (and #xfffff address))) 2253 2254(define-pmacro (mem32 mode address) 2255 (mem mode (and #xffffff address))) 2256 2257; Like mem16 and mem32, but takes MACH as a parameter. MACH must be 2258; either 16 or 32. 2259(define-pmacro (mem-mach mach mode address) 2260 ((.sym mem mach) mode address)) 2261 2262;------------------------------------------------------------- 2263; Source 2264;------------------------------------------------------------- 2265; Rn direct 2266;------------------------------------------------------------- 2267 2268(define-pmacro (src16-Rn-direct-operand xmode) 2269 (begin 2270 (define-derived-operand 2271 (name (.sym src16-Rn-direct- xmode)) 2272 (comment (.str "m16c Rn direct source " xmode)) 2273 (attrs (machine 16)) 2274 (mode xmode) 2275 (args ((.sym Src16Rn xmode))) 2276 (syntax (.str "$Src16Rn" xmode)) 2277 (base-ifield f-8-4) 2278 (encoding (+ (f-8-2 0) (.sym Src16Rn xmode))) 2279 (ifield-assertion (eq f-8-2 0)) 2280 (getter (trunc xmode (.sym Src16Rn xmode))) 2281 (setter (set (.sym Src16Rn xmode) newval)) 2282 ) 2283 ) 2284) 2285(src16-Rn-direct-operand QI) 2286(src16-Rn-direct-operand HI) 2287 2288(define-pmacro (src32-Rn-direct-operand group base xmode) 2289 (begin 2290 (define-derived-operand 2291 (name (.sym src32-Rn-direct- group - xmode)) 2292 (comment (.str "m32c Rn direct source " xmode)) 2293 (attrs (machine 32)) 2294 (mode xmode) 2295 (args ((.sym Src32Rn group xmode))) 2296 (syntax (.str "$Src32Rn" group xmode)) 2297 (base-ifield (.sym f- base -11)) 2298 (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode))) 2299 (ifield-assertion (eq (.sym f- base -3) 4)) 2300 (getter (trunc xmode (.sym Src32Rn group xmode))) 2301 (setter (set (.sym Src32Rn group xmode) newval)) 2302 ) 2303 ) 2304) 2305 2306(src32-Rn-direct-operand Unprefixed 1 QI) 2307(src32-Rn-direct-operand Prefixed 9 QI) 2308(src32-Rn-direct-operand Unprefixed 1 HI) 2309(src32-Rn-direct-operand Prefixed 9 HI) 2310(src32-Rn-direct-operand Unprefixed 1 SI) 2311(src32-Rn-direct-operand Prefixed 9 SI) 2312 2313;------------------------------------------------------------- 2314; An direct 2315;------------------------------------------------------------- 2316 2317(define-pmacro (src16-An-direct-operand xmode) 2318 (begin 2319 (define-derived-operand 2320 (name (.sym src16-An-direct- xmode)) 2321 (comment (.str "m16c An direct destination " xmode)) 2322 (attrs (machine 16)) 2323 (mode xmode) 2324 (args ((.sym Src16An xmode))) 2325 (syntax (.str "$Src16An" xmode)) 2326 (base-ifield f-8-4) 2327 (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode))) 2328 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0))) 2329 (getter (trunc xmode (.sym Src16An xmode))) 2330 (setter (set (.sym Src16An xmode) newval)) 2331 ) 2332 ) 2333) 2334(src16-An-direct-operand QI) 2335(src16-An-direct-operand HI) 2336 2337(define-pmacro (src32-An-direct-operand group base1 base2 xmode) 2338 (begin 2339 (define-derived-operand 2340 (name (.sym src32-An-direct- group - xmode)) 2341 (comment (.str "m32c An direct destination " xmode)) 2342 (attrs (machine 32)) 2343 (mode xmode) 2344 (args ((.sym Src32An group xmode))) 2345 (syntax (.str "$Src32An" group xmode)) 2346 (base-ifield (.sym f- base1 -11)) 2347 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode))) 2348 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 2349 (getter (trunc xmode (.sym Src32An group xmode))) 2350 (setter (set (.sym Src32An group xmode) newval)) 2351 ) 2352 ) 2353) 2354 2355(src32-An-direct-operand Unprefixed 1 10 QI) 2356(src32-An-direct-operand Unprefixed 1 10 HI) 2357(src32-An-direct-operand Unprefixed 1 10 SI) 2358(src32-An-direct-operand Prefixed 9 18 QI) 2359(src32-An-direct-operand Prefixed 9 18 HI) 2360(src32-An-direct-operand Prefixed 9 18 SI) 2361 2362;------------------------------------------------------------- 2363; An indirect 2364;------------------------------------------------------------- 2365 2366(define-pmacro (src16-An-indirect-operand xmode) 2367 (begin 2368 (define-derived-operand 2369 (name (.sym src16-An-indirect- xmode)) 2370 (comment (.str "m16c An indirect destination " xmode)) 2371 (attrs (machine 16)) 2372 (mode xmode) 2373 (args (Src16An)) 2374 (syntax "[$Src16An]") 2375 (base-ifield f-8-4) 2376 (encoding (+ (f-8-2 1) (f-10-1 1) Src16An)) 2377 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1))) 2378 (getter (mem16 xmode Src16An)) 2379 (setter (set (mem16 xmode Src16An) newval)) 2380 ) 2381 ) 2382) 2383(src16-An-indirect-operand QI) 2384(src16-An-indirect-operand HI) 2385 2386(define-pmacro (src32-An-indirect-operand group base1 base2 xmode) 2387 (begin 2388 (define-derived-operand 2389 (name (.sym src32-An-indirect- group - xmode)) 2390 (comment (.str "m32c An indirect destination " xmode)) 2391 (attrs (machine 32)) 2392 (mode xmode) 2393 (args ((.sym Src32An group))) 2394 (syntax (.str "[$Src32An" group "]")) 2395 (base-ifield (.sym f- base1 -11)) 2396 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group))) 2397 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 2398 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) 2399 (const 0))) 2400 (setter (c-call DFLT (.str "operand_setter_" xmode) newval 2401 (.sym Src32An group) (const 0))) 2402; (getter (mem32 xmode (.sym Src32An group))) 2403; (setter (set (mem32 xmode (.sym Src32An group)) newval)) 2404 ) 2405 ) 2406) 2407 2408(src32-An-indirect-operand Unprefixed 1 10 QI) 2409(src32-An-indirect-operand Unprefixed 1 10 HI) 2410(src32-An-indirect-operand Unprefixed 1 10 SI) 2411(src32-An-indirect-operand Prefixed 9 18 QI) 2412(src32-An-indirect-operand Prefixed 9 18 HI) 2413(src32-An-indirect-operand Prefixed 9 18 SI) 2414 2415;------------------------------------------------------------- 2416; dsp:d[r] relative 2417;------------------------------------------------------------- 2418 2419(define-pmacro (src16-relative-operand xmode) 2420 (begin 2421 (define-derived-operand 2422 (name (.sym src16-16-8-SB-relative- xmode)) 2423 (comment (.str "m16c dsp:8[sb] relative destination " xmode)) 2424 (attrs (machine 16)) 2425 (mode xmode) 2426 (args (Dsp-16-u8)) 2427 (syntax "${Dsp-16-u8}[sb]") 2428 (base-ifield f-8-4) 2429 (encoding (+ (f-8-4 #xA) Dsp-16-u8)) 2430 (ifield-assertion (eq f-8-4 #xA)) 2431 (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb)))) 2432 (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval)) 2433 ) 2434 (define-derived-operand 2435 (name (.sym src16-16-16-SB-relative- xmode)) 2436 (comment (.str "m16c dsp:16[sb] relative destination " xmode)) 2437 (attrs (machine 16)) 2438 (mode xmode) 2439 (args (Dsp-16-u16)) 2440 (syntax "${Dsp-16-u16}[sb]") 2441 (base-ifield f-8-4) 2442 (encoding (+ (f-8-4 #xE) Dsp-16-u16)) 2443 (ifield-assertion (eq f-8-4 #xE)) 2444 (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb)))) 2445 (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval)) 2446 ) 2447 (define-derived-operand 2448 (name (.sym src16-16-8-FB-relative- xmode)) 2449 (comment (.str "m16c dsp:8[fb] relative destination " xmode)) 2450 (attrs (machine 16)) 2451 (mode xmode) 2452 (args (Dsp-16-s8)) 2453 (syntax "${Dsp-16-s8}[fb]") 2454 (base-ifield f-8-4) 2455 (encoding (+ (f-8-4 #xB) Dsp-16-s8)) 2456 (ifield-assertion (eq f-8-4 #xB)) 2457 (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb)))) 2458 (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval)) 2459 ) 2460 (define-derived-operand 2461 (name (.sym src16-16-8-An-relative- xmode)) 2462 (comment (.str "m16c dsp:8[An] relative destination " xmode)) 2463 (attrs (machine 16)) 2464 (mode xmode) 2465 (args (Src16An Dsp-16-u8)) 2466 (syntax "${Dsp-16-u8}[$Src16An]") 2467 (base-ifield f-8-4) 2468 (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An)) 2469 (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0))) 2470 (getter (mem16 xmode (add Dsp-16-u8 Src16An))) 2471 (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval)) 2472 ) 2473 (define-derived-operand 2474 (name (.sym src16-16-16-An-relative- xmode)) 2475 (comment (.str "m16c dsp:16[An] relative destination " xmode)) 2476 (attrs (machine 16)) 2477 (mode xmode) 2478 (args (Src16An Dsp-16-u16)) 2479 (syntax "${Dsp-16-u16}[$Src16An]") 2480 (base-ifield f-8-4) 2481 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An)) 2482 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) 2483 (getter (mem16 xmode (add Dsp-16-u16 Src16An))) 2484 (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) 2485 ) 2486 (define-derived-operand 2487 (name (.sym src16-16-20-An-relative- xmode)) 2488 (comment (.str "m16c dsp:20[An] relative destination " xmode)) 2489 (attrs (machine 16)) 2490 (mode xmode) 2491 (args (Src16An Dsp-16-u20)) 2492 (syntax "${Dsp-16-u20}[$Src16An]") 2493 (base-ifield f-8-4) 2494 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) 2495 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) 2496 (getter (mem20 xmode (add Dsp-16-u20 Src16An))) 2497 (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) 2498 ) 2499 ) 2500) 2501 2502(src16-relative-operand QI) 2503(src16-relative-operand HI) 2504 2505(define-pmacro (src32-relative-operand offset group base1 base2 xmode) 2506 (begin 2507 (define-derived-operand 2508 (name (.sym src32- offset -8-SB-relative- group - xmode)) 2509 (comment (.str "m32c dsp:8[sb] relative destination " xmode)) 2510 (attrs (machine 32)) 2511 (mode xmode) 2512 (args ((.sym Dsp- offset -u8))) 2513 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 2514 (base-ifield (.sym f- base1 -11)) 2515 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) 2516 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 2517 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8))) 2518 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8))) 2519; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) 2520; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 2521 ) 2522 (define-derived-operand 2523 (name (.sym src32- offset -16-SB-relative- group - xmode)) 2524 (comment (.str "m32c dsp:16[sb] relative destination " xmode)) 2525 (attrs (machine 32)) 2526 (mode xmode) 2527 (args ((.sym Dsp- offset -u16))) 2528 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 2529 (base-ifield (.sym f- base1 -11)) 2530 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) 2531 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 2532 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16))) 2533 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16))) 2534; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) 2535; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 2536 ) 2537 (define-derived-operand 2538 (name (.sym src32- offset -8-FB-relative- group - xmode)) 2539 (comment (.str "m32c dsp:8[fb] relative destination " xmode)) 2540 (attrs (machine 32)) 2541 (mode xmode) 2542 (args ((.sym Dsp- offset -s8))) 2543 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 2544 (base-ifield (.sym f- base1 -11)) 2545 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) 2546 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 2547 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8))) 2548 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8))) 2549; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) 2550; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 2551 ) 2552 (define-derived-operand 2553 (name (.sym src32- offset -16-FB-relative- group - xmode)) 2554 (comment (.str "m32c dsp:16[fb] relative destination " xmode)) 2555 (attrs (machine 32)) 2556 (mode xmode) 2557 (args ((.sym Dsp- offset -s16))) 2558 (syntax (.str "${Dsp-" offset "-s16}[fb]")) 2559 (base-ifield (.sym f- base1 -11)) 2560 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) 2561 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 2562 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16))) 2563 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16))) 2564; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb)))) 2565; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) 2566 ) 2567 (define-derived-operand 2568 (name (.sym src32- offset -8-An-relative- group - xmode)) 2569 (comment (.str "m32c dsp:8[An] relative destination " xmode)) 2570 (attrs (machine 32)) 2571 (mode xmode) 2572 (args ((.sym Src32An group) (.sym Dsp- offset -u8))) 2573 (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]")) 2574 (base-ifield (.sym f- base1 -11)) 2575 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group))) 2576 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 2577 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8))) 2578 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8))) 2579; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group)))) 2580; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval)) 2581 ) 2582 (define-derived-operand 2583 (name (.sym src32- offset -16-An-relative- group - xmode)) 2584 (comment (.str "m32c dsp:16[An] relative destination " xmode)) 2585 (attrs (machine 32)) 2586 (mode xmode) 2587 (args ((.sym Src32An group) (.sym Dsp- offset -u16))) 2588 (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]")) 2589 (base-ifield (.sym f- base1 -11)) 2590 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group))) 2591 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 2592 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16))) 2593 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16))) 2594; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group)))) 2595; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval)) 2596 ) 2597 (define-derived-operand 2598 (name (.sym src32- offset -24-An-relative- group - xmode)) 2599 (comment (.str "m32c dsp:16[An] relative destination " xmode)) 2600 (attrs (machine 32)) 2601 (mode xmode) 2602 (args ((.sym Src32An group) (.sym Dsp- offset -u24))) 2603 (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]")) 2604 (base-ifield (.sym f- base1 -11)) 2605 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group))) 2606 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 2607 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) )) 2608 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24))) 2609; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group)))) 2610; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval)) 2611 ) 2612 ) 2613) 2614 2615(src32-relative-operand 16 Unprefixed 1 10 QI) 2616(src32-relative-operand 16 Unprefixed 1 10 HI) 2617(src32-relative-operand 16 Unprefixed 1 10 SI) 2618(src32-relative-operand 24 Prefixed 9 18 QI) 2619(src32-relative-operand 24 Prefixed 9 18 HI) 2620(src32-relative-operand 24 Prefixed 9 18 SI) 2621 2622;------------------------------------------------------------- 2623; Absolute address 2624;------------------------------------------------------------- 2625 2626(define-pmacro (src16-absolute xmode) 2627 (begin 2628 (define-derived-operand 2629 (name (.sym src16-16-16-absolute- xmode)) 2630 (comment (.str "m16c absolute address " xmode)) 2631 (attrs (machine 16)) 2632 (mode xmode) 2633 (args (Dsp-16-u16)) 2634 (syntax (.str "${Dsp-16-u16}")) 2635 (base-ifield f-8-4) 2636 (encoding (+ (f-8-4 #xF) Dsp-16-u16)) 2637 (ifield-assertion (eq f-8-4 #xF)) 2638 (getter (mem16 xmode Dsp-16-u16)) 2639 (setter (set (mem16 xmode Dsp-16-u16) newval)) 2640 ) 2641 ) 2642) 2643 2644(src16-absolute QI) 2645(src16-absolute HI) 2646 2647(define-pmacro (src32-absolute offset group base1 base2 xmode) 2648 (begin 2649 (define-derived-operand 2650 (name (.sym src32- offset -16-absolute- group - xmode)) 2651 (comment (.str "m32c absolute address " xmode)) 2652 (attrs (machine 32)) 2653 (mode xmode) 2654 (args ((.sym Dsp- offset -u16))) 2655 (syntax (.str "${Dsp-" offset "-u16}")) 2656 (base-ifield (.sym f- base1 -11)) 2657 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 2658 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 2659 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16))) 2660 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16))) 2661; (getter (mem32 xmode (.sym Dsp- offset -u16))) 2662; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval)) 2663 ) 2664 (define-derived-operand 2665 (name (.sym src32- offset -24-absolute- group - xmode)) 2666 (comment (.str "m32c absolute address " xmode)) 2667 (attrs (machine 32)) 2668 (mode xmode) 2669 (args ((.sym Dsp- offset -u24))) 2670 (syntax (.str "${Dsp-" offset "-u24}")) 2671 (base-ifield (.sym f- base1 -11)) 2672 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 2673 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 2674 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24))) 2675 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24))) 2676; (getter (mem32 xmode (.sym Dsp- offset -u24))) 2677; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval)) 2678 ) 2679 ) 2680) 2681 2682(src32-absolute 16 Unprefixed 1 10 QI) 2683(src32-absolute 16 Unprefixed 1 10 HI) 2684(src32-absolute 16 Unprefixed 1 10 SI) 2685(src32-absolute 24 Prefixed 9 18 QI) 2686(src32-absolute 24 Prefixed 9 18 HI) 2687(src32-absolute 24 Prefixed 9 18 SI) 2688 2689;------------------------------------------------------------- 2690; An indirect indirect 2691; 2692; Double indirect addressing uses the lower 3 bytes of the value stored 2693; at the address referenced by 'op' as the effective address. 2694;------------------------------------------------------------- 2695 2696(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff)) 2697 2698; (define-pmacro (src-An-indirect-indirect-operand xmode) 2699; (define-derived-operand 2700; (name (.sym src32-An-indirect-indirect- xmode)) 2701; (comment (.str "m32c An indirect indirect destination " xmode)) 2702; (attrs (machine 32)) 2703; (mode xmode) 2704; (args (Src32AnPrefixed)) 2705; (syntax (.str "[[$Src32AnPrefixed]]")) 2706; (base-ifield f-9-11) 2707; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed)) 2708; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0))) 2709; (getter (mem32 xmode (indirect-addr Src32AnPrefixed))) 2710; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval)) 2711; ) 2712; ) 2713 2714; (src-An-indirect-indirect-operand QI) 2715; (src-An-indirect-indirect-operand HI) 2716; (src-An-indirect-indirect-operand SI) 2717 2718;------------------------------------------------------------- 2719; Relative indirect 2720;------------------------------------------------------------- 2721 2722(define-pmacro (src-relative-indirect-operand xmode) 2723 (begin 2724; (define-derived-operand 2725; (name (.sym src32-24-8-SB-relative-indirect- xmode)) 2726; (comment (.str "m32c dsp:8[sb] relative source " xmode)) 2727; (attrs (machine 32)) 2728; (mode xmode) 2729; (args (Dsp-24-u8)) 2730; (syntax "[${Dsp-24-u8}[sb]]") 2731; (base-ifield f-9-11) 2732; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8)) 2733; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2))) 2734; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb))))) 2735; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval)) 2736; ) 2737; (define-derived-operand 2738; (name (.sym src32-24-16-SB-relative-indirect- xmode)) 2739; (comment (.str "m32c dsp:16[sb] relative source " xmode)) 2740; (attrs (machine 32)) 2741; (mode xmode) 2742; (args (Dsp-24-u16)) 2743; (syntax "[${Dsp-24-u16}[sb]]") 2744; (base-ifield f-9-11) 2745; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16)) 2746; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2))) 2747; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb))))) 2748; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval)) 2749; ) 2750; (define-derived-operand 2751; (name (.sym src32-24-8-FB-relative-indirect- xmode)) 2752; (comment (.str "m32c dsp:8[fb] relative source " xmode)) 2753; (attrs (machine 32)) 2754; (mode xmode) 2755; (args (Dsp-24-s8)) 2756; (syntax "[${Dsp-24-s8}[fb]]") 2757; (base-ifield f-9-11) 2758; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8)) 2759; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3))) 2760; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb))))) 2761; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval)) 2762; ) 2763; (define-derived-operand 2764; (name (.sym src32-24-16-FB-relative-indirect- xmode)) 2765; (comment (.str "m32c dsp:16[fb] relative source " xmode)) 2766; (attrs (machine 32)) 2767; (mode xmode) 2768; (args (Dsp-24-s16)) 2769; (syntax "[${Dsp-24-s16}[fb]]") 2770; (base-ifield f-9-11) 2771; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16)) 2772; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3))) 2773; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb))))) 2774; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval)) 2775; ) 2776; (define-derived-operand 2777; (name (.sym src32-24-8-An-relative-indirect- xmode)) 2778; (comment (.str "m32c dsp:8[An] relative indirect source " xmode)) 2779; (attrs (machine 32)) 2780; (mode xmode) 2781; (args (Src32AnPrefixed Dsp-24-u8)) 2782; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]") 2783; (base-ifield f-9-11) 2784; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed)) 2785; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0))) 2786; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed)))) 2787; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval)) 2788; ) 2789; (define-derived-operand 2790; (name (.sym src32-24-16-An-relative-indirect- xmode)) 2791; (comment (.str "m32c dsp:16[An] relative source " xmode)) 2792; (attrs (machine 32)) 2793; (mode xmode) 2794; (args (Src32AnPrefixed Dsp-24-u16)) 2795; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]") 2796; (base-ifield f-9-11) 2797; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed)) 2798; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0))) 2799; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed)))) 2800; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval)) 2801; ) 2802; (define-derived-operand 2803; (name (.sym src32-24-24-An-relative-indirect- xmode)) 2804; (comment (.str "m32c dsp:24[An] relative source " xmode)) 2805; (attrs (machine 32)) 2806; (mode xmode) 2807; (args (Src32AnPrefixed Dsp-24-u24)) 2808; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]") 2809; (base-ifield f-9-11) 2810; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed)) 2811; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0))) 2812; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed)))) 2813; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval)) 2814; ) 2815 ) 2816) 2817 2818; (src-relative-indirect-operand QI) 2819; (src-relative-indirect-operand HI) 2820; (src-relative-indirect-operand SI) 2821 2822;------------------------------------------------------------- 2823; Absolute Indirect address 2824;------------------------------------------------------------- 2825 2826(define-pmacro (src32-absolute-indirect offset base1 base2 xmode) 2827 (begin 2828; (define-derived-operand 2829; (name (.sym src32- offset -16-absolute-indirect-derived- xmode)) 2830; (comment (.str "m32c absolute indirect address " xmode)) 2831; (attrs (machine 32)) 2832; (mode xmode) 2833; (args ((.sym Dsp- offset -u16))) 2834; (syntax (.str "[${Dsp-" offset "-u16}]")) 2835; (base-ifield (.sym f- base1 -11)) 2836; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 2837; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 2838; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) 2839; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) 2840; ) 2841; (define-derived-operand 2842; (name (.sym src32- offset -24-absolute-indirect-derived- xmode)) 2843; (comment (.str "m32c absolute indirect address " xmode)) 2844; (attrs (machine 32)) 2845; (mode xmode) 2846; (args ((.sym Dsp- offset -u24))) 2847; (syntax (.str "[${Dsp-" offset "-u24}]")) 2848; (base-ifield (.sym f- base1 -11)) 2849; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 2850; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 2851; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) 2852; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) 2853; ) 2854 ) 2855) 2856 2857(src32-absolute-indirect 24 9 18 QI) 2858(src32-absolute-indirect 24 9 18 HI) 2859(src32-absolute-indirect 24 9 18 SI) 2860 2861;------------------------------------------------------------- 2862; Register relative source operands for short format insns 2863;------------------------------------------------------------- 2864 2865(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3) 2866 (begin 2867 (define-derived-operand 2868 (name (.sym src mach -2-S-8-SB-relative- xmode)) 2869 (comment (.str "m" mach "c SB relative address")) 2870 (attrs (machine mach)) 2871 (mode xmode) 2872 (args (Dsp-8-u8)) 2873 (syntax "${Dsp-8-u8}[sb]") 2874 (base-ifield (.sym f- base -2)) 2875 (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8)) 2876 (ifield-assertion (eq (.sym f- base -2) opc1)) 2877 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) 2878 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) 2879; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8)))) 2880; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval)) 2881 ) 2882 (define-derived-operand 2883 (name (.sym src mach -2-S-8-FB-relative- xmode)) 2884 (comment (.str "m" mach "c FB relative address")) 2885 (attrs (machine mach)) 2886 (mode xmode) 2887 (args (Dsp-8-s8)) 2888 (syntax "${Dsp-8-s8}[fb]") 2889 (base-ifield (.sym f- base -2)) 2890 (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8)) 2891 (ifield-assertion (eq (.sym f- base -2) opc2)) 2892 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) 2893 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) 2894; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8)))) 2895; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval)) 2896 ) 2897 (define-derived-operand 2898 (name (.sym src mach -2-S-16-absolute- xmode)) 2899 (comment (.str "m" mach "c absolute address")) 2900 (attrs (machine mach)) 2901 (mode xmode) 2902 (args (Dsp-8-u16)) 2903 (syntax "${Dsp-8-u16}") 2904 (base-ifield (.sym f- base -2)) 2905 (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16)) 2906 (ifield-assertion (eq (.sym f- base -2) opc3)) 2907 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) 2908 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) 2909; (getter (mem-mach mach xmode Dsp-8-u16)) 2910; (setter (set (mem-mach mach xmode Dsp-8-u16) newval)) 2911 ) 2912 ) 2913) 2914 2915(src-2-S-operands 16 QI 6 1 2 3) 2916(src-2-S-operands 32 QI 2 2 3 1) 2917(src-2-S-operands 32 HI 2 2 3 1) 2918 2919;============================================================= 2920; Derived Operands 2921;------------------------------------------------------------- 2922; Destination 2923;------------------------------------------------------------- 2924; Rn direct 2925;------------------------------------------------------------- 2926 2927(define-pmacro (dst16-Rn-direct-operand xmode) 2928 (begin 2929 (define-derived-operand 2930 (name (.sym dst16-Rn-direct- xmode)) 2931 (comment (.str "m16c Rn direct destination " xmode)) 2932 (attrs (machine 16)) 2933 (mode xmode) 2934 (args ((.sym Dst16Rn xmode))) 2935 (syntax (.str "$Dst16Rn" xmode)) 2936 (base-ifield f-12-4) 2937 (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode))) 2938 (ifield-assertion (eq f-12-2 0)) 2939 (getter (trunc xmode (.sym Dst16Rn xmode))) 2940 (setter (set (.sym Dst16Rn xmode) newval)) 2941 ) 2942 ) 2943) 2944 2945(dst16-Rn-direct-operand QI) 2946(dst16-Rn-direct-operand HI) 2947(dst16-Rn-direct-operand SI) 2948 2949(define-derived-operand 2950 (name dst16-Rn-direct-Ext-QI) 2951 (comment "m16c Rn direct destination QI") 2952 (attrs (machine 16)) 2953 (mode HI) 2954 (args (Dst16RnExtQI)) 2955 (syntax "$Dst16RnExtQI") 2956 (base-ifield f-12-4) 2957 (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0))) 2958 (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0))) 2959 (getter (trunc QI (.sym Dst16RnExtQI))) 2960 (setter (set Dst16RnExtQI newval)) 2961) 2962 2963(define-pmacro (dst32-Rn-direct-operand group base xmode) 2964 (begin 2965 (define-derived-operand 2966 (name (.sym dst32-Rn-direct- group - xmode)) 2967 (comment (.str "m32c Rn direct destination " xmode)) 2968 (attrs (machine 32)) 2969 (mode xmode) 2970 (args ((.sym Dst32Rn group xmode))) 2971 (syntax (.str "$Dst32Rn" group xmode)) 2972 (base-ifield (.sym f- base -6)) 2973 (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode))) 2974 (ifield-assertion (eq (.sym f- base -3) 4)) 2975 (getter (trunc xmode (.sym Dst32Rn group xmode))) 2976 (setter (set (.sym Dst32Rn group xmode) newval)) 2977 ) 2978 ) 2979) 2980 2981(dst32-Rn-direct-operand Unprefixed 4 QI) 2982(dst32-Rn-direct-operand Prefixed 12 QI) 2983(dst32-Rn-direct-operand Unprefixed 4 HI) 2984(dst32-Rn-direct-operand Prefixed 12 HI) 2985(dst32-Rn-direct-operand Unprefixed 4 SI) 2986(dst32-Rn-direct-operand Prefixed 12 SI) 2987 2988(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode) 2989 (begin 2990 (define-derived-operand 2991 (name (.sym dst32-Rn-direct- group - smode)) 2992 (comment (.str "m32c Rn direct destination " smode)) 2993 (attrs (machine 32)) 2994 (mode dmode) 2995 (args ((.sym Dst32Rn group smode))) 2996 (syntax (.str "$Dst32Rn" group smode)) 2997 (base-ifield (.sym f- base1 -6)) 2998 (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode))) 2999 (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1))) 3000 (getter (trunc smode (.sym Dst32Rn group smode))) 3001 (setter (set (.sym Dst32Rn group smode) newval)) 3002 ) 3003 ) 3004) 3005 3006(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI) 3007(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI) 3008 3009(define-derived-operand 3010 (name dst32-R3-direct-Unprefixed-HI) 3011 (comment "m32c R3 direct HI") 3012 (attrs (machine 32)) 3013 (mode HI) 3014 (args (R3)) 3015 (syntax "$R3") 3016 (base-ifield f-4-6) 3017 (encoding (+ (f-4-3 4) (f-8-2 #x1))) 3018 (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1))) 3019 (getter (trunc HI R3)) 3020 (setter (set R3 newval)) 3021) 3022;------------------------------------------------------------- 3023; An direct 3024;------------------------------------------------------------- 3025 3026(define-pmacro (dst16-An-direct-operand xmode) 3027 (begin 3028 (define-derived-operand 3029 (name (.sym dst16-An-direct- xmode)) 3030 (comment (.str "m16c An direct destination " xmode)) 3031 (attrs (machine 16)) 3032 (mode xmode) 3033 (args ((.sym Dst16An xmode))) 3034 (syntax (.str "$Dst16An" xmode)) 3035 (base-ifield f-12-4) 3036 (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode))) 3037 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) 3038 (getter (trunc xmode (.sym Dst16An xmode))) 3039 (setter (set (.sym Dst16An xmode) newval)) 3040 ) 3041 ) 3042) 3043 3044(dst16-An-direct-operand QI) 3045(dst16-An-direct-operand HI) 3046(dst16-An-direct-operand SI) 3047 3048(define-pmacro (dst32-An-direct-operand group base1 base2 xmode) 3049 (begin 3050 (define-derived-operand 3051 (name (.sym dst32-An-direct- group - xmode)) 3052 (comment (.str "m32c An direct destination " xmode)) 3053 (attrs (machine 32)) 3054 (mode xmode) 3055 (args ((.sym Dst32An group xmode))) 3056 (syntax (.str "$Dst32An" group xmode)) 3057 (base-ifield (.sym f- base1 -6)) 3058 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode))) 3059 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 3060 (getter (trunc xmode (.sym Dst32An group xmode))) 3061 (setter (set (.sym Dst32An group xmode) newval)) 3062 ) 3063 ) 3064) 3065 3066(dst32-An-direct-operand Unprefixed 4 8 QI) 3067(dst32-An-direct-operand Prefixed 12 16 QI) 3068(dst32-An-direct-operand Unprefixed 4 8 HI) 3069(dst32-An-direct-operand Prefixed 12 16 HI) 3070(dst32-An-direct-operand Unprefixed 4 8 SI) 3071(dst32-An-direct-operand Prefixed 12 16 SI) 3072 3073;------------------------------------------------------------- 3074; An indirect 3075;------------------------------------------------------------- 3076 3077(define-pmacro (dst16-An-indirect-operand xmode) 3078 (begin 3079 (define-derived-operand 3080 (name (.sym dst16-An-indirect- xmode)) 3081 (comment (.str "m16c An indirect destination " xmode)) 3082 (attrs (machine 16)) 3083 (mode xmode) 3084 (args (Dst16An)) 3085 (syntax "[$Dst16An]") 3086 (base-ifield f-12-4) 3087 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 3088 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3089 (getter (mem16 xmode Dst16An)) 3090 (setter (set (mem16 xmode Dst16An) newval)) 3091 ) 3092 ) 3093) 3094 3095(dst16-An-indirect-operand QI) 3096(dst16-An-indirect-operand HI) 3097(dst16-An-indirect-operand SI) 3098 3099(define-derived-operand 3100 (name dst16-An-indirect-Ext-QI) 3101 (comment "m16c An indirect destination QI") 3102 (attrs (machine 16)) 3103 (mode HI) 3104 (args (Dst16An)) 3105 (syntax "[$Dst16An]") 3106 (base-ifield f-12-4) 3107 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 3108 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3109 (getter (mem16 QI Dst16An)) 3110 (setter (set (mem16 HI Dst16An) newval)) 3111) 3112 3113(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode) 3114 (begin 3115 (define-derived-operand 3116 (name (.sym dst32-An-indirect- group - smode)) 3117 (comment (.str "m32c An indirect destination " smode)) 3118 (attrs (machine 32)) 3119 (mode dmode) 3120 (args ((.sym Dst32An group))) 3121 (syntax (.str "[$Dst32An" group "]")) 3122 (base-ifield (.sym f- base1 -6)) 3123 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group))) 3124 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 3125 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) 3126 (const 0))) 3127 (setter (c-call DFLT (.str "operand_setter_" dmode) newval 3128 (.sym Dst32An group) (const 0))) 3129; (getter (mem32 smode (.sym Dst32An group))) 3130; (setter (set (mem32 dmode (.sym Dst32An group)) newval)) 3131 ) 3132 ) 3133) 3134 3135(dst32-An-indirect-operand Unprefixed 4 8 QI QI) 3136(dst32-An-indirect-operand Prefixed 12 16 QI QI) 3137(dst32-An-indirect-operand Unprefixed 4 8 HI HI) 3138(dst32-An-indirect-operand Prefixed 12 16 HI HI) 3139(dst32-An-indirect-operand Unprefixed 4 8 SI SI) 3140(dst32-An-indirect-operand Prefixed 12 16 SI SI) 3141(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI) 3142(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI) 3143 3144;------------------------------------------------------------- 3145; dsp:d[r] relative 3146;------------------------------------------------------------- 3147 3148(define-pmacro (dst16-relative-operand offset xmode) 3149 (begin 3150 (define-derived-operand 3151 (name (.sym dst16- offset -8-SB-relative- xmode)) 3152 (comment (.str "m16c dsp:8[sb] relative destination " xmode)) 3153 (attrs (machine 16)) 3154 (mode xmode) 3155 (args ((.sym Dsp- offset -u8))) 3156 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3157 (base-ifield f-12-4) 3158 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) 3159 (ifield-assertion (eq f-12-4 #xA)) 3160 (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3161 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3162 ) 3163 (define-derived-operand 3164 (name (.sym dst16- offset -16-SB-relative- xmode)) 3165 (comment (.str "m16c dsp:16[sb] relative destination " xmode)) 3166 (attrs (machine 16)) 3167 (mode xmode) 3168 (args ((.sym Dsp- offset -u16))) 3169 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3170 (base-ifield f-12-4) 3171 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) 3172 (ifield-assertion (eq f-12-4 #xE)) 3173 (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3174 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3175 ) 3176 (define-derived-operand 3177 (name (.sym dst16- offset -8-FB-relative- xmode)) 3178 (comment (.str "m16c dsp:8[fb] relative destination " xmode)) 3179 (attrs (machine 16)) 3180 (mode xmode) 3181 (args ((.sym Dsp- offset -s8))) 3182 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3183 (base-ifield f-12-4) 3184 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) 3185 (ifield-assertion (eq f-12-4 #xB)) 3186 (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3187 (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3188 ) 3189 (define-derived-operand 3190 (name (.sym dst16- offset -8-An-relative- xmode)) 3191 (comment (.str "m16c dsp:8[An] relative destination " xmode)) 3192 (attrs (machine 16)) 3193 (mode xmode) 3194 (args (Dst16An (.sym Dsp- offset -u8))) 3195 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) 3196 (base-ifield f-12-4) 3197 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) 3198 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3199 (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An))) 3200 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) 3201 ) 3202 (define-derived-operand 3203 (name (.sym dst16- offset -16-An-relative- xmode)) 3204 (comment (.str "m16c dsp:16[An] relative destination " xmode)) 3205 (attrs (machine 16)) 3206 (mode xmode) 3207 (args (Dst16An (.sym Dsp- offset -u16))) 3208 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) 3209 (base-ifield f-12-4) 3210 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) 3211 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3212 (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) 3213 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) 3214 ) 3215 (define-derived-operand 3216 (name (.sym dst16- offset -20-An-relative- xmode)) 3217 (comment (.str "m16c dsp:20[An] relative destination " xmode)) 3218 (attrs (machine 16)) 3219 (mode xmode) 3220 (args (Dst16An (.sym Dsp- offset -u20))) 3221 (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) 3222 (base-ifield f-12-4) 3223 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) 3224 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3225 (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) 3226 (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) 3227 ) 3228 ) 3229) 3230 3231(dst16-relative-operand 16 QI) 3232(dst16-relative-operand 24 QI) 3233(dst16-relative-operand 32 QI) 3234(dst16-relative-operand 40 QI) 3235(dst16-relative-operand 48 QI) 3236(dst16-relative-operand 16 HI) 3237(dst16-relative-operand 24 HI) 3238(dst16-relative-operand 32 HI) 3239(dst16-relative-operand 40 HI) 3240(dst16-relative-operand 48 HI) 3241(dst16-relative-operand 16 SI) 3242(dst16-relative-operand 24 SI) 3243(dst16-relative-operand 32 SI) 3244(dst16-relative-operand 40 SI) 3245(dst16-relative-operand 48 SI) 3246 3247(define-pmacro (dst16-relative-Ext-operand offset smode dmode) 3248 (begin 3249 (define-derived-operand 3250 (name (.sym dst16- offset -8-SB-relative-Ext- smode)) 3251 (comment (.str "m16c dsp:8[sb] relative destination " smode)) 3252 (attrs (machine 16)) 3253 (mode dmode) 3254 (args ((.sym Dsp- offset -u8))) 3255 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3256 (base-ifield f-12-4) 3257 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) 3258 (ifield-assertion (eq f-12-4 #xA)) 3259 (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3260 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3261 ) 3262 (define-derived-operand 3263 (name (.sym dst16- offset -16-SB-relative-Ext- smode)) 3264 (comment (.str "m16c dsp:16[sb] relative destination " smode)) 3265 (attrs (machine 16)) 3266 (mode dmode) 3267 (args ((.sym Dsp- offset -u16))) 3268 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3269 (base-ifield f-12-4) 3270 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) 3271 (ifield-assertion (eq f-12-4 #xE)) 3272 (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3273 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3274 ) 3275 (define-derived-operand 3276 (name (.sym dst16- offset -8-FB-relative-Ext- smode)) 3277 (comment (.str "m16c dsp:8[fb] relative destination " smode)) 3278 (attrs (machine 16)) 3279 (mode dmode) 3280 (args ((.sym Dsp- offset -s8))) 3281 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3282 (base-ifield f-12-4) 3283 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) 3284 (ifield-assertion (eq f-12-4 #xB)) 3285 (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3286 (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3287 ) 3288 (define-derived-operand 3289 (name (.sym dst16- offset -8-An-relative-Ext- smode)) 3290 (comment (.str "m16c dsp:8[An] relative destination " smode)) 3291 (attrs (machine 16)) 3292 (mode dmode) 3293 (args (Dst16An (.sym Dsp- offset -u8))) 3294 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) 3295 (base-ifield f-12-4) 3296 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) 3297 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3298 (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An))) 3299 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) 3300 ) 3301 (define-derived-operand 3302 (name (.sym dst16- offset -16-An-relative-Ext- smode)) 3303 (comment (.str "m16c dsp:16[An] relative destination " smode)) 3304 (attrs (machine 16)) 3305 (mode dmode) 3306 (args (Dst16An (.sym Dsp- offset -u16))) 3307 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) 3308 (base-ifield f-12-4) 3309 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) 3310 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3311 (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An))) 3312 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) 3313 ) 3314 ) 3315) 3316 3317(dst16-relative-Ext-operand 16 QI HI) 3318 3319(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode) 3320 (begin 3321 (define-derived-operand 3322 (name (.sym dst32- offset -8-SB-relative- group - smode)) 3323 (comment (.str "m32c dsp:8[sb] relative destination " smode)) 3324 (attrs (machine 32)) 3325 (mode dmode) 3326 (args ((.sym Dsp- offset -u8))) 3327 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3328 (base-ifield (.sym f- base1 -6)) 3329 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) 3330 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 3331 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8))) 3332 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8))) 3333; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3334; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3335 ) 3336 (define-derived-operand 3337 (name (.sym dst32- offset -16-SB-relative- group - smode)) 3338 (comment (.str "m32c dsp:16[sb] relative destination " smode)) 3339 (attrs (machine 32)) 3340 (mode dmode) 3341 (args ((.sym Dsp- offset -u16))) 3342 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3343 (base-ifield (.sym f- base1 -6)) 3344 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) 3345 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 3346 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16))) 3347 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16))) 3348; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3349; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3350 ) 3351 (define-derived-operand 3352 (name (.sym dst32- offset -8-FB-relative- group - smode)) 3353 (comment (.str "m32c dsp:8[fb] relative destination " smode)) 3354 (attrs (machine 32)) 3355 (mode dmode) 3356 (args ((.sym Dsp- offset -s8))) 3357 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3358 (base-ifield (.sym f- base1 -6)) 3359 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) 3360 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 3361 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8))) 3362 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8))) 3363; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3364; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3365 ) 3366 (define-derived-operand 3367 (name (.sym dst32- offset -16-FB-relative- group - smode)) 3368 (comment (.str "m32c dsp:16[fb] relative destination " smode)) 3369 (attrs (machine 32)) 3370 (mode dmode) 3371 (args ((.sym Dsp- offset -s16))) 3372 (syntax (.str "${Dsp-" offset "-s16}[fb]")) 3373 (base-ifield (.sym f- base1 -6)) 3374 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) 3375 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 3376 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16))) 3377 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16))) 3378; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb)))) 3379; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) 3380 ) 3381 (define-derived-operand 3382 (name (.sym dst32- offset -8-An-relative- group - smode)) 3383 (comment (.str "m32c dsp:8[An] relative destination " smode)) 3384 (attrs (machine 32)) 3385 (mode dmode) 3386 (args ((.sym Dst32An group) (.sym Dsp- offset -u8))) 3387 (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]")) 3388 (base-ifield (.sym f- base1 -6)) 3389 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group))) 3390 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 3391 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8))) 3392 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8))) 3393; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group)))) 3394; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval)) 3395 ) 3396 (define-derived-operand 3397 (name (.sym dst32- offset -16-An-relative- group - smode)) 3398 (comment (.str "m32c dsp:16[An] relative destination " smode)) 3399 (attrs (machine 32)) 3400 (mode dmode) 3401 (args ((.sym Dst32An group) (.sym Dsp- offset -u16))) 3402 (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]")) 3403 (base-ifield (.sym f- base1 -6)) 3404 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group))) 3405 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 3406 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16))) 3407 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16))) 3408; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group)))) 3409; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval)) 3410 ) 3411 (define-derived-operand 3412 (name (.sym dst32- offset -24-An-relative- group - smode)) 3413 (comment (.str "m32c dsp:16[An] relative destination " smode)) 3414 (attrs (machine 32)) 3415 (mode dmode) 3416 (args ((.sym Dst32An group) (.sym Dsp- offset -u24))) 3417 (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]")) 3418 (base-ifield (.sym f- base1 -6)) 3419 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group))) 3420 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 3421 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24))) 3422 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24))) 3423; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group)))) 3424; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval)) 3425 ) 3426 ) 3427) 3428 3429(dst32-relative-operand 16 Unprefixed 4 8 QI QI) 3430(dst32-relative-operand 24 Unprefixed 4 8 QI QI) 3431(dst32-relative-operand 32 Unprefixed 4 8 QI QI) 3432(dst32-relative-operand 40 Unprefixed 4 8 QI QI) 3433(dst32-relative-operand 16 Unprefixed 4 8 HI HI) 3434(dst32-relative-operand 24 Unprefixed 4 8 HI HI) 3435(dst32-relative-operand 32 Unprefixed 4 8 HI HI) 3436(dst32-relative-operand 40 Unprefixed 4 8 HI HI) 3437(dst32-relative-operand 16 Unprefixed 4 8 SI SI) 3438(dst32-relative-operand 24 Unprefixed 4 8 SI SI) 3439(dst32-relative-operand 32 Unprefixed 4 8 SI SI) 3440(dst32-relative-operand 40 Unprefixed 4 8 SI SI) 3441 3442(dst32-relative-operand 24 Prefixed 12 16 QI QI) 3443(dst32-relative-operand 32 Prefixed 12 16 QI QI) 3444(dst32-relative-operand 40 Prefixed 12 16 QI QI) 3445(dst32-relative-operand 48 Prefixed 12 16 QI QI) 3446(dst32-relative-operand 24 Prefixed 12 16 HI HI) 3447(dst32-relative-operand 32 Prefixed 12 16 HI HI) 3448(dst32-relative-operand 40 Prefixed 12 16 HI HI) 3449(dst32-relative-operand 48 Prefixed 12 16 HI HI) 3450(dst32-relative-operand 24 Prefixed 12 16 SI SI) 3451(dst32-relative-operand 32 Prefixed 12 16 SI SI) 3452(dst32-relative-operand 40 Prefixed 12 16 SI SI) 3453(dst32-relative-operand 48 Prefixed 12 16 SI SI) 3454 3455(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI) 3456(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI) 3457 3458;------------------------------------------------------------- 3459; Absolute address 3460;------------------------------------------------------------- 3461 3462(define-pmacro (dst16-absolute offset xmode) 3463 (begin 3464 (define-derived-operand 3465 (name (.sym dst16- offset -16-absolute- xmode)) 3466 (comment (.str "m16c absolute address " xmode)) 3467 (attrs (machine 16)) 3468 (mode xmode) 3469 (args ((.sym Dsp- offset -u16))) 3470 (syntax (.str "${Dsp-" offset "-u16}")) 3471 (base-ifield f-12-4) 3472 (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16))) 3473 (ifield-assertion (eq f-12-4 #xF)) 3474 (getter (mem16 xmode (.sym Dsp- offset -u16))) 3475 (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval)) 3476 ) 3477 ) 3478) 3479 3480(dst16-absolute 16 QI) 3481(dst16-absolute 24 QI) 3482(dst16-absolute 32 QI) 3483(dst16-absolute 40 QI) 3484(dst16-absolute 48 QI) 3485(dst16-absolute 16 HI) 3486(dst16-absolute 24 HI) 3487(dst16-absolute 32 HI) 3488(dst16-absolute 40 HI) 3489(dst16-absolute 48 HI) 3490(dst16-absolute 16 SI) 3491(dst16-absolute 24 SI) 3492(dst16-absolute 32 SI) 3493(dst16-absolute 40 SI) 3494(dst16-absolute 48 SI) 3495 3496(define-derived-operand 3497 (name dst16-16-16-absolute-Ext-QI) 3498 (comment "m16c absolute address QI") 3499 (attrs (machine 16)) 3500 (mode HI) 3501 (args (Dsp-16-u16)) 3502 (syntax "${Dsp-16-u16}") 3503 (base-ifield f-12-4) 3504 (encoding (+ (f-12-4 #xF) Dsp-16-u16)) 3505 (ifield-assertion (eq f-12-4 #xF)) 3506 (getter (mem16 QI Dsp-16-u16)) 3507 (setter (set (mem16 HI Dsp-16-u16) newval)) 3508) 3509 3510(define-pmacro (dst32-absolute offset group base1 base2 smode dmode) 3511 (begin 3512 (define-derived-operand 3513 (name (.sym dst32- offset -16-absolute- group - smode)) 3514 (comment (.str "m32c absolute address " smode)) 3515 (attrs (machine 32)) 3516 (mode dmode) 3517 (args ((.sym Dsp- offset -u16))) 3518 (syntax (.str "${Dsp-" offset "-u16}")) 3519 (base-ifield (.sym f- base1 -6)) 3520 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 3521 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 3522 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16))) 3523 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16))) 3524; (getter (mem32 smode (.sym Dsp- offset -u16))) 3525; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval)) 3526 ) 3527 (define-derived-operand 3528 (name (.sym dst32- offset -24-absolute- group - smode)) 3529 (comment (.str "m32c absolute address " smode)) 3530 (attrs (machine 32)) 3531 (mode dmode) 3532 (args ((.sym Dsp- offset -u24))) 3533 (syntax (.str "${Dsp-" offset "-u24}")) 3534 (base-ifield (.sym f- base1 -6)) 3535 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 3536 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 3537 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24))) 3538 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24))) 3539; (getter (mem32 smode (.sym Dsp- offset -u24))) 3540; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval)) 3541 ) 3542 ) 3543) 3544 3545(dst32-absolute 16 Unprefixed 4 8 QI QI) 3546(dst32-absolute 24 Unprefixed 4 8 QI QI) 3547(dst32-absolute 32 Unprefixed 4 8 QI QI) 3548(dst32-absolute 40 Unprefixed 4 8 QI QI) 3549(dst32-absolute 16 Unprefixed 4 8 HI HI) 3550(dst32-absolute 24 Unprefixed 4 8 HI HI) 3551(dst32-absolute 32 Unprefixed 4 8 HI HI) 3552(dst32-absolute 40 Unprefixed 4 8 HI HI) 3553(dst32-absolute 16 Unprefixed 4 8 SI SI) 3554(dst32-absolute 24 Unprefixed 4 8 SI SI) 3555(dst32-absolute 32 Unprefixed 4 8 SI SI) 3556(dst32-absolute 40 Unprefixed 4 8 SI SI) 3557 3558(dst32-absolute 24 Prefixed 12 16 QI QI) 3559(dst32-absolute 32 Prefixed 12 16 QI QI) 3560(dst32-absolute 40 Prefixed 12 16 QI QI) 3561(dst32-absolute 48 Prefixed 12 16 QI QI) 3562(dst32-absolute 24 Prefixed 12 16 HI HI) 3563(dst32-absolute 32 Prefixed 12 16 HI HI) 3564(dst32-absolute 40 Prefixed 12 16 HI HI) 3565(dst32-absolute 48 Prefixed 12 16 HI HI) 3566(dst32-absolute 24 Prefixed 12 16 SI SI) 3567(dst32-absolute 32 Prefixed 12 16 SI SI) 3568(dst32-absolute 40 Prefixed 12 16 SI SI) 3569(dst32-absolute 48 Prefixed 12 16 SI SI) 3570 3571(dst32-absolute 16 ExtUnprefixed 4 8 QI HI) 3572(dst32-absolute 16 ExtUnprefixed 4 8 HI SI) 3573 3574;------------------------------------------------------------- 3575; An indirect indirect 3576;------------------------------------------------------------- 3577 3578;(define-pmacro (dst-An-indirect-indirect-operand xmode) 3579; (define-derived-operand 3580; (name (.sym dst32-An-indirect-indirect- xmode)) 3581; (comment (.str "m32c An indirect indirect destination " xmode)) 3582; (attrs (machine 32)) 3583; (mode xmode) 3584; (args (Dst32AnPrefixed)) 3585; (syntax (.str "[[$Dst32AnPrefixed]]")) 3586; (base-ifield f-12-6) 3587; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed)) 3588; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0))) 3589; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed))) 3590; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval)) 3591; ) 3592;) 3593 3594; (dst-An-indirect-indirect-operand QI) 3595; (dst-An-indirect-indirect-operand HI) 3596; (dst-An-indirect-indirect-operand SI) 3597 3598;------------------------------------------------------------- 3599; Relative indirect 3600;------------------------------------------------------------- 3601 3602(define-pmacro (dst-relative-indirect-operand offset xmode) 3603 (begin 3604; (define-derived-operand 3605; (name (.sym dst32- offset -8-SB-relative-indirect- xmode)) 3606; (comment (.str "m32c dsp:8[sb] relative destination " xmode)) 3607; (attrs (machine 32)) 3608; (mode xmode) 3609; (args ((.sym Dsp- offset -u8))) 3610; (syntax (.str "[${Dsp-" offset "-u8}[sb]]")) 3611; (base-ifield f-12-6) 3612; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8))) 3613; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2))) 3614; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb))))) 3615; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval)) 3616; ) 3617; (define-derived-operand 3618; (name (.sym dst32- offset -16-SB-relative-indirect- xmode)) 3619; (comment (.str "m32c dsp:16[sb] relative destination " xmode)) 3620; (attrs (machine 32)) 3621; (mode xmode) 3622; (args ((.sym Dsp- offset -u16))) 3623; (syntax (.str "[${Dsp-" offset "-u16}[sb]]")) 3624; (base-ifield f-12-6) 3625; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16))) 3626; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2))) 3627; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb))))) 3628; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval)) 3629; ) 3630; (define-derived-operand 3631; (name (.sym dst32- offset -8-FB-relative-indirect- xmode)) 3632; (comment (.str "m32c dsp:8[fb] relative destination " xmode)) 3633; (attrs (machine 32)) 3634; (mode xmode) 3635; (args ((.sym Dsp- offset -s8))) 3636; (syntax (.str "[${Dsp-" offset "-s8}[fb]]")) 3637; (base-ifield f-12-6) 3638; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8))) 3639; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3))) 3640; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb))))) 3641; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval)) 3642; ) 3643; (define-derived-operand 3644; (name (.sym dst32- offset -16-FB-relative-indirect- xmode)) 3645; (comment (.str "m32c dsp:16[fb] relative destination " xmode)) 3646; (attrs (machine 32)) 3647; (mode xmode) 3648; (args ((.sym Dsp- offset -s16))) 3649; (syntax (.str "[${Dsp-" offset "-s16}[fb]]")) 3650; (base-ifield f-12-6) 3651; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16))) 3652; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3))) 3653; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb))))) 3654; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval)) 3655; ) 3656; (define-derived-operand 3657; (name (.sym dst32- offset -8-An-relative-indirect- xmode)) 3658; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode)) 3659; (attrs (machine 32)) 3660; (mode xmode) 3661; (args (Dst32AnPrefixed (.sym Dsp- offset -u8))) 3662; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]")) 3663; (base-ifield f-12-6) 3664; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed)) 3665; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0))) 3666; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed)))) 3667; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval)) 3668; ) 3669; (define-derived-operand 3670; (name (.sym dst32- offset -16-An-relative-indirect- xmode)) 3671; (comment (.str "m32c dsp:16[An] relative destination " xmode)) 3672; (attrs (machine 32)) 3673; (mode xmode) 3674; (args (Dst32AnPrefixed (.sym Dsp- offset -u16))) 3675; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]")) 3676; (base-ifield f-12-6) 3677; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed)) 3678; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0))) 3679; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed)))) 3680; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval)) 3681; ) 3682; (define-derived-operand 3683; (name (.sym dst32- offset -24-An-relative-indirect- xmode)) 3684; (comment (.str "m32c dsp:24[An] relative destination " xmode)) 3685; (attrs (machine 32)) 3686; (mode xmode) 3687; (args (Dst32AnPrefixed (.sym Dsp- offset -u24))) 3688; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]")) 3689; (base-ifield f-12-6) 3690; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed)) 3691; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0))) 3692; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed)))) 3693; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval)) 3694; ) 3695 ) 3696) 3697 3698; (dst-relative-indirect-operand 24 QI) 3699; (dst-relative-indirect-operand 32 QI) 3700; (dst-relative-indirect-operand 40 QI) 3701; (dst-relative-indirect-operand 48 QI) 3702; (dst-relative-indirect-operand 24 HI) 3703; (dst-relative-indirect-operand 32 HI) 3704; (dst-relative-indirect-operand 40 HI) 3705; (dst-relative-indirect-operand 48 HI) 3706; (dst-relative-indirect-operand 24 SI) 3707; (dst-relative-indirect-operand 32 SI) 3708; (dst-relative-indirect-operand 40 SI) 3709; (dst-relative-indirect-operand 48 SI) 3710 3711;------------------------------------------------------------- 3712; Absolute indirect 3713;------------------------------------------------------------- 3714 3715(define-pmacro (dst-absolute-indirect offset xmode) 3716 (begin 3717; (define-derived-operand 3718; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode)) 3719; (comment (.str "m32c absolute indirect address " xmode)) 3720; (attrs (machine 32)) 3721; (mode xmode) 3722; (args ((.sym Dsp- offset -u16))) 3723; (syntax (.str "[${Dsp-" offset "-u16}]")) 3724; (base-ifield f-12-6) 3725; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16))) 3726; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3))) 3727; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) 3728; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) 3729; ) 3730; (define-derived-operand 3731; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode)) 3732; (comment (.str "m32c absolute indirect address " xmode)) 3733; (attrs (machine 32)) 3734; (mode xmode) 3735; (args ((.sym Dsp- offset -u24))) 3736; (syntax (.str "[${Dsp-" offset "-u24}]")) 3737; (base-ifield f-12-6) 3738; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24))) 3739; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2))) 3740; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) 3741; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) 3742; ) 3743 ) 3744) 3745 3746(dst-absolute-indirect 24 QI) 3747(dst-absolute-indirect 32 QI) 3748(dst-absolute-indirect 40 QI) 3749(dst-absolute-indirect 48 QI) 3750(dst-absolute-indirect 24 HI) 3751(dst-absolute-indirect 32 HI) 3752(dst-absolute-indirect 40 HI) 3753(dst-absolute-indirect 48 HI) 3754(dst-absolute-indirect 24 SI) 3755(dst-absolute-indirect 32 SI) 3756(dst-absolute-indirect 40 SI) 3757(dst-absolute-indirect 48 SI) 3758 3759;------------------------------------------------------------- 3760; Bit operands 3761;------------------------------------------------------------- 3762(define-pmacro (get-register-bit reg bitno) 3763 (and (srl reg bitno) 1) 3764) 3765 3766(define-pmacro (set-register-bit reg bitno value) 3767 (set reg (or (and reg (inv (sll 1 bitno))) 3768 (sll (and QI value 1) bitno))) 3769) 3770 3771(define-pmacro (get-memory-bit mach base bitno) 3772 (and (srl (mem-mach mach QI (add base (div bitno 8))) 3773 (mod bitno 8)) 3774 1) 3775) 3776 3777(define-pmacro (set-memory-bit mach base bitno value) 3778 (sequence ((USI addr)) 3779 (set addr (add base (div bitno 8))) 3780 (set (mem-mach mach QI addr) 3781 (or (and (mem-mach mach QI addr) 3782 (inv (sll 1 (mod bitno 8)))) 3783 (sll (and QI value 1) (mod bitno 8))))) 3784) 3785 3786;------------------------------------------------------------- 3787; Rn direct 3788;------------------------------------------------------------- 3789 3790(define-derived-operand 3791 (name bit16-Rn-direct) 3792 (comment "m16c Rn direct bit") 3793 (attrs (machine 16)) 3794 (mode BI) 3795 (args (Bitno16R Bit16Rn)) 3796 (syntax "$Bitno16R,$Bit16Rn") 3797 (base-ifield f-12-4) 3798 (encoding (+ (f-12-2 0) Bit16Rn Bitno16R)) 3799 (ifield-assertion (eq f-12-2 0)) 3800 (getter (get-register-bit Bit16Rn Bitno16R)) 3801 (setter (set-register-bit Bit16Rn Bitno16R newval)) 3802) 3803 3804(define-pmacro (bit32-Rn-direct-operand group base) 3805 (begin 3806 (define-derived-operand 3807 (name (.sym bit32-Rn-direct- group)) 3808 (comment "m32c Rn direct bit") 3809 (attrs (machine 32)) 3810 (mode BI) 3811 (args ((.sym Bitno32 group) (.sym Bit32Rn group))) 3812 (syntax (.str "$Bitno32" group ",$Bit32Rn" group)) 3813 (base-ifield (.sym f- base -6)) 3814 (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group))) 3815 (ifield-assertion (eq (.sym f- base -3) 4)) 3816 (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group))) 3817 (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval)) 3818 ) 3819 ) 3820) 3821 3822(bit32-Rn-direct-operand Unprefixed 4) 3823(bit32-Rn-direct-operand Prefixed 12) 3824 3825;------------------------------------------------------------- 3826; An direct 3827;------------------------------------------------------------- 3828 3829(define-derived-operand 3830 (name bit16-An-direct) 3831 (comment "m16c An direct bit") 3832 (attrs (machine 16)) 3833 (mode BI) 3834 (args (Bitno16R Bit16An)) 3835 (syntax "$Bitno16R,$Bit16An") 3836 (base-ifield f-12-4) 3837 (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R)) 3838 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) 3839 (getter (get-register-bit Bit16An Bitno16R)) 3840 (setter (set-register-bit Bit16An Bitno16R newval)) 3841) 3842 3843(define-pmacro (bit32-An-direct-operand group base1 base2) 3844 (begin 3845 (define-derived-operand 3846 (name (.sym bit32-An-direct- group)) 3847 (comment "m32c An direct bit") 3848 (attrs (machine 32)) 3849 (mode BI) 3850 (args ((.sym Bitno32 group) (.sym Bit32An group))) 3851 (syntax (.str "$Bitno32" group ",$Bit32An" group)) 3852 (base-ifield (.sym f- base1 -6)) 3853 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group))) 3854 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 3855 (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group))) 3856 (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval)) 3857 ) 3858 ) 3859) 3860 3861(bit32-An-direct-operand Unprefixed 4 8) 3862(bit32-An-direct-operand Prefixed 12 16) 3863 3864;------------------------------------------------------------- 3865; An indirect 3866;------------------------------------------------------------- 3867 3868(define-derived-operand 3869 (name bit16-An-indirect) 3870 (comment "m16c An indirect bit") 3871 (attrs (machine 16)) 3872 (mode BI) 3873 (args (Bit16An)) 3874 (syntax "[$Bit16An]") 3875 (base-ifield f-12-4) 3876 (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An)) 3877 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3878 (getter (get-memory-bit 16 0 Bit16An)) 3879 (setter (set-memory-bit 16 0 Bit16An newval)) 3880) 3881 3882(define-pmacro (bit32-An-indirect-operand group base1 base2) 3883 (begin 3884 (define-derived-operand 3885 (name (.sym bit32-An-indirect- group)) 3886 (comment "m32c An indirect destination ") 3887 (attrs (machine 32)) 3888 (mode BI) 3889 (args ((.sym Bitno32 group) (.sym Bit32An group))) 3890 (syntax (.str "$Bitno32" group ",[$Bit32An" group "]")) 3891 (base-ifield (.sym f- base1 -6)) 3892 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group))) 3893 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 3894 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group))) 3895 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval)) 3896 ) 3897 ) 3898) 3899 3900(bit32-An-indirect-operand Unprefixed 4 8) 3901(bit32-An-indirect-operand Prefixed 12 16) 3902 3903;------------------------------------------------------------- 3904; dsp:d[r] relative 3905;------------------------------------------------------------- 3906 3907(define-pmacro (bit16-relative-operand offset) 3908 (begin 3909 (define-derived-operand 3910 (name (.sym bit16- offset -8-SB-relative)) 3911 (comment (.str "m16c dsp:8[sb] relative bit " xmode)) 3912 (attrs (machine 16)) 3913 (mode BI) 3914 (args ((.sym BitBase16- offset -u8))) 3915 (syntax (.str "${BitBase16-" offset "-u8}[sb]")) 3916 (base-ifield f-12-4) 3917 (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8))) 3918 (ifield-assertion (eq f-12-4 #xA)) 3919 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8))) 3920 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval)) 3921 ) 3922 (define-derived-operand 3923 (name (.sym bit16- offset -16-SB-relative)) 3924 (comment (.str "m16c dsp:16[sb] relative bit " xmode)) 3925 (attrs (machine 16)) 3926 (mode BI) 3927 (args ((.sym BitBase16- offset -u16))) 3928 (syntax (.str "${BitBase16-" offset "-u16}[sb]")) 3929 (base-ifield f-12-4) 3930 (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16))) 3931 (ifield-assertion (eq f-12-4 #xE)) 3932 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16))) 3933 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval)) 3934 ) 3935 (define-derived-operand 3936 (name (.sym bit16- offset -8-FB-relative)) 3937 (comment (.str "m16c dsp:8[fb] relative bit " xmode)) 3938 (attrs (machine 16)) 3939 (mode BI) 3940 (args ((.sym BitBase16- offset -s8))) 3941 (syntax (.str "${BitBase16-" offset "-s8}[fb]")) 3942 (base-ifield f-12-4) 3943 (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8))) 3944 (ifield-assertion (eq f-12-4 #xB)) 3945 (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8))) 3946 (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval)) 3947 ) 3948 (define-derived-operand 3949 (name (.sym bit16- offset -8-An-relative)) 3950 (comment (.str "m16c dsp:8[An] relative bit " xmode)) 3951 (attrs (machine 16)) 3952 (mode BI) 3953 (args (Bit16An (.sym Dsp- offset -u8))) 3954 (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]")) 3955 (base-ifield f-12-4) 3956 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An)) 3957 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3958 (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An)) 3959 (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval)) 3960 ) 3961 (define-derived-operand 3962 (name (.sym bit16- offset -16-An-relative)) 3963 (comment (.str "m16c dsp:16[An] relative bit " xmode)) 3964 (attrs (machine 16)) 3965 (mode BI) 3966 (args (Bit16An (.sym Dsp- offset -u16))) 3967 (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]")) 3968 (base-ifield f-12-4) 3969 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An)) 3970 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3971 (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An)) 3972 (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval)) 3973 ) 3974 ) 3975) 3976 3977(bit16-relative-operand 16) 3978 3979(define-pmacro (bit32-relative-operand offset group base1 base2) 3980 (begin 3981 (define-derived-operand 3982 (name (.sym bit32- offset -11-SB-relative- group)) 3983 (comment "m32c bit,base:11[sb] relative bit") 3984 (attrs (machine 32)) 3985 (mode BI) 3986 (args ((.sym BitBase32- offset -u11- group))) 3987 (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]")) 3988 (base-ifield (.sym f- base1 -12)) 3989 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group))) 3990 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 3991 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group))) 3992 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval)) 3993 ) 3994 (define-derived-operand 3995 (name (.sym bit32- offset -19-SB-relative- group)) 3996 (comment "m32c bit,base:19[sb] relative bit") 3997 (attrs (machine 32)) 3998 (mode BI) 3999 (args ((.sym BitBase32- offset -u19- group))) 4000 (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]")) 4001 (base-ifield (.sym f- base1 -12)) 4002 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group))) 4003 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 4004 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group))) 4005 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval)) 4006 ) 4007 (define-derived-operand 4008 (name (.sym bit32- offset -11-FB-relative- group)) 4009 (comment "m32c bit,base:11[fb] relative bit") 4010 (attrs (machine 32)) 4011 (mode BI) 4012 (args ((.sym BitBase32- offset -s11- group))) 4013 (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]")) 4014 (base-ifield (.sym f- base1 -12)) 4015 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group))) 4016 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 4017 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group))) 4018 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval)) 4019 ) 4020 (define-derived-operand 4021 (name (.sym bit32- offset -19-FB-relative- group)) 4022 (comment "m32c bit,base:19[fb] relative bit") 4023 (attrs (machine 32)) 4024 (mode BI) 4025 (args ((.sym BitBase32- offset -s19- group))) 4026 (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]")) 4027 (base-ifield (.sym f- base1 -12)) 4028 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group))) 4029 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 4030 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group))) 4031 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval)) 4032 ) 4033 (define-derived-operand 4034 (name (.sym bit32- offset -11-An-relative- group)) 4035 (comment "m32c bit,base:11[An] relative bit") 4036 (attrs (machine 32)) 4037 (mode BI) 4038 (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group))) 4039 (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]")) 4040 (base-ifield (.sym f- base1 -12)) 4041 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group))) 4042 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 4043 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group))) 4044 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval)) 4045 ) 4046 (define-derived-operand 4047 (name (.sym bit32- offset -19-An-relative- group)) 4048 (comment "m32c bit,base:19[An] relative bit") 4049 (attrs (machine 32)) 4050 (mode BI) 4051 (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group))) 4052 (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]")) 4053 (base-ifield (.sym f- base1 -12)) 4054 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group))) 4055 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 4056 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group))) 4057 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval)) 4058 ) 4059 (define-derived-operand 4060 (name (.sym bit32- offset -27-An-relative- group)) 4061 (comment "m32c bit,base:27[An] relative bit") 4062 (attrs (machine 32)) 4063 (mode BI) 4064 (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group))) 4065 (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]")) 4066 (base-ifield (.sym f- base1 -12)) 4067 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group))) 4068 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 4069 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group))) 4070 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval)) 4071 ) 4072 ) 4073) 4074 4075(bit32-relative-operand 16 Unprefixed 4 8) 4076(bit32-relative-operand 24 Prefixed 12 16) 4077 4078(define-derived-operand 4079 (name bit16-11-SB-relative-S) 4080 (comment "m16c bit,base:11[sb] relative bit") 4081 (attrs (machine 16)) 4082 (mode BI) 4083 (args (BitBase16-8-u11-S)) 4084 (syntax "${BitBase16-8-u11-S}[sb]") 4085 (base-ifield (.sym f-5-3)) 4086 (encoding (+ BitBase16-8-u11-S)) 4087; (ifield-assertion (#t)) 4088 (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S)) 4089 (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval)) 4090) 4091 4092(define-derived-operand 4093 (name Rn16-push-S-derived) 4094 (comment "m16c r0[lh] for push,pop short version") 4095 (attrs (machine 16)) 4096 (mode QI) 4097 (args (Rn16-push-S)) 4098 (syntax "${Rn16-push-S}") 4099 (base-ifield (.sym f-4-1)) 4100 (encoding (+ Rn16-push-S)) 4101; (ifield-assertion (#t)) 4102 (getter (trunc QI Rn16-push-S)) 4103 (setter (set Rn16-push-S newval)) 4104) 4105 4106(define-derived-operand 4107 (name An16-push-S-derived) 4108 (comment "m16c r0[lh] for push,pop short version") 4109 (attrs (machine 16)) 4110 (mode HI) 4111 (args (An16-push-S)) 4112 (syntax "${An16-push-S}") 4113 (base-ifield (.sym f-4-1)) 4114 (encoding (+ An16-push-S)) 4115; (ifield-assertion (#t)) 4116 (getter (trunc QI An16-push-S)) 4117 (setter (set An16-push-S newval)) 4118) 4119 4120;------------------------------------------------------------- 4121; Absolute address 4122;------------------------------------------------------------- 4123 4124(define-pmacro (bit16-absolute offset) 4125 (begin 4126 (define-derived-operand 4127 (name (.sym bit16- offset -16-absolute)) 4128 (comment "m16c absolute address") 4129 (attrs (machine 16)) 4130 (mode BI) 4131 (args ((.sym BitBase16- offset -u16))) 4132 (syntax (.str "${BitBase16-" offset "-u16}")) 4133 (base-ifield f-12-4) 4134 (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16))) 4135 (ifield-assertion (eq f-12-4 #xF)) 4136 (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16))) 4137 (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval)) 4138 ) 4139 ) 4140) 4141 4142(bit16-absolute 16) 4143 4144(define-pmacro (bit32-absolute offset group base1 base2) 4145 (begin 4146 (define-derived-operand 4147 (name (.sym bit32- offset -19-absolute- group)) 4148 (comment "m32c absolute address bit") 4149 (attrs (machine 32)) 4150 (mode BI) 4151 (args ((.sym BitBase32- offset -u19- group))) 4152 (syntax (.str "${BitBase32-" offset "-u19-" group "}")) 4153 (base-ifield (.sym f- base1 -12)) 4154 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group))) 4155 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 4156 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group))) 4157 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval)) 4158 ) 4159 (define-derived-operand 4160 (name (.sym bit32- offset -27-absolute- group)) 4161 (comment "m32c absolute address bit") 4162 (attrs (machine 32)) 4163 (mode BI) 4164 (args ((.sym BitBase32- offset -u27- group))) 4165 (syntax (.str "${BitBase32-" offset "-u27-" group "}")) 4166 (base-ifield (.sym f- base1 -12)) 4167 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group))) 4168 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 4169 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group))) 4170 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval)) 4171 ) 4172 ) 4173) 4174 4175(bit32-absolute 16 Unprefixed 4 8) 4176(bit32-absolute 24 Prefixed 12 16) 4177 4178;------------------------------------------------------------- 4179; Destination operands for short fomat insns 4180;------------------------------------------------------------- 4181 4182(define-derived-operand 4183 (name dst16-3-S-R0l-direct-QI) 4184 (comment "m16c R0l direct QI") 4185 (attrs (machine 16)) 4186 (mode QI) 4187 (args (R0l)) 4188 (syntax "r0l") 4189 (base-ifield f-5-3) 4190 (encoding (+ (f-5-3 4))) 4191 (ifield-assertion (eq f-5-3 4)) 4192 (getter (trunc QI R0l)) 4193 (setter (set R0l newval)) 4194) 4195(define-derived-operand 4196 (name dst16-3-S-R0h-direct-QI) 4197 (comment "m16c R0h direct QI") 4198 (attrs (machine 16)) 4199 (mode QI) 4200 (args (R0h)) 4201 (syntax "r0h") 4202 (base-ifield f-5-3) 4203 (encoding (+ (f-5-3 3))) 4204 (ifield-assertion (eq f-5-3 3)) 4205 (getter (trunc QI R0h)) 4206 (setter (set R0h newval)) 4207) 4208(define-derived-operand 4209 (name dst16-3-S-8-8-SB-relative-QI) 4210 (comment "m16c SB relative QI") 4211 (attrs (machine 16)) 4212 (mode QI) 4213 (args (Dsp-8-u8)) 4214 (syntax "${Dsp-8-u8}[sb]") 4215 (base-ifield f-5-3) 4216 (encoding (+ (f-5-3 5) Dsp-8-u8)) 4217 (ifield-assertion (eq f-5-3 5)) 4218 (getter (mem16 QI (add Dsp-8-u8 (reg h-sb)))) 4219 (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval)) 4220) 4221(define-derived-operand 4222 (name dst16-3-S-8-8-FB-relative-QI) 4223 (comment "m16c FB relative QI") 4224 (attrs (machine 16)) 4225 (mode QI) 4226 (args (Dsp-8-s8)) 4227 (syntax "${Dsp-8-s8}[fb]") 4228 (base-ifield f-5-3) 4229 (encoding (+ (f-5-3 6) Dsp-8-s8)) 4230 (ifield-assertion (eq f-5-3 6)) 4231 (getter (mem16 QI (add Dsp-8-s8 (reg h-fb)))) 4232 (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval)) 4233) 4234(define-derived-operand 4235 (name dst16-3-S-8-16-absolute-QI) 4236 (comment "m16c absolute address QI") 4237 (attrs (machine 16)) 4238 (mode QI) 4239 (args (Dsp-8-u16)) 4240 (syntax "${Dsp-8-u16}") 4241 (base-ifield f-5-3) 4242 (encoding (+ (f-5-3 7) Dsp-8-u16)) 4243 (ifield-assertion (eq f-5-3 7)) 4244 (getter (mem16 QI Dsp-8-u16)) 4245 (setter (set (mem16 QI Dsp-8-u16) newval)) 4246) 4247(define-derived-operand 4248 (name dst16-3-S-16-8-SB-relative-QI) 4249 (comment "m16c SB relative QI") 4250 (attrs (machine 16)) 4251 (mode QI) 4252 (args (Dsp-16-u8)) 4253 (syntax "${Dsp-16-u8}[sb]") 4254 (base-ifield f-5-3) 4255 (encoding (+ (f-5-3 5) Dsp-16-u8)) 4256 (ifield-assertion (eq f-5-3 5)) 4257 (getter (mem16 QI (add Dsp-16-u8 (reg h-sb)))) 4258 (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval)) 4259) 4260(define-derived-operand 4261 (name dst16-3-S-16-8-FB-relative-QI) 4262 (comment "m16c FB relative QI") 4263 (attrs (machine 16)) 4264 (mode QI) 4265 (args (Dsp-16-s8)) 4266 (syntax "${Dsp-16-s8}[fb]") 4267 (base-ifield f-5-3) 4268 (encoding (+ (f-5-3 6) Dsp-16-s8)) 4269 (ifield-assertion (eq f-5-3 6)) 4270 (getter (mem16 QI (add Dsp-16-s8 (reg h-fb)))) 4271 (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval)) 4272) 4273(define-derived-operand 4274 (name dst16-3-S-16-16-absolute-QI) 4275 (comment "m16c absolute address QI") 4276 (attrs (machine 16)) 4277 (mode QI) 4278 (args (Dsp-16-u16)) 4279 (syntax "${Dsp-16-u16}") 4280 (base-ifield f-5-3) 4281 (encoding (+ (f-5-3 7) Dsp-16-u16)) 4282 (ifield-assertion (eq f-5-3 7)) 4283 (getter (mem16 QI Dsp-16-u16)) 4284 (setter (set (mem16 QI Dsp-16-u16) newval)) 4285) 4286(define-derived-operand 4287 (name srcdst16-r0l-r0h-S-derived) 4288 (comment "m16c r0l/r0h operand for short format insns") 4289 (attrs (machine 16)) 4290 (mode SI) 4291 (args (SrcDst16-r0l-r0h-S-normal)) 4292 (syntax "${SrcDst16-r0l-r0h-S-normal}") 4293 (base-ifield f-6-3) 4294 (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal)) 4295 (ifield-assertion (eq f-6-2 0)) 4296 (getter (trunc SI SrcDst16-r0l-r0h-S-normal)) 4297 (setter ()) ; no setter 4298) 4299(define-derived-operand 4300 (name dst32-2-S-R0l-direct-QI) 4301 (comment "m32c R0l direct QI") 4302 (attrs (machine 32)) 4303 (mode QI) 4304 (args (R0l)) 4305 (syntax "r0l") 4306 (base-ifield f-2-2) 4307 (encoding (+ (f-2-2 0))) 4308 (ifield-assertion (eq f-2-2 0)) 4309 (getter (trunc QI R0l)) 4310 (setter (set R0l newval)) 4311) 4312(define-derived-operand 4313 (name dst32-2-S-R0-direct-HI) 4314 (comment "m32c R0 direct HI") 4315 (attrs (machine 32)) 4316 (mode HI) 4317 (args (R0)) 4318 (syntax "r0") 4319 (base-ifield f-2-2) 4320 (encoding (+ (f-2-2 0))) 4321 (ifield-assertion (eq f-2-2 0)) 4322 (getter (trunc HI R0)) 4323 (setter (set R0 newval)) 4324) 4325(define-derived-operand 4326 (name dst32-1-S-A0-direct-HI) 4327 (comment "m32c A0 direct HI") 4328 (attrs (machine 32)) 4329 (mode HI) 4330 (args (A0)) 4331 (syntax "a0") 4332 (base-ifield f-7-1) 4333 (encoding (+ (f-7-1 0))) 4334 (ifield-assertion (eq f-7-1 0)) 4335 (getter (trunc HI A0)) 4336 (setter (set A0 newval)) 4337) 4338(define-derived-operand 4339 (name dst32-1-S-A1-direct-HI) 4340 (comment "m32c A1 direct HI") 4341 (attrs (machine 32)) 4342 (mode HI) 4343 (args (A1)) 4344 (syntax "a1") 4345 (base-ifield f-7-1) 4346 (encoding (+ (f-7-1 1))) 4347 (ifield-assertion (eq f-7-1 1)) 4348 (getter (trunc HI A1)) 4349 (setter (set A1 newval)) 4350) 4351(define-pmacro (dst32-2-S-operands xmode) 4352 (begin 4353 (define-derived-operand 4354 (name (.sym dst32-2-S-8-SB-relative- xmode)) 4355 (comment "m32c SB relative for short binary insns") 4356 (attrs (machine 32)) 4357 (mode xmode) 4358 (args (Dsp-8-u8)) 4359 (syntax "${Dsp-8-u8}[sb]") 4360 (base-ifield f-2-2) 4361 (encoding (+ (f-2-2 2) Dsp-8-u8)) 4362 (ifield-assertion (eq f-2-2 2)) 4363 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) 4364 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) 4365; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb)))) 4366; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval)) 4367 ) 4368 (define-derived-operand 4369 (name (.sym dst32-2-S-8-FB-relative- xmode)) 4370 (comment "m32c FB relative for short binary insns") 4371 (attrs (machine 32)) 4372 (mode xmode) 4373 (args (Dsp-8-s8)) 4374 (syntax "${Dsp-8-s8}[fb]") 4375 (base-ifield f-2-2) 4376 (encoding (+ (f-2-2 3) Dsp-8-s8)) 4377 (ifield-assertion (eq f-2-2 3)) 4378 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) 4379 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) 4380; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb)))) 4381; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval)) 4382 ) 4383 (define-derived-operand 4384 (name (.sym dst32-2-S-16-absolute- xmode)) 4385 (comment "m32c absolute address for short binary insns") 4386 (attrs (machine 32)) 4387 (mode xmode) 4388 (args (Dsp-8-u16)) 4389 (syntax "${Dsp-8-u16}") 4390 (base-ifield f-2-2) 4391 (encoding (+ (f-2-2 1) Dsp-8-u16)) 4392 (ifield-assertion (eq f-2-2 1)) 4393 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) 4394 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) 4395; (getter (mem32 xmode Dsp-8-u16)) 4396; (setter (set (mem32 xmode Dsp-8-u16) newval)) 4397 ) 4398; (define-derived-operand 4399; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode)) 4400; (comment "m32c SB relative for short binary insns") 4401; (attrs (machine 32)) 4402; (mode xmode) 4403; (args (Dsp-16-u8)) 4404; (syntax "[${Dsp-16-u8}[sb]]") 4405; (base-ifield f-10-2) 4406; (encoding (+ (f-10-2 2) Dsp-16-u8)) 4407; (ifield-assertion (eq f-10-2 2)) 4408; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb))))) 4409; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval)) 4410; ) 4411; (define-derived-operand 4412; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode)) 4413; (comment "m32c FB relative for short binary insns") 4414; (attrs (machine 32)) 4415; (mode xmode) 4416; (args (Dsp-16-s8)) 4417; (syntax "[${Dsp-16-s8}[fb]]") 4418; (base-ifield f-10-2) 4419; (encoding (+ (f-10-2 3) Dsp-16-s8)) 4420; (ifield-assertion (eq f-10-2 3)) 4421; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb))))) 4422; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval)) 4423; ) 4424; (define-derived-operand 4425; (name (.sym dst32-2-S-16-absolute-indirect- xmode)) 4426; (comment "m32c absolute address for short binary insns") 4427; (attrs (machine 32)) 4428; (mode xmode) 4429; (args (Dsp-16-u16)) 4430; (syntax "[${Dsp-16-u16}]") 4431; (base-ifield f-10-2) 4432; (encoding (+ (f-10-2 1) Dsp-16-u16)) 4433; (ifield-assertion (eq f-10-2 1)) 4434; (getter (mem32 xmode (indirect-addr Dsp-16-u16))) 4435; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval)) 4436; ) 4437 ) 4438) 4439 4440(dst32-2-S-operands QI) 4441(dst32-2-S-operands HI) 4442(dst32-2-S-operands SI) 4443 4444;============================================================= 4445; Anyof operands 4446;------------------------------------------------------------- 4447; Source operands with no additional fields 4448;------------------------------------------------------------- 4449 4450(define-pmacro (src16-basic-operand xmode) 4451 (begin 4452 (define-anyof-operand 4453 (name (.sym src16-basic- xmode)) 4454 (comment (.str "m16c source operand of size " xmode " with no additional fields")) 4455 (attrs (machine 16)) 4456 (mode xmode) 4457 (choices 4458 (.sym src16-Rn-direct- xmode) 4459 (.sym src16-An-direct- xmode) 4460 (.sym src16-An-indirect- xmode) 4461 ) 4462 ) 4463 ) 4464) 4465(src16-basic-operand QI) 4466(src16-basic-operand HI) 4467 4468(define-pmacro (src32-basic-operand xmode) 4469 (begin 4470 (define-anyof-operand 4471 (name (.sym src32-basic-Unprefixed- xmode)) 4472 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4473 (attrs (machine 32)) 4474 (mode xmode) 4475 (choices 4476 (.sym src32-Rn-direct-Unprefixed- xmode) 4477 (.sym src32-An-direct-Unprefixed- xmode) 4478 (.sym src32-An-indirect-Unprefixed- xmode) 4479 ) 4480 ) 4481 (define-anyof-operand 4482 (name (.sym src32-basic-Prefixed- xmode)) 4483 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4484 (attrs (machine 32)) 4485 (mode xmode) 4486 (choices 4487 (.sym src32-Rn-direct-Prefixed- xmode) 4488 (.sym src32-An-direct-Prefixed- xmode) 4489 (.sym src32-An-indirect-Prefixed- xmode) 4490 ) 4491 ) 4492; (define-anyof-operand 4493; (name (.sym src32-basic-indirect- xmode)) 4494; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields")) 4495; (attrs (machine 32)) 4496; (mode xmode) 4497; (choices 4498; (.sym src32-An-indirect-indirect- xmode) 4499; ) 4500; ) 4501 ) 4502) 4503 4504(src32-basic-operand QI) 4505(src32-basic-operand HI) 4506(src32-basic-operand SI) 4507 4508(define-anyof-operand 4509 (name src32-basic-ExtPrefixed-QI) 4510 (comment "m32c source operand of size QI with no additional fields") 4511 (attrs (machine 32)) 4512 (mode QI) 4513 (choices 4514 src32-Rn-direct-Prefixed-QI 4515 src32-An-indirect-Prefixed-QI 4516 ) 4517) 4518 4519;------------------------------------------------------------- 4520; Source operands with additional fields at offset 16 bits 4521;------------------------------------------------------------- 4522 4523(define-pmacro (src16-16-operand xmode) 4524 (begin 4525 (define-anyof-operand 4526 (name (.sym src16-16-8- xmode)) 4527 (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16")) 4528 (attrs (machine 16)) 4529 (mode xmode) 4530 (choices 4531 (.sym src16-16-8-An-relative- xmode) 4532 (.sym src16-16-8-SB-relative- xmode) 4533 (.sym src16-16-8-FB-relative- xmode) 4534 ) 4535 ) 4536 (define-anyof-operand 4537 (name (.sym src16-16-16- xmode)) 4538 (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4539 (attrs (machine 16)) 4540 (mode xmode) 4541 (choices 4542 (.sym src16-16-16-An-relative- xmode) 4543 (.sym src16-16-16-SB-relative- xmode) 4544 (.sym src16-16-16-absolute- xmode) 4545 ) 4546 ) 4547 ) 4548) 4549(src16-16-operand QI) 4550(src16-16-operand HI) 4551 4552(define-pmacro (src32-16-operand xmode) 4553 (begin 4554 (define-anyof-operand 4555 (name (.sym src32-16-8-Unprefixed- xmode)) 4556 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16")) 4557 (attrs (machine 32)) 4558 (mode xmode) 4559 (choices 4560 (.sym src32-16-8-An-relative-Unprefixed- xmode) 4561 (.sym src32-16-8-SB-relative-Unprefixed- xmode) 4562 (.sym src32-16-8-FB-relative-Unprefixed- xmode) 4563 ) 4564 ) 4565 (define-anyof-operand 4566 (name (.sym src32-16-16-Unprefixed- xmode)) 4567 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4568 (attrs (machine 32)) 4569 (mode xmode) 4570 (choices 4571 (.sym src32-16-16-An-relative-Unprefixed- xmode) 4572 (.sym src32-16-16-SB-relative-Unprefixed- xmode) 4573 (.sym src32-16-16-FB-relative-Unprefixed- xmode) 4574 (.sym src32-16-16-absolute-Unprefixed- xmode) 4575 ) 4576 ) 4577 (define-anyof-operand 4578 (name (.sym src32-16-24-Unprefixed- xmode)) 4579 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) 4580 (attrs (machine 32)) 4581 (mode xmode) 4582 (choices 4583 (.sym src32-16-24-An-relative-Unprefixed- xmode) 4584 (.sym src32-16-24-absolute-Unprefixed- xmode) 4585 ) 4586 ) 4587 ) 4588) 4589 4590(src32-16-operand QI) 4591(src32-16-operand HI) 4592(src32-16-operand SI) 4593 4594;------------------------------------------------------------- 4595; Source operands with additional fields at offset 24 bits 4596;------------------------------------------------------------- 4597 4598(define-pmacro (src-24-operand group xmode) 4599 (begin 4600 (define-anyof-operand 4601 (name (.sym src32-24-8- group - xmode)) 4602 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24")) 4603 (attrs (machine 32)) 4604 (mode xmode) 4605 (choices 4606 (.sym src32-24-8-An-relative- group - xmode) 4607 (.sym src32-24-8-SB-relative- group - xmode) 4608 (.sym src32-24-8-FB-relative- group - xmode) 4609 ) 4610 ) 4611 (define-anyof-operand 4612 (name (.sym src32-24-16- group - xmode)) 4613 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4614 (attrs (machine 32)) 4615 (mode xmode) 4616 (choices 4617 (.sym src32-24-16-An-relative- group - xmode) 4618 (.sym src32-24-16-SB-relative- group - xmode) 4619 (.sym src32-24-16-FB-relative- group - xmode) 4620 (.sym src32-24-16-absolute- group - xmode) 4621 ) 4622 ) 4623 (define-anyof-operand 4624 (name (.sym src32-24-24- group - xmode)) 4625 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) 4626 (attrs (machine 32)) 4627 (mode xmode) 4628 (choices 4629 (.sym src32-24-24-An-relative- group - xmode) 4630 (.sym src32-24-24-absolute- group - xmode) 4631 ) 4632 ) 4633 ) 4634) 4635 4636(src-24-operand Prefixed QI) 4637(src-24-operand Prefixed HI) 4638(src-24-operand Prefixed SI) 4639 4640(define-pmacro (src-24-indirect-operand xmode) 4641 (begin 4642; (define-anyof-operand 4643; (name (.sym src32-24-8-indirect- xmode)) 4644; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4645; (attrs (machine 32)) 4646; (mode xmode) 4647; (choices 4648; (.sym src32-24-8-An-relative-indirect- xmode) 4649; (.sym src32-24-8-SB-relative-indirect- xmode) 4650; (.sym src32-24-8-FB-relative-indirect- xmode) 4651; ) 4652; ) 4653; (define-anyof-operand 4654; (name (.sym src32-24-16-indirect- xmode)) 4655; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4656; (attrs (machine 32)) 4657; (mode xmode) 4658; (choices 4659; (.sym src32-24-16-An-relative-indirect- xmode) 4660; (.sym src32-24-16-SB-relative-indirect- xmode) 4661; (.sym src32-24-16-FB-relative-indirect- xmode) 4662; ) 4663; ) 4664; (define-anyof-operand 4665; (name (.sym src32-24-24-indirect- xmode)) 4666; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4667; (attrs (machine 32)) 4668; (mode xmode) 4669; (choices 4670; (.sym src32-24-24-An-relative-indirect- xmode) 4671; ) 4672; ) 4673; (define-anyof-operand 4674; (name (.sym src32-24-16-absolute-indirect- xmode)) 4675; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect")) 4676; (attrs (machine 32)) 4677; (mode xmode) 4678; (choices 4679; (.sym src32-24-16-absolute-indirect-derived- xmode) 4680; ) 4681; ) 4682; (define-anyof-operand 4683; (name (.sym src32-24-24-absolute-indirect- xmode)) 4684; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect")) 4685; (attrs (machine 32)) 4686; (mode xmode) 4687; (choices 4688; (.sym src32-24-24-absolute-indirect-derived- xmode) 4689; ) 4690; ) 4691 ) 4692) 4693 4694; (src-24-indirect-operand QI) 4695; (src-24-indirect-operand HI) 4696; (src-24-indirect-operand SI) 4697 4698;------------------------------------------------------------- 4699; Destination operands with no additional fields 4700;------------------------------------------------------------- 4701 4702(define-pmacro (dst16-basic-operand xmode) 4703 (begin 4704 (define-anyof-operand 4705 (name (.sym dst16-basic- xmode)) 4706 (comment (.str "m16c destination operand of size " xmode " with no additional fields")) 4707 (attrs (machine 16)) 4708 (mode xmode) 4709 (choices 4710 (.sym dst16-Rn-direct- xmode) 4711 (.sym dst16-An-direct- xmode) 4712 (.sym dst16-An-indirect- xmode) 4713 ) 4714 ) 4715 ) 4716) 4717 4718(dst16-basic-operand QI) 4719(dst16-basic-operand HI) 4720(dst16-basic-operand SI) 4721 4722(define-pmacro (dst32-basic-operand xmode) 4723 (begin 4724 (define-anyof-operand 4725 (name (.sym dst32-basic-Unprefixed- xmode)) 4726 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4727 (attrs (machine 32)) 4728 (mode xmode) 4729 (choices 4730 (.sym dst32-Rn-direct-Unprefixed- xmode) 4731 (.sym dst32-An-direct-Unprefixed- xmode) 4732 (.sym dst32-An-indirect-Unprefixed- xmode) 4733 ) 4734 ) 4735 (define-anyof-operand 4736 (name (.sym dst32-basic-Prefixed- xmode)) 4737 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4738 (attrs (machine 32)) 4739 (mode xmode) 4740 (choices 4741 (.sym dst32-Rn-direct-Prefixed- xmode) 4742 (.sym dst32-An-direct-Prefixed- xmode) 4743 (.sym dst32-An-indirect-Prefixed- xmode) 4744 ) 4745 ) 4746 ) 4747) 4748 4749(dst32-basic-operand QI) 4750(dst32-basic-operand HI) 4751(dst32-basic-operand SI) 4752 4753;------------------------------------------------------------- 4754; Destination operands with possible additional fields at offset 16 bits 4755;------------------------------------------------------------- 4756 4757(define-pmacro (dst16-16-operand xmode) 4758 (begin 4759 (define-anyof-operand 4760 (name (.sym dst16-16- xmode)) 4761 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4762 (attrs (machine 16)) 4763 (mode xmode) 4764 (choices 4765 (.sym dst16-Rn-direct- xmode) 4766 (.sym dst16-An-direct- xmode) 4767 (.sym dst16-An-indirect- xmode) 4768 (.sym dst16-16-8-An-relative- xmode) 4769 (.sym dst16-16-16-An-relative- xmode) 4770 (.sym dst16-16-8-SB-relative- xmode) 4771 (.sym dst16-16-16-SB-relative- xmode) 4772 (.sym dst16-16-8-FB-relative- xmode) 4773 (.sym dst16-16-16-absolute- xmode) 4774 ) 4775 ) 4776 (define-anyof-operand 4777 (name (.sym dst16-16-8- xmode)) 4778 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4779 (attrs (machine 16)) 4780 (mode xmode) 4781 (choices 4782 (.sym dst16-16-8-An-relative- xmode) 4783 (.sym dst16-16-8-SB-relative- xmode) 4784 (.sym dst16-16-8-FB-relative- xmode) 4785 ) 4786 ) 4787 (define-anyof-operand 4788 (name (.sym dst16-16-16- xmode)) 4789 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4790 (attrs (machine 16)) 4791 (mode xmode) 4792 (choices 4793 (.sym dst16-16-16-An-relative- xmode) 4794 (.sym dst16-16-16-SB-relative- xmode) 4795 (.sym dst16-16-16-absolute- xmode) 4796 ) 4797 ) 4798 (define-anyof-operand 4799 (name (.sym dst16-16-16sa- xmode)) 4800 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4801 (attrs (machine 16)) 4802 (mode xmode) 4803 (choices 4804 (.sym dst16-16-16-SB-relative- xmode) 4805 (.sym dst16-16-16-absolute- xmode) 4806 ) 4807 ) 4808 (define-anyof-operand 4809 (name (.sym dst16-16-20ar- xmode)) 4810 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4811 (attrs (machine 16)) 4812 (mode xmode) 4813 (choices 4814 (.sym dst16-16-20-An-relative- xmode) 4815 ) 4816 ) 4817 ) 4818) 4819 4820(dst16-16-operand QI) 4821(dst16-16-operand HI) 4822(dst16-16-operand SI) 4823 4824(define-anyof-operand 4825 (name dst16-16-Ext-QI) 4826 (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16") 4827 (attrs (machine 16)) 4828 (mode QI) 4829 (choices 4830 dst16-Rn-direct-Ext-QI 4831 dst16-An-indirect-Ext-QI 4832 dst16-16-8-An-relative-Ext-QI 4833 dst16-16-16-An-relative-Ext-QI 4834 dst16-16-8-SB-relative-Ext-QI 4835 dst16-16-16-SB-relative-Ext-QI 4836 dst16-16-8-FB-relative-Ext-QI 4837 dst16-16-16-absolute-Ext-QI 4838 ) 4839) 4840 4841(define-derived-operand 4842 (name dst16-An-indirect-Mova-HI) 4843 (comment "m16c addressof An indirect destination HI") 4844 (attrs (ISA m16c)) 4845 (mode HI) 4846 (args (Dst16An)) 4847 (syntax "[$Dst16An]") 4848 (base-ifield f-12-4) 4849 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 4850 (ifield-assertion 4851 (andif (eq f-12-2 1) (eq f-14-1 1))) 4852 (getter Dst16An) 4853 (setter (nop)) 4854 ) 4855 4856(define-derived-operand 4857 (name dst16-16-8-An-relative-Mova-HI) 4858 (comment 4859 "m16c addressof dsp:8[An] relative destination HI") 4860 (attrs (ISA m16c)) 4861 (mode HI) 4862 (args (Dst16An Dsp-16-u8)) 4863 (syntax "${Dsp-16-u8}[$Dst16An]") 4864 (base-ifield f-12-4) 4865 (encoding 4866 (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An)) 4867 (ifield-assertion 4868 (andif (eq f-12-2 2) (eq f-14-1 0))) 4869 (getter (add Dsp-16-u8 Dst16An)) 4870 (setter (nop)) 4871) 4872(define-derived-operand 4873 (name dst16-16-16-An-relative-Mova-HI) 4874 (comment 4875 "m16c addressof dsp:16[An] relative destination HI") 4876 (attrs (ISA m16c)) 4877 (mode HI) 4878 (args (Dst16An Dsp-16-u16)) 4879 (syntax "${Dsp-16-u16}[$Dst16An]") 4880 (base-ifield f-12-4) 4881 (encoding 4882 (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An)) 4883 (ifield-assertion 4884 (andif (eq f-12-2 3) (eq f-14-1 0))) 4885 (getter (add Dsp-16-u16 Dst16An)) 4886 (setter (nop)) 4887 ) 4888(define-derived-operand 4889 (name dst16-16-8-SB-relative-Mova-HI) 4890 (comment 4891 "m16c addressof dsp:8[sb] relative destination HI") 4892 (attrs (ISA m16c)) 4893 (mode HI) 4894 (args (Dsp-16-u8)) 4895 (syntax "${Dsp-16-u8}[sb]") 4896 (base-ifield f-12-4) 4897 (encoding (+ (f-12-4 10) Dsp-16-u8)) 4898 (ifield-assertion (eq f-12-4 10)) 4899 (getter (add Dsp-16-u8 (reg h-sb))) 4900 (setter (nop)) 4901) 4902(define-derived-operand 4903 (name dst16-16-16-SB-relative-Mova-HI) 4904 (comment 4905 "m16c addressof dsp:16[sb] relative destination HI") 4906 (attrs (ISA m16c)) 4907 (mode HI) 4908 (args (Dsp-16-u16)) 4909 (syntax "${Dsp-16-u16}[sb]") 4910 (base-ifield f-12-4) 4911 (encoding (+ (f-12-4 14) Dsp-16-u16)) 4912 (ifield-assertion (eq f-12-4 14)) 4913 (getter (add Dsp-16-u16 (reg h-sb))) 4914 (setter (nop)) 4915 ) 4916(define-derived-operand 4917 (name dst16-16-8-FB-relative-Mova-HI) 4918 (comment 4919 "m16c addressof dsp:8[fb] relative destination HI") 4920 (attrs (ISA m16c)) 4921 (mode HI) 4922 (args (Dsp-16-s8)) 4923 (syntax "${Dsp-16-s8}[fb]") 4924 (base-ifield f-12-4) 4925 (encoding (+ (f-12-4 11) Dsp-16-s8)) 4926 (ifield-assertion (eq f-12-4 11)) 4927 (getter (add Dsp-16-s8 (reg h-fb))) 4928 (setter (nop)) 4929 ) 4930(define-derived-operand 4931 (name dst16-16-16-absolute-Mova-HI) 4932 (comment "m16c addressof absolute address HI") 4933 (attrs (ISA m16c)) 4934 (mode HI) 4935 (args (Dsp-16-u16)) 4936 (syntax "${Dsp-16-u16}") 4937 (base-ifield f-12-4) 4938 (encoding (+ (f-12-4 15) Dsp-16-u16)) 4939 (ifield-assertion (eq f-12-4 15)) 4940 (getter Dsp-16-u16) 4941 (setter (nop)) 4942 ) 4943 4944(define-anyof-operand 4945 (name dst16-16-Mova-HI) 4946 (comment "m16c addressof destination operand of size HI with additional fields at offset 16") 4947 (attrs (machine 16)) 4948 (mode HI) 4949 (choices 4950 dst16-An-indirect-Mova-HI 4951 dst16-16-8-An-relative-Mova-HI 4952 dst16-16-16-An-relative-Mova-HI 4953 dst16-16-8-SB-relative-Mova-HI 4954 dst16-16-16-SB-relative-Mova-HI 4955 dst16-16-8-FB-relative-Mova-HI 4956 dst16-16-16-absolute-Mova-HI 4957 ) 4958) 4959 4960(define-derived-operand 4961 (name dst32-An-indirect-Unprefixed-Mova-SI) 4962 (comment "m32c addressof An indirect destination SI") 4963 (attrs (ISA m32c)) 4964 (mode SI) 4965 (args (Dst32AnUnprefixed)) 4966 (syntax "[$Dst32AnUnprefixed]") 4967 (base-ifield f-4-6) 4968 (encoding 4969 (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed)) 4970 (ifield-assertion 4971 (andif (eq f-4-3 0) (eq f-8-1 0))) 4972 (getter Dst32AnUnprefixed) 4973 (setter (nop)) 4974 ) 4975 4976(define-derived-operand 4977 (name dst32-16-8-An-relative-Unprefixed-Mova-SI) 4978 (comment "m32c addressof dsp:8[An] relative destination SI") 4979 (attrs (ISA m32c)) 4980 (mode SI) 4981 (args (Dst32AnUnprefixed Dsp-16-u8)) 4982 (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]") 4983 (base-ifield f-4-6) 4984 (encoding 4985 (+ (f-4-3 1) 4986 (f-8-1 0) 4987 Dsp-16-u8 4988 Dst32AnUnprefixed)) 4989 (ifield-assertion 4990 (andif (eq f-4-3 1) (eq f-8-1 0))) 4991 (getter (add Dsp-16-u8 Dst32AnUnprefixed)) 4992 (setter (nop)) 4993) 4994 4995(define-derived-operand 4996 (name dst32-16-16-An-relative-Unprefixed-Mova-SI) 4997 (comment 4998 "m32c addressof dsp:16[An] relative destination SI") 4999 (attrs (ISA m32c)) 5000 (mode SI) 5001 (args (Dst32AnUnprefixed Dsp-16-u16)) 5002 (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]") 5003 (base-ifield f-4-6) 5004 (encoding 5005 (+ (f-4-3 2) 5006 (f-8-1 0) 5007 Dsp-16-u16 5008 Dst32AnUnprefixed)) 5009 (ifield-assertion 5010 (andif (eq f-4-3 2) (eq f-8-1 0))) 5011 (getter (add Dsp-16-u16 Dst32AnUnprefixed)) 5012 (setter (nop)) 5013 ) 5014 5015(define-derived-operand 5016 (name dst32-16-24-An-relative-Unprefixed-Mova-SI) 5017 (comment "addressof m32c dsp:16[An] relative destination SI") 5018 (attrs (ISA m32c)) 5019 (mode SI) 5020 (args (Dst32AnUnprefixed Dsp-16-u24)) 5021 (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]") 5022 (base-ifield f-4-6) 5023 (encoding 5024 (+ (f-4-3 3) 5025 (f-8-1 0) 5026 Dsp-16-u24 5027 Dst32AnUnprefixed)) 5028 (ifield-assertion 5029 (andif (eq f-4-3 3) (eq f-8-1 0))) 5030 (getter (add Dsp-16-u24 Dst32AnUnprefixed)) 5031 (setter (nop)) 5032 ) 5033 5034(define-derived-operand 5035 (name dst32-16-8-SB-relative-Unprefixed-Mova-SI) 5036 (comment "m32c addressof dsp:8[sb] relative destination SI") 5037 (attrs (ISA m32c)) 5038 (mode SI) 5039 (args (Dsp-16-u8)) 5040 (syntax "${Dsp-16-u8}[sb]") 5041 (base-ifield f-4-6) 5042 (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8)) 5043 (ifield-assertion 5044 (andif (eq f-4-3 1) (eq f-8-2 2))) 5045 (getter (add Dsp-16-u8 (reg h-sb))) 5046 (setter (nop)) 5047 ) 5048 5049(define-derived-operand 5050 (name dst32-16-16-SB-relative-Unprefixed-Mova-SI) 5051 (comment "m32c addressof dsp:16[sb] relative destination SI") 5052 (attrs (ISA m32c)) 5053 (mode SI) 5054 (args (Dsp-16-u16)) 5055 (syntax "${Dsp-16-u16}[sb]") 5056 (base-ifield f-4-6) 5057 (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16)) 5058 (ifield-assertion 5059 (andif (eq f-4-3 2) (eq f-8-2 2))) 5060 (getter (add Dsp-16-u16 (reg h-sb))) 5061 (setter (nop)) 5062 ) 5063 5064(define-derived-operand 5065 (name dst32-16-8-FB-relative-Unprefixed-Mova-SI) 5066 (comment "m32c addressof dsp:8[fb] relative destination SI") 5067 (attrs (ISA m32c)) 5068 (mode SI) 5069 (args (Dsp-16-s8)) 5070 (syntax "${Dsp-16-s8}[fb]") 5071 (base-ifield f-4-6) 5072 (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8)) 5073 (ifield-assertion 5074 (andif (eq f-4-3 1) (eq f-8-2 3))) 5075 (getter (add Dsp-16-s8 (reg h-fb))) 5076 (setter (nop)) 5077 ) 5078 5079(define-derived-operand 5080 (name dst32-16-16-FB-relative-Unprefixed-Mova-SI) 5081 (comment "m32c addressof dsp:16[fb] relative destination SI") 5082 (attrs (ISA m32c)) 5083 (mode SI) 5084 (args (Dsp-16-s16)) 5085 (syntax "${Dsp-16-s16}[fb]") 5086 (base-ifield f-4-6) 5087 (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16)) 5088 (ifield-assertion 5089 (andif (eq f-4-3 2) (eq f-8-2 3))) 5090 (getter (add Dsp-16-s16 (reg h-fb))) 5091 (setter (nop)) 5092 ) 5093 5094(define-derived-operand 5095 (name dst32-16-16-absolute-Unprefixed-Mova-SI) 5096 (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) 5097 (mode SI) 5098 (args (Dsp-16-u16)) 5099 (syntax "${Dsp-16-u16}") 5100 (base-ifield f-4-6) 5101 (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16)) 5102 (ifield-assertion 5103 (andif (eq f-4-3 3) (eq f-8-2 3))) 5104 (getter Dsp-16-u16) 5105 (setter (nop)) 5106 ) 5107 5108(define-derived-operand 5109 (name dst32-16-24-absolute-Unprefixed-Mova-SI) 5110 (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) 5111 (mode SI) 5112 (args (Dsp-16-u24)) 5113 (syntax "${Dsp-16-u24}") 5114 (base-ifield f-4-6) 5115 (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24)) 5116 (ifield-assertion 5117 (andif (eq f-4-3 3) (eq f-8-2 2))) 5118 (getter Dsp-16-u24) 5119 (setter (nop)) 5120 ) 5121 5122(define-anyof-operand 5123 (name dst32-16-Unprefixed-Mova-SI) 5124 (comment 5125 "m32c addressof destination operand of size SI with additional fields at offset 16") 5126 (attrs (ISA m32c)) 5127 (mode SI) 5128 (choices 5129 dst32-An-indirect-Unprefixed-Mova-SI 5130 dst32-16-8-An-relative-Unprefixed-Mova-SI 5131 dst32-16-16-An-relative-Unprefixed-Mova-SI 5132 dst32-16-24-An-relative-Unprefixed-Mova-SI 5133 dst32-16-8-SB-relative-Unprefixed-Mova-SI 5134 dst32-16-16-SB-relative-Unprefixed-Mova-SI 5135 dst32-16-8-FB-relative-Unprefixed-Mova-SI 5136 dst32-16-16-FB-relative-Unprefixed-Mova-SI 5137 dst32-16-16-absolute-Unprefixed-Mova-SI 5138 dst32-16-24-absolute-Unprefixed-Mova-SI)) 5139 5140(define-pmacro (dst32-16-operand xmode) 5141 (begin 5142 (define-anyof-operand 5143 (name (.sym dst32-16-Unprefixed- xmode)) 5144 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5145 (attrs (machine 32)) 5146 (mode xmode) 5147 (choices 5148 (.sym dst32-Rn-direct-Unprefixed- xmode) 5149 (.sym dst32-An-direct-Unprefixed- xmode) 5150 (.sym dst32-An-indirect-Unprefixed- xmode) 5151 (.sym dst32-16-8-An-relative-Unprefixed- xmode) 5152 (.sym dst32-16-16-An-relative-Unprefixed- xmode) 5153 (.sym dst32-16-24-An-relative-Unprefixed- xmode) 5154 (.sym dst32-16-8-SB-relative-Unprefixed- xmode) 5155 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5156 (.sym dst32-16-8-FB-relative-Unprefixed- xmode) 5157 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5158 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5159 (.sym dst32-16-24-absolute-Unprefixed- xmode) 5160 ) 5161 ) 5162 (define-anyof-operand 5163 (name (.sym dst32-16-8-Unprefixed- xmode)) 5164 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5165 (attrs (machine 32)) 5166 (mode xmode) 5167 (choices 5168 (.sym dst32-16-8-An-relative-Unprefixed- xmode) 5169 (.sym dst32-16-8-SB-relative-Unprefixed- xmode) 5170 (.sym dst32-16-8-FB-relative-Unprefixed- xmode) 5171 ) 5172 ) 5173 (define-anyof-operand 5174 (name (.sym dst32-16-16-Unprefixed- xmode)) 5175 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5176 (attrs (machine 32)) 5177 (mode xmode) 5178 (choices 5179 (.sym dst32-16-16-An-relative-Unprefixed- xmode) 5180 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5181 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5182 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5183 ) 5184 ) 5185 (define-anyof-operand 5186 (name (.sym dst32-16-16sa-Unprefixed- xmode)) 5187 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5188 (attrs (machine 32)) 5189 (mode xmode) 5190 (choices 5191 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5192 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5193 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5194 ) 5195 ) 5196 (define-anyof-operand 5197 (name (.sym dst32-16-24-Unprefixed- xmode)) 5198 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5199 (attrs (machine 32)) 5200 (mode xmode) 5201 (choices 5202 (.sym dst32-16-24-An-relative-Unprefixed- xmode) 5203 (.sym dst32-16-24-absolute-Unprefixed- xmode) 5204 ) 5205 ) 5206 ) 5207) 5208 5209(dst32-16-operand QI) 5210(dst32-16-operand HI) 5211(dst32-16-operand SI) 5212 5213(define-pmacro (dst32-16-Ext-operand smode dmode) 5214 (begin 5215 (define-anyof-operand 5216 (name (.sym dst32-16-ExtUnprefixed- smode)) 5217 (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16")) 5218 (attrs (machine 32)) 5219 (mode dmode) 5220 (choices 5221 (.sym dst32-Rn-direct-ExtUnprefixed- smode) 5222 (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version 5223 (.sym dst32-An-indirect-ExtUnprefixed- smode) 5224 (.sym dst32-16-8-An-relative-ExtUnprefixed- smode) 5225 (.sym dst32-16-16-An-relative-ExtUnprefixed- smode) 5226 (.sym dst32-16-24-An-relative-ExtUnprefixed- smode) 5227 (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode) 5228 (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode) 5229 (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode) 5230 (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode) 5231 (.sym dst32-16-16-absolute-ExtUnprefixed- smode) 5232 (.sym dst32-16-24-absolute-ExtUnprefixed- smode) 5233 ) 5234 ) 5235 ) 5236) 5237 5238(dst32-16-Ext-operand QI HI) 5239(dst32-16-Ext-operand HI SI) 5240 5241(define-anyof-operand 5242 (name dst32-16-Unprefixed-Mulex-HI) 5243 (comment "m32c destination operand of size HI with additional fields at offset 16") 5244 (attrs (machine 32)) 5245 (mode HI) 5246 (choices 5247 dst32-R3-direct-Unprefixed-HI 5248 dst32-An-direct-Unprefixed-HI 5249 dst32-An-indirect-Unprefixed-HI 5250 dst32-16-8-An-relative-Unprefixed-HI 5251 dst32-16-16-An-relative-Unprefixed-HI 5252 dst32-16-24-An-relative-Unprefixed-HI 5253 dst32-16-8-SB-relative-Unprefixed-HI 5254 dst32-16-16-SB-relative-Unprefixed-HI 5255 dst32-16-8-FB-relative-Unprefixed-HI 5256 dst32-16-16-FB-relative-Unprefixed-HI 5257 dst32-16-16-absolute-Unprefixed-HI 5258 dst32-16-24-absolute-Unprefixed-HI 5259 ) 5260) 5261;------------------------------------------------------------- 5262; Destination operands with possible additional fields at offset 24 bits 5263;------------------------------------------------------------- 5264 5265(define-pmacro (dst16-24-operand xmode) 5266 (begin 5267 (define-anyof-operand 5268 (name (.sym dst16-24- xmode)) 5269 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24")) 5270 (attrs (machine 16)) 5271 (mode xmode) 5272 (choices 5273 (.sym dst16-Rn-direct- xmode) 5274 (.sym dst16-An-direct- xmode) 5275 (.sym dst16-An-indirect- xmode) 5276 (.sym dst16-24-8-An-relative- xmode) 5277 (.sym dst16-24-16-An-relative- xmode) 5278 (.sym dst16-24-8-SB-relative- xmode) 5279 (.sym dst16-24-16-SB-relative- xmode) 5280 (.sym dst16-24-8-FB-relative- xmode) 5281 (.sym dst16-24-16-absolute- xmode) 5282 ) 5283 ) 5284 ) 5285) 5286 5287(dst16-24-operand QI) 5288(dst16-24-operand HI) 5289 5290(define-pmacro (dst32-24-operand xmode) 5291 (begin 5292 (define-anyof-operand 5293 (name (.sym dst32-24-Unprefixed- xmode)) 5294 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5295 (attrs (machine 32)) 5296 (mode xmode) 5297 (choices 5298 (.sym dst32-Rn-direct-Unprefixed- xmode) 5299 (.sym dst32-An-direct-Unprefixed- xmode) 5300 (.sym dst32-An-indirect-Unprefixed- xmode) 5301 (.sym dst32-24-8-An-relative-Unprefixed- xmode) 5302 (.sym dst32-24-16-An-relative-Unprefixed- xmode) 5303 (.sym dst32-24-24-An-relative-Unprefixed- xmode) 5304 (.sym dst32-24-8-SB-relative-Unprefixed- xmode) 5305 (.sym dst32-24-16-SB-relative-Unprefixed- xmode) 5306 (.sym dst32-24-8-FB-relative-Unprefixed- xmode) 5307 (.sym dst32-24-16-FB-relative-Unprefixed- xmode) 5308 (.sym dst32-24-16-absolute-Unprefixed- xmode) 5309 (.sym dst32-24-24-absolute-Unprefixed- xmode) 5310 ) 5311 ) 5312 (define-anyof-operand 5313 (name (.sym dst32-24-Prefixed- xmode)) 5314 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5315 (attrs (machine 32)) 5316 (mode xmode) 5317 (choices 5318 (.sym dst32-Rn-direct-Prefixed- xmode) 5319 (.sym dst32-An-direct-Prefixed- xmode) 5320 (.sym dst32-An-indirect-Prefixed- xmode) 5321 (.sym dst32-24-8-An-relative-Prefixed- xmode) 5322 (.sym dst32-24-16-An-relative-Prefixed- xmode) 5323 (.sym dst32-24-24-An-relative-Prefixed- xmode) 5324 (.sym dst32-24-8-SB-relative-Prefixed- xmode) 5325 (.sym dst32-24-16-SB-relative-Prefixed- xmode) 5326 (.sym dst32-24-8-FB-relative-Prefixed- xmode) 5327 (.sym dst32-24-16-FB-relative-Prefixed- xmode) 5328 (.sym dst32-24-16-absolute-Prefixed- xmode) 5329 (.sym dst32-24-24-absolute-Prefixed- xmode) 5330 ) 5331 ) 5332 (define-anyof-operand 5333 (name (.sym dst32-24-8-Prefixed- xmode)) 5334 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5335 (attrs (machine 32)) 5336 (mode xmode) 5337 (choices 5338 (.sym dst32-24-8-An-relative-Prefixed- xmode) 5339 (.sym dst32-24-8-SB-relative-Prefixed- xmode) 5340 (.sym dst32-24-8-FB-relative-Prefixed- xmode) 5341 ) 5342 ) 5343 (define-anyof-operand 5344 (name (.sym dst32-24-16-Prefixed- xmode)) 5345 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5346 (attrs (machine 32)) 5347 (mode xmode) 5348 (choices 5349 (.sym dst32-24-16-An-relative-Prefixed- xmode) 5350 (.sym dst32-24-16-SB-relative-Prefixed- xmode) 5351 (.sym dst32-24-16-FB-relative-Prefixed- xmode) 5352 (.sym dst32-24-16-absolute-Prefixed- xmode) 5353 ) 5354 ) 5355 (define-anyof-operand 5356 (name (.sym dst32-24-24-Prefixed- xmode)) 5357 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5358 (attrs (machine 32)) 5359 (mode xmode) 5360 (choices 5361 (.sym dst32-24-24-An-relative-Prefixed- xmode) 5362 (.sym dst32-24-24-absolute-Prefixed- xmode) 5363 ) 5364 ) 5365; (define-anyof-operand 5366; (name (.sym dst32-24-indirect- xmode)) 5367; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5368; (attrs (machine 32)) 5369; (mode xmode) 5370; (choices 5371; (.sym dst32-An-indirect-indirect- xmode) 5372; (.sym dst32-24-8-An-relative-indirect- xmode) 5373; (.sym dst32-24-16-An-relative-indirect- xmode) 5374; (.sym dst32-24-24-An-relative-indirect- xmode) 5375; (.sym dst32-24-8-SB-relative-indirect- xmode) 5376; (.sym dst32-24-16-SB-relative-indirect- xmode) 5377; (.sym dst32-24-8-FB-relative-indirect- xmode) 5378; (.sym dst32-24-16-FB-relative-indirect- xmode) 5379; ) 5380; ) 5381; (define-anyof-operand 5382; (name (.sym dst32-basic-indirect- xmode)) 5383; (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 5384; (attrs (machine 32)) 5385; (mode xmode) 5386; (choices 5387; (.sym dst32-An-indirect-indirect- xmode) 5388; ) 5389; ) 5390; (define-anyof-operand 5391; (name (.sym dst32-24-8-indirect- xmode)) 5392; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5393; (attrs (machine 32)) 5394; (mode xmode) 5395; (choices 5396; (.sym dst32-24-8-An-relative-indirect- xmode) 5397; (.sym dst32-24-8-SB-relative-indirect- xmode) 5398; (.sym dst32-24-8-FB-relative-indirect- xmode) 5399; ) 5400; ) 5401; (define-anyof-operand 5402; (name (.sym dst32-24-16-indirect- xmode)) 5403; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5404; (attrs (machine 32)) 5405; (mode xmode) 5406; (choices 5407; (.sym dst32-24-16-An-relative-indirect- xmode) 5408; (.sym dst32-24-16-SB-relative-indirect- xmode) 5409; (.sym dst32-24-16-FB-relative-indirect- xmode) 5410; ) 5411; ) 5412; (define-anyof-operand 5413; (name (.sym dst32-24-24-indirect- xmode)) 5414; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5415; (attrs (machine 32)) 5416; (mode xmode) 5417; (choices 5418; (.sym dst32-24-24-An-relative-indirect- xmode) 5419; ) 5420; ) 5421; (define-anyof-operand 5422; (name (.sym dst32-24-absolute-indirect- xmode)) 5423; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5424; (attrs (machine 32)) 5425; (mode xmode) 5426; (choices 5427; (.sym dst32-24-16-absolute-indirect-derived- xmode) 5428; (.sym dst32-24-24-absolute-indirect-derived- xmode) 5429; ) 5430; ) 5431; (define-anyof-operand 5432; (name (.sym dst32-24-16-absolute-indirect- xmode)) 5433; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5434; (attrs (machine 32)) 5435; (mode xmode) 5436; (choices 5437; (.sym dst32-24-16-absolute-indirect-derived- xmode) 5438; ) 5439; ) 5440; (define-anyof-operand 5441; (name (.sym dst32-24-24-absolute-indirect- xmode)) 5442; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5443; (attrs (machine 32)) 5444; (mode xmode) 5445; (choices 5446; (.sym dst32-24-24-absolute-indirect-derived- xmode) 5447; ) 5448; ) 5449 ) 5450) 5451 5452(dst32-24-operand QI) 5453(dst32-24-operand HI) 5454(dst32-24-operand SI) 5455 5456;------------------------------------------------------------- 5457; Destination operands with possible additional fields at offset 32 bits 5458;------------------------------------------------------------- 5459 5460(define-pmacro (dst16-32-operand xmode) 5461 (begin 5462 (define-anyof-operand 5463 (name (.sym dst16-32- xmode)) 5464 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32")) 5465 (attrs (machine 16)) 5466 (mode xmode) 5467 (choices 5468 (.sym dst16-Rn-direct- xmode) 5469 (.sym dst16-An-direct- xmode) 5470 (.sym dst16-An-indirect- xmode) 5471 (.sym dst16-32-8-An-relative- xmode) 5472 (.sym dst16-32-16-An-relative- xmode) 5473 (.sym dst16-32-8-SB-relative- xmode) 5474 (.sym dst16-32-16-SB-relative- xmode) 5475 (.sym dst16-32-8-FB-relative- xmode) 5476 (.sym dst16-32-16-absolute- xmode) 5477 ) 5478 ) 5479 ) 5480) 5481(dst16-32-operand QI) 5482(dst16-32-operand HI) 5483 5484; This macro actually handles operands at offset 32, 40 and 48 bits 5485(define-pmacro (dst32-32plus-operand offset xmode) 5486 (begin 5487 (define-anyof-operand 5488 (name (.sym dst32- offset -Unprefixed- xmode)) 5489 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5490 (attrs (machine 32)) 5491 (mode xmode) 5492 (choices 5493 (.sym dst32-Rn-direct-Unprefixed- xmode) 5494 (.sym dst32-An-direct-Unprefixed- xmode) 5495 (.sym dst32-An-indirect-Unprefixed- xmode) 5496 (.sym dst32- offset -8-An-relative-Unprefixed- xmode) 5497 (.sym dst32- offset -16-An-relative-Unprefixed- xmode) 5498 (.sym dst32- offset -24-An-relative-Unprefixed- xmode) 5499 (.sym dst32- offset -8-SB-relative-Unprefixed- xmode) 5500 (.sym dst32- offset -16-SB-relative-Unprefixed- xmode) 5501 (.sym dst32- offset -8-FB-relative-Unprefixed- xmode) 5502 (.sym dst32- offset -16-FB-relative-Unprefixed- xmode) 5503 (.sym dst32- offset -16-absolute-Unprefixed- xmode) 5504 (.sym dst32- offset -24-absolute-Unprefixed- xmode) 5505 ) 5506 ) 5507 (define-anyof-operand 5508 (name (.sym dst32- offset -Prefixed- xmode)) 5509 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5510 (attrs (machine 32)) 5511 (mode xmode) 5512 (choices 5513 (.sym dst32-Rn-direct-Prefixed- xmode) 5514 (.sym dst32-An-direct-Prefixed- xmode) 5515 (.sym dst32-An-indirect-Prefixed- xmode) 5516 (.sym dst32- offset -8-An-relative-Prefixed- xmode) 5517 (.sym dst32- offset -16-An-relative-Prefixed- xmode) 5518 (.sym dst32- offset -24-An-relative-Prefixed- xmode) 5519 (.sym dst32- offset -8-SB-relative-Prefixed- xmode) 5520 (.sym dst32- offset -16-SB-relative-Prefixed- xmode) 5521 (.sym dst32- offset -8-FB-relative-Prefixed- xmode) 5522 (.sym dst32- offset -16-FB-relative-Prefixed- xmode) 5523 (.sym dst32- offset -16-absolute-Prefixed- xmode) 5524 (.sym dst32- offset -24-absolute-Prefixed- xmode) 5525 ) 5526 ) 5527; (define-anyof-operand 5528; (name (.sym dst32- offset -indirect- xmode)) 5529; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5530; (attrs (machine 32)) 5531; (mode xmode) 5532; (choices 5533; (.sym dst32-An-indirect-indirect- xmode) 5534; (.sym dst32- offset -8-An-relative-indirect- xmode) 5535; (.sym dst32- offset -16-An-relative-indirect- xmode) 5536; (.sym dst32- offset -24-An-relative-indirect- xmode) 5537; (.sym dst32- offset -8-SB-relative-indirect- xmode) 5538; (.sym dst32- offset -16-SB-relative-indirect- xmode) 5539; (.sym dst32- offset -8-FB-relative-indirect- xmode) 5540; (.sym dst32- offset -16-FB-relative-indirect- xmode) 5541; ) 5542; ) 5543; (define-anyof-operand 5544; (name (.sym dst32- offset -absolute-indirect- xmode)) 5545; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5546; (attrs (machine 32)) 5547; (mode xmode) 5548; (choices 5549; (.sym dst32- offset -16-absolute-indirect-derived- xmode) 5550; (.sym dst32- offset -24-absolute-indirect-derived- xmode) 5551; ) 5552; ) 5553 ) 5554) 5555 5556(dst32-32plus-operand 32 QI) 5557(dst32-32plus-operand 32 HI) 5558(dst32-32plus-operand 32 SI) 5559(dst32-32plus-operand 40 QI) 5560(dst32-32plus-operand 40 HI) 5561(dst32-32plus-operand 40 SI) 5562 5563;------------------------------------------------------------- 5564; Destination operands with possible additional fields at offset 48 bits 5565;------------------------------------------------------------- 5566 5567(define-pmacro (dst32-48-operand offset xmode) 5568 (begin 5569 (define-anyof-operand 5570 (name (.sym dst32- offset -Prefixed- xmode)) 5571 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5572 (attrs (machine 32)) 5573 (mode xmode) 5574 (choices 5575 (.sym dst32-Rn-direct-Prefixed- xmode) 5576 (.sym dst32-An-direct-Prefixed- xmode) 5577 (.sym dst32-An-indirect-Prefixed- xmode) 5578 (.sym dst32- offset -8-An-relative-Prefixed- xmode) 5579 (.sym dst32- offset -16-An-relative-Prefixed- xmode) 5580 (.sym dst32- offset -24-An-relative-Prefixed- xmode) 5581 (.sym dst32- offset -8-SB-relative-Prefixed- xmode) 5582 (.sym dst32- offset -16-SB-relative-Prefixed- xmode) 5583 (.sym dst32- offset -8-FB-relative-Prefixed- xmode) 5584 (.sym dst32- offset -16-FB-relative-Prefixed- xmode) 5585 (.sym dst32- offset -16-absolute-Prefixed- xmode) 5586 (.sym dst32- offset -24-absolute-Prefixed- xmode) 5587 ) 5588 ) 5589; (define-anyof-operand 5590; (name (.sym dst32- offset -indirect- xmode)) 5591; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5592; (attrs (machine 32)) 5593; (mode xmode) 5594; (choices 5595; (.sym dst32-An-indirect-indirect- xmode) 5596; (.sym dst32- offset -8-An-relative-indirect- xmode) 5597; (.sym dst32- offset -16-An-relative-indirect- xmode) 5598; (.sym dst32- offset -24-An-relative-indirect- xmode) 5599; (.sym dst32- offset -8-SB-relative-indirect- xmode) 5600; (.sym dst32- offset -16-SB-relative-indirect- xmode) 5601; (.sym dst32- offset -8-FB-relative-indirect- xmode) 5602; (.sym dst32- offset -16-FB-relative-indirect- xmode) 5603; ) 5604; ) 5605; (define-anyof-operand 5606; (name (.sym dst32- offset -absolute-indirect- xmode)) 5607; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5608; (attrs (machine 32)) 5609; (mode xmode) 5610; (choices 5611; (.sym dst32- offset -16-absolute-indirect-derived- xmode) 5612; (.sym dst32- offset -24-absolute-indirect-derived- xmode) 5613; ) 5614; ) 5615 ) 5616) 5617 5618(dst32-48-operand 48 QI) 5619(dst32-48-operand 48 HI) 5620(dst32-48-operand 48 SI) 5621 5622;------------------------------------------------------------- 5623; Bit operands for m16c 5624;------------------------------------------------------------- 5625 5626(define-pmacro (bit16-operand offset) 5627 (begin 5628 (define-anyof-operand 5629 (name (.sym bit16- offset)) 5630 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5631 (attrs (machine 16)) 5632 (mode BI) 5633 (choices 5634 bit16-Rn-direct 5635 bit16-An-direct 5636 bit16-An-indirect 5637 (.sym bit16- offset -8-An-relative) 5638 (.sym bit16- offset -16-An-relative) 5639 (.sym bit16- offset -8-SB-relative) 5640 (.sym bit16- offset -16-SB-relative) 5641 (.sym bit16- offset -8-FB-relative) 5642 (.sym bit16- offset -16-absolute) 5643 ) 5644 ) 5645 (define-anyof-operand 5646 (name (.sym bit16- offset -basic)) 5647 (comment (.str "m16c bit operand with no additional fields")) 5648 (attrs (machine 16)) 5649 (mode BI) 5650 (choices 5651 bit16-An-indirect 5652 ) 5653 ) 5654 (define-anyof-operand 5655 (name (.sym bit16- offset -8)) 5656 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5657 (attrs (machine 16)) 5658 (mode BI) 5659 (choices 5660 bit16-Rn-direct 5661 bit16-An-direct 5662 (.sym bit16- offset -8-An-relative) 5663 (.sym bit16- offset -8-SB-relative) 5664 (.sym bit16- offset -8-FB-relative) 5665 ) 5666 ) 5667 (define-anyof-operand 5668 (name (.sym bit16- offset -16)) 5669 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5670 (attrs (machine 16)) 5671 (mode BI) 5672 (choices 5673 (.sym bit16- offset -16-An-relative) 5674 (.sym bit16- offset -16-SB-relative) 5675 (.sym bit16- offset -16-absolute) 5676 ) 5677 ) 5678 ) 5679) 5680 5681(bit16-operand 16) 5682 5683;------------------------------------------------------------- 5684; Bit operands for m32c 5685;------------------------------------------------------------- 5686 5687(define-pmacro (bit32-operand offset group) 5688 (begin 5689 (define-anyof-operand 5690 (name (.sym bit32- offset - group)) 5691 (comment (.str "m32c bit operand with possible additional fields at offset 24")) 5692 (attrs (machine 32)) 5693 (mode BI) 5694 (choices 5695 (.sym bit32-Rn-direct- group) 5696 (.sym bit32-An-direct- group) 5697 (.sym bit32-An-indirect- group) 5698 (.sym bit32- offset -11-An-relative- group) 5699 (.sym bit32- offset -19-An-relative- group) 5700 (.sym bit32- offset -27-An-relative- group) 5701 (.sym bit32- offset -11-SB-relative- group) 5702 (.sym bit32- offset -19-SB-relative- group) 5703 (.sym bit32- offset -11-FB-relative- group) 5704 (.sym bit32- offset -19-FB-relative- group) 5705 (.sym bit32- offset -19-absolute- group) 5706 (.sym bit32- offset -27-absolute- group) 5707 ) 5708 ) 5709 ) 5710) 5711 5712(bit32-operand 16 Unprefixed) 5713(bit32-operand 24 Prefixed) 5714 5715(define-anyof-operand 5716 (name bit32-basic-Unprefixed) 5717 (comment "m32c bit operand with no additional fields") 5718 (attrs (machine 32)) 5719 (mode BI) 5720 (choices 5721 bit32-Rn-direct-Unprefixed 5722 bit32-An-direct-Unprefixed 5723 bit32-An-indirect-Unprefixed 5724 ) 5725) 5726 5727(define-anyof-operand 5728 (name bit32-16-8-Unprefixed) 5729 (comment "m32c bit operand with 8 bit additional fields") 5730 (attrs (machine 32)) 5731 (mode BI) 5732 (choices 5733 bit32-16-11-An-relative-Unprefixed 5734 bit32-16-11-SB-relative-Unprefixed 5735 bit32-16-11-FB-relative-Unprefixed 5736 ) 5737) 5738 5739(define-anyof-operand 5740 (name bit32-16-16-Unprefixed) 5741 (comment "m32c bit operand with 16 bit additional fields") 5742 (attrs (machine 32)) 5743 (mode BI) 5744 (choices 5745 bit32-16-19-An-relative-Unprefixed 5746 bit32-16-19-SB-relative-Unprefixed 5747 bit32-16-19-FB-relative-Unprefixed 5748 bit32-16-19-absolute-Unprefixed 5749 ) 5750) 5751 5752(define-anyof-operand 5753 (name bit32-16-24-Unprefixed) 5754 (comment "m32c bit operand with 24 bit additional fields") 5755 (attrs (machine 32)) 5756 (mode BI) 5757 (choices 5758 bit32-16-27-An-relative-Unprefixed 5759 bit32-16-27-absolute-Unprefixed 5760 ) 5761) 5762 5763;------------------------------------------------------------- 5764; Operands for short format binary insns 5765;------------------------------------------------------------- 5766 5767(define-anyof-operand 5768 (name src16-2-S) 5769 (comment "m16c source operand of size QI for short format insns") 5770 (attrs (machine 16)) 5771 (mode QI) 5772 (choices 5773 src16-2-S-8-SB-relative-QI 5774 src16-2-S-8-FB-relative-QI 5775 src16-2-S-16-absolute-QI 5776 ) 5777) 5778 5779(define-anyof-operand 5780 (name src32-2-S-QI) 5781 (comment "m32c source operand of size QI for short format insns") 5782 (attrs (machine 32)) 5783 (mode QI) 5784 (choices 5785 src32-2-S-8-SB-relative-QI 5786 src32-2-S-8-FB-relative-QI 5787 src32-2-S-16-absolute-QI 5788 ) 5789) 5790 5791(define-anyof-operand 5792 (name src32-2-S-HI) 5793 (comment "m32c source operand of size QI for short format insns") 5794 (attrs (machine 32)) 5795 (mode HI) 5796 (choices 5797 src32-2-S-8-SB-relative-HI 5798 src32-2-S-8-FB-relative-HI 5799 src32-2-S-16-absolute-HI 5800 ) 5801) 5802 5803(define-anyof-operand 5804 (name Dst16-3-S-8) 5805 (comment "m16c destination operand of size QI for short format insns") 5806 (attrs (machine 16)) 5807 (mode QI) 5808 (choices 5809 dst16-3-S-R0l-direct-QI 5810 dst16-3-S-R0h-direct-QI 5811 dst16-3-S-8-8-SB-relative-QI 5812 dst16-3-S-8-8-FB-relative-QI 5813 dst16-3-S-8-16-absolute-QI 5814 ) 5815) 5816 5817(define-anyof-operand 5818 (name Dst16-3-S-16) 5819 (comment "m16c destination operand of size QI for short format insns") 5820 (attrs (machine 16)) 5821 (mode QI) 5822 (choices 5823 dst16-3-S-R0l-direct-QI 5824 dst16-3-S-R0h-direct-QI 5825 dst16-3-S-16-8-SB-relative-QI 5826 dst16-3-S-16-8-FB-relative-QI 5827 dst16-3-S-16-16-absolute-QI 5828 ) 5829) 5830 5831(define-anyof-operand 5832 (name srcdst16-r0l-r0h-S) 5833 (comment "m16c r0l/r0h operand of size QI for short format insns") 5834 (attrs (machine 16)) 5835 (mode SI) 5836 (choices 5837 srcdst16-r0l-r0h-S-derived 5838 ) 5839) 5840 5841(define-anyof-operand 5842 (name dst32-2-S-basic-QI) 5843 (comment "m32c r0l operand of size QI for short format binary insns") 5844 (attrs (machine 32)) 5845 (mode QI) 5846 (choices 5847 dst32-2-S-R0l-direct-QI 5848 ) 5849) 5850 5851(define-anyof-operand 5852 (name dst32-2-S-basic-HI) 5853 (comment "m32c r0 operand of size HI for short format binary insns") 5854 (attrs (machine 32)) 5855 (mode HI) 5856 (choices 5857 dst32-2-S-R0-direct-HI 5858 ) 5859) 5860 5861(define-pmacro (dst32-2-S-operands xmode) 5862 (begin 5863 (define-anyof-operand 5864 (name (.sym dst32-2-S-8- xmode)) 5865 (comment "m32c operand of size " xmode " for short format binary insns") 5866 (attrs (machine 32)) 5867 (mode xmode) 5868 (choices 5869 (.sym dst32-2-S-8-SB-relative- xmode) 5870 (.sym dst32-2-S-8-FB-relative- xmode) 5871 ) 5872 ) 5873 (define-anyof-operand 5874 (name (.sym dst32-2-S-16- xmode)) 5875 (comment "m32c operand of size " xmode " for short format binary insns") 5876 (attrs (machine 32)) 5877 (mode xmode) 5878 (choices 5879 (.sym dst32-2-S-16-absolute- xmode) 5880 ) 5881 ) 5882; (define-anyof-operand 5883; (name (.sym dst32-2-S-8-indirect- xmode)) 5884; (comment "m32c operand of size " xmode " for short format binary insns") 5885; (attrs (machine 32)) 5886; (mode xmode) 5887; (choices 5888; (.sym dst32-2-S-8-SB-relative-indirect- xmode) 5889; (.sym dst32-2-S-8-FB-relative-indirect- xmode) 5890; ) 5891; ) 5892; (define-anyof-operand 5893; (name (.sym dst32-2-S-absolute-indirect- xmode)) 5894; (comment "m32c operand of size " xmode " for short format binary insns") 5895; (attrs (machine 32)) 5896; (mode xmode) 5897; (choices 5898; (.sym dst32-2-S-16-absolute-indirect- xmode) 5899; ) 5900; ) 5901 ) 5902) 5903 5904(dst32-2-S-operands QI) 5905(dst32-2-S-operands HI) 5906(dst32-2-S-operands SI) 5907 5908(define-anyof-operand 5909 (name dst32-an-S) 5910 (comment "m32c An operand for short format binary insns") 5911 (attrs (machine 32)) 5912 (mode HI) 5913 (choices 5914 dst32-1-S-A0-direct-HI 5915 dst32-1-S-A1-direct-HI 5916 ) 5917) 5918 5919(define-anyof-operand 5920 (name bit16-11-S) 5921 (comment "m16c bit operand for short format insns") 5922 (attrs (machine 16)) 5923 (mode BI) 5924 (choices 5925 bit16-11-SB-relative-S 5926 ) 5927) 5928 5929(define-anyof-operand 5930 (name Rn16-push-S-anyof) 5931 (comment "m16c bit operand for short format insns") 5932 (attrs (machine 16)) 5933 (mode QI) 5934 (choices 5935 Rn16-push-S-derived 5936 ) 5937) 5938 5939(define-anyof-operand 5940 (name An16-push-S-anyof) 5941 (comment "m16c bit operand for short format insns") 5942 (attrs (machine 16)) 5943 (mode HI) 5944 (choices 5945 An16-push-S-derived 5946 ) 5947) 5948 5949;============================================================= 5950; Common macros for instruction definitions 5951; 5952(define-pmacro (set-z x) 5953 (sequence () 5954 (set zbit (zflag x))) 5955 5956) 5957 5958(define-pmacro (set-s x) 5959 (sequence () 5960 (set sbit (nflag x))) 5961) 5962 5963(define-pmacro (set-z-and-s x) 5964 (sequence () 5965 (set-z x) 5966 (set-s x)) 5967) 5968 5969;============================================================= 5970; Unary insn macros 5971;------------------------------------------------------------- 5972 5973(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) 5974 (dni (.sym op mach wstr - group) 5975 (.str op wstr opg " dst" mach "-" group "-" mode) 5976 ((machine mach) RL_1ADDR) 5977 (.str op wstr opg " ${dst" mach "-" group "-" mode "}") 5978 encoding 5979 (sem mode (.sym dst mach - group - mode)) 5980 ()) 5981) 5982 5983(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) 5984 (unary-insn-defn-g mach group mode wstr op encoding sem "") 5985) 5986 5987 5988(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) 5989 (unary-insn-defn-g 16 16 mode wstr op 5990 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) 5991 sem opg) 5992) 5993(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) 5994 (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") 5995) 5996 5997(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) 5998 (begin 5999 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6000 ; define the absolute-indirect insns first in order to prevent them from being selected 6001 ; when the mode is register-indirect 6002; (unary-insn-defn 32 24-absolute-indirect mode wstr op 6003; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) 6004; sem) 6005 (unary-insn-defn-g 32 16-Unprefixed mode wstr op 6006 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) 6007 sem opg) 6008; (unary-insn-defn 32 24-indirect mode wstr op 6009; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) 6010; sem) 6011 ) 6012) 6013(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) 6014 (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") 6015) 6016 6017(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg) 6018 (begin 6019 (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg)) 6020 (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg)) 6021 ) 6022) 6023(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) 6024 (unary-insn-mach-g mach op opc1 opc2 opc3 sem "") 6025) 6026 6027(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6028 (begin 6029 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "") 6030 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "") 6031 ) 6032) 6033 6034(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6035 (begin 6036 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G") 6037 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G") 6038 ) 6039) 6040 6041;------------------------------------------------------------- 6042; Sign/zero extension macros 6043;------------------------------------------------------------- 6044 6045(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem) 6046 (dni (.sym op mach wstr - group) 6047 (.str op wstr " dst" mach "-" group "-" smode) 6048 ((machine mach)) 6049 (.str op wstr " ${dst" mach "-" group "-" smode "}") 6050 encoding 6051 (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode)) 6052 ()) 6053) 6054 6055(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) 6056 (ext-insn-defn 16 16-Ext smode dmode wstr op 6057 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode)) 6058 sem) 6059) 6060 6061(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) 6062 (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op 6063 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode)) 6064 sem) 6065) 6066 6067(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem) 6068 (dni (.sym op 32 wstr - src-group - dst-group) 6069 (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI") 6070 ((machine 32)) 6071 (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}") 6072 encoding 6073 (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI)) 6074 ()) 6075) 6076 6077(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem) 6078 (begin 6079 (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr 6080 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2)) 6081 sem) 6082 (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr 6083 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2)) 6084 sem) 6085 (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr 6086 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2)) 6087 sem) 6088 (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr 6089 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2)) 6090 sem) 6091 ) 6092) 6093 6094;============================================================= 6095; Binary Arithmetic macros 6096; 6097;------------------------------------------------------------- 6098;<arith>.size:S src2,r0[l] -- for m32c 6099;------------------------------------------------------------- 6100 6101(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem) 6102 (dni (.sym op 32 wstr .S-src2-r0- xmode) 6103 (.str op 32 wstr ":S src2,r0[l]") 6104 ((machine 32)) 6105 (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}") 6106 (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit)) 6107 (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S)) 6108 ()) 6109) 6110 6111;------------------------------------------------------------- 6112;<arith>.b:S src2,r0l/r0h -- for m16c 6113;------------------------------------------------------------- 6114 6115(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem) 6116 (begin 6117 (dni (.sym op 16 .b.S-src2) 6118 (.str op ".b:S src2,r0[lh]") 6119 ((machine 16)) 6120 (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}") 6121 (+ opc1 opc2 Dst16RnQI-S src16-2-S) 6122 (sem QI src16-2-S Dst16RnQI-S) 6123 ()) 6124 (dni (.sym op 16 .b.S-r0l-r0h) 6125 (.str op ".b:S r0l/r0h") 6126 ((machine 16)) 6127 (.str op ".b$S ${srcdst16-r0l-r0h-S}") 6128 (+ opc1 opc2 srcdst16-r0l-r0h-S) 6129 (if (eq srcdst16-r0l-r0h-S 0) 6130 (sem QI R0h R0l) 6131 (sem QI R0l R0h)) 6132 ()) 6133 ) 6134) 6135 6136;------------------------------------------------------------- 6137;<arith>.b:S #imm8,dst3 -- for m16c 6138;------------------------------------------------------------- 6139 6140(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem) 6141 (dni (.sym op 16 .b.S-imm8-dst3) 6142 (.str op sz ":S imm8,dst3") 6143 ((machine 16)) 6144 (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}") 6145 (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI) 6146 (sem QI Imm-8-QI Dst16-3-S-16) 6147 ()) 6148) 6149 6150;------------------------------------------------------------- 6151;<arith>.size:Q #imm4,sp -- for m16c 6152;------------------------------------------------------------- 6153 6154(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) 6155 (dni (.sym op 16 -wQ-sp) 6156 (.str op ".w:q #imm4,sp") 6157 ((machine 16)) 6158 (.str op ".w$Q #${Imm-12-s4},sp") 6159 (+ opc1 opc2 opc3 Imm-12-s4) 6160 (sem QI Imm-12-s4 sp) 6161 ()) 6162) 6163 6164;------------------------------------------------------------- 6165;<arith>.size:G #imm,sp -- for m16c 6166;------------------------------------------------------------- 6167 6168(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem) 6169 (dni (.sym op 16 wstr - G-sp) 6170 (.str op wstr " imm-sp " mode) 6171 ((machine 16)) 6172 (.str op wstr "$G #${Imm-16-" mode "},sp") 6173 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode)) 6174 (sem mode (.sym Imm-16- mode) sp) 6175 ()) 6176) 6177 6178(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem) 6179 (begin 6180 (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem) 6181 (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem) 6182 ) 6183) 6184 6185;------------------------------------------------------------- 6186;<arith>.size:G #imm,dst -- for m16c and m32c 6187;------------------------------------------------------------- 6188 6189(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) 6190 (dni (.sym op mach wstr - imm-G - dstgroup) 6191 (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) 6192 ((machine mach) RL_1ADDR) 6193 (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") 6194 encoding 6195 (sem dmode src (.sym dst mach - dstgroup - dmode)) 6196 ()) 6197) 6198 6199; m16c variants 6200(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6201 (begin 6202 (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix 6203 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode)) 6204 sem) 6205 (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix 6206 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode)) 6207 sem) 6208 (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix 6209 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode)) 6210 sem) 6211 ) 6212) 6213 6214; m32c Unprefixed variants 6215(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6216 (begin 6217 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix 6218 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode)) 6219 sem) 6220 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix 6221 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode)) 6222 sem) 6223 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix 6224 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode)) 6225 sem) 6226 (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix 6227 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode)) 6228 sem) 6229 ) 6230) 6231 6232; m32c Prefixed variants 6233(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6234 (begin 6235 (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix 6236 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode)) 6237 sem) 6238 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix 6239 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode)) 6240 sem) 6241 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix 6242 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode)) 6243 sem) 6244 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix 6245 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode)) 6246 sem) 6247 ) 6248) 6249 6250; All m32c variants 6251(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6252 (begin 6253 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6254 ; define the absolute-indirect insns first in order to prevent them from being selected 6255 ; when the mode is register-indirect 6256; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix 6257; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode)) 6258; sem) 6259; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix 6260; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode)) 6261; sem) 6262 ; Unprefixed modes next 6263 (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6264 6265 ; Remaining indirect modes 6266; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix 6267; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode)) 6268; sem) 6269; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix 6270; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode)) 6271; sem) 6272; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix 6273; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode)) 6274; sem) 6275; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix 6276; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode)) 6277; sem) 6278 ) 6279) 6280 6281(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem) 6282 (begin 6283 (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem)) 6284 (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem)) 6285 ) 6286) 6287 6288(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6289 (begin 6290 (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem) 6291 (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem) 6292 ) 6293) 6294 6295;------------------------------------------------------------- 6296;<arith>.size:Q #imm4,dst -- for m16c and m32c 6297;------------------------------------------------------------- 6298 6299(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) 6300 (dni (.sym op mach wstr - imm4-Q - dstgroup) 6301 (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) 6302 ((machine mach) RL_1ADDR) 6303 (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") 6304 encoding 6305 (sem mode src (.sym dst mach - dstgroup - mode)) 6306 ()) 6307) 6308 6309; m16c variants 6310(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6311 (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op 6312 (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode)) 6313 sem) 6314) 6315 6316(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6317 (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op 6318 (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode)) 6319 sem) 6320) 6321 6322; m32c variants 6323(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6324 (begin 6325 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6326 ; define the absolute-indirect insns first in order to prevent them from being selected 6327 ; when the mode is register-indirect 6328; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op 6329; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4) 6330; sem) 6331 (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op 6332 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4) 6333 sem) 6334; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op 6335; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4) 6336; sem) 6337 ) 6338) 6339 6340(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6341 (begin 6342 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6343 ; define the absolute-indirect insns first in order to prevent them from being selected 6344 ; when the mode is register-indirect 6345; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op 6346; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) 6347; sem) 6348 (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op 6349 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4) 6350 sem) 6351; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op 6352; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) 6353; sem) 6354 ) 6355) 6356 6357(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem) 6358 (begin 6359 (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem)) 6360 (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem)) 6361 ) 6362) 6363 6364(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) 6365 (begin 6366 (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem) 6367 (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem) 6368 ) 6369) 6370 6371;------------------------------------------------------------- 6372;<arith>.size:G src,dst -- for m16c and m32c 6373;------------------------------------------------------------- 6374 6375(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) 6376 (dni (.sym op mach wstr - srcgroup - dstgroup) 6377 (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) 6378 ((machine mach) RL_2ADDR) 6379 (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") 6380 encoding 6381 (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) 6382 ()) 6383) 6384 6385; m16c variants 6386(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) 6387 (begin 6388 (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix 6389 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode)) 6390 sem) 6391 (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix 6392 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode)) 6393 sem) 6394 (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix 6395 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode)) 6396 sem) 6397 ) 6398) 6399 6400; m32c Prefixed variants 6401(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem) 6402 (begin 6403 (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix 6404 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) 6405 sem) 6406 (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix 6407 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6408 sem) 6409 (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix 6410 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6411 sem) 6412 (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix 6413 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) 6414 sem) 6415 ) 6416) 6417 6418; all m32c variants 6419(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) 6420 (begin 6421 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6422 ; define the absolute-indirect insns first in order to prevent them from being selected 6423 ; when the mode is register-indirect 6424; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix 6425; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6426; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6427; sem) 6428; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix 6429; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6430; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6431; sem) 6432; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix 6433; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6434; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6435; sem) 6436; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix 6437; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6438; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6439; sem) 6440; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix 6441; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6442; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6443; sem) 6444; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix 6445; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6446; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6447; sem) 6448; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix 6449; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6450; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) 6451; sem) 6452; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix 6453; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6454; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6455; sem) 6456; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix 6457; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6458; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6459; sem) 6460; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix 6461; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6462; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) 6463; sem) 6464; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix 6465; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6466; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) 6467; sem) 6468; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix 6469; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6470; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6471; sem) 6472; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix 6473; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6474; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6475; sem) 6476; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix 6477; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6478; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) 6479; sem) 6480 (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix 6481 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2)) 6482 sem) 6483 (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix 6484 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2)) 6485 sem) 6486 (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix 6487 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2)) 6488 sem) 6489 (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix 6490 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2)) 6491 sem) 6492; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix 6493; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6494; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) 6495; sem) 6496; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix 6497; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6498; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6499; sem) 6500; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix 6501; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6502; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6503; sem) 6504; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix 6505; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6506; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) 6507; sem) 6508; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix 6509; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6510; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) 6511; sem) 6512; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix 6513; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6514; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6515; sem) 6516; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix 6517; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6518; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6519; sem) 6520; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix 6521; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6522; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) 6523; sem) 6524; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix 6525; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6526; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) 6527; sem) 6528; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix 6529; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6530; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6531; sem) 6532; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix 6533; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6534; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6535; sem) 6536; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix 6537; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6538; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) 6539; sem) 6540 ) 6541) 6542 6543(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem) 6544 (begin 6545 (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem)) 6546 (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem)) 6547 ) 6548) 6549 6550(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem) 6551 (begin 6552 (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem) 6553 (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem) 6554 ) 6555) 6556 6557;------------------------------------------------------------- 6558;<arith>.size:S #imm,dst -- for m32c 6559;------------------------------------------------------------- 6560 6561(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem) 6562 (dni (.sym op 32 wstr - imm-S - dstgroup) 6563 (.str op wstr " 32-imm-S-" dstgroup "-" mode) 6564 ((machine 32)) 6565 (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}") 6566 encoding 6567 (sem mode src (.sym dst32- dstgroup - mode)) 6568 ()) 6569) 6570 6571(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem) 6572 (dni (.sym op 32 wstr - imm-Z - dstgroup) 6573 (.str op wstr " 32-imm-Z-" dstgroup "-" mode) 6574 ((machine 32)) 6575 (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}") 6576 encoding 6577 (sem mode (const 0) (.sym dst32- dstgroup - mode)) 6578 ()) 6579) 6580 6581(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem) 6582 (begin 6583; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op 6584; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) 6585; sem) 6586 (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op 6587 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode)) 6588 sem) 6589 (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op 6590 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode)) 6591 sem) 6592 (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op 6593 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode)) 6594 sem) 6595; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op 6596; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) 6597; sem) 6598 ) 6599) 6600 6601(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem) 6602 (begin 6603; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op 6604; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) 6605; sem) 6606 (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op 6607 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit)) 6608 sem) 6609 (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op 6610 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit)) 6611 sem) 6612 (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op 6613 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit)) 6614 sem) 6615; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op 6616; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) 6617; sem) 6618 ) 6619) 6620 6621;------------------------------------------------------------- 6622;<arith>.L:S #imm1,An -- for m32c 6623;------------------------------------------------------------- 6624 6625(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem) 6626 (begin 6627 (dni (.sym op 32.l-s-imm1-S-an) 6628 (.str op ".l 32-imm1-S-an") 6629 ((machine 32)) 6630 (.str op ".l$S #${Imm1-S},${dst32-an-S}") 6631 (+ opc1 Imm1-S opc2 dst32-an-S) 6632 (sem SI Imm1-S dst32-an-S) 6633 ()) 6634 ) 6635) 6636 6637;------------------------------------------------------------- 6638;<arith>.L:Q #imm3,sp -- for m32c 6639;------------------------------------------------------------- 6640 6641(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem) 6642 (begin 6643 (dni (.sym op 32.l-imm3-Q) 6644 (.str op ".l 32-imm3-Q") 6645 ((machine 32)) 6646 (.str op ".l$Q #${Imm3-S},sp") 6647 (+ opc1 Imm3-S opc2) 6648 (sem SI Imm3-S sp) 6649 ()) 6650 ) 6651) 6652 6653;------------------------------------------------------------- 6654;<arith>.L:S #imm8,sp -- for m32c 6655;------------------------------------------------------------- 6656 6657(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem) 6658 (begin 6659 (dni (.sym op 32.l-imm8-S) 6660 (.str op ".l 32-imm8-S") 6661 ((machine 32)) 6662 (.str op ".l$S #${Imm-16-QI},sp") 6663 (+ opc1 opc2 opc3 opc4 Imm-16-QI) 6664 (sem SI Imm-16-QI sp) 6665 ()) 6666 ) 6667) 6668 6669;------------------------------------------------------------- 6670;<arith>.L:G #imm16,sp -- for m32c 6671;------------------------------------------------------------- 6672 6673(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem) 6674 (begin 6675 (dni (.sym op 32.l-imm16-G) 6676 (.str op ".l 32-imm16-G") 6677 ((machine 32)) 6678 (.str op ".l$G #${Imm-16-HI},sp") 6679 (+ opc1 opc2 opc3 opc4 Imm-16-HI) 6680 (sem SI Imm-16-HI sp) 6681 ()) 6682 ) 6683) 6684 6685;------------------------------------------------------------- 6686;<arith>jnz.size #imm4,dst,label -- for m16c and m32c 6687;------------------------------------------------------------- 6688 6689(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) 6690 (dni (.sym op mach wstr - imm4 - dstgroup) 6691 (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) 6692 (RL_JUMP RELAXABLE (machine mach)) 6693 (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") 6694 encoding 6695 (sem mode src (.sym dst mach - dstgroup - mode) label) 6696 ()) 6697) 6698 6699; m16c variants 6700(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) 6701 (begin 6702 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op 6703 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) 6704 sem) 6705 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op 6706 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) 6707 sem) 6708 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op 6709 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) 6710 sem) 6711 ) 6712) 6713 6714; m32c variants 6715(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) 6716 (begin 6717 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op 6718 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8) 6719 sem) 6720 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op 6721 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8) 6722 sem) 6723 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op 6724 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8) 6725 sem) 6726 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op 6727 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8) 6728 sem) 6729 ) 6730) 6731 6732(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem) 6733 (begin 6734 (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem)) 6735 (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem)) 6736 ) 6737) 6738 6739(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem) 6740 (begin 6741 (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem) 6742 (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem) 6743 ) 6744) 6745 6746;------------------------------------------------------------- 6747;mov.size dsp8[sp],dst -- for m16c and m32c 6748;------------------------------------------------------------- 6749(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem) 6750 (dni (.sym op mach wstr -dspsp-dst- dstgroup) 6751 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) 6752 ((machine mach)) 6753 (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") 6754 encoding 6755 (sem mach mode dsp (.sym dst mach - dstgroup - mode)) 6756 ()) 6757) 6758(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem) 6759 (dni (.sym op mach wstr -dst-dspsp- dstgroup) 6760 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) 6761 ((machine mach)) 6762 (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") 6763 encoding 6764 (sem mach mode (.sym dst mach - dstgroup - mode) dsp) 6765 ()) 6766) 6767 6768; m16c variants 6769(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) 6770 (begin 6771 (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op 6772 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) 6773 sem) 6774 (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op 6775 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) 6776 sem) 6777 (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op 6778 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) 6779 sem) 6780 ) 6781) 6782 6783(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) 6784 (begin 6785 (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op 6786 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) 6787 sem) 6788 (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op 6789 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) 6790 sem) 6791 (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op 6792 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) 6793 sem) 6794 ) 6795) 6796 6797; m32c variants 6798(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) 6799 (begin 6800 (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op 6801 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) 6802 sem) 6803 (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op 6804 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) 6805 sem) 6806 (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op 6807 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) 6808 sem) 6809 (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op 6810 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) 6811 sem) 6812 ) 6813) 6814(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) 6815 (begin 6816 (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op 6817 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) 6818 sem) 6819 (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op 6820 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) 6821 sem) 6822 (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op 6823 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) 6824 sem) 6825 (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op 6826 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) 6827 sem) 6828 ) 6829) 6830 6831(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem) 6832 (begin 6833 (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem)) 6834 (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem)) 6835 ) 6836) 6837 6838(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem) 6839 (begin 6840 (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem)) 6841 (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem)) 6842 ) 6843) 6844 6845(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6846 (begin 6847 (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem) 6848 (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem) 6849 ) 6850) 6851(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6852 (begin 6853 (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem) 6854 (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem) 6855 ) 6856) 6857 6858;------------------------------------------------------------- 6859; lde dsp24,dst -- for m16c 6860;------------------------------------------------------------- 6861 6862(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) 6863 (begin 6864 6865 (dni (.sym lde wstr - dstgroup -u20) 6866 (.str "lde" wstr "-" dstgroup "-u20") 6867 ((machine 16)) 6868 (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") 6869 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) 6870 (.sym dst16- dstgroup - mode) srcdisp) 6871 (nop) 6872 ()) 6873 6874 (dni (.sym lde wstr - dstgroup -u20a0) 6875 (.str "lde" wstr "-" dstgroup "-u20a0") 6876 ((machine 16)) 6877 (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") 6878 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) 6879 (.sym dst16- dstgroup - mode) srcdisp) 6880 (nop) 6881 ()) 6882 6883 (dni (.sym lde wstr - dstgroup -a1a0) 6884 (.str "lde" wstr "-" dstgroup "-a1a0") 6885 ((machine 16)) 6886 (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") 6887 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) 6888 (.sym dst16- dstgroup - mode)) 6889 (nop) 6890 ()) 6891 ) 6892 ) 6893 6894(define-pmacro (lde-dst mode wstr wbit) 6895 (begin 6896 ; like: QI .b 0 6897 (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) 6898 (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) 6899 (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) 6900 ) 6901) 6902 6903;------------------------------------------------------------- 6904; ste dst,dsp24 -- for m16c 6905;------------------------------------------------------------- 6906 6907(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) 6908 (begin 6909 6910 (dni (.sym ste wstr - dstgroup -u20) 6911 (.str "ste" wstr "-" dstgroup "-u20") 6912 ((machine 16)) 6913 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") 6914 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) 6915 (.sym dst16- dstgroup - mode) srcdisp) 6916 (nop) 6917 ()) 6918 6919 (dni (.sym ste wstr - dstgroup -u20a0) 6920 (.str "ste" wstr "-" dstgroup "-u20a0") 6921 ((machine 16)) 6922 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") 6923 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) 6924 (.sym dst16- dstgroup - mode) srcdisp) 6925 (nop) 6926 ()) 6927 6928 (dni (.sym ste wstr - dstgroup -a1a0) 6929 (.str "ste" wstr "-" dstgroup "-a1a0") 6930 ((machine 16)) 6931 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") 6932 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) 6933 (.sym dst16- dstgroup - mode)) 6934 (nop) 6935 ()) 6936 ) 6937 ) 6938 6939(define-pmacro (ste-dst mode wstr wbit) 6940 (begin 6941 ; like: QI .b 0 6942 (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) 6943 (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) 6944 (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) 6945 ) 6946) 6947 6948;============================================================= 6949; Division 6950;------------------------------------------------------------- 6951 6952(define-pmacro (div-sem divop modop opmode reg src quot rem max min) 6953 (sequence () 6954 (if (eq src 0) 6955 (set obit (const BI 1)) 6956 (sequence ((opmode quot-result) (opmode rem-result)) 6957 (set quot-result (divop opmode (ext opmode reg) src)) 6958 (set rem-result (modop opmode (ext opmode reg) src)) 6959 (set obit (orif (gt opmode quot-result max) 6960 (lt opmode quot-result min))) 6961 (set quot quot-result) 6962 (set rem rem-result)))) 6963) 6964 6965;<divop>.size #imm -- for m16c and m32c 6966(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) 6967 (dni (.sym op mach wstr - src) 6968 (.str op mach wstr "-" src) 6969 ((machine mach)) 6970 (.str op wstr " #${" src "}") 6971 encoding 6972 (sem divop modop opmode reg src quot rem max min) 6973 ()) 6974) 6975(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) 6976 (div-imm-defn 16 wstr op (.sym Imm-16 - smode) 6977 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode)) 6978 divop modop opmode reg quot rem max min 6979 sem) 6980) 6981(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) 6982 (div-imm-defn 32 wstr op (.sym Imm-16 - smode) 6983 (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode)) 6984 divop modop opmode reg quot rem max min 6985 sem) 6986) 6987(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem) 6988 (begin 6989 (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem)) 6990 (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem)) 6991 ) 6992) 6993(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem) 6994 (begin 6995 (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem) 6996 (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem) 6997 ) 6998) 6999 7000;<divop>.size src -- for m16c and m32c 7001(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) 7002 (dni (.sym op mach wstr - src) 7003 (.str op mach wstr "-" src) 7004 ((machine mach)) 7005 (.str op wstr " ${" src "}") 7006 encoding 7007 (sem divop modop opmode reg src quot rem max min) 7008 ()) 7009) 7010(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) 7011 (div-src-defn 16 wstr op (.sym dst16-16 - smode) 7012 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode)) 7013 divop modop opmode reg quot rem max min 7014 sem) 7015) 7016(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) 7017 (begin 7018 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 7019 ; define the absolute-indirect insns first in order to prevent them from being selected 7020 ; when the mode is register-indirect 7021; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode) 7022; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode)) 7023; divop modop opmode reg quot rem max min 7024; sem) 7025 (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode) 7026 (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode)) 7027 divop modop opmode reg quot rem max min 7028 sem) 7029; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode) 7030; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode)) 7031; divop modop opmode reg quot rem max min 7032; sem) 7033 ) 7034) 7035(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem) 7036 (begin 7037 (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem)) 7038 (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem)) 7039 ) 7040) 7041(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7042 (begin 7043 (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem) 7044 (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem) 7045 ) 7046) 7047 7048;============================================================= 7049; Bit manipulation 7050; 7051(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem) 7052 (dni (.sym op mach - suffix - opnd) 7053 (.str op mach ":" suffix " " opnd) 7054 ((machine mach)) 7055 (.str op "$" suffix " ${" opnd "}") 7056 encoding 7057 (sem opnd) 7058 ()) 7059) 7060 7061(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem) 7062 (bit-insn-defn 16 op X bit16-16 7063 (+ opc1 opc2 opc3 bit16-16) 7064 sem) 7065) 7066 7067(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem) 7068 (begin 7069 (bit-insn-defn 32 op X bit32-24-Prefixed 7070 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3)) 7071 sem) 7072 ) 7073) 7074 7075(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7076 (begin 7077 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) 7078 (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem) 7079 ) 7080) 7081 7082(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem) 7083 (begin 7084 (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem) 7085 (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem) 7086 (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem) 7087 (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem) 7088 ) 7089) 7090 7091(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem) 7092 (begin 7093 (bit-insn-defn 32 op X bit32-16-Unprefixed 7094 (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3)) 7095 sem) 7096 ) 7097) 7098 7099(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7100 (begin 7101 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) 7102 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) 7103 ) 7104) 7105 7106(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem) 7107 (begin 7108 (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem) 7109 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) 7110 ) 7111) 7112 7113;============================================================= 7114; Bit condition 7115; 7116(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem) 7117 (dni (.sym op mach - bit-opnd - cond-opnd) 7118 (.str op mach " " bit-opnd " " cond-opnd) 7119 ((machine mach)) 7120 (.str op "${" cond-opnd "} ${" bit-opnd "}") 7121 encoding 7122 (sem mach bit-opnd cond-opnd) 7123 ()) 7124) 7125 7126(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem) 7127 (begin 7128 (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem) 7129 (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem) 7130 (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem) 7131 ) 7132) 7133 7134(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem) 7135 (begin 7136 (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40 7137 (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40) 7138 sem) 7139 (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32 7140 (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32) 7141 sem) 7142 (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24 7143 (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24) 7144 sem) 7145 (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16 7146 (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16) 7147 sem) 7148 ) 7149) 7150 7151(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7152 (begin 7153 (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem) 7154 (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem) 7155 ) 7156) 7157 7158;============================================================= 7159;<insn>.size #imm1,#imm2,dst -- for m32c 7160; 7161(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem) 7162 (dni (.sym op 32 wstr - src1 - src2 - dstgroup) 7163 (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode) 7164 ((machine 32)) 7165 (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}") 7166 encoding 7167 (sem xmode src1 src2 (.sym dst32- dstgroup - xmode)) 7168 ()) 7169) 7170 7171; m32c Prefixed variants 7172(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) 7173 (begin 7174 (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op 7175 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7176 (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode)) 7177 sem) 7178 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op 7179 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7180 (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode)) 7181 sem) 7182 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op 7183 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7184 (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode)) 7185 sem) 7186 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op 7187 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7188 (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode)) 7189 sem) 7190 ) 7191) 7192 7193; m32c Unprefixed variants 7194(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) 7195 (begin 7196 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op 7197 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7198 (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode)) 7199 sem) 7200 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op 7201 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7202 (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode)) 7203 sem) 7204 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op 7205 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7206 (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode)) 7207 sem) 7208 (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op 7209 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7210 (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode)) 7211 sem) 7212 ) 7213) 7214 7215(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem) 7216 (begin 7217 (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) 7218 (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem) 7219 ) 7220) 7221(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem) 7222 (begin 7223 (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem) 7224 (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) 7225 ) 7226) 7227 7228;============================================================= 7229; Insn definitions 7230;------------------------------------------------------------- 7231; abs - absolute 7232;------------------------------------------------------------- 7233 7234(define-pmacro (abs-sem mode dst) 7235 (sequence ((mode result)) 7236 (set result (abs mode dst)) 7237 (set obit (eq result dst)) 7238 (set-z-and-s result) 7239 (set dst result)) 7240) 7241(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem) 7242 7243;------------------------------------------------------------- 7244; adcf - addition carry flag 7245;------------------------------------------------------------- 7246 7247(define-pmacro (adcf-sem mode dst) 7248 (sequence ((mode result)) 7249 (set result (addc mode dst 0 cbit)) 7250 (set obit (add-oflag mode dst 0 cbit)) 7251 (set cbit (add-cflag mode dst 0 cbit)) 7252 (set-z-and-s result) 7253 (set dst result)) 7254) 7255(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem) 7256 7257;------------------------------------------------------------- 7258; add - binary addition 7259;------------------------------------------------------------- 7260 7261(define-pmacro (add-sem mode src1 dst) 7262 (sequence ((mode result)) 7263 (set result (add mode src1 dst)) 7264 (set obit (add-oflag mode src1 dst 0)) 7265 (set cbit (add-cflag mode src1 dst 0)) 7266 (set-z-and-s result) 7267 (set dst result)) 7268) 7269 7270; add.L:G #imm32,dst (m32 #2) 7271(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem) 7272; add.size:G #imm,dst (m16 #1 m32 #1) 7273(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem) 7274; add.size:Q #imm4,dst (m16 #2 m32 #3) 7275(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem) 7276(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem) 7277; add.b:S #imm8,dst3 (m16 #3) 7278(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) 7279; add.BW:Q #imm4,sp (m16 #7) 7280(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) 7281(dnmi add16-bQ-sp "add16-bQ-sp" () 7282 "add.b:q #${Imm-12-s4},sp" 7283 (emit add16-wQ-sp Imm-12-s4)) 7284; add.BW:G #imm,sp (m16 #6) 7285(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) 7286; add.BW:G src,dst (m16 #4 m32 #6) 7287(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem) 7288; add.B.S src2,r0l/r0h (m16 #5) 7289(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem) 7290; add.L:G src,dst (m32 #7) 7291(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem) 7292; add.L:S #imm{1,2},A0/A1 (m32 #5) 7293(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem) 7294; add.L:Q #imm3,sp (m32 #9) 7295(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem) 7296; add.L:S #imm8,sp (m32 #10) 7297(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem) 7298; add.L:G #imm16,sp (m32 #8) 7299(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem) 7300; add.BW:S #imm,dst2 (m32 #4) 7301(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem) 7302(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem) 7303 7304;------------------------------------------------------------- 7305; adc - binary add with carry 7306;------------------------------------------------------------- 7307 7308(define-pmacro (addc-sem mode src dst) 7309 (sequence ((mode result)) 7310 (set result (addc mode src dst cbit)) 7311 (set obit (add-oflag mode src dst cbit)) 7312 (set cbit (add-cflag mode src dst cbit)) 7313 (set-z-and-s result) 7314 (set dst result)) 7315) 7316 7317; adc.size:G #imm,dst 7318(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) 7319(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) 7320(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem) 7321(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem) 7322 7323; adc.BW:G src,dst 7324(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) 7325(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) 7326(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem) 7327(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem) 7328 7329;------------------------------------------------------------- 7330; dadc - decimal add with carry 7331; dadd - decimal addition 7332;------------------------------------------------------------- 7333 7334(define-pmacro (dadc-sem mode src dst) 7335 (sequence ((mode result)) 7336 (set result (subc mode dst src (not cbit))) 7337 (set cbit (sub-cflag mode dst src (not cbit))) 7338 (set-z-and-s result) 7339 (set dst result)) 7340) 7341 7342(define-pmacro (decimal-subtraction16-insn op opc1 opc2) 7343 (begin 7344 ; op.b #imm8,r0l 7345 (dni (.sym op 16.b-imm8) 7346 (.str op ".b #imm8") 7347 ((machine 16)) 7348 (.str op ".b #${Imm-16-QI},r0l") 7349 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) 7350 ((.sym op -sem) QI Imm-16-QI R0l) 7351 ()) 7352 ; op.w #imm16,r0 7353 (dni (.sym op 16.w-imm16) 7354 (.str op ".b #imm16") 7355 ((machine 16)) 7356 (.str op ".w #${Imm-16-HI},r0") 7357 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) 7358 ((.sym op -sem) HI Imm-16-HI R0) 7359 ()) 7360 ; op.b #r0h,r0l 7361 (dni (.sym op 16.b-r0h-r0l) 7362 (.str op ".b r0h,r0l") 7363 ((machine 16)) 7364 (.str op ".b r0h,r0l") 7365 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2)) 7366 ((.sym op -sem) QI R0h R0l) 7367 ()) 7368 ; op.w #r1,r0 7369 (dni (.sym op 16.w-r1-r0) 7370 (.str op ".b r1,r0") 7371 ((machine 16)) 7372 (.str op ".w r1,r0") 7373 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2)) 7374 ((.sym op -sem) HI R1 R0) 7375 ()) 7376 ) 7377) 7378 7379; dadc for m16c 7380(decimal-subtraction16-insn dadc #xE #x6 ) 7381 7382; dadc.size #imm,dst 7383(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem) 7384(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem) 7385; dadc.BW src,dst 7386(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem) 7387(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem) 7388 7389(define-pmacro (dadd-sem mode src dst) 7390 (sequence ((mode result)) 7391 (set result (subc mode dst src 0)) 7392 (set cbit (sub-cflag mode dst src 0)) 7393 (set-z-and-s result) 7394 (set dst result)) 7395) 7396 7397; dadd for m16c 7398(decimal-subtraction16-insn dadd #xC #x4) 7399 7400; dadd.size #imm,dst 7401(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem) 7402(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem) 7403; dadd.BW src,dst 7404(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem) 7405(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem) 7406 7407;-------------------------------------------------------------; 7408; addx - Add extend sign with no carry 7409;-------------------------------------------------------------; 7410 7411(define-pmacro (addx-sem mode src dst) 7412 (sequence ((SI source) (SI result)) 7413 (set source (zext SI (trunc QI src))) 7414 (set result (add SI source dst)) 7415 (set obit (add-oflag SI source dst 0)) 7416 (set cbit (add-cflag SI source dst 0)) 7417 (set-z-and-s result) 7418 (set dst result)) 7419) 7420 7421; addx #imm,dst 7422(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem) 7423; addx src,dst 7424(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem) 7425 7426;------------------------------------------------------------- 7427; adjnz - Add/Sub and branch if not zero 7428;------------------------------------------------------------- 7429 7430(define-pmacro (arith-jnz-sem mode src dst label) 7431 (sequence ((mode result)) 7432 (set result (add mode src dst)) 7433 (set dst result) 7434 (if (ne result 0) 7435 (set pc label))) 7436) 7437 7438; adjnz.size #imm4,dst,label 7439(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) 7440 7441;------------------------------------------------------------- 7442; and - binary and 7443;------------------------------------------------------------- 7444 7445(define-pmacro (and-sem mode src1 dst) 7446 (sequence ((mode result)) 7447 (set result (and mode src1 dst)) 7448 (set-z-and-s result) 7449 (set dst result)) 7450) 7451 7452; and.size:G #imm,dst (m16 #1 m32 #1) 7453(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem) 7454; and.b:S #imm8,dst3 (m16 #2) 7455(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem) 7456; and.BW:G src,dst (m16 #3 m32 #3) 7457(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem) 7458; and.B.S src2,r0l/r0h (m16 #4) 7459(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem) 7460; and.BW:S #imm,dst2 (m32 #2) 7461(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem) 7462(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem) 7463 7464;------------------------------------------------------------- 7465; band - bit and 7466;------------------------------------------------------------- 7467 7468(define-pmacro (band-sem src) 7469 (set cbit (and src cbit)) 7470) 7471(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem) 7472 7473;------------------------------------------------------------- 7474; bclr - bit clear 7475;------------------------------------------------------------- 7476 7477(define-pmacro (bclr-sem dst) 7478 (set dst 0) 7479) 7480(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem) 7481 7482;------------------------------------------------------------- 7483; bitindex - bit index 7484;------------------------------------------------------------- 7485 7486(define-pmacro (bitindex-sem mode dst) 7487 (set BitIndex dst) 7488) 7489(unary-insn-defn 32 16-Unprefixed QI .b bitindex 7490 (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE)) 7491 bitindex-sem) 7492(unary-insn-defn 32 16-Unprefixed HI .w bitindex 7493 (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE)) 7494 bitindex-sem) 7495 7496;------------------------------------------------------------- 7497; bmCnd - bit move condition 7498;------------------------------------------------------------- 7499 7500(define-pmacro (test-condition16 cond) 7501 (case UQI cond 7502 ((#x00) (trunc BI cbit)) 7503 ((#x01) (not (or cbit zbit))) 7504 ((#x02) (trunc BI zbit)) 7505 ((#x03) (trunc BI sbit)) 7506 ((#x04) (or zbit (xor sbit obit))) 7507 ((#x05) (trunc BI obit)) 7508 ((#x06) (xor sbit obit)) 7509 ((#xf8) (not cbit)) 7510 ((#xf9) (or cbit zbit)) 7511 ((#xfa) (not zbit)) 7512 ((#xfb) (not sbit)) 7513 ((#xfc) (not (or zbit (xor sbit obit)))) 7514 ((#xfd) (not obit)) 7515 ((#xfe) (not (xor sbit obit))) 7516 (else (const BI 0)) 7517 ) 7518) 7519 7520(define-pmacro (test-condition32 cond) 7521 (case UQI cond 7522 ((#x00) (not cbit)) 7523 ((#x01) (or cbit zbit)) 7524 ((#x02) (not zbit)) 7525 ((#x03) (not sbit)) 7526 ((#x04) (not obit)) 7527 ((#x05) (not (or zbit (xor sbit obit)))) 7528 ((#x06) (not (xor sbit obit))) 7529 ((#x08) (trunc BI cbit)) 7530 ((#x09) (not (or cbit zbit))) 7531 ((#x0a) (trunc BI zbit)) 7532 ((#x0b) (trunc BI sbit)) 7533 ((#x0c) (trunc BI obit)) 7534 ((#x0d) (or zbit (xor sbit obit))) 7535 ((#x0e) (xor sbit obit)) 7536 (else (const BI 0)) 7537 ) 7538) 7539 7540(define-pmacro (bitcond-sem mach op cond) 7541 (if ((.sym test-condition mach) cond) 7542 (set op 1) 7543 (set op 0)) 7544) 7545(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem) 7546 7547(dni bm16-c 7548 "bm16 C" 7549 ((machine 16)) 7550 "bm$cond16c c" 7551 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c) 7552 (bitcond-sem 16 cbit cond16c) 7553 ()) 7554 7555(dni bm32-c 7556 "bm32 C" 7557 ((machine 32)) 7558 "bm$cond32 c" 7559 (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32) 7560 (bitcond-sem 32 cbit cond32) 7561 ()) 7562 7563;------------------------------------------------------------- 7564; bnand 7565;------------------------------------------------------------- 7566 7567(define-pmacro (bnand-sem src) 7568 (set cbit (and (inv src) cbit)) 7569) 7570(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem) 7571 7572;------------------------------------------------------------- 7573; bnor 7574;------------------------------------------------------------- 7575 7576(define-pmacro (bnor-sem src) 7577 (set cbit (or (inv src) cbit)) 7578) 7579(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem) 7580 7581;------------------------------------------------------------- 7582; bnot 7583;------------------------------------------------------------- 7584 7585(define-pmacro (bnot-sem dst) 7586 (set dst (inv dst)) 7587) 7588(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem) 7589 7590;------------------------------------------------------------- 7591; bntst 7592;------------------------------------------------------------- 7593 7594(define-pmacro (bntst-sem src) 7595 (set cbit (inv src)) 7596 (set zbit (inv src)) 7597) 7598(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem) 7599 7600;------------------------------------------------------------- 7601; bnxor 7602;------------------------------------------------------------- 7603 7604(define-pmacro (bnxor-sem src) 7605 (set cbit (xor (inv src) cbit)) 7606) 7607(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem) 7608 7609;------------------------------------------------------------- 7610; bor 7611;------------------------------------------------------------- 7612 7613(define-pmacro (bor-sem src) 7614 (set cbit (or src cbit)) 7615) 7616(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem) 7617 7618;------------------------------------------------------------- 7619; brk 7620;------------------------------------------------------------- 7621 7622(dni brk16 7623 "brk" 7624 ((machine 16)) 7625 "brk" 7626 (+ (f-0-4 #x0) (f-4-4 #x0)) 7627 (nop) 7628 ()) 7629 7630(dni brk32 7631 "brk" 7632 ((machine 32)) 7633 "brk" 7634 (+ (f-0-4 #x0) (f-4-4 #x0)) 7635 (nop) 7636 ()) 7637 7638;------------------------------------------------------------- 7639; brk2 7640;------------------------------------------------------------- 7641 7642(dni brk232 7643 "brk2" 7644 ((machine 32)) 7645 "brk2" 7646 (+ (f-0-4 #x0) (f-4-4 #x8)) 7647 (nop) 7648 ()) 7649 7650;------------------------------------------------------------- 7651; bset 7652;------------------------------------------------------------- 7653 7654(define-pmacro (bset-sem dst) 7655 (set dst 1) 7656) 7657(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem) 7658 7659;------------------------------------------------------------- 7660; btst 7661;------------------------------------------------------------- 7662 7663(define-pmacro (btst-sem dst) 7664 (set zbit (inv dst)) 7665 (set cbit dst) 7666) 7667(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem) 7668 7669(bit-insn-defn 32 btst G bit32-16-Unprefixed 7670 (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0)) 7671 btst-sem) 7672 7673(dni btst.s "btst:s" ((machine 32)) 7674 "btst:s ${Bit3-S},${Dsp-8-u16}" 7675 (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16) 7676 () ()) 7677 7678;------------------------------------------------------------- 7679; btstc 7680;------------------------------------------------------------- 7681 7682(define-pmacro (btstc-sem dst) 7683 (set zbit (inv dst)) 7684 (set cbit dst) 7685 (set dst (const 0)) 7686) 7687(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem) 7688 7689;------------------------------------------------------------- 7690; btsts 7691;------------------------------------------------------------- 7692 7693(define-pmacro (btsts-sem dst) 7694 (set zbit (inv dst)) 7695 (set cbit dst) 7696 (set dst (const 0)) 7697) 7698(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem) 7699 7700;------------------------------------------------------------- 7701; bxor 7702;------------------------------------------------------------- 7703 7704(define-pmacro (bxor-sem src) 7705 (set cbit (xor src cbit)) 7706) 7707(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem) 7708 7709;------------------------------------------------------------- 7710; clip 7711;------------------------------------------------------------- 7712 7713(define-pmacro (clip-sem mode imm1 imm2 dest) 7714 (sequence () 7715 (if (gt mode imm1 dest) 7716 (set dest imm1)) 7717 (if (lt mode imm2 dest) 7718 (set dest imm2))) 7719) 7720 7721(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem) 7722 7723;------------------------------------------------------------- 7724; cmp - binary compare 7725;------------------------------------------------------------- 7726 7727(define-pmacro (cmp-sem mode src1 dst) 7728 (sequence ((mode result)) 7729 (set result (sub mode dst src1)) 7730 (set obit (sub-oflag mode dst src1 0)) 7731 (set cbit (not (sub-cflag mode dst src1 0))) 7732 (set-z-and-s result)) 7733) 7734 7735; cmp.L:G #imm32,dst (m32 #2) 7736(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem) 7737; cmp.size:G #imm,dst (m16 #1 m32 #1) 7738(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem) 7739; cmp.size:Q #imm4,dst (m16 #2 m32 #3) 7740(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem) 7741; cmp.b:S #imm8,dst3 (m16 #3) 7742(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem) 7743; cmp.BW:G src,dst (m16 #4 m32 #5) 7744(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem) 7745; cmp.B.S src2,r0l/r0h (m16 #5) 7746(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem) 7747; cmp.L:G src,dst (m32 #6) 7748(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem) 7749; cmp.BW:S #imm,dst2 (m32 #4) 7750(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem) 7751(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem) 7752; cmp.BW:s src2,r0[l] (m32 #7) 7753(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem) 7754(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem) 7755 7756;------------------------------------------------------------- 7757; cmpx - binary compare extend sign 7758;------------------------------------------------------------- 7759 7760(define-pmacro (cmpx-sem mode src1 dst) 7761 (sequence ((mode result)) 7762 (set result (sub mode dst (ext mode src1))) 7763 (set obit (sub-oflag mode dst (ext mode src1) 0)) 7764 (set cbit (sub-cflag mode dst (ext mode src1) 0)) 7765 (set-z-and-s result)) 7766) 7767 7768(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem) 7769 7770;------------------------------------------------------------- 7771; dec - decrement 7772;------------------------------------------------------------- 7773 7774(define-pmacro (dec-sem mode dest) 7775 (sequence ((mode result)) 7776 (set result (sub mode dest 1)) 7777 (set-z-and-s result) 7778 (set dest result)) 7779) 7780 7781(dni dec16.b 7782 "dec.b Dst16-3-S-8" 7783 ((machine 16)) 7784 "dec.b ${Dst16-3-S-8}" 7785 (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8) 7786 (dec-sem QI Dst16-3-S-8) 7787 ()) 7788 7789(dni dec16.w 7790 "dec.w Dst16An-S" 7791 ((machine 16)) 7792 "dec.w ${Dst16An-S}" 7793 (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S) 7794 (dec-sem HI Dst16An-S) 7795 ()) 7796 7797(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem) 7798(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem) 7799 7800;------------------------------------------------------------- 7801; div - divide 7802; divu - divide unsigned 7803; divx - divide extension 7804;------------------------------------------------------------- 7805 7806; div.BW #imm 7807(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem) 7808(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem) 7809(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem) 7810; div.BW src 7811(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem) 7812(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem) 7813(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem) 7814 7815(div-src-defn 32 .l div dst32-24-Prefixed-SI 7816 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI) 7817 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) 7818 div-sem) 7819(div-src-defn 32 .l divu dst32-24-Prefixed-SI 7820 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI) 7821 udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0 7822 div-sem) 7823(div-src-defn 32 .l divx dst32-24-Prefixed-SI 7824 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI) 7825 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) 7826 div-sem) 7827 7828;------------------------------------------------------------- 7829; dsbb - decimal subtraction with borrow 7830; dsub - decimal subtraction 7831;------------------------------------------------------------- 7832 7833(define-pmacro (dsbb-sem mode src dst) 7834 (sequence ((mode result)) 7835 (set result (subc mode dst src (not cbit))) 7836 (set cbit (sub-cflag mode dst src (not cbit))) 7837 (set-z-and-s result) 7838 (set dst result)) 7839) 7840 7841; dsbb for m16c 7842(decimal-subtraction16-insn dsbb #xF #x7) 7843 7844; dsbb.size #imm,dst 7845(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem) 7846(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem) 7847; dsbb.BW src,dst 7848(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem) 7849(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem) 7850 7851(define-pmacro (dsub-sem mode src dst) 7852 (sequence ((mode result)) 7853 (set result (subc mode dst src 0)) 7854 (set cbit (sub-cflag mode dst src 0)) 7855 (set-z-and-s result) 7856 (set dst result)) 7857) 7858 7859; dsub for m16c 7860(decimal-subtraction16-insn dsub #xD #x5) 7861 7862; dsub.size #imm,dst 7863(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem) 7864(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem) 7865; dsub.BW src,dst 7866(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem) 7867(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem) 7868 7869;------------------------------------------------------------- 7870; sub - binary subtraction 7871;------------------------------------------------------------- 7872 7873(define-pmacro (sub-sem mode src1 dst) 7874 (sequence ((mode result)) 7875 (set result (sub mode dst src1)) 7876 (set obit (sub-oflag mode dst src1 0)) 7877 (set cbit (sub-cflag mode dst src1 0)) 7878 (set dst result) 7879 (set-z-and-s result))) 7880 7881; sub.size:G #imm,dst (m16 #1 m32 #1) 7882(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem) 7883; sub.b:S #imm8,dst3 (m16 #2) 7884(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem) 7885; sub.BW:G src,dst (m16 #3 m32 #4) 7886(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem) 7887; sub.B.S src2,r0l/r0h (m16 #4) 7888(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem) 7889; sub.L:G #imm32,dst (m32 #2) 7890(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem) 7891; sub.BW:S #imm,dst2 (m32 #3) 7892(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem) 7893(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem) 7894; sub.L:G src,dst (m32 #5) 7895(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem) 7896 7897;------------------------------------------------------------- 7898; enter - enter function 7899; exitd - exit and deallocate stack frame 7900;------------------------------------------------------------- 7901 7902(define-pmacro (enter16-sem mach amt) 7903 (sequence () 7904 (set (reg h-sp) (sub (reg h-sp) 2)) 7905 (set (mem16 HI (reg h-sp)) (reg h-fb)) 7906 (set (reg h-fb) (reg h-sp)) 7907 (set (reg h-sp) (sub (reg h-sp) amt)))) 7908 7909(define-pmacro (exit16-sem mach) 7910 (sequence ((SI newpc)) 7911 (set (reg h-sp) (reg h-fb)) 7912 (set (reg h-fb) (mem16 HI (reg h-sp))) 7913 (set (reg h-sp) (add (reg h-sp) 2)) 7914 (set newpc (mem16 HI (reg h-sp))) 7915 (set (reg h-sp) (add (reg h-sp) 2)) 7916 (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16)))) 7917 (set (reg h-sp) (add (reg h-sp) 1)) 7918 (set pc newpc))) 7919 7920(define-pmacro (enter32-sem mach amt) 7921 (sequence () 7922 (set (reg h-sp) (sub (reg h-sp) 4)) 7923 (set (mem32 SI (reg h-sp)) (reg h-fb)) 7924 (set (reg h-fb) (reg h-sp)) 7925 (set (reg h-sp) (sub (reg h-sp) amt)))) 7926 7927(define-pmacro (exit32-sem mach) 7928 (sequence ((SI newpc)) 7929 (set (reg h-sp) (reg h-fb)) 7930 (set (reg h-fb) (mem32 SI (reg h-sp))) 7931 (set (reg h-sp) (add (reg h-sp) 4)) 7932 (set newpc (mem32 SI (reg h-sp))) 7933 (set (reg h-sp) (add (reg h-sp) 4)) 7934 (set pc newpc))) 7935 7936(dni enter16 "enter #Imm-16-QI" ((machine 16)) 7937 ("enter #${Dsp-16-u8}") 7938 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8) 7939 (enter16-sem 16 Dsp-16-u8) 7940 ()) 7941 7942(dni exitd16 "exitd" ((machine 16)) 7943 ("exitd") 7944 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2)) 7945 (exit16-sem 16) 7946 ()) 7947 7948(dni enter32 "enter #Imm-8-QI" ((machine 32)) 7949 ("enter #${Dsp-8-u8}") 7950 (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8) 7951 (enter32-sem 32 Dsp-8-u8) 7952 ()) 7953 7954(dni exitd32 "exitd" ((machine 32)) 7955 ("exitd") 7956 (+ (f-0-4 #xF) (f-4-4 #xC)) 7957 (exit32-sem 32) 7958 ()) 7959 7960;------------------------------------------------------------- 7961; fclr - flag register clear 7962; fset - flag register set 7963;------------------------------------------------------------- 7964 7965(define-pmacro (set-flags-sem flag) 7966 (sequence ((SI tmp)) 7967 (case DFLT flag 7968 ((#x0) (set cbit 1)) 7969 ((#x1) (set dbit 1)) 7970 ((#x2) (set zbit 1)) 7971 ((#x3) (set sbit 1)) 7972 ((#x4) (set bbit 1)) 7973 ((#x5) (set obit 1)) 7974 ((#x6) (set ibit 1)) 7975 ((#x7) (set ubit 1))) 7976 ) 7977 ) 7978 7979(define-pmacro (clear-flags-sem flag) 7980 (sequence ((SI tmp)) 7981 (case DFLT flag 7982 ((#x0) (set cbit 0)) 7983 ((#x1) (set dbit 0)) 7984 ((#x2) (set zbit 0)) 7985 ((#x3) (set sbit 0)) 7986 ((#x4) (set bbit 0)) 7987 ((#x5) (set obit 0)) 7988 ((#x6) (set ibit 0)) 7989 ((#x7) (set ubit 0))) 7990 ) 7991 ) 7992 7993(dni fclr16 "fclr flag" ((machine 16)) 7994 ("fclr ${flags16}") 7995 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5)) 7996 (clear-flags-sem flags16) 7997 ()) 7998 7999(dni fset16 "fset flag" ((machine 16)) 8000 ("fset ${flags16}") 8001 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4)) 8002 (set-flags-sem flags16) 8003 ()) 8004 8005(dni fclr "fclr" ((machine 32)) 8006 ("fclr ${flags32}") 8007 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32) 8008 (clear-flags-sem flags32) 8009 ()) 8010 8011(dni fset "fset" ((machine 32)) 8012 ("fset ${flags32}") 8013 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32) 8014 (set-flags-sem flags32) 8015 ()) 8016 8017;------------------------------------------------------------- 8018; inc - increment 8019;------------------------------------------------------------- 8020 8021(define-pmacro (inc-sem mode dest) 8022 (sequence ((mode result)) 8023 (set result (add mode dest 1)) 8024 (set-z-and-s result) 8025 (set dest result)) 8026) 8027 8028(dni inc16.b 8029 "inc.b Dst16-3-S-8" 8030 ((machine 16)) 8031 "inc.b ${Dst16-3-S-8}" 8032 (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8) 8033 (inc-sem QI Dst16-3-S-8) 8034 ()) 8035 8036(dni inc16.w 8037 "inc.w Dst16An-S" 8038 ((machine 16)) 8039 "inc.w ${Dst16An-S}" 8040 (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S) 8041 (inc-sem HI Dst16An-S) 8042 ()) 8043 8044(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem) 8045(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem) 8046 8047;------------------------------------------------------------- 8048; freit - fast return from interrupt (m32) 8049; int - interrupt 8050; into - interrupt on overflow 8051;------------------------------------------------------------- 8052 8053; ??? semantics 8054(dni freit32 "FREIT" ((machine 32)) 8055 ("freit") 8056 (+ (f-0-4 9) (f-4-4 #xF)) 8057 (nop) 8058 ()) 8059 8060(dni int16 "int Dsp-10-u6" ((machine 16)) 8061 ("int #${Dsp-10-u6}") 8062 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6) 8063 (c-call VOID "do_int" pc Dsp-10-u6) 8064 ()) 8065 8066(dni into16 "into" ((machine 16)) 8067 ("into") 8068 (+ (f-0-4 #xF) (f-4-4 6)) 8069 (nop) 8070 ()) 8071 8072(dni int32 "int Dsp-8-u6" ((machine 32)) 8073 ("int #${Dsp-8-u6}") 8074 (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0)) 8075 (c-call VOID "do_int" pc Dsp-8-u6) 8076 ()) 8077 8078(dni into32 "into" ((machine 32)) 8079 ("into") 8080 (+ (f-0-4 #xB) (f-4-4 #xF)) 8081 (nop) 8082 ()) 8083 8084;------------------------------------------------------------- 8085; index (m32c) 8086;------------------------------------------------------------- 8087 8088; TODO add support to insns allowing index 8089(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d)) 8090(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d)) 8091(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0))) 8092(define-pmacro (indexw-sem mode d) 8093 (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2)))) 8094(define-pmacro (indexwd-sem mode d) 8095 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) 8096(define-pmacro (indexws-sem mode d) 8097 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) 8098(define-pmacro (indexl-sem mode d) 8099 (set SrcIndex d) (set DstIndex (sll d (const 2)))) 8100(define-pmacro (indexld-sem mode d) 8101 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) 8102(define-pmacro (indexls-sem mode d) 8103 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) 8104 8105; Note that "wbit" not where the size bit goes here, hence, it's 8106; always 0 in these calls but op2 differs instead. 8107 8108; indexb src (index byte) 8109(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) 8110(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) 8111; indexbd src (index byte dest) 8112(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) 8113(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) 8114; indexbs src (index byte src) 8115(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) 8116(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) 8117; indexl src (index long) 8118(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) 8119(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) 8120; indexld src (index long dest) 8121(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) 8122(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) 8123; indexls src (index long src) 8124(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) 8125(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) 8126; indexw src (index word) 8127(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) 8128(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) 8129; indexwd src (index word dest) 8130(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) 8131(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) 8132; indexws (index word src) 8133(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) 8134(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) 8135 8136;------------------------------------------------------------- 8137; jcc - jump on condition 8138;------------------------------------------------------------- 8139 8140(define-pmacro (jcnd32-sem cnd label) 8141 (sequence () 8142 (case DFLT cnd 8143 ((#x00) (if (not cbit) (set pc label))) ;ltu nc 8144 ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu 8145 ((#x02) (if (not zbit) (set pc label))) ;ne nz 8146 ((#x03) (if (not sbit) (set pc label))) ;pz 8147 ((#x04) (if (not obit) (set pc label))) ;no 8148 ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt 8149 ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge 8150 ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c 8151 ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu 8152 ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z 8153 ((#x0b) (if (trunc BI sbit) (set pc label))) ;n 8154 ((#x0c) (if (trunc BI obit) (set pc label))) ;o 8155 ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le 8156 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt 8157 ) 8158 ) 8159 ) 8160 8161(define-pmacro (jcnd16-sem cnd label) 8162 (sequence () 8163 (case DFLT cnd 8164 ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c 8165 ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu 8166 ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z 8167 ((#x03) (if (trunc BI sbit) (set pc label))) ;n 8168 ((#x04) (if (not cbit) (set pc label))) ;ltu nc 8169 ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu 8170 ((#x06) (if (not zbit) (set pc label))) ;ne nz 8171 ((#x07) (if (not sbit) (set pc label))) ;pz 8172 ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le 8173 ((#x09) (if (trunc BI obit) (set pc label))) ;o 8174 ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge 8175 ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt 8176 ((#x0d) (if (not obit) (set pc label))) ;no 8177 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt 8178 ) 8179 ) 8180 ) 8181 8182(dni jcnd16-5 8183 "jCnd label" 8184 (RL_JUMP RELAXABLE (machine 16)) 8185 "j$cond16j5 ${Lab-8-8}" 8186 (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) 8187 (jcnd16-sem cond16j5 Lab-8-8) 8188 () 8189) 8190 8191(dni jcnd16 8192 "jCnd label" 8193 (RL_JUMP RELAXABLE (machine 16)) 8194 "j$cond16j ${Lab-16-8}" 8195 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) 8196 (jcnd16-sem cond16j Lab-16-8) 8197 () 8198) 8199 8200(dni jcnd32 8201 "jCnd label" 8202 (RL_JUMP RELAXABLE (machine 32)) 8203 "j$cond32j ${Lab-8-8}" 8204 (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) 8205 (jcnd32-sem cond32j Lab-8-8) 8206 () 8207) 8208 8209;------------------------------------------------------------- 8210; jmp - jump 8211;------------------------------------------------------------- 8212 8213; jmp.s label3 (m16 #1) 8214(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16)) 8215 ("jmp.s ${Lab-5-3}") 8216 (+ (f-0-4 6) (f-4-1 0) Lab-5-3) 8217 (sequence () (set pc Lab-5-3)) 8218 ()) 8219; jmp.b label8 (m16 #2) 8220(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16)) 8221 ("jmp.b ${Lab-8-8}") 8222 (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) 8223 (sequence () (set pc Lab-8-8)) 8224 ()) 8225; jmp.w label16 (m16 #3) 8226(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) 8227 ("jmp.w ${Lab-8-16}") 8228 (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) 8229 (sequence () (set pc Lab-8-16)) 8230 ()) 8231; jmp.a label24 (m16 #4) 8232(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) 8233 ("jmp.a ${Lab-8-24}") 8234 (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) 8235 (sequence () (set pc Lab-8-24)) 8236 ()) 8237 8238(define-pmacro (jmp16-sem mode dst) 8239 (set pc (and dst #xfffff)) 8240) 8241(define-pmacro (jmp32-sem mode dst) 8242 (set pc dst) 8243) 8244; jmpi.w dst (m16 #1 m32 #2) 8245(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem) 8246(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem) 8247; jmpi.a dst (m16 #2 m32 #2) 8248(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem) 8249(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem) 8250; jmps imm8 (m16 #1) 8251(dni jmps16 "jmps Imm-8-QI" ((machine 16)) 8252 ("jmps #${Imm-8-QI}") 8253 (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI) 8254 (sequence () (set pc Imm-8-QI)) 8255 ()) 8256; jmp.s label3 (m32 #1) 8257(dni jmp32.s 8258 "jmp.s label" 8259 (RL_JUMP RELAXABLE (machine 32)) 8260 "jmp.s ${Lab32-jmp-s}" 8261 (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) 8262 (set pc Lab32-jmp-s) 8263 () 8264) 8265; jmp.b label8 (m32 #2) 8266(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32)) 8267 ("jmp.b ${Lab-8-8}") 8268 (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) 8269 (set pc Lab-8-8) 8270 ()) 8271; jmp.w label16 (m32 #3) 8272(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32)) 8273 ("jmp.w ${Lab-8-16}") 8274 (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) 8275 (set pc Lab-8-16) 8276 ()) 8277; jmp.a label24 (m32 #4) 8278(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32)) 8279 ("jmp.a ${Lab-8-24}") 8280 (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) 8281 (set pc Lab-8-24) 8282 ()) 8283; jmp.s imm8 (m32 #1) 8284(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32)) 8285 ("jmps #${Imm-8-QI}") 8286 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) 8287 (set pc Imm-8-QI) 8288 ()) 8289 8290;------------------------------------------------------------- 8291; jsr jump subroutine 8292;------------------------------------------------------------- 8293 8294(define-pmacro (jsr16-sem length dst) 8295 (sequence ((SI tpc)) 8296 (set tpc (add pc length)) 8297 (set (reg h-sp) (sub (reg h-sp) 2)) 8298 (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8)) 8299 (set (reg h-sp) (sub (reg h-sp) 1)) 8300 (set (mem16 QI (reg h-sp)) (and tpc #xff)) 8301 (set pc dst) 8302 ) 8303) 8304(define-pmacro (jsr32-sem length dst) 8305 (sequence ((SI tpc)) 8306 (set tpc (add pc length)) 8307 (set (reg h-sp) (sub (reg h-sp) 2)) 8308 (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16)) 8309 (set (reg h-sp) (sub (reg h-sp) 2)) 8310 (set (mem32 HI (reg h-sp)) (and tpc #xffff)) 8311 (set pc dst) 8312 ) 8313) 8314 8315; jsr.w label16 (m16 #1) 8316(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) 8317 ("jsr.w ${Lab-8-16}") 8318 (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) 8319 (jsr16-sem 3 Lab-8-16) 8320 ()) 8321; jsr.a label24 (m16 #2) 8322(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) 8323 ("jsr.a ${Lab-8-24}") 8324 (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) 8325 (jsr16-sem 4 Lab-8-24) 8326 ()) 8327(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem 8328 op32 op32-1 op32-2 op32-3 op32-4 op32-sem len) 8329 (begin 8330 (dni (.sym jsri16 mode - op16) 8331 (.str "jsri." mode " " op16) 8332 (RL_1ADDR (machine 16)) 8333 (.str "jsri." mode " ${" op16 "}") 8334 (+ op16-1 op16-2 op16-3 op16) 8335 (op16-sem len op16) 8336 ()) 8337 (dni (.sym jsri32 mode - op32) 8338 (.str "jsri." mode " " op32) 8339 (RL_1ADDR (machine 32)) 8340 (.str "jsri." mode " ${" op32 "}") 8341 (+ op32-1 op32-2 op32-3 op32-4 op32) 8342 (op32-sem len op32) 8343 ()) 8344 ) 8345 ) 8346; jsri.w dst (m16 #1 m32 #1)) 8347(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8348 dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) 8349(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8350 dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) 8351(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8352 dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) 8353(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8354 dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) 8355 8356; jsri.a (m16 #2 m32 #2) 8357(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8358 dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) 8359(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8360 dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) 8361(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8362 dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) 8363(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8364 dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) 8365 8366(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) 8367 ("jsri.a ${dst32-16-24-Unprefixed-SI}") 8368 (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) 8369 (jsr32-sem 6 dst32-16-24-Unprefixed-SI) 8370 ()) 8371; jsr.w label16 (m32 #1) 8372(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32)) 8373 ("jsr.w ${Lab-8-16}") 8374 (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) 8375 (jsr32-sem 3 Lab-8-16) 8376 ()) 8377; jsr.a label16 (m32 #2) 8378(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32)) 8379 ("jsr.a ${Lab-8-24}") 8380 (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) 8381 (jsr32-sem 4 Lab-8-24) 8382 ()) 8383; jsrs imm8 (m16 #1) 8384(dni jsrs16 "jsrs Imm-8-QI" ((machine 16)) 8385 ("jsrs #${Imm-8-QI}") 8386 (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI) 8387 (jsr16-sem 2 Imm-8-QI) 8388 ()) 8389; jsrs imm8 (m32 #1) 8390(dni jsrs "jsrs #Imm-8-QI" ((machine 32)) 8391 ("jsrs #${Imm-8-QI}") 8392 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI) 8393 (jsr32-sem 2 Imm-8-QI) 8394 ()) 8395 8396;------------------------------------------------------------- 8397; ldc - load control register 8398; stc - store control register 8399;------------------------------------------------------------- 8400 8401(define-pmacro (ldc32-cr1-sem src dst) 8402 (sequence () 8403 (case DFLT dst 8404 ((#x0) (set (reg h-dct0) src)) 8405 ((#x1) (set (reg h-dct1) src)) 8406 ((#x2) (sequence ((HI tflag)) 8407 (set tflag src) 8408 (if (and tflag #x1) (set cbit 1)) 8409 (if (and tflag #x2) (set dbit 1)) 8410 (if (and tflag #x4) (set zbit 1)) 8411 (if (and tflag #x8) (set sbit 1)) 8412 (if (and tflag #x10) (set bbit 1)) 8413 (if (and tflag #x20) (set obit 1)) 8414 (if (and tflag #x40) (set ibit 1)) 8415 (if (and tflag #x80) (set ubit 1)))) 8416 ((#x3) (set (reg h-svf) src)) 8417 ((#x4) (set (reg h-drc0) src)) 8418 ((#x5) (set (reg h-drc1) src)) 8419 ((#x6) (set (reg h-dmd0) src)) 8420 ((#x7) (set (reg h-dmd1) src)) 8421 ) 8422 ) 8423) 8424(define-pmacro (ldc32-cr2-sem src dst) 8425 (sequence () 8426 (case DFLT dst 8427 ((#x0) (set (reg h-intb) src)) 8428 ((#x1) (set (reg h-sp) src)) 8429 ((#x2) (set (reg h-sb) src)) 8430 ((#x3) (set (reg h-fb) src)) 8431 ((#x4) (set (reg h-svp) src)) 8432 ((#x5) (set (reg h-vct) src)) 8433 ((#x7) (set (reg h-isp) src)) 8434 ) 8435 ) 8436) 8437(define-pmacro (ldc32-cr3-sem src dst) 8438 (sequence () 8439 (case DFLT dst 8440 ((#x2) (set (reg h-dma0) src)) 8441 ((#x3) (set (reg h-dma1) src)) 8442 ((#x4) (set (reg h-dra0) src)) 8443 ((#x5) (set (reg h-dra1) src)) 8444 ((#x6) (set (reg h-dsa0) src)) 8445 ((#x7) (set (reg h-dsa1) src)) 8446 ) 8447 ) 8448) 8449(define-pmacro (ldc16-sem src dst) 8450 (sequence () 8451 (case DFLT dst 8452 ((#x1) (set (reg h-intb) src)) 8453 ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16))))) 8454 ((#x3) (sequence ((HI tflag)) 8455 (set tflag src) 8456 (if (and tflag #x1) (set cbit 1)) 8457 (if (and tflag #x2) (set dbit 1)) 8458 (if (and tflag #x4) (set zbit 1)) 8459 (if (and tflag #x8) (set sbit 1)) 8460 (if (and tflag #x10) (set bbit 1)) 8461 (if (and tflag #x20) (set obit 1)) 8462 (if (and tflag #x40) (set ibit 1)) 8463 (if (and tflag #x80) (set ubit 1)))) 8464 ((#x4) (set (reg h-isp) src)) 8465 ((#x5) (set (reg h-sp) src)) 8466 ((#x6) (set (reg h-sb) src)) 8467 ((#x7) (set (reg h-fb) src)) 8468 ) 8469 ) 8470) 8471 8472(define-pmacro (stc32-cr1-sem src dst) 8473 (sequence () 8474 (case DFLT src 8475 ((#x0) (set dst (reg h-dct0))) 8476 ((#x1) (set dst (reg h-dct1))) 8477 ((#x2) (sequence ((HI tflag)) 8478 (set tflag 0) 8479 (if (eq cbit 1) (set tflag (or tflag #x1))) 8480 (if (eq dbit 1) (set tflag (or tflag #x2))) 8481 (if (eq zbit 1) (set tflag (or tflag #x4))) 8482 (if (eq sbit 1) (set tflag (or tflag #x8))) 8483 (if (eq bbit 1) (set tflag (or tflag #x10))) 8484 (if (eq obit 1) (set tflag (or tflag #x20))) 8485 (if (eq ibit 1) (set tflag (or tflag #x40))) 8486 (if (eq ubit 1) (set tflag (or tflag #x80))) 8487 (set dst tflag))) 8488 ((#x3) (set dst (reg h-svf))) 8489 ((#x4) (set dst (reg h-drc0))) 8490 ((#x5) (set dst (reg h-drc1))) 8491 ((#x6) (set dst (reg h-dmd0))) 8492 ((#x7) (set dst (reg h-dmd1))) 8493 ) 8494 ) 8495) 8496(define-pmacro (stc32-cr2-sem src dst) 8497 (sequence () 8498 (case DFLT src 8499 ((#x0) (set dst (reg h-intb))) 8500 ((#x1) (set dst (reg h-sp))) 8501 ((#x2) (set dst (reg h-sb))) 8502 ((#x3) (set dst (reg h-fb))) 8503 ((#x4) (set dst (reg h-svp))) 8504 ((#x5) (set dst (reg h-vct))) 8505 ((#x7) (set dst (reg h-isp))) 8506 ) 8507 ) 8508) 8509(define-pmacro (stc32-cr3-sem src dst) 8510 (sequence () 8511 (case DFLT src 8512 ((#x2) (set dst (reg h-dma0))) 8513 ((#x3) (set dst (reg h-dma1))) 8514 ((#x4) (set dst (reg h-dra0))) 8515 ((#x5) (set dst (reg h-dra1))) 8516 ((#x6) (set dst (reg h-dsa0))) 8517 ((#x7) (set dst (reg h-dsa1))) 8518 ) 8519 ) 8520) 8521(define-pmacro (stc16-sem src dst) 8522 (sequence () 8523 (case DFLT src 8524 ((#x1) (set dst (and (reg h-intb) (const #xffff)))) 8525 ((#x2) (set dst (srl (reg h-intb) (const 16)))) 8526 ((#x3) (sequence ((HI tflag)) 8527 (set tflag 0) 8528 (if (eq cbit 1) (set tflag (or tflag #x1))) 8529 (if (eq dbit 1) (set tflag (or tflag #x2))) 8530 (if (eq zbit 1) (set tflag (or tflag #x4))) 8531 (if (eq sbit 1) (set tflag (or tflag #x8))) 8532 (if (eq bbit 1) (set tflag (or tflag #x10))) 8533 (if (eq obit 1) (set tflag (or tflag #x20))) 8534 (if (eq ibit 1) (set tflag (or tflag #x40))) 8535 (if (eq ubit 1) (set tflag (or tflag #x80))) 8536 (set dst tflag))) 8537 ((#x4) (set dst (reg h-isp))) 8538 ((#x5) (set dst (reg h-sp))) 8539 ((#x6) (set dst (reg h-sb))) 8540 ((#x7) (set dst (reg h-fb))) 8541 ) 8542 ) 8543) 8544 8545(dni ldc16.imm16 "ldc #imm,dst" ((machine 16)) 8546 ("ldc #${Imm-16-HI},${cr16}") 8547 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI) 8548 (ldc16-sem Imm-16-HI cr16) 8549 ()) 8550 8551(dni ldc16.dst "ldc src,dest" ((machine 16)) 8552 ("ldc ${dst16-16-HI},${cr16}") 8553 (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI) 8554 (ldc16-sem dst16-16-HI cr16) 8555 ()) 8556; ldc src,dest (m32c #4) 8557(dni ldc32.src-cr1 "ldc src,dst" ((machine 32)) 8558 ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}") 8559 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32) 8560 (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32) 8561 ()) 8562; ldc src,dest (m32c #5) 8563(dni ldc32.src-cr2 "ldc src,dest" ((machine 32)) 8564 ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}") 8565 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32) 8566 (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32) 8567 ()) 8568; ldc src,dest (m32c #6) 8569(dni ldc32.src-cr3 "ldc src,dst" ((machine 32)) 8570 ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}") 8571 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32) 8572 (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32) 8573 ()) 8574; ldc src,dest (m32c #1) 8575(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32)) 8576 ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}") 8577 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI) 8578 (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32) 8579 ()) 8580; ldc src,dest (m32c #2) 8581(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32)) 8582 ("ldc #${Dsp-16-u24},${cr2-32}") 8583 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24) 8584 (ldc32-cr2-sem Dsp-16-u24 cr2-32) 8585 ()) 8586; ldc src,dest (m32c #3) 8587(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32)) 8588 ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}") 8589 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24) 8590 (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32) 8591 ()) 8592 8593(dni stc16.src "stc src,dest" ((machine 16)) 8594 ("stc ${cr16},${dst16-16-HI}") 8595 (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI) 8596 (stc16-sem cr16 dst16-16-HI ) 8597 ()) 8598 8599(dni stc16.pc "stc pc,dest" ((machine 16)) 8600 ("stc pc,${dst16-16-HI}") 8601 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI) 8602 (sequence () (set dst16-16-HI (reg h-pc))) 8603 ()) 8604 8605(dni stc32.src-cr1 "stc src,dst" ((machine 32)) 8606 ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}") 8607 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32) 8608 (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI ) 8609 ()) 8610 8611(dni stc32.src-cr2 "stc src,dest" ((machine 32)) 8612 ("stc ${cr2-32},${dst32-16-Unprefixed-SI}") 8613 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32) 8614 (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI ) 8615 ()) 8616 8617(dni stc32.src-cr3 "stc src,dst" ((machine 32)) 8618 ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}") 8619 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32) 8620 (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI ) 8621 ()) 8622 8623;------------------------------------------------------------- 8624; ldctx - load context 8625; stctx - store context 8626;------------------------------------------------------------- 8627 8628; ??? semantics 8629(dni ldctx16 "ldctx abs16,abs24" ((machine 16)) 8630 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") 8631 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) 8632 (nop) 8633 ()) 8634(dni ldctx32 "ldctx abs16,abs24" ((machine 32)) 8635 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") 8636 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) 8637 (nop) 8638 ()) 8639(dni stctx16 "stctx abs16,abs24" ((machine 16)) 8640 ("stctx ${Dsp-16-u16},${Dsp-32-u24}") 8641 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) 8642 (nop) 8643 ()) 8644(dni stctx32 "stctx abs16,abs24" ((machine 32)) 8645 ("stctx ${Dsp-16-u16},${Dsp-32-u24}") 8646 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) 8647 (nop) 8648 ()) 8649 8650;------------------------------------------------------------- 8651; lde - load from extra far data area (m16) 8652; ste - store to extra far data area (m16) 8653;------------------------------------------------------------- 8654 8655(lde-dst QI .b 0) 8656(lde-dst HI .w 1) 8657 8658(ste-dst QI .b 0) 8659(ste-dst HI .w 1) 8660 8661;------------------------------------------------------------- 8662; ldipl - load interrupt permission level 8663;------------------------------------------------------------- 8664 8665; ??? semantics 8666; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl 8667 8668(dni ldipl16.imm "ldipl #imm" ((machine 16)) 8669 ("ldipl #${Imm-13-u3}") 8670 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) 8671 (nop) 8672 ()) 8673(dni ldipl32.imm "ldipl #imm" ((machine 32)) 8674 ("ldipl #${Imm-13-u3}") 8675 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3) 8676 (nop) 8677 ()) 8678 8679 8680;------------------------------------------------------------- 8681; max - maximum value 8682;------------------------------------------------------------- 8683 8684; TODO check semantics for min -1,0 8685(define-pmacro (max-sem mode src dst) 8686 (sequence () 8687 (if (gt mode src dst) 8688 (set mode dst src))) 8689) 8690 8691; max.size:G #imm,dst 8692(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem) 8693(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem) 8694 8695; max.BW:G src,dst 8696(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem) 8697(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem) 8698 8699;------------------------------------------------------------- 8700; min - minimum value 8701;------------------------------------------------------------- 8702 8703(define-pmacro (min-sem mode src dst) 8704 (sequence () 8705 (if (lt mode src dst) 8706 (set mode dst src))) 8707) 8708 8709; min.size:G #imm,dst 8710(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem) 8711(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem) 8712 8713; min.BW:G src,dst 8714(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem) 8715(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem) 8716 8717;------------------------------------------------------------- 8718; mov - move 8719;------------------------------------------------------------- 8720 8721(define-pmacro (mov-sem mode src1 dst) 8722 (sequence ((mode result)) 8723 (set result src1) 8724 (set-z-and-s result) 8725 (set mode dst src1)) 8726) 8727 8728(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst) 8729 (set dst (mem-mach mach mode (add sp src1))) 8730) 8731 8732(define-pmacro (mov-src-dspsp-sem mach mode src dst1) 8733 (set (mem-mach mach mode (add sp dst1)) src) 8734) 8735 8736(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2) 8737 (dni (.sym mov16. size .S-imm- regn) 8738 (.str "mov." size ":S " imm "," regn) 8739 ((machine 16)) 8740 (.str "mov." size "$S #${" imm "}," regn) 8741 (+ op1 op2 imm) 8742 (mov-sem mode imm (reg (.sym h- regn))) 8743 ()) 8744) 8745; mov.size:G #imm,dst (m16 #1 m32 #1) 8746(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem) 8747; mov.L:G #imm32,dst (m32 #2) 8748(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem) 8749; mov.BW:S #imm,dst2 (m32 #4) 8750(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem) 8751(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem) 8752; mov.b:S #imm8,dst3 (m16 #3) 8753(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem) 8754; mov.b:S #imm8,aN (m16 #4) 8755(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2)) 8756(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA)) 8757(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2)) 8758(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA)) 8759; mov.WL:S #imm,A0/A1 (m32 #5) 8760(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2) 8761 (dni (.sym mov32- sz - regn) 8762 (.str "mov." sz ":s" imm "," regn) 8763 ((machine 32)) 8764 (.str "mov." sz "$S #${" imm "}," regn) 8765 (+ (f-0-4 op1) (f-4-4 op2) imm) 8766 (mov-sem mode imm (reg (.sym h- regn))) 8767 ()) 8768) 8769(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) 8770(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) 8771(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC) 8772(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD) 8773 8774; mov.size:Q #imm4,dst (m16 #2 m32 #3) 8775(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) 8776(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) 8777(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) 8778(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) 8779 8780; mov.BW:Z #0,dst (m16 #5 m32 #6) 8781(dni mov16.b-Z-imm8-dst3 8782 "mov.b:Z #0,Dst16-3-S-8" 8783 ((machine 16)) 8784 "mov.b$Z #0,${Dst16-3-S-8}" 8785 (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8) 8786 (mov-sem QI (const 0) Dst16-3-S-8) 8787 ()) 8788; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem) 8789(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem) 8790(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem) 8791; mov.BW:G src,dst (m16 #6 m32 #7) 8792(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem) 8793; mov.B:S src2,a0/a1 (m16 #7) 8794(dni (.sym mov 16 .b.S-An) 8795 (.str mov ".b:S src2,a[01]") 8796 ((machine 16)) 8797 (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}") 8798 (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S) 8799 (mov-sem QI src16-2-S Dst16AnQI-S) 8800 ()) 8801(define-pmacro (mov16-b-s-an-defn op1 op2 op2c) 8802 (dni (.sym mov16.b.S- op1 - op2) 8803 (.str mov ".b:S " op1 "," op2) 8804 ((machine 16)) 8805 (.str mov ".b$S " op1 "," op2) 8806 (+ (f-0-4 #x3) op2c) 8807 (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2))) 8808 ()) 8809 ) 8810(mov16-b-s-an-defn r0l a1 (f-4-4 #x4)) 8811(mov16-b-s-an-defn r0h a0 (f-4-4 #x0)) 8812 8813; mov.L:G src,dst (m32 #8) 8814(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem) 8815; mov.B:S r0l/r0h,dst2 (m16 #8) 8816(dni (.sym mov 16 .b.S-Rn-An) 8817 (.str mov ".b:S r0[lh],src2") 8818 ((machine 16)) 8819 (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}") 8820 (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S) 8821 (mov-sem QI src16-2-S Dst16RnQI-S) 8822 ()) 8823 8824; mov.B.S src2,r0l/r0h (m16 #9) 8825(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem) 8826 8827; mov.BW:S src2,r0l/r0 (m32 #9) 8828; mov.BW:S src2,r1l/r1 (m32 #10) 8829(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2) 8830 (begin 8831 (dni (.sym mov32. sz - src - dst) 8832 (.str "mov." sz "src," dst) 8833 ((machine 32)) 8834 (.str "mov." sz "$S ${" (.sym src - mode) "}," dst) 8835 (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode)) 8836 (mov-sem mode (.sym src - mode) (reg (.sym h- dst))) 8837 ()) 8838 ) 8839 ) 8840(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4) 8841(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4) 8842(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) 8843(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) 8844(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) 8845(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7) 8846(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) 8847(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) 8848(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) 8849(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7) 8850 8851; mov.BW:S r0l/r0,dst2 (m32 #11) 8852(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2) 8853 (begin 8854 (dni (.sym mov32. sz - src - dst) 8855 (.str "mov." sz "src," dst) 8856 ((machine 32)) 8857 (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}") 8858 (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode)) 8859 (mov-sem mode (reg (.sym h- src)) (.sym dst - mode)) 8860 ()) 8861 ) 8862 ) 8863(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0) 8864(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0) 8865(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0) 8866(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0) 8867 8868; mov.L:S src,A0/A1 (m32 #12) 8869(define-pmacro (mov32-src-a src dst dstcode opc1 opc2) 8870 (begin 8871 (dni (.sym mov32. sz - src - dst) 8872 (.str "mov." sz "src," dst) 8873 ((machine 32)) 8874 (.str "mov.l" "$S ${" (.sym src - SI) "}," dst) 8875 (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode)) 8876 (mov-sem SI (.sym src - SI) (reg (.sym h- dst))) 8877 ()) 8878 ) 8879 ) 8880(mov32-src-a dst32-2-S-16 a0 0 1 4) 8881(mov32-src-a dst32-2-S-16 a1 1 1 4) 8882(mov32-src-a dst32-2-S-8 a0 0 1 4) 8883(mov32-src-a dst32-2-S-8 a1 1 1 4) 8884 8885; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13) 8886; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14) 8887(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem) 8888(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem) 8889 8890;------------------------------------------------------------- 8891; mova - move effective address 8892;------------------------------------------------------------- 8893 8894(define-pmacro (mov16a-defn dst dstop dstcode) 8895 (dni (.sym mova16. src - dst) 8896 (.str "mova src," dst) 8897 ((machine 16)) 8898 (.str "mova ${dst16-16-Mova-HI}," dst) 8899 (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode)) 8900 (sequence () (set HI (reg dstop) dst16-16-Mova-HI)) 8901 ()) 8902) 8903(mov16a-defn r0 h-r0 0) 8904(mov16a-defn r1 h-r1 1) 8905(mov16a-defn r2 h-r2 2) 8906(mov16a-defn r3 h-r3 3) 8907(mov16a-defn a0 h-a0 4) 8908(mov16a-defn a1 h-a1 5) 8909 8910(define-pmacro (mov32a-defn dst dstop dstcode) 8911 (dni (.sym mova32. src - dst) 8912 (.str "mova src," dst) 8913 ((machine 32)) 8914 (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst) 8915 (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode)) 8916 (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI)) 8917 ()) 8918) 8919(mov32a-defn r2r0 h-r2r0 0) 8920(mov32a-defn r3r1 h-r3r1 1) 8921(mov32a-defn a0 h-a0 2) 8922(mov32a-defn a1 h-a1 3) 8923 8924;------------------------------------------------------------- 8925; movDir - move nibble 8926;------------------------------------------------------------- 8927 8928(define-pmacro (movdir-sem nib src dst) 8929 (sequence ((SI tmp)) 8930 (case DFLT nib 8931 ((0) (set dst (or (and dst #xf0) (and src #xf)))) 8932 ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4)))) 8933 ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4)))) 8934 ((3) (set dst (or (and dst #x0f) (and src #xf0)))) 8935 ) 8936 ) 8937 ) 8938; movDir src,dst 8939(define-pmacro (mov16dir-1-defn nib dircode dir) 8940 (dni (.sym mov nib 16 ".r0l-dst") 8941 (.str "mov" nib " r0l,dst") 8942 ((machine 16)) 8943 (.str "mov" nib " r0l,${dst16-16-QI}") 8944 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) 8945 (movdir-sem dircode (reg h-r0l) dst16-16-QI) 8946 ()) 8947) 8948(mov16dir-1-defn ll 0 8) 8949(mov16dir-1-defn lh 1 #xA) 8950(mov16dir-1-defn hl 2 9) 8951(mov16dir-1-defn hh 3 #xB) 8952(define-pmacro (mov16dir-2-defn nib dircode dir) 8953 (dni (.sym mov nib 16 ".src-r0l") 8954 (.str "mov" nib " src,r0l") 8955 ((machine 16)) 8956 (.str "mov" nib " ${dst16-16-QI},r0l") 8957 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) 8958 (movdir-sem dircode dst16-16-QI (reg h-r0l)) 8959 ()) 8960) 8961(mov16dir-2-defn ll 0 0) 8962(mov16dir-2-defn lh 1 2) 8963(mov16dir-2-defn hl 2 1) 8964(mov16dir-2-defn hh 3 3) 8965 8966(define-pmacro (mov32dir-1-defn nib o1o0) 8967 (dni (.sym mov nib 32 ".r0l-dst") 8968 (.str "mov" nib " r0l,dst") 8969 ((machine 32)) 8970 (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}") 8971 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) 8972 (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI) 8973 ()) 8974) 8975(mov32dir-1-defn ll 0) 8976(mov32dir-1-defn lh 1) 8977(mov32dir-1-defn hl 2) 8978(mov32dir-1-defn hh 3) 8979(define-pmacro (mov32dir-2-defn nib o1o0) 8980 (dni (.sym mov nib 32 ".src-r0l") 8981 (.str "mov" nib " src,r0l") 8982 ((machine 32)) 8983 (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l") 8984 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) 8985 (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l)) 8986 ()) 8987) 8988(mov32dir-2-defn ll 0) 8989(mov32dir-2-defn lh 1) 8990(mov32dir-2-defn hl 2) 8991(mov32dir-2-defn hh 3) 8992 8993;------------------------------------------------------------- 8994; movx - move extend sign (m32) 8995;------------------------------------------------------------- 8996 8997(define-pmacro (movx-sem mode src dst) 8998 (sequence ((SI source) (SI result)) 8999 (set SI result src) 9000 (set-z-and-s result) 9001 (set dst result)) 9002) 9003 9004; movx #imm,dst 9005(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem) 9006 9007;------------------------------------------------------------- 9008; mul - multiply 9009;------------------------------------------------------------- 9010 9011(define-pmacro (mul-sem mode src1 dst) 9012 (sequence ((mode result)) 9013 (set obit (add-oflag mode src1 dst 0)) 9014 (set result (mul mode src1 dst)) 9015 (set dst result)) 9016) 9017 9018; mul.BW #imm,dst 9019(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem) 9020; mul.BW src,dst 9021(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) 9022 9023(dni mul_l "mul.l src,r2r0" ((machine 32)) 9024 ("mul.l ${dst32-24-Prefixed-SI},r2r0") 9025 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf) 9026 dst32-24-Prefixed-SI) 9027 () ()) 9028 9029(dni mulu_l "mulu.l src,r2r0" ((machine 32)) 9030 ("mulu.l ${dst32-24-Prefixed-SI},r2r0") 9031 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf) 9032 dst32-24-Prefixed-SI) 9033 () ()) 9034;------------------------------------------------------------- 9035; mulex - multiple extend sign (m32) 9036;------------------------------------------------------------- 9037 9038; mulex src,dst 9039; (dni mulex-absolute-indirect "mulex [src]" ((machine 32)) 9040; ("mulex ${dst32-24-absolute-indirect-HI}") 9041; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) 9042; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI))) 9043; ()) 9044(dni mulex "mulex src" ((machine 32)) 9045 ("mulex ${dst32-16-Unprefixed-Mulex-HI}") 9046 (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 9047 (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI))) 9048 ()) 9049; (dni mulex-indirect "mulex [src]" ((machine 32)) 9050; ("mulex ${dst32-24-indirect-HI}") 9051; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) 9052; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI))) 9053; ()) 9054 9055;------------------------------------------------------------- 9056; mulu - multiply unsigned 9057;------------------------------------------------------------- 9058 9059(define-pmacro (mulu-sem mode src1 dst) 9060 (sequence ((mode result)) 9061 (set obit (add-oflag mode src1 dst 0)) 9062 (set result (mul mode src1 dst)) 9063 (set dst result)) 9064) 9065 9066; mulu.BW #imm,dst 9067(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem) 9068; mulu.BW src,dst 9069(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem) 9070 9071;------------------------------------------------------------- 9072; neg - twos complement 9073;------------------------------------------------------------- 9074 9075(define-pmacro (neg-sem mode dst) 9076 (sequence ((mode result)) 9077 (set result (neg mode dst)) 9078 (set-z-and-s result) 9079 (set dst result)) 9080) 9081 9082; neg.BW:G 9083(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem) 9084 9085;------------------------------------------------------------- 9086; not - twos complement 9087;------------------------------------------------------------- 9088 9089(define-pmacro (not-sem mode dst) 9090 (sequence ((mode result)) 9091 (set result (not mode dst)) 9092 (set-z-and-s result) 9093 (set dst result)) 9094) 9095 9096; not.BW:G 9097(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) 9098 9099(dni not16.b.s 9100 "not.b:s Dst16-3-S-8" 9101 ((machine 16)) 9102 "not.b:s ${Dst16-3-S-8}" 9103 (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8) 9104 (not-sem QI Dst16-3-S-8) 9105 ()) 9106 9107;------------------------------------------------------------- 9108; nop 9109;------------------------------------------------------------- 9110 9111(dni nop16 9112 "nop" 9113 ((machine 16)) 9114 "nop" 9115 (+ (f-0-4 #x0) (f-4-4 #x4)) 9116 (nop) 9117 ()) 9118 9119(dni nop32 9120 "nop" 9121 ((machine 32)) 9122 "nop" 9123 (+ (f-0-4 #xD) (f-4-4 #xE)) 9124 (nop) 9125 ()) 9126 9127;------------------------------------------------------------- 9128; or - logical or 9129;------------------------------------------------------------- 9130 9131(define-pmacro (or-sem mode src1 dst) 9132 (sequence ((mode result)) 9133 (set result (or mode src1 dst)) 9134 (set-z-and-s result) 9135 (set dst result)) 9136) 9137 9138; or.BW #imm,dst (m16 #1 m32 #1) 9139(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem) 9140; or.b:S #imm8,dst3 (m16 #2 m32 #2) 9141(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem) 9142(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem) 9143(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) 9144; or.BW src,dst (m16 #3 m32 #3) 9145(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) 9146; or.b:S src,r0[lh] (m16) 9147(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem) 9148 9149;------------------------------------------------------------- 9150; pop - restore register/memory 9151;------------------------------------------------------------- 9152 9153; TODO future: split this into .b and .w semantics 9154(define-pmacro (pop-sem-mach mach mode dst) 9155 (sequence ((mode b_or_w) (SI length)) 9156 (set b_or_w -1) 9157 (set b_or_w (srl b_or_w #x8)) 9158 (if (eq b_or_w #x0) 9159 (set length 1) ; .b 9160 (set length 2)) ; .w 9161 9162 (case DFLT length 9163 ((1) (set dst (mem-mach mach QI (reg h-sp)))) 9164 ((2) (set dst (mem-mach mach HI (reg h-sp))))) 9165 (set (reg h-sp) (add (reg h-sp) length)) 9166 ) 9167) 9168 9169(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest)) 9170(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) 9171 9172; pop.BW:G (m16 #1) 9173(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G) 9174; pop.BW:G (m32 #1) 9175(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) 9176 9177; pop.b:S r0l/r0h 9178(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16)) 9179 "pop.b$S ${Rn16-push-S-anyof}" 9180 (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2)) 9181 (pop-sem16 QI Rn16-push-S-anyof) 9182 ()) 9183; pop.w:S a0/a1 9184(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16)) 9185 "pop.w$S ${An16-push-S-anyof}" 9186 (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2)) 9187 (pop-sem16 HI An16-push-S-anyof) 9188 ()) 9189 9190;------------------------------------------------------------- 9191; popc - pop control register 9192; pushc - push control register 9193;------------------------------------------------------------- 9194 9195(define-pmacro (popc32-cr1-sem mode dst) 9196 (sequence () 9197 (case DFLT dst 9198 ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp)))) 9199 ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp)))) 9200 ((#x2) (sequence ((HI tflag)) 9201 (set tflag (mem32 mode (reg h-sp))) 9202 (if (and tflag #x1) (set cbit 1)) 9203 (if (and tflag #x2) (set dbit 1)) 9204 (if (and tflag #x4) (set zbit 1)) 9205 (if (and tflag #x8) (set sbit 1)) 9206 (if (and tflag #x10) (set bbit 1)) 9207 (if (and tflag #x20) (set obit 1)) 9208 (if (and tflag #x40) (set ibit 1)) 9209 (if (and tflag #x80) (set ubit 1)))) 9210 ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp)))) 9211 ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp)))) 9212 ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp)))) 9213 ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp)))) 9214 ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp)))) 9215 ) 9216 (set (reg h-sp) (add (reg h-sp) 2)) 9217 ) 9218) 9219(define-pmacro (popc32-cr2-sem mode dst) 9220 (sequence () 9221 (case DFLT dst 9222 ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp)))) 9223 ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp)))) 9224 ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp)))) 9225 ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp)))) 9226 ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp)))) 9227 ) 9228 (set (reg h-sp) (add (reg h-sp) 4)) 9229 ) 9230) 9231(define-pmacro (popc16-sem mode dst) 9232 (sequence () 9233 (case DFLT dst 9234 ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000) 9235 (mem16 mode (reg h-sp))))) 9236 ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000) 9237 (mem16 mode (reg h-sp))))) 9238 ((#x3) (sequence ((HI tflag)) 9239 (set tflag (mem16 mode (reg h-sp))) 9240 (if (and tflag #x1) (set cbit 1)) 9241 (if (and tflag #x2) (set dbit 1)) 9242 (if (and tflag #x4) (set zbit 1)) 9243 (if (and tflag #x8) (set sbit 1)) 9244 (if (and tflag #x10) (set bbit 1)) 9245 (if (and tflag #x20) (set obit 1)) 9246 (if (and tflag #x40) (set ibit 1)) 9247 (if (and tflag #x80) (set ubit 1)))) 9248 ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp)))) 9249 ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp)))) 9250 ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp)))) 9251 ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp)))) 9252 ) 9253 (set (reg h-sp) (add (reg h-sp) 2)) 9254 ) 9255) 9256; popc dest (m16c #1) 9257(dni popc16.imm16 "popc dst" ((machine 16)) 9258 ("popc ${cr16}") 9259 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16) 9260 (popc16-sem HI cr16) 9261 ()) 9262; popc dest (m32c #1) 9263(dni popc32.imm16-cr1 "popc dst" ((machine 32)) 9264 ("popc ${cr1-Unprefixed-32}") 9265 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) 9266 (popc32-cr1-sem HI cr1-Unprefixed-32) 9267 ()) 9268; popc dest (m32c #2) 9269(dni popc32.imm16-cr2 "popc dst" ((machine 32)) 9270 ("popc ${cr2-32}") 9271 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32) 9272 (popc32-cr2-sem SI cr2-32) 9273 ()) 9274 9275(define-pmacro (pushc32-cr1-sem mode dst) 9276 (sequence () 9277 (set (reg h-sp) (sub (reg h-sp) 2)) 9278 (case DFLT dst 9279 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0))) 9280 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1))) 9281 ((#x2) (sequence ((HI tflag)) 9282 (set tflag 0) 9283 (if (eq cbit 1) (set tflag (or tflag #x1))) 9284 (if (eq dbit 1) (set tflag (or tflag #x2))) 9285 (if (eq zbit 1) (set tflag (or tflag #x4))) 9286 (if (eq sbit 1) (set tflag (or tflag #x8))) 9287 (if (eq bbit 1) (set tflag (or tflag #x10))) 9288 (if (eq obit 1) (set tflag (or tflag #x20))) 9289 (if (eq ibit 1) (set tflag (or tflag #x40))) 9290 (if (eq ubit 1) (set tflag (or tflag #x80))) 9291 (set (mem32 mode (reg h-sp)) tflag))) 9292 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf))) 9293 ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0))) 9294 ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1))) 9295 ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0))) 9296 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1))) 9297 ) 9298 ) 9299) 9300(define-pmacro (pushc32-cr2-sem mode dst) 9301 (sequence () 9302 (set (reg h-sp) (sub (reg h-sp) 4)) 9303 (case DFLT dst 9304 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb))) 9305 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp))) 9306 ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb))) 9307 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb))) 9308 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp))) 9309 ) 9310 ) 9311) 9312(define-pmacro (pushc16-sem mode dst) 9313 (sequence () 9314 (set (reg h-sp) (sub (reg h-sp) 2)) 9315 (case DFLT dst 9316 ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff))) 9317 ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000))) 9318 ((#x3) (sequence ((HI tflag)) 9319 (if (eq cbit 1) (set tflag (or tflag #x1))) 9320 (if (eq dbit 1) (set tflag (or tflag #x2))) 9321 (if (eq zbit 1) (set tflag (or tflag #x4))) 9322 (if (eq sbit 1) (set tflag (or tflag #x8))) 9323 (if (eq bbit 1) (set tflag (or tflag #x10))) 9324 (if (eq obit 1) (set tflag (or tflag #x20))) 9325 (if (eq ibit 1) (set tflag (or tflag #x40))) 9326 (if (eq ubit 1) (set tflag (or tflag #x80))) 9327 (set (mem16 mode (reg h-sp)) tflag))) 9328 9329 ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp))) 9330 ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp))) 9331 ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb))) 9332 ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb))) 9333 ) 9334 ) 9335) 9336; pushc src (m16c) 9337(dni pushc16.imm16 "pushc dst" ((machine 16)) 9338 ("pushc ${cr16}") 9339 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16) 9340 (pushc16-sem HI cr16) 9341 ()) 9342; pushc src (m32c #1) 9343(dni pushc32.imm16-cr1 "pushc dst" ((machine 32)) 9344 ("pushc ${cr1-Unprefixed-32}") 9345 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) 9346 (pushc32-cr1-sem HI cr1-Unprefixed-32) 9347 ()) 9348; pushc src (m32c #2) 9349(dni pushc32.imm16-cr2 "pushc dst" ((machine 32)) 9350 ("pushc ${cr2-32}") 9351 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32) 9352 (pushc32-cr2-sem SI cr2-32) 9353 ()) 9354 9355;------------------------------------------------------------- 9356; popm - pop multiple 9357; pushm - push multiple 9358;------------------------------------------------------------- 9359 9360(define-pmacro (popm-sem machine dst) 9361 (sequence ((SI addrlen)) 9362 (if (eq machine 16) 9363 (set addrlen 2) 9364 (set addrlen 4)) 9365 (if (and dst 1) 9366 (sequence () (set R0 (mem-mach machine HI (reg h-sp))) 9367 (set (reg h-sp) (add (reg h-sp) 2)))) 9368 (if (and dst 2) 9369 (sequence () (set R1 (mem-mach machine HI (reg h-sp))) 9370 (set (reg h-sp) (add (reg h-sp) 2)))) 9371 (if (and dst 4) 9372 (sequence () (set R2 (mem-mach machine HI (reg h-sp))) 9373 (set (reg h-sp) (add (reg h-sp) 2)))) 9374 (if (and dst 8) 9375 (sequence () (set R3 (mem-mach machine HI (reg h-sp))) 9376 (set (reg h-sp) (add (reg h-sp) 2)))) 9377 (if (and dst 16) 9378 (sequence () (set A0 (mem-mach machine HI (reg h-sp))) 9379 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9380 (if (and dst 32) 9381 (sequence () (set A1 (mem-mach machine HI (reg h-sp))) 9382 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9383 (if (and dst 64) 9384 (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp))) 9385 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9386 (if (eq dst 128) 9387 (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp))) 9388 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9389 ) 9390) 9391 9392(define-pmacro (pushm-sem machine dst) 9393 (sequence ((SI count) (SI addrlen)) 9394 (if (eq machine 16) 9395 (set addrlen 2) 9396 (set addrlen 4)) 9397 (if (eq dst 1) 9398 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9399 (set (mem-mach machine HI (reg h-sp)) (reg h-fb)))) 9400 (if (and dst 2) 9401 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9402 (set (mem-mach machine HI (reg h-sp)) (reg h-sb)))) 9403 (if (and dst 4) 9404 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9405 (set (mem-mach machine HI (reg h-sp)) A1))) 9406 (if (and dst 8) 9407 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9408 (set (mem-mach machine HI (reg h-sp)) A0))) 9409 (if (and dst 16) 9410 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9411 (set (mem-mach machine HI (reg h-sp)) R3))) 9412 (if (and dst 32) 9413 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9414 (set (mem-mach machine HI (reg h-sp)) R2))) 9415 (if (and dst 64) 9416 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9417 (set (mem-mach machine HI (reg h-sp)) R1))) 9418 (if (and dst 128) 9419 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9420 (set (mem-mach machine HI (reg h-sp)) R0))) 9421 ) 9422) 9423 9424(dni popm16 "popm regs" ((machine 16)) 9425 ("popm ${Regsetpop}") 9426 (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop) 9427 (popm-sem 16 Regsetpop) 9428 ()) 9429(dni pushm16 "pushm regs" ((machine 16)) 9430 ("pushm ${Regsetpush}") 9431 (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush) 9432 (pushm-sem 16 Regsetpush) 9433 ()) 9434(dni popm "popm regs" ((machine 32)) 9435 ("popm ${Regsetpop}") 9436 (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop) 9437 (popm-sem 32 Regsetpop) 9438 ()) 9439(dni pushm "pushm regs" ((machine 32)) 9440 ("pushm ${Regsetpush}") 9441 (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush) 9442 (pushm-sem 32 Regsetpush) 9443 ()) 9444 9445;------------------------------------------------------------- 9446; push - Save register/memory/immediate data 9447;------------------------------------------------------------- 9448 9449; TODO future: split this into .b and .w semantics 9450(define-pmacro (push-sem-mach mach mode dst) 9451 (sequence ((mode b_or_w) (SI length)) 9452 (set b_or_w -1) 9453 (set b_or_w (srl b_or_w #x8)) 9454 (if (eq b_or_w #x0) 9455 (set length 1) ; .b 9456 (if (eq b_or_w #xff) 9457 (set length 2) ; .w 9458 (set length 4))) ; .l 9459 (set (reg h-sp) (sub (reg h-sp) length)) 9460 (case DFLT length 9461 ((1) (set (mem-mach mach QI (reg h-sp)) dst)) 9462 ((2) (set (mem-mach mach HI (reg h-sp)) dst)) 9463 ((4) (set (mem-mach mach SI (reg h-sp)) dst))) 9464 ) 9465 ) 9466 9467(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst)) 9468(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst)) 9469 9470; push.BW:G imm (m16 #1 m32 #1) 9471(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16)) 9472 ("push.b$G #${Imm-16-QI}") 9473 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI) 9474 (push-sem16 QI Imm-16-QI) 9475 ()) 9476 9477(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16)) 9478 ("push.w$G #${Imm-16-HI}") 9479 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI) 9480 (push-sem16 HI Imm-16-HI) 9481 ()) 9482 9483(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32)) 9484 ("push.b #${Imm-8-QI}") 9485 (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) 9486 (push-sem32 QI Imm-8-QI) 9487 ()) 9488 9489(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32)) 9490 ("push.w #${Imm-8-HI}") 9491 (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI) 9492 (push-sem32 HI Imm-8-HI) 9493 ()) 9494 9495; push.BW:G src (m16 #2) 9496(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G) 9497; push.BW:G src (m32 #2) 9498(unary-insn-mach 32 push #xC #x0 #xE push-sem32) 9499 9500 9501; push.b:S r0l/r0h (m16 #3) 9502(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16)) 9503 "push.b$S ${Rn16-push-S-anyof}" 9504 (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2)) 9505 (push-sem16 QI Rn16-push-S-anyof) 9506 ()) 9507; push.w:S a0/a1 (m16 #4) 9508(dni push16.b-s-an "push.w:S a[01]" ((machine 16)) 9509 "push.w$S ${An16-push-S-anyof}" 9510 (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2)) 9511 (push-sem16 HI An16-push-S-anyof) 9512 ()) 9513 9514; push.l imm32 (m32 #3) 9515(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32)) 9516 ("push.l #${Imm-16-SI}") 9517 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI) 9518 (push-sem32 SI Imm-16-SI) 9519 ()) 9520; push.l src (m32 #4) 9521(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32) 9522 9523;------------------------------------------------------------- 9524; pusha - push effective address 9525;------------------------------------------------------------ 9526 9527(define-pmacro (push16a-sem mode dst) 9528 (sequence () 9529 (set (reg h-sp) (sub (reg h-sp) 2)) 9530 (set (mem16 HI (reg h-sp)) dst)) 9531) 9532(define-pmacro (push32a-sem mode dst) 9533 (sequence () 9534 (set (reg h-sp) (sub (reg h-sp) 4)) 9535 (set (mem32 SI (reg h-sp)) dst)) 9536) 9537(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem) 9538(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem) 9539 9540;------------------------------------------------------------- 9541; reit - return from interrupt 9542;------------------------------------------------------------- 9543 9544; ??? semantics 9545(dni reit16 "REIT" ((machine 16)) 9546 ("reit") 9547 (+ (f-0-4 #xF) (f-4-4 #xB)) 9548 (nop) 9549 ()) 9550(dni reit32 "REIT" ((machine 32)) 9551 ("reit") 9552 (+ (f-0-4 9) (f-4-4 #xE)) 9553 (nop) 9554 ()) 9555 9556;------------------------------------------------------------- 9557; rmpa - repeat multiple and addition 9558;------------------------------------------------------------- 9559 9560; TODO semantics 9561(dni rmpa16.b "rmpa.size" ((machine 16)) 9562 ("rmpa.b") 9563 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1)) 9564 (nop) 9565 ()) 9566(dni rmpa16.w "rmpa.size" ((machine 16)) 9567 ("rmpa.w") 9568 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1)) 9569 (nop) 9570 ()) 9571(dni rmpa32.b "rmpa.size" ((machine 32)) 9572 ("rmpa.b") 9573 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3)) 9574 (nop) 9575 ()) 9576 9577(dni rmpa32.w "rmpa.size" ((machine 32)) 9578 ("rmpa.w") 9579 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3)) 9580 (nop) 9581 ()) 9582 9583;------------------------------------------------------------- 9584; rolc - rotate left with carry 9585;------------------------------------------------------------- 9586 9587; TODO check semantics 9588; TODO future: split this into .b and .w semantics 9589(define-pmacro (rolc-sem mode dst) 9590 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask)) 9591 (set b_or_w -1) 9592 (set b_or_w (srl b_or_w #x8)) 9593 (if (eq b_or_w #x0) 9594 (set mask #x8000) ; .b 9595 (set mask #x80000000)) ; .w 9596 (set ocbit cbit) 9597 (set cbit (and dst mask)) 9598 (set result (sll mode dst 1)) 9599 (set result (or result ocbit)) 9600 (set-z-and-s result) 9601 (set dst result)) 9602) 9603; rolc.BW src,dst 9604(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem) 9605 9606;------------------------------------------------------------- 9607; rorc - rotate right with carry 9608;------------------------------------------------------------- 9609 9610; TODO check semantics 9611; TODO future: split this into .b and .w semantics 9612(define-pmacro (rorc-sem mode dst) 9613 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt)) 9614 (set b_or_w -1) 9615 (set b_or_w (srl b_or_w #x8)) 9616 (if (eq b_or_w #x0) 9617 (sequence () (set mask #x7fff) (set shamt 15)) ; .b 9618 (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w 9619 (set ocbit cbit) 9620 (set cbit (and dst #x1)) 9621 (set result (srl mode dst (const 1))) 9622 (set result (or (and result mask) (sll ocbit shamt))) 9623 (set-z-and-s result) 9624 (set dst result)) 9625) 9626; rorc.BW src,dst 9627(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem) 9628 9629;------------------------------------------------------------- 9630; rot - rotate 9631;------------------------------------------------------------- 9632 9633; TODO future: split this into .b and .w semantics 9634(define-pmacro (rot-1-sem mode src1 dst) 9635 (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift)) 9636 (case DFLT src1 9637 ((#x0) (set shift 1)) 9638 ((#x1) (set shift 2)) 9639 ((#x2) (set shift 3)) 9640 ((#x3) (set shift 4)) 9641 ((#x4) (set shift 5)) 9642 ((#x5) (set shift 6)) 9643 ((#x6) (set shift 7)) 9644 ((#x7) (set shift 8)) 9645 ((-8) (set shift -1)) 9646 ((-7) (set shift -2)) 9647 ((-6) (set shift -3)) 9648 ((-5) (set shift -4)) 9649 ((-4) (set shift -5)) 9650 ((-3) (set shift -6)) 9651 ((-2) (set shift -7)) 9652 ((-1) (set shift -8)) 9653 (else (set shift 0)) 9654 ) 9655 (set b_or_w -1) 9656 (set b_or_w (srl b_or_w #x8)) 9657 (if (eq b_or_w #x0) 9658 (set mask #x7fff) ; .b 9659 (set mask #x7fffffff)) ; .w 9660 (set tmp dst) 9661 (if (gt mode shift 0) 9662 (sequence () 9663 (set tmp (rol mode tmp shift)) 9664 (set cbit (and tmp #x1))) 9665 (sequence () 9666 (set tmp (ror mode tmp (mul shift -1))) 9667 (set cbit (and tmp mask)))) 9668 (set-z-and-s tmp) 9669 (set dst tmp)) 9670) 9671(define-pmacro (rot-2-sem mode dst) 9672 (sequence ((mode tmp) (mode b_or_w) (USI mask)) 9673 (set b_or_w -1) 9674 (set b_or_w (srl b_or_w #x8)) 9675 (if (eq b_or_w #x0) 9676 (set mask #x7fff) ; .b 9677 (set mask #x7fffffff)) ; .w 9678 (set tmp dst) 9679 (if (gt mode (reg h-r1h) 0) 9680 (sequence () 9681 (set tmp (rol mode tmp (reg h-r1h))) 9682 (set cbit (and tmp #x1))) 9683 (sequence () 9684 (set tmp (ror mode tmp (reg h-r1h))) 9685 (set cbit (and tmp mask)))) 9686 (set-z-and-s tmp) 9687 (set dst tmp)) 9688) 9689 9690; rot.BW #imm4,dst 9691(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) 9692(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) 9693(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem) 9694(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem) 9695; rot.BW src,dst 9696 9697(dni rot16.b-dst "rot r1h,dest" ((machine 16)) 9698 ("rot.b r1h,${dst16-16-QI}") 9699 (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) 9700 (rot-2-sem QI dst16-16-QI) 9701 ()) 9702(dni rot16.w-dst "rot r1h,dest" ((machine 16)) 9703 ("rot.w r1h,${dst16-16-HI}") 9704 (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI) 9705 (rot-2-sem HI dst16-16-HI) 9706 ()) 9707 9708(dni rot32.b-dst "rot r1h,dest" ((machine 32)) 9709 ("rot.b r1h,${dst32-16-Unprefixed-QI}") 9710 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) 9711 (rot-2-sem QI dst32-16-Unprefixed-QI) 9712 ()) 9713(dni rot32.w-dst "rot r1h,dest" ((machine 32)) 9714 ("rot.w r1h,${dst32-16-Unprefixed-HI}") 9715 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) 9716 (rot-2-sem HI dst32-16-Unprefixed-HI) 9717 ()) 9718 9719;------------------------------------------------------------- 9720; rts - return from subroutine 9721;------------------------------------------------------------- 9722 9723(define-pmacro (rts16-sem) 9724 (sequence ((SI tpc)) 9725 (set tpc (mem16 HI (reg h-sp))) 9726 (set (reg h-sp) (add (reg h-sp) 2)) 9727 (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16))) 9728 (set (reg h-sp) (add (reg h-sp) 1)) 9729 (set pc tpc) 9730 ) 9731) 9732(define-pmacro (rts32-sem) 9733 (sequence ((SI tpc)) 9734 (set tpc (mem32 HI (reg h-sp))) 9735 (set (reg h-sp) (add (reg h-sp) 2)) 9736 (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16))) 9737 (set (reg h-sp) (add (reg h-sp) 2)) 9738 (set pc tpc) 9739 ) 9740) 9741 9742(dni rts16 "rts" ((machine 16)) 9743 ("rts") 9744 (+ (f-0-4 #xF) (f-4-4 3)) 9745 (rts16-sem) 9746 ()) 9747 9748(dni rts32 "rts" ((machine 32)) 9749 ("rts") 9750 (+ (f-0-4 #xD) (f-4-4 #xF)) 9751 (rts32-sem) 9752 ()) 9753 9754;------------------------------------------------------------- 9755; sbb - subtract with borrow 9756;------------------------------------------------------------- 9757 9758(define-pmacro (sbb-sem mode src dst) 9759 (sequence ((mode result)) 9760 (set result (subc mode dst src cbit)) 9761 (set obit (add-oflag mode dst src cbit)) 9762 (set cbit (add-oflag mode dst src cbit)) 9763 (set-z-and-s result) 9764 (set dst result)) 9765) 9766 9767; sbb.size:G #imm,dst 9768(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) 9769(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) 9770(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem) 9771(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem) 9772 9773; sbb.BW:G src,dst 9774(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) 9775(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) 9776(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem) 9777(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem) 9778 9779;------------------------------------------------------------- 9780; sbjnz - subtract then jump on not zero 9781;------------------------------------------------------------- 9782 9783(define-pmacro (sub-jnz-sem mode src dst label) 9784 (sequence ((mode result)) 9785 (set result (sub mode dst src)) 9786 (set dst result) 9787 (if (ne result 0) 9788 (set pc label))) 9789) 9790 9791; sbjnz.size #imm4,dst,label 9792(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) 9793 9794;------------------------------------------------------------- 9795; sccnd - store condition on condition (m32) 9796;------------------------------------------------------------- 9797 9798(define-pmacro (sccnd-sem cnd dst) 9799 (sequence () 9800 (set dst 0) 9801 (case DFLT cnd 9802 ((#x00) (if (not cbit) (set dst 1))) ;ltu nc 9803 ((#x01) (if (or cbit zbit) (set dst 1))) ;leu 9804 ((#x02) (if (not zbit) (set dst 1))) ;ne nz 9805 ((#x03) (if (not sbit) (set dst 1))) ;pz 9806 ((#x04) (if (not obit) (set dst 1))) ;no 9807 ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt 9808 ((#x06) (if (xor sbit obit) (set dst 1))) ;ge 9809 ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c 9810 ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu 9811 ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z 9812 ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n 9813 ((#x0c) (if (trunc BI obit) (set dst 1))) ;o 9814 ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le 9815 ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt 9816 ) 9817 ) 9818 ) 9819 9820; scCND dst 9821(dni sccnd 9822 "sccnd dst" 9823 ((machine 32)) 9824 "sc$sccond32 ${dst32-16-Unprefixed-HI}" 9825 (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32) 9826 (sccnd-sem sccond32 dst32-16-Unprefixed-HI) 9827 ()) 9828 9829;------------------------------------------------------------- 9830; scmpu - string compare unequal (m32) 9831;------------------------------------------------------------- 9832 9833; TODO semantics 9834(dni scmpu.b "scmpu.b" ((machine 32)) 9835 ("scmpu.b") 9836 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3)) 9837 (c-call VOID "scmpu_QI_semantics") 9838 ()) 9839 9840(dni scmpu.w "scmpu.w" ((machine 32)) 9841 ("scmpu.w") 9842 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3)) 9843 (c-call VOID "scmpu_HI_semantics") 9844 ()) 9845 9846;------------------------------------------------------------- 9847; sha - shift arithmetic 9848;------------------------------------------------------------- 9849 9850; TODO future: split this into .b and .w semantics 9851(define-pmacro (sha-sem mode src1 dst) 9852 (sequence ((mode result)(mode shift)(mode shmode)) 9853 (case DFLT src1 9854 ((#x0) (set shift 1)) 9855 ((#x1) (set shift 2)) 9856 ((#x2) (set shift 3)) 9857 ((#x3) (set shift 4)) 9858 ((#x4) (set shift 5)) 9859 ((#x5) (set shift 6)) 9860 ((#x6) (set shift 7)) 9861 ((#x7) (set shift 8)) 9862 ((-8) (set shift -1)) 9863 ((-7) (set shift -2)) 9864 ((-6) (set shift -3)) 9865 ((-5) (set shift -4)) 9866 ((-4) (set shift -5)) 9867 ((-3) (set shift -6)) 9868 ((-2) (set shift -7)) 9869 ((-1) (set shift -8)) 9870 (else (set shift 0)) 9871 ) 9872 (set shmode -1) 9873 (set shmode (srl shmode #x8)) 9874 (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1)))) 9875 (if (gt mode shift 0) (set result (sll mode dst shift))) 9876 (if (eq shmode #x0) ; QI 9877 (sequence 9878 ((mode cbitamt)) 9879 (if (lt mode shift #x0) 9880 (set cbitamt (sub #x8 shift)) ; sra 9881 (set cbitamt (sub shift 1))) ; sll 9882 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 9883 (set obit (ne (and dst #x80) (and result #x80))) 9884 )) 9885 (if (eq shmode #xff) ; HI 9886 (sequence 9887 ((mode cbitamt)) 9888 (if (lt mode shift #x0) 9889 (set cbitamt (sub 16 shift)) ; sra 9890 (set cbitamt (sub shift 1))) ; sll 9891 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 9892 (set obit (ne (and dst #x8000) (and result #x8000))) 9893 )) 9894 (set-z-and-s result) 9895 (set dst result)) 9896) 9897(define-pmacro (shar1h-sem mode dst) 9898 (sequence ((mode result)(mode shmode)) 9899 (set shmode -1) 9900 (set shmode (srl shmode #x8)) 9901 (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h)))) 9902 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) 9903 (if (eq shmode #x0) ; QI 9904 (sequence 9905 ((mode cbitamt)) 9906 (if (lt mode (reg h-r1h) #x0) 9907 (set cbitamt (sub #x8 (reg h-r1h))) ; sra 9908 (set cbitamt (sub (reg h-r1h) 1))) ; sll 9909 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 9910 (set obit (ne (and dst #x80) (and result #x80))) 9911 )) 9912 (if (eq shmode #xff) ; HI 9913 (sequence 9914 ((mode cbitamt)) 9915 (if (lt mode (reg h-r1h) #x0) 9916 (set cbitamt (sub 16 (reg h-r1h))) ; sra 9917 (set cbitamt (sub (reg h-r1h) 1))) ; sll 9918 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 9919 (set obit (ne (and dst #x8000) (and result #x8000))) 9920 )) 9921 (set-z-and-s result) 9922 (set dst result)) 9923) 9924; sha.BW #imm4,dst (m16 #1 m32 #1) 9925(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem) 9926(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem) 9927(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem) 9928(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem) 9929; sha.BW r1h,dst (m16 #2 m32 #3) 9930(dni sha16.b-dst "sha.b r1h,dest" ((machine 16)) 9931 ("sha.b r1h,${dst16-16-QI}") 9932 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI) 9933 (shar1h-sem HI dst16-16-QI) 9934 ()) 9935(dni sha16.w-dst "sha.w r1h,dest" ((machine 16)) 9936 ("sha.w r1h,${dst16-16-HI}") 9937 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI) 9938 (shar1h-sem HI dst16-16-HI) 9939 ()) 9940(dni sha32.b-dst "sha.b r1h,dest" ((machine 32)) 9941 ("sha.b r1h,${dst32-16-Unprefixed-QI}") 9942 (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) 9943 (shar1h-sem QI dst32-16-Unprefixed-QI) 9944 ()) 9945(dni sha32.w-dst "sha.w r1h,dest" ((machine 32)) 9946 ("sha.w r1h,${dst32-16-Unprefixed-HI}") 9947 (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 9948 (shar1h-sem HI dst32-16-Unprefixed-HI) 9949 ()) 9950; sha.L #imm,dst (m16 #3) 9951(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16)) 9952 "sha.l #${Imm-sh-12-s4},r2r0" 9953 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4) 9954 (sha-sem SI Imm-sh-12-s4 (reg h-r2r0)) 9955 ()) 9956(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16)) 9957 "sha.l #${Imm-sh-12-s4},r3r1" 9958 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4) 9959 (sha-sem SI Imm-sh-12-s4 (reg h-r3r1)) 9960 ()) 9961; sha.L r1h,dst (m16 #4) 9962(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16)) 9963 "sha.l r1h,r2r0" 9964 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1)) 9965 (sha-sem SI (reg h-r1h) (reg h-r2r0)) 9966 ()) 9967(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16)) 9968 "sha.l r1h,r3r1" 9969 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1)) 9970 (sha-sem SI (reg h-r1h) (reg h-r3r1)) 9971 ()) 9972; sha.L #imm8,dst (m32 #2) 9973(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem) 9974; sha.L r1h,dst (m32 #4) 9975(dni sha32.l-dst "sha.l r1h,dest" ((machine 32)) 9976 ("sha.l r1h,${dst32-16-Unprefixed-SI}") 9977 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1)) 9978 (shar1h-sem QI dst32-16-Unprefixed-SI) 9979 ()) 9980 9981;------------------------------------------------------------- 9982; shanc - shift arithmetic non carry (m32) 9983;------------------------------------------------------------- 9984 9985; TODO check semantics 9986; shanc.L #imm8,dst 9987(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem) 9988 9989;------------------------------------------------------------- 9990; shl - shift logical 9991;------------------------------------------------------------- 9992 9993; TODO future: split this into .b and .w semantics 9994(define-pmacro (shl-sem mode src1 dst) 9995 (sequence ((mode result)(mode shift)(mode shmode)) 9996 (case DFLT src1 9997 ((#x0) (set shift 1)) 9998 ((#x1) (set shift 2)) 9999 ((#x2) (set shift 3)) 10000 ((#x3) (set shift 4)) 10001 ((#x4) (set shift 5)) 10002 ((#x5) (set shift 6)) 10003 ((#x6) (set shift 7)) 10004 ((#x7) (set shift 8)) 10005 ((-8) (set shift -1)) 10006 ((-7) (set shift -2)) 10007 ((-6) (set shift -3)) 10008 ((-5) (set shift -4)) 10009 ((-4) (set shift -5)) 10010 ((-3) (set shift -6)) 10011 ((-2) (set shift -7)) 10012 ((-1) (set shift -8)) 10013 (else (set shift 0)) 10014 ) 10015 (set shmode -1) 10016 (set shmode (srl shmode #x8)) 10017 (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1)))) 10018 (if (gt mode shift 0) (set result (sll mode dst shift))) 10019 (if (eq shmode #x0) ; QI 10020 (sequence 10021 ((mode cbitamt)) 10022 (if (lt mode shift #x0) 10023 (set cbitamt (sub #x8 shift)); srl 10024 (set cbitamt (sub shift 1))) ; sll 10025 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 10026 (set obit (ne (and dst #x80) (and result #x80))) 10027 )) 10028 (if (eq shmode #xff) ; HI 10029 (sequence 10030 ((mode cbitamt)) 10031 (if (lt mode shift #x0) 10032 (set cbitamt (sub 16 shift)) ; srl 10033 (set cbitamt (sub shift 1))) ; sll 10034 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 10035 (set obit (ne (and dst #x8000) (and result #x8000))) 10036 )) 10037 (set-z-and-s result) 10038 (set dst result)) 10039 ) 10040(define-pmacro (shlr1h-sem mode dst) 10041 (sequence ((mode result)(mode shmode)) 10042 (set shmode -1) 10043 (set shmode (srl shmode #x8)) 10044 (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h)))) 10045 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) 10046 (if (eq shmode #x0) ; QI 10047 (sequence 10048 ((mode cbitamt)) 10049 (if (lt mode (reg h-r1h) #x0) 10050 (set cbitamt (sub #x8 (reg h-r1h))) ; srl 10051 (set cbitamt (sub (reg h-r1h) 1))) ; sll 10052 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 10053 (set obit (ne (and dst #x80) (and result #x80))) 10054 )) 10055 (if (eq shmode #xff) ; HI 10056 (sequence 10057 ((mode cbitamt)) 10058 (if (lt mode (reg h-r1h) #x0) 10059 (set cbitamt (sub 16 (reg h-r1h))) ; srl 10060 (set cbitamt (sub (reg h-r1h) 1))) ; sll 10061 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 10062 (set obit (ne (and dst #x8000) (and result #x8000))) 10063 )) 10064 (set-z-and-s result) 10065 (set dst result)) 10066 ) 10067; shl.BW #imm4,dst (m16 #1 m32 #1) 10068(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem) 10069(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem) 10070(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem) 10071(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem) 10072; shl.BW r1h,dst (m16 #2 m32 #3) 10073(dni shl16.b-dst "shl.b r1h,dest" ((machine 16)) 10074 ("shl.b r1h,${dst16-16-QI}") 10075 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI) 10076 (shlr1h-sem HI dst16-16-QI) 10077 ()) 10078(dni shl16.w-dst "shl.w r1h,dest" ((machine 16)) 10079 ("shl.w r1h,${dst16-16-HI}") 10080 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI) 10081 (shlr1h-sem HI dst16-16-HI) 10082 ()) 10083(dni shl32.b-dst "shl.b r1h,dest" ((machine 32)) 10084 ("shl.b r1h,${dst32-16-Unprefixed-QI}") 10085 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) 10086 (shlr1h-sem QI dst32-16-Unprefixed-QI) 10087 ()) 10088(dni shl32.w-dst "shl.w r1h,dest" ((machine 32)) 10089 ("shl.w r1h,${dst32-16-Unprefixed-HI}") 10090 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 10091 (shlr1h-sem HI dst32-16-Unprefixed-HI) 10092 ()) 10093; shl.L #imm,dst (m16 #3) 10094(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16)) 10095 "shl.l #${Imm-sh-12-s4},r2r0" 10096 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4) 10097 (shl-sem SI Imm-sh-12-s4 (reg h-r2r0)) 10098 ()) 10099(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16)) 10100 "shl.l #${Imm-sh-12-s4},r3r1" 10101 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4) 10102 (shl-sem SI Imm-sh-12-s4 (reg h-r3r1)) 10103 ()) 10104; shl.L r1h,dst (m16 #4) 10105(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16)) 10106 "shl.l r1h,r2r0" 10107 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1)) 10108 (shl-sem SI (reg h-r1h) (reg h-r2r0)) 10109 ()) 10110(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16)) 10111 "shl.l r1h,r3r1" 10112 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1)) 10113 (shl-sem SI (reg h-r1h) (reg h-r3r1)) 10114 ()) 10115; shl.L #imm8,dst (m32 #2) 10116(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem) 10117; shl.L r1h,dst (m32 #4) 10118(dni shl32.l-dst "shl.l r1h,dest" ((machine 32)) 10119 ("shl.l r1h,${dst32-16-Unprefixed-SI}") 10120 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1)) 10121 (shlr1h-sem QI dst32-16-Unprefixed-SI) 10122 ()) 10123 10124;------------------------------------------------------------- 10125; shlnc - shift logical non carry 10126;------------------------------------------------------------- 10127 10128; TODO check semantics 10129; shlnc.L #imm8,dst 10130(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem) 10131 10132;------------------------------------------------------------- 10133; sin - string input (m32) 10134;------------------------------------------------------------- 10135 10136; TODO semantics 10137(dni sin32.b "sin" ((machine 32)) 10138 ("sin.b") 10139 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3)) 10140 (c-call VOID "sin_QI_semantics") 10141 ()) 10142 10143(dni sin32.w "sin" ((machine 32)) 10144 ("sin.w") 10145 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3)) 10146 (c-call VOID "sin_HI_semantics") 10147 ()) 10148 10149;------------------------------------------------------------- 10150; smovb - string move backward 10151;------------------------------------------------------------- 10152 10153; TODO semantics 10154(dni smovb16.b "smovb.b" ((machine 16)) 10155 ("smovb.b") 10156 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9)) 10157 (c-call VOID "smovb_QI_semantics") 10158 ()) 10159 10160(dni smovb16.w "smovb.w" ((machine 16)) 10161 ("smovb.w") 10162 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9)) 10163 (c-call VOID "smovb_HI_semantics") 10164 ()) 10165 10166(dni smovb32.b "smovb.b" ((machine 32)) 10167 ("smovb.b") 10168 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3)) 10169 (c-call VOID "smovb_QI_semantics") 10170 ()) 10171 10172(dni smovb32.w "smovb.w" ((machine 32)) 10173 ("smovb.w") 10174 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3)) 10175 (c-call VOID "smovb_HI_semantics") 10176 ()) 10177 10178;------------------------------------------------------------- 10179; smovf - string move forward (m32) 10180;------------------------------------------------------------- 10181 10182; TODO semantics 10183(dni smovf16.b "smovf.b" ((machine 16)) 10184 ("smovf.b") 10185 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8)) 10186 (c-call VOID "smovf_QI_semantics") 10187 ()) 10188 10189(dni smovf16.w "smovf.w" ((machine 16)) 10190 ("smovf.w") 10191 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8)) 10192 (c-call VOID "smovf_HI_semantics") 10193 ()) 10194 10195(dni smovf32.b "smovf.b" ((machine 32)) 10196 ("smovf.b") 10197 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3)) 10198 (c-call VOID "smovf_QI_semantics") 10199 ()) 10200 10201(dni smovf32.w "smovf.w" ((machine 32)) 10202 ("smovf.w") 10203 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3)) 10204 (c-call VOID "smovf_HI_semantics") 10205 ()) 10206 10207;------------------------------------------------------------- 10208; smovu - string move unequal (m32) 10209;------------------------------------------------------------- 10210 10211; TODO semantics 10212(dni smovu.b "smovu.b" ((machine 32)) 10213 ("smovu.b") 10214 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3)) 10215 (c-call VOID "smovu_QI_semantics") 10216 ()) 10217 10218(dni smovu.w "smovu.w" ((machine 32)) 10219 ("smovu.w") 10220 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3)) 10221 (c-call VOID "smovu_HI_semantics") 10222 ()) 10223 10224;------------------------------------------------------------- 10225; sout - string output (m32) 10226;------------------------------------------------------------- 10227 10228; TODO semantics 10229(dni sout.b "sout.b" ((machine 32)) 10230 ("sout.b") 10231 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3)) 10232 (c-call VOID "sout_QI_semantics") 10233 ()) 10234 10235(dni sout.w "sout" ((machine 32)) 10236 ("sout.w") 10237 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3)) 10238 (c-call VOID "sout_HI_semantics") 10239 ()) 10240 10241;------------------------------------------------------------- 10242; sstr - string store 10243;------------------------------------------------------------- 10244 10245; TODO semantics 10246(dni sstr16.b "sstr.b" ((machine 16)) 10247 ("sstr.b") 10248 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA)) 10249 (c-call VOID "sstr_QI_semantics") 10250 ()) 10251 10252(dni sstr16.w "sstr.w" ((machine 16)) 10253 ("sstr.w") 10254 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA)) 10255 (c-call VOID "sstr_HI_semantics") 10256 ()) 10257 10258(dni sstr.b "sstr" ((machine 32)) 10259 ("sstr.b") 10260 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3)) 10261 (c-call VOID "sstr_QI_semantics") 10262 ()) 10263 10264(dni sstr.w "sstr" ((machine 32)) 10265 ("sstr.w") 10266 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3)) 10267 (c-call VOID "sstr_HI_semantics") 10268 ()) 10269 10270;------------------------------------------------------------- 10271; stnz - store on not zero 10272;------------------------------------------------------------- 10273 10274(define-pmacro (stnz-sem mode src dst) 10275 (sequence () 10276 (if (ne zbit (const 1)) 10277 (set dst src))) 10278) 10279; stnz #imm8,dst3 (m16) 10280(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem) 10281; stnz.BW #imm,dst (m32) 10282(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem) 10283(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem) 10284 10285;------------------------------------------------------------- 10286; stz - store on zero 10287;------------------------------------------------------------- 10288 10289(define-pmacro (stz-sem mode src dst) 10290 (sequence () 10291 (if (eq zbit (const 1)) 10292 (set dst src))) 10293) 10294; stz #imm8,dst3 (m16) 10295(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem) 10296; stz.BW #imm,dst (m32) 10297(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem) 10298(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem) 10299 10300;------------------------------------------------------------- 10301; stzx - store on zero extention 10302;------------------------------------------------------------- 10303 10304(define-pmacro (stzx-sem mode src1 src2 dst) 10305 (sequence () 10306 (if (eq zbit (const 1)) 10307 (set dst src1) 10308 (set dst src2))) 10309 ) 10310; stzx #imm8,dst3 (m16) 10311(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16)) 10312 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h") 10313 (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI) 10314 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h)) 10315 ()) 10316(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16)) 10317 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l") 10318 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI) 10319 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) 10320 ()) 10321(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) 10322 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]") 10323 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) 10324 (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) 10325 ()) 10326(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) 10327 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]") 10328 (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI) 10329 (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8))) 10330 ()) 10331(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) 10332 ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") 10333 (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) 10334 (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) 10335 ()) 10336; stzx.BW #imm,dst (m32) 10337(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem) 10338 10339;------------------------------------------------------------- 10340; subx - subtract extend (m32) 10341;------------------------------------------------------------- 10342 10343(define-pmacro (subx-sem mode src1 dst) 10344 (sequence ((mode result)) 10345 (set result (sub mode dst (ext mode src1))) 10346 (set obit (sub-oflag mode dst (ext mode src1) 0)) 10347 (set cbit (sub-cflag mode dst (ext mode src1) 0)) 10348 (set dst result) 10349 (set-z-and-s result))) 10350; subx #imm8,dst 10351(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem) 10352; subx src,dst 10353(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem) 10354 10355;------------------------------------------------------------- 10356; tst - test 10357;------------------------------------------------------------- 10358 10359(define-pmacro (tst-sem mode src1 dst) 10360 (sequence ((mode result)) 10361 (set result (and mode dst src1)) 10362 (set-z-and-s result)) 10363) 10364 10365; tst.BW #imm,dst (m16 #1 m32 #1) 10366(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) 10367; tst.BW src,dst (m16 #2 m32 #3) 10368(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) 10369(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) 10370(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem) 10371(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem) 10372; tst.BW:S #imm,dst2 (m32 #2) 10373(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) 10374(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) 10375 10376;------------------------------------------------------------- 10377; und - undefined 10378;------------------------------------------------------------- 10379 10380(dni und16 "und" ((machine 16)) 10381 ("und") 10382 (+ (f-0-4 #xF) (f-4-4 #xF)) 10383 (nop) 10384 ()) 10385 10386(dni und32 "und" ((machine 32)) 10387 ("und") 10388 (+ (f-0-4 #xF) (f-4-4 #xF)) 10389 (nop) 10390 ()) 10391 10392;------------------------------------------------------------- 10393; wait 10394;------------------------------------------------------------- 10395 10396; ??? semantics 10397(dni wait16 "wait" ((machine 16)) 10398 ("wait") 10399 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3)) 10400 (nop) 10401 ()) 10402 10403(dni wait "wait" ((machine 32)) 10404 ("wait") 10405 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3)) 10406 (nop) 10407 ()) 10408 10409;------------------------------------------------------------- 10410; xchg - exchange 10411;------------------------------------------------------------- 10412 10413(define-pmacro (xchg-sem mode src dst) 10414 (sequence ((mode result)) 10415 (set result src) 10416 (set src dst) 10417 (set dst result)) 10418 ) 10419(define-pmacro (xchg16-defn mode sz szc src srcreg) 10420 (dni (.sym xchg16 sz - srcreg) 10421 (.str "xchg" sz "-" srcreg ",dst16-16-" mode) 10422 ((machine 16)) 10423 (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}") 10424 (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode)) 10425 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode)) 10426 ()) 10427) 10428(xchg16-defn QI b 0 0 r0l) 10429(xchg16-defn QI b 0 1 r0h) 10430(xchg16-defn QI b 0 2 r1l) 10431(xchg16-defn QI b 0 3 r1h) 10432(xchg16-defn HI w 1 0 r0) 10433(xchg16-defn HI w 1 1 r1) 10434(xchg16-defn HI w 1 2 r2) 10435(xchg16-defn HI w 1 3 r3) 10436(define-pmacro (xchg32-defn mode sz szc src srcreg) 10437 (dni (.sym xchg32 sz - srcreg) 10438 (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode) 10439 ((machine 32)) 10440 (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}") 10441 (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src)) 10442 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode)) 10443 ()) 10444) 10445(xchg32-defn QI b 0 0 r0l) 10446(xchg32-defn QI b 0 1 r1l) 10447(xchg32-defn QI b 0 2 a0) 10448(xchg32-defn QI b 0 3 a1) 10449(xchg32-defn QI b 0 4 r0h) 10450(xchg32-defn QI b 0 5 r1h) 10451(xchg32-defn HI w 1 0 r0) 10452(xchg32-defn HI w 1 1 r1) 10453(xchg32-defn HI w 1 2 a0) 10454(xchg32-defn HI w 1 3 a1) 10455(xchg32-defn HI w 1 4 r2) 10456(xchg32-defn HI w 1 5 r3) 10457 10458;------------------------------------------------------------- 10459; xor - exclusive or 10460;------------------------------------------------------------- 10461 10462(define-pmacro (xor-sem mode src1 dst) 10463 (sequence ((mode result)) 10464 (set result (xor mode src1 dst)) 10465 (set-z-and-s result) 10466 (set dst result)) 10467) 10468 10469; xor.BW #imm,dst (m16 #1 m32 #1) 10470(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem) 10471; xor.BW src,dst (m16 #3 m32 #3) 10472(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem) 10473 10474;------------------------------------------------------------- 10475; Widening 10476;------------------------------------------------------------- 10477 10478(define-pmacro (exts-sem smode dmode src dst) 10479 (set dst (ext dmode (trunc smode src))) 10480) 10481(define-pmacro (extz-sem smode dmode src dst) 10482 (set dst (zext dmode (trunc smode src))) 10483) 10484 10485; exts.b dst for m16c 10486(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem) 10487 10488; exts.w r0 for m16c 10489(dni exts16.w-r0 10490 "exts.w r0" 10491 ((machine 16)) 10492 "exts.w r0" 10493 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3)) 10494 (exts-sem HI SI R0 R2R0) 10495 ()) 10496 10497; exts.size dst for m32c 10498(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) 10499(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) 10500; exts.b src,dst for m32c 10501(ext32-binary-defn exts .b #x1 #x7 exts-sem) 10502 10503; extz.b src,dst for m32c 10504(ext32-binary-defn extz "" #x1 #xB extz-sem) 10505 10506;------------------------------------------------------------- 10507; Indirect 10508;------------------------------------------------------------- 10509 10510; TODO semantics 10511(dni srcind "SRC-INDIRECT" ((machine 32)) 10512 ("src-indirect") 10513 (+ (f-0-4 4) (f-4-4 1)) 10514 (set (reg h-src-indirect) 1) 10515 ()) 10516 10517(dni destind "DEST-INDIRECT" ((machine 32)) 10518 ("dest-indirect") 10519 (+ (f-0-4 0) (f-4-4 9)) 10520 (set (reg h-dst-indirect) 1) 10521 ()) 10522 10523(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32)) 10524 ("src-dest-indirect") 10525 (+ (f-0-4 4) (f-4-4 9)) 10526 (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1)) 10527 ()) 10528