1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "as.h" 23 #include "safe-ctype.h" 24 #include "subsegs.h" 25 26 #include "opcode/sparc.h" 27 #include "dw2gencfi.h" 28 29 #ifdef OBJ_ELF 30 #include "elf/sparc.h" 31 #include "dwarf2dbg.h" 32 #endif 33 34 /* Some ancient Sun C compilers would not take such hex constants as 35 unsigned, and would end up sign-extending them to form an offsetT, 36 so use these constants instead. */ 37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 39 40 static int sparc_ip (char *, const struct sparc_opcode **); 41 static int parse_keyword_arg (int (*) (const char *), char **, int *); 42 static int parse_const_expr_arg (char **, int *); 43 static int get_expression (char *); 44 45 /* Default architecture. */ 46 /* ??? The default value should be V8, but sparclite support was added 47 by making it the default. GCC now passes -Asparclite, so maybe sometime in 48 the future we can set this to V8. */ 49 #ifndef DEFAULT_ARCH 50 #define DEFAULT_ARCH "sparclite" 51 #endif 52 static char *default_arch = DEFAULT_ARCH; 53 54 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 55 have been set. */ 56 static int default_init_p; 57 58 /* Current architecture. We don't bump up unless necessary. */ 59 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 60 61 /* The maximum architecture level we can bump up to. 62 In a 32 bit environment, don't allow bumping up to v9 by default. 63 The native assembler works this way. The user is required to pass 64 an explicit argument before we'll create v9 object files. However, if 65 we don't see any v9 insns, a v8plus object file is not created. */ 66 static enum sparc_opcode_arch_val max_architecture; 67 68 /* Either 32 or 64, selects file format. */ 69 static int sparc_arch_size; 70 /* Initial (default) value, recorded separately in case a user option 71 changes the value before md_show_usage is called. */ 72 static int default_arch_size; 73 74 #ifdef OBJ_ELF 75 /* The currently selected v9 memory model. Currently only used for 76 ELF. */ 77 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 78 #endif 79 80 static int architecture_requested; 81 static int warn_on_bump; 82 83 /* If warn_on_bump and the needed architecture is higher than this 84 architecture, issue a warning. */ 85 static enum sparc_opcode_arch_val warn_after_architecture; 86 87 /* Non-zero if as should generate error if an undeclared g[23] register 88 has been used in -64. */ 89 static int no_undeclared_regs; 90 91 /* Non-zero if we should try to relax jumps and calls. */ 92 static int sparc_relax; 93 94 /* Non-zero if we are generating PIC code. */ 95 int sparc_pic_code; 96 97 /* Non-zero if we should give an error when misaligned data is seen. */ 98 static int enforce_aligned_data; 99 100 extern int target_big_endian; 101 102 static int target_little_endian_data; 103 104 /* Symbols for global registers on v9. */ 105 static symbolS *globals[8]; 106 107 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 108 int sparc_cie_data_alignment; 109 110 /* V9 and 86x have big and little endian data, but instructions are always big 111 endian. The sparclet has bi-endian support but both data and insns have 112 the same endianness. Global `target_big_endian' is used for data. 113 The following macro is used for instructions. */ 114 #ifndef INSN_BIG_ENDIAN 115 #define INSN_BIG_ENDIAN (target_big_endian \ 116 || default_arch_type == sparc86x \ 117 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 118 #endif 119 120 /* Handle of the OPCODE hash table. */ 121 static struct hash_control *op_hash; 122 123 static void s_data1 (void); 124 static void s_seg (int); 125 static void s_proc (int); 126 static void s_reserve (int); 127 static void s_common (int); 128 static void s_empty (int); 129 static void s_uacons (int); 130 static void s_ncons (int); 131 #ifdef OBJ_ELF 132 static void s_register (int); 133 #endif 134 135 const pseudo_typeS md_pseudo_table[] = 136 { 137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 138 {"common", s_common, 0}, 139 {"empty", s_empty, 0}, 140 {"global", s_globl, 0}, 141 {"half", cons, 2}, 142 {"nword", s_ncons, 0}, 143 {"optim", s_ignore, 0}, 144 {"proc", s_proc, 0}, 145 {"reserve", s_reserve, 0}, 146 {"seg", s_seg, 0}, 147 {"skip", s_space, 0}, 148 {"word", cons, 4}, 149 {"xword", cons, 8}, 150 {"uahalf", s_uacons, 2}, 151 {"uaword", s_uacons, 4}, 152 {"uaxword", s_uacons, 8}, 153 #ifdef OBJ_ELF 154 /* These are specific to sparc/svr4. */ 155 {"2byte", s_uacons, 2}, 156 {"4byte", s_uacons, 4}, 157 {"8byte", s_uacons, 8}, 158 {"register", s_register, 0}, 159 #endif 160 {NULL, 0, 0}, 161 }; 162 163 /* This array holds the chars that always start a comment. If the 164 pre-processor is disabled, these aren't very useful. */ 165 const char comment_chars[] = "!"; /* JF removed '|' from 166 comment_chars. */ 167 168 /* This array holds the chars that only start a comment at the beginning of 169 a line. If the line seems to have the form '# 123 filename' 170 .line and .file directives will appear in the pre-processed output. */ 171 /* Note that input_file.c hand checks for '#' at the beginning of the 172 first line of the input file. This is because the compiler outputs 173 #NO_APP at the beginning of its output. */ 174 /* Also note that comments started like this one will always 175 work if '/' isn't otherwise defined. */ 176 const char line_comment_chars[] = "#"; 177 178 const char line_separator_chars[] = ";"; 179 180 /* Chars that can be used to separate mant from exp in floating point 181 nums. */ 182 const char EXP_CHARS[] = "eE"; 183 184 /* Chars that mean this number is a floating point constant. 185 As in 0f12.456 186 or 0d1.2345e12 */ 187 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 188 189 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 190 changed in read.c. Ideally it shouldn't have to know about it at all, 191 but nothing is ideal around here. */ 192 193 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 194 195 struct sparc_it 196 { 197 char *error; 198 unsigned long opcode; 199 struct nlist *nlistp; 200 expressionS exp; 201 expressionS exp2; 202 int pcrel; 203 bfd_reloc_code_real_type reloc; 204 }; 205 206 struct sparc_it the_insn, set_insn; 207 208 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 209 210 /* Table of arguments to -A. 211 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 212 for this use. That table is for opcodes only. This table is for opcodes 213 and file formats. */ 214 215 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 216 v8plusa, v9, v9a, v9b, v9_64}; 217 218 static struct sparc_arch { 219 char *name; 220 char *opcode_arch; 221 enum sparc_arch_types arch_type; 222 /* Default word size, as specified during configuration. 223 A value of zero means can't be used to specify default architecture. */ 224 int default_arch_size; 225 /* Allowable arg to -A? */ 226 int user_option_p; 227 } sparc_arch_table[] = { 228 { "v6", "v6", v6, 0, 1 }, 229 { "v7", "v7", v7, 0, 1 }, 230 { "v8", "v8", v8, 32, 1 }, 231 { "sparclet", "sparclet", sparclet, 32, 1 }, 232 { "sparclite", "sparclite", sparclite, 32, 1 }, 233 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 234 { "v8plus", "v9", v9, 0, 1 }, 235 { "v8plusa", "v9a", v9, 0, 1 }, 236 { "v8plusb", "v9b", v9, 0, 1 }, 237 { "v9", "v9", v9, 0, 1 }, 238 { "v9a", "v9a", v9, 0, 1 }, 239 { "v9b", "v9b", v9, 0, 1 }, 240 /* This exists to allow configure.in/Makefile.in to pass one 241 value to specify both the default machine and default word size. */ 242 { "v9-64", "v9", v9, 64, 0 }, 243 { NULL, NULL, v8, 0, 0 } 244 }; 245 246 /* Variant of default_arch */ 247 static enum sparc_arch_types default_arch_type; 248 249 static struct sparc_arch * 250 lookup_arch (char *name) 251 { 252 struct sparc_arch *sa; 253 254 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 255 if (strcmp (sa->name, name) == 0) 256 break; 257 if (sa->name == NULL) 258 return NULL; 259 return sa; 260 } 261 262 /* Initialize the default opcode arch and word size from the default 263 architecture name. */ 264 265 static void 266 init_default_arch (void) 267 { 268 struct sparc_arch *sa = lookup_arch (default_arch); 269 270 if (sa == NULL 271 || sa->default_arch_size == 0) 272 as_fatal (_("Invalid default architecture, broken assembler.")); 273 274 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 275 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 276 as_fatal (_("Bad opcode table, broken assembler.")); 277 default_arch_size = sparc_arch_size = sa->default_arch_size; 278 default_init_p = 1; 279 default_arch_type = sa->arch_type; 280 } 281 282 /* Called by TARGET_FORMAT. */ 283 284 const char * 285 sparc_target_format (void) 286 { 287 /* We don't get a chance to initialize anything before we're called, 288 so handle that now. */ 289 if (! default_init_p) 290 init_default_arch (); 291 292 #ifdef OBJ_AOUT 293 #ifdef TE_NetBSD 294 return "a.out-sparc-netbsd"; 295 #else 296 #ifdef TE_SPARCAOUT 297 if (target_big_endian) 298 return "a.out-sunos-big"; 299 else if (default_arch_type == sparc86x && target_little_endian_data) 300 return "a.out-sunos-big"; 301 else 302 return "a.out-sparc-little"; 303 #else 304 return "a.out-sunos-big"; 305 #endif 306 #endif 307 #endif 308 309 #ifdef OBJ_BOUT 310 return "b.out.big"; 311 #endif 312 313 #ifdef OBJ_COFF 314 #ifdef TE_LYNX 315 return "coff-sparc-lynx"; 316 #else 317 return "coff-sparc"; 318 #endif 319 #endif 320 321 #ifdef TE_VXWORKS 322 return "elf32-sparc-vxworks"; 323 #endif 324 325 #ifdef OBJ_ELF 326 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 327 #endif 328 329 abort (); 330 } 331 332 /* md_parse_option 333 * Invocation line includes a switch not recognized by the base assembler. 334 * See if it's a processor-specific option. These are: 335 * 336 * -bump 337 * Warn on architecture bumps. See also -A. 338 * 339 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 340 * Standard 32 bit architectures. 341 * -Av9, -Av9a, -Av9b 342 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 343 * This used to only mean 64 bits, but properly specifying it 344 * complicated gcc's ASM_SPECs, so now opcode selection is 345 * specified orthogonally to word size (except when specifying 346 * the default, but that is an internal implementation detail). 347 * -Av8plus, -Av8plusa, -Av8plusb 348 * Same as -Av9{,a,b}. 349 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 350 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 351 * assembler. 352 * -xarch=v9, -xarch=v9a, -xarch=v9b 353 * Same as -Av9{,a,b} -64, for compatibility with Sun's 354 * assembler. 355 * 356 * Select the architecture and possibly the file format. 357 * Instructions or features not supported by the selected 358 * architecture cause fatal errors. 359 * 360 * The default is to start at v6, and bump the architecture up 361 * whenever an instruction is seen at a higher level. In 32 bit 362 * environments, v9 is not bumped up to, the user must pass 363 * -Av8plus{,a,b}. 364 * 365 * If -bump is specified, a warning is printing when bumping to 366 * higher levels. 367 * 368 * If an architecture is specified, all instructions must match 369 * that architecture. Any higher level instructions are flagged 370 * as errors. Note that in the 32 bit environment specifying 371 * -Av8plus does not automatically create a v8plus object file, a 372 * v9 insn must be seen. 373 * 374 * If both an architecture and -bump are specified, the 375 * architecture starts at the specified level, but bumps are 376 * warnings. Note that we can't set `current_architecture' to 377 * the requested level in this case: in the 32 bit environment, 378 * we still must avoid creating v8plus object files unless v9 379 * insns are seen. 380 * 381 * Note: 382 * Bumping between incompatible architectures is always an 383 * error. For example, from sparclite to v9. 384 */ 385 386 #ifdef OBJ_ELF 387 const char *md_shortopts = "A:K:VQ:sq"; 388 #else 389 #ifdef OBJ_AOUT 390 const char *md_shortopts = "A:k"; 391 #else 392 const char *md_shortopts = "A:"; 393 #endif 394 #endif 395 struct option md_longopts[] = { 396 #define OPTION_BUMP (OPTION_MD_BASE) 397 {"bump", no_argument, NULL, OPTION_BUMP}, 398 #define OPTION_SPARC (OPTION_MD_BASE + 1) 399 {"sparc", no_argument, NULL, OPTION_SPARC}, 400 #define OPTION_XARCH (OPTION_MD_BASE + 2) 401 {"xarch", required_argument, NULL, OPTION_XARCH}, 402 #ifdef OBJ_ELF 403 #define OPTION_32 (OPTION_MD_BASE + 3) 404 {"32", no_argument, NULL, OPTION_32}, 405 #define OPTION_64 (OPTION_MD_BASE + 4) 406 {"64", no_argument, NULL, OPTION_64}, 407 #define OPTION_TSO (OPTION_MD_BASE + 5) 408 {"TSO", no_argument, NULL, OPTION_TSO}, 409 #define OPTION_PSO (OPTION_MD_BASE + 6) 410 {"PSO", no_argument, NULL, OPTION_PSO}, 411 #define OPTION_RMO (OPTION_MD_BASE + 7) 412 {"RMO", no_argument, NULL, OPTION_RMO}, 413 #endif 414 #ifdef SPARC_BIENDIAN 415 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 416 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 417 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 418 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 419 #endif 420 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 421 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 422 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 423 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 424 #ifdef OBJ_ELF 425 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 426 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 427 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 428 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 429 #endif 430 #define OPTION_RELAX (OPTION_MD_BASE + 14) 431 {"relax", no_argument, NULL, OPTION_RELAX}, 432 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 433 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 434 {NULL, no_argument, NULL, 0} 435 }; 436 437 size_t md_longopts_size = sizeof (md_longopts); 438 439 int 440 md_parse_option (int c, char *arg) 441 { 442 /* We don't get a chance to initialize anything before we're called, 443 so handle that now. */ 444 if (! default_init_p) 445 init_default_arch (); 446 447 switch (c) 448 { 449 case OPTION_BUMP: 450 warn_on_bump = 1; 451 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 452 break; 453 454 case OPTION_XARCH: 455 #ifdef OBJ_ELF 456 if (strncmp (arg, "v9", 2) != 0) 457 md_parse_option (OPTION_32, NULL); 458 else 459 md_parse_option (OPTION_64, NULL); 460 #endif 461 /* Fall through. */ 462 463 case 'A': 464 { 465 struct sparc_arch *sa; 466 enum sparc_opcode_arch_val opcode_arch; 467 468 sa = lookup_arch (arg); 469 if (sa == NULL 470 || ! sa->user_option_p) 471 { 472 if (c == OPTION_XARCH) 473 as_bad (_("invalid architecture -xarch=%s"), arg); 474 else 475 as_bad (_("invalid architecture -A%s"), arg); 476 return 0; 477 } 478 479 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 480 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 481 as_fatal (_("Bad opcode table, broken assembler.")); 482 483 max_architecture = opcode_arch; 484 architecture_requested = 1; 485 } 486 break; 487 488 case OPTION_SPARC: 489 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 490 break; 491 492 case OPTION_ENFORCE_ALIGNED_DATA: 493 enforce_aligned_data = 1; 494 break; 495 496 #ifdef SPARC_BIENDIAN 497 case OPTION_LITTLE_ENDIAN: 498 target_big_endian = 0; 499 if (default_arch_type != sparclet) 500 as_fatal ("This target does not support -EL"); 501 break; 502 case OPTION_LITTLE_ENDIAN_DATA: 503 target_little_endian_data = 1; 504 target_big_endian = 0; 505 if (default_arch_type != sparc86x 506 && default_arch_type != v9) 507 as_fatal ("This target does not support --little-endian-data"); 508 break; 509 case OPTION_BIG_ENDIAN: 510 target_big_endian = 1; 511 break; 512 #endif 513 514 #ifdef OBJ_AOUT 515 case 'k': 516 sparc_pic_code = 1; 517 break; 518 #endif 519 520 #ifdef OBJ_ELF 521 case OPTION_32: 522 case OPTION_64: 523 { 524 const char **list, **l; 525 526 sparc_arch_size = c == OPTION_32 ? 32 : 64; 527 list = bfd_target_list (); 528 for (l = list; *l != NULL; l++) 529 { 530 if (sparc_arch_size == 32) 531 { 532 if (CONST_STRNEQ (*l, "elf32-sparc")) 533 break; 534 } 535 else 536 { 537 if (CONST_STRNEQ (*l, "elf64-sparc")) 538 break; 539 } 540 } 541 if (*l == NULL) 542 as_fatal (_("No compiled in support for %d bit object file format"), 543 sparc_arch_size); 544 free (list); 545 } 546 break; 547 548 case OPTION_TSO: 549 sparc_memory_model = MM_TSO; 550 break; 551 552 case OPTION_PSO: 553 sparc_memory_model = MM_PSO; 554 break; 555 556 case OPTION_RMO: 557 sparc_memory_model = MM_RMO; 558 break; 559 560 case 'V': 561 print_version_id (); 562 break; 563 564 case 'Q': 565 /* Qy - do emit .comment 566 Qn - do not emit .comment. */ 567 break; 568 569 case 's': 570 /* Use .stab instead of .stab.excl. */ 571 break; 572 573 case 'q': 574 /* quick -- Native assembler does fewer checks. */ 575 break; 576 577 case 'K': 578 if (strcmp (arg, "PIC") != 0) 579 as_warn (_("Unrecognized option following -K")); 580 else 581 sparc_pic_code = 1; 582 break; 583 584 case OPTION_NO_UNDECLARED_REGS: 585 no_undeclared_regs = 1; 586 break; 587 588 case OPTION_UNDECLARED_REGS: 589 no_undeclared_regs = 0; 590 break; 591 #endif 592 593 case OPTION_RELAX: 594 sparc_relax = 1; 595 break; 596 597 case OPTION_NO_RELAX: 598 sparc_relax = 0; 599 break; 600 601 default: 602 return 0; 603 } 604 605 return 1; 606 } 607 608 void 609 md_show_usage (FILE *stream) 610 { 611 const struct sparc_arch *arch; 612 int column; 613 614 /* We don't get a chance to initialize anything before we're called, 615 so handle that now. */ 616 if (! default_init_p) 617 init_default_arch (); 618 619 fprintf (stream, _("SPARC options:\n")); 620 column = 0; 621 for (arch = &sparc_arch_table[0]; arch->name; arch++) 622 { 623 if (!arch->user_option_p) 624 continue; 625 if (arch != &sparc_arch_table[0]) 626 fprintf (stream, " | "); 627 if (column + strlen (arch->name) > 70) 628 { 629 column = 0; 630 fputc ('\n', stream); 631 } 632 column += 5 + 2 + strlen (arch->name); 633 fprintf (stream, "-A%s", arch->name); 634 } 635 for (arch = &sparc_arch_table[0]; arch->name; arch++) 636 { 637 if (!arch->user_option_p) 638 continue; 639 fprintf (stream, " | "); 640 if (column + strlen (arch->name) > 65) 641 { 642 column = 0; 643 fputc ('\n', stream); 644 } 645 column += 5 + 7 + strlen (arch->name); 646 fprintf (stream, "-xarch=%s", arch->name); 647 } 648 fprintf (stream, _("\n\ 649 specify variant of SPARC architecture\n\ 650 -bump warn when assembler switches architectures\n\ 651 -sparc ignored\n\ 652 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 653 -relax relax jumps and branches (default)\n\ 654 -no-relax avoid changing any jumps and branches\n")); 655 #ifdef OBJ_AOUT 656 fprintf (stream, _("\ 657 -k generate PIC\n")); 658 #endif 659 #ifdef OBJ_ELF 660 fprintf (stream, _("\ 661 -32 create 32 bit object file\n\ 662 -64 create 64 bit object file\n")); 663 fprintf (stream, _("\ 664 [default is %d]\n"), default_arch_size); 665 fprintf (stream, _("\ 666 -TSO use Total Store Ordering\n\ 667 -PSO use Partial Store Ordering\n\ 668 -RMO use Relaxed Memory Ordering\n")); 669 fprintf (stream, _("\ 670 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 671 fprintf (stream, _("\ 672 -KPIC generate PIC\n\ 673 -V print assembler version number\n\ 674 -undeclared-regs ignore application global register usage without\n\ 675 appropriate .register directive (default)\n\ 676 -no-undeclared-regs force error on application global register usage\n\ 677 without appropriate .register directive\n\ 678 -q ignored\n\ 679 -Qy, -Qn ignored\n\ 680 -s ignored\n")); 681 #endif 682 #ifdef SPARC_BIENDIAN 683 fprintf (stream, _("\ 684 -EL generate code for a little endian machine\n\ 685 -EB generate code for a big endian machine\n\ 686 --little-endian-data generate code for a machine having big endian\n\ 687 instructions and little endian data.\n")); 688 #endif 689 } 690 691 /* Native operand size opcode translation. */ 692 struct 693 { 694 char *name; 695 char *name32; 696 char *name64; 697 } native_op_table[] = 698 { 699 {"ldn", "ld", "ldx"}, 700 {"ldna", "lda", "ldxa"}, 701 {"stn", "st", "stx"}, 702 {"stna", "sta", "stxa"}, 703 {"slln", "sll", "sllx"}, 704 {"srln", "srl", "srlx"}, 705 {"sran", "sra", "srax"}, 706 {"casn", "cas", "casx"}, 707 {"casna", "casa", "casxa"}, 708 {"clrn", "clr", "clrx"}, 709 {NULL, NULL, NULL}, 710 }; 711 712 /* sparc64 privileged and hyperprivileged registers. */ 713 714 struct priv_reg_entry 715 { 716 char *name; 717 int regnum; 718 }; 719 720 struct priv_reg_entry priv_reg_table[] = 721 { 722 {"tpc", 0}, 723 {"tnpc", 1}, 724 {"tstate", 2}, 725 {"tt", 3}, 726 {"tick", 4}, 727 {"tba", 5}, 728 {"pstate", 6}, 729 {"tl", 7}, 730 {"pil", 8}, 731 {"cwp", 9}, 732 {"cansave", 10}, 733 {"canrestore", 11}, 734 {"cleanwin", 12}, 735 {"otherwin", 13}, 736 {"wstate", 14}, 737 {"fq", 15}, 738 {"gl", 16}, 739 {"ver", 31}, 740 {"", -1}, /* End marker. */ 741 }; 742 743 struct priv_reg_entry hpriv_reg_table[] = 744 { 745 {"hpstate", 0}, 746 {"htstate", 1}, 747 {"hintp", 3}, 748 {"htba", 5}, 749 {"hver", 6}, 750 {"hstick_cmpr", 31}, 751 {"", -1}, /* End marker. */ 752 }; 753 754 /* v9a specific asrs. This table is ordered by initial 755 letter, in reverse. */ 756 757 struct priv_reg_entry v9a_asr_table[] = 758 { 759 {"tick_cmpr", 23}, 760 {"sys_tick_cmpr", 25}, 761 {"sys_tick", 24}, 762 {"stick_cmpr", 25}, 763 {"stick", 24}, 764 {"softint_clear", 21}, 765 {"softint_set", 20}, 766 {"softint", 22}, 767 {"set_softint", 20}, 768 {"pic", 17}, 769 {"pcr", 16}, 770 {"gsr", 19}, 771 {"dcr", 18}, 772 {"clear_softint", 21}, 773 {"", -1}, /* End marker. */ 774 }; 775 776 static int 777 cmp_reg_entry (const void *parg, const void *qarg) 778 { 779 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 780 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 781 782 return strcmp (q->name, p->name); 783 } 784 785 /* This function is called once, at assembler startup time. It should 786 set up all the tables, etc. that the MD part of the assembler will 787 need. */ 788 789 void 790 md_begin (void) 791 { 792 register const char *retval = NULL; 793 int lose = 0; 794 register unsigned int i = 0; 795 796 /* We don't get a chance to initialize anything before md_parse_option 797 is called, and it may not be called, so handle default initialization 798 now if not already done. */ 799 if (! default_init_p) 800 init_default_arch (); 801 802 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 803 op_hash = hash_new (); 804 805 while (i < (unsigned int) sparc_num_opcodes) 806 { 807 const char *name = sparc_opcodes[i].name; 808 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 809 if (retval != NULL) 810 { 811 as_bad (_("Internal error: can't hash `%s': %s\n"), 812 sparc_opcodes[i].name, retval); 813 lose = 1; 814 } 815 do 816 { 817 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 818 { 819 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 820 sparc_opcodes[i].name, sparc_opcodes[i].args); 821 lose = 1; 822 } 823 ++i; 824 } 825 while (i < (unsigned int) sparc_num_opcodes 826 && !strcmp (sparc_opcodes[i].name, name)); 827 } 828 829 for (i = 0; native_op_table[i].name; i++) 830 { 831 const struct sparc_opcode *insn; 832 char *name = ((sparc_arch_size == 32) 833 ? native_op_table[i].name32 834 : native_op_table[i].name64); 835 insn = (struct sparc_opcode *) hash_find (op_hash, name); 836 if (insn == NULL) 837 { 838 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 839 name, native_op_table[i].name); 840 lose = 1; 841 } 842 else 843 { 844 retval = hash_insert (op_hash, native_op_table[i].name, 845 (void *) insn); 846 if (retval != NULL) 847 { 848 as_bad (_("Internal error: can't hash `%s': %s\n"), 849 sparc_opcodes[i].name, retval); 850 lose = 1; 851 } 852 } 853 } 854 855 if (lose) 856 as_fatal (_("Broken assembler. No assembly attempted.")); 857 858 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 859 sizeof (priv_reg_table[0]), cmp_reg_entry); 860 861 /* If -bump, record the architecture level at which we start issuing 862 warnings. The behaviour is different depending upon whether an 863 architecture was explicitly specified. If it wasn't, we issue warnings 864 for all upwards bumps. If it was, we don't start issuing warnings until 865 we need to bump beyond the requested architecture or when we bump between 866 conflicting architectures. */ 867 868 if (warn_on_bump 869 && architecture_requested) 870 { 871 /* `max_architecture' records the requested architecture. 872 Issue warnings if we go above it. */ 873 warn_after_architecture = max_architecture; 874 875 /* Find the highest architecture level that doesn't conflict with 876 the requested one. */ 877 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 878 max_architecture > warn_after_architecture; 879 --max_architecture) 880 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 881 warn_after_architecture)) 882 break; 883 } 884 } 885 886 /* Called after all assembly has been done. */ 887 888 void 889 sparc_md_end (void) 890 { 891 unsigned long mach = bfd_mach_sparc; 892 893 if (sparc_arch_size == 64) 894 switch (current_architecture) 895 { 896 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 897 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 898 default: mach = bfd_mach_sparc_v9; break; 899 } 900 else 901 switch (current_architecture) 902 { 903 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 904 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 905 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 906 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 907 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 908 be but for now it is (since that's the way it's always been 909 treated). */ 910 default: break; 911 } 912 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 913 } 914 915 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 916 917 static inline int 918 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 919 { 920 if (max <= 0) 921 abort (); 922 /* Sign-extend the value from the architecture word size, so that 923 0xffffffff is always considered -1 on sparc32. */ 924 if (sparc_arch_size == 32) 925 { 926 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 927 val = ((val & U0xffffffff) ^ sign) - sign; 928 } 929 if (val > max) 930 return 0; 931 if (val < ~max) 932 return 0; 933 return 1; 934 } 935 936 /* Return non-zero if VAL is in the range 0 to MAX. */ 937 938 static inline int 939 in_unsigned_range (bfd_vma val, bfd_vma max) 940 { 941 if (val > max) 942 return 0; 943 return 1; 944 } 945 946 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 947 (e.g. -15 to +31). */ 948 949 static inline int 950 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 951 { 952 if (max <= 0) 953 abort (); 954 if (val > max) 955 return 0; 956 if (val < ~(max >> 1)) 957 return 0; 958 return 1; 959 } 960 961 static int 962 sparc_ffs (unsigned int mask) 963 { 964 int i; 965 966 if (mask == 0) 967 return -1; 968 969 for (i = 0; (mask & 1) == 0; ++i) 970 mask >>= 1; 971 return i; 972 } 973 974 /* Implement big shift right. */ 975 static bfd_vma 976 BSR (bfd_vma val, int amount) 977 { 978 if (sizeof (bfd_vma) <= 4 && amount >= 32) 979 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 980 return val >> amount; 981 } 982 983 /* For communication between sparc_ip and get_expression. */ 984 static char *expr_end; 985 986 /* Values for `special_case'. 987 Instructions that require wierd handling because they're longer than 988 4 bytes. */ 989 #define SPECIAL_CASE_NONE 0 990 #define SPECIAL_CASE_SET 1 991 #define SPECIAL_CASE_SETSW 2 992 #define SPECIAL_CASE_SETX 3 993 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 994 #define SPECIAL_CASE_FDIV 4 995 996 /* Bit masks of various insns. */ 997 #define NOP_INSN 0x01000000 998 #define OR_INSN 0x80100000 999 #define XOR_INSN 0x80180000 1000 #define FMOVS_INSN 0x81A00020 1001 #define SETHI_INSN 0x01000000 1002 #define SLLX_INSN 0x81281000 1003 #define SRA_INSN 0x81380000 1004 1005 /* The last instruction to be assembled. */ 1006 static const struct sparc_opcode *last_insn; 1007 /* The assembled opcode of `last_insn'. */ 1008 static unsigned long last_opcode; 1009 1010 /* Handle the set and setuw synthetic instructions. */ 1011 1012 static void 1013 synthetize_setuw (const struct sparc_opcode *insn) 1014 { 1015 int need_hi22_p = 0; 1016 int rd = (the_insn.opcode & RD (~0)) >> 25; 1017 1018 if (the_insn.exp.X_op == O_constant) 1019 { 1020 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1021 { 1022 if (sizeof (offsetT) > 4 1023 && (the_insn.exp.X_add_number < 0 1024 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1025 as_warn (_("set: number not in 0..4294967295 range")); 1026 } 1027 else 1028 { 1029 if (sizeof (offsetT) > 4 1030 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1031 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1032 as_warn (_("set: number not in -2147483648..4294967295 range")); 1033 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1034 } 1035 } 1036 1037 /* See if operand is absolute and small; skip sethi if so. */ 1038 if (the_insn.exp.X_op != O_constant 1039 || the_insn.exp.X_add_number >= (1 << 12) 1040 || the_insn.exp.X_add_number < -(1 << 12)) 1041 { 1042 the_insn.opcode = (SETHI_INSN | RD (rd) 1043 | ((the_insn.exp.X_add_number >> 10) 1044 & (the_insn.exp.X_op == O_constant 1045 ? 0x3fffff : 0))); 1046 the_insn.reloc = (the_insn.exp.X_op != O_constant 1047 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1048 output_insn (insn, &the_insn); 1049 need_hi22_p = 1; 1050 } 1051 1052 /* See if operand has no low-order bits; skip OR if so. */ 1053 if (the_insn.exp.X_op != O_constant 1054 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1055 || ! need_hi22_p) 1056 { 1057 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1058 | RD (rd) | IMMED 1059 | (the_insn.exp.X_add_number 1060 & (the_insn.exp.X_op != O_constant 1061 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1062 the_insn.reloc = (the_insn.exp.X_op != O_constant 1063 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1064 output_insn (insn, &the_insn); 1065 } 1066 } 1067 1068 /* Handle the setsw synthetic instruction. */ 1069 1070 static void 1071 synthetize_setsw (const struct sparc_opcode *insn) 1072 { 1073 int low32, rd, opc; 1074 1075 rd = (the_insn.opcode & RD (~0)) >> 25; 1076 1077 if (the_insn.exp.X_op != O_constant) 1078 { 1079 synthetize_setuw (insn); 1080 1081 /* Need to sign extend it. */ 1082 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1083 the_insn.reloc = BFD_RELOC_NONE; 1084 output_insn (insn, &the_insn); 1085 return; 1086 } 1087 1088 if (sizeof (offsetT) > 4 1089 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1090 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1091 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1092 1093 low32 = the_insn.exp.X_add_number; 1094 1095 if (low32 >= 0) 1096 { 1097 synthetize_setuw (insn); 1098 return; 1099 } 1100 1101 opc = OR_INSN; 1102 1103 the_insn.reloc = BFD_RELOC_NONE; 1104 /* See if operand is absolute and small; skip sethi if so. */ 1105 if (low32 < -(1 << 12)) 1106 { 1107 the_insn.opcode = (SETHI_INSN | RD (rd) 1108 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1109 output_insn (insn, &the_insn); 1110 low32 = 0x1c00 | (low32 & 0x3ff); 1111 opc = RS1 (rd) | XOR_INSN; 1112 } 1113 1114 the_insn.opcode = (opc | RD (rd) | IMMED 1115 | (low32 & 0x1fff)); 1116 output_insn (insn, &the_insn); 1117 } 1118 1119 /* Handle the setsw synthetic instruction. */ 1120 1121 static void 1122 synthetize_setx (const struct sparc_opcode *insn) 1123 { 1124 int upper32, lower32; 1125 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1126 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1127 int upper_dstreg; 1128 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1129 int need_xor10_p = 0; 1130 1131 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1132 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1133 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1134 #undef SIGNEXT32 1135 1136 upper_dstreg = tmpreg; 1137 /* The tmp reg should not be the dst reg. */ 1138 if (tmpreg == dstreg) 1139 as_warn (_("setx: temporary register same as destination register")); 1140 1141 /* ??? Obviously there are other optimizations we can do 1142 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1143 doing some of these. Later. If you do change things, try to 1144 change all of this to be table driven as well. */ 1145 /* What to output depends on the number if it's constant. 1146 Compute that first, then output what we've decided upon. */ 1147 if (the_insn.exp.X_op != O_constant) 1148 { 1149 if (sparc_arch_size == 32) 1150 { 1151 /* When arch size is 32, we want setx to be equivalent 1152 to setuw for anything but constants. */ 1153 the_insn.exp.X_add_number &= 0xffffffff; 1154 synthetize_setuw (insn); 1155 return; 1156 } 1157 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1158 lower32 = 0; 1159 upper32 = 0; 1160 } 1161 else 1162 { 1163 /* Reset X_add_number, we've extracted it as upper32/lower32. 1164 Otherwise fixup_segment will complain about not being able to 1165 write an 8 byte number in a 4 byte field. */ 1166 the_insn.exp.X_add_number = 0; 1167 1168 /* Only need hh22 if `or' insn can't handle constant. */ 1169 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1170 need_hh22_p = 1; 1171 1172 /* Does bottom part (after sethi) have bits? */ 1173 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1174 /* No hh22, but does upper32 still have bits we can't set 1175 from lower32? */ 1176 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1177 need_hm10_p = 1; 1178 1179 /* If the lower half is all zero, we build the upper half directly 1180 into the dst reg. */ 1181 if (lower32 != 0 1182 /* Need lower half if number is zero or 0xffffffff00000000. */ 1183 || (! need_hh22_p && ! need_hm10_p)) 1184 { 1185 /* No need for sethi if `or' insn can handle constant. */ 1186 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1187 /* Note that we can't use a negative constant in the `or' 1188 insn unless the upper 32 bits are all ones. */ 1189 || (lower32 < 0 && upper32 != -1) 1190 || (lower32 >= 0 && upper32 == -1)) 1191 need_hi22_p = 1; 1192 1193 if (need_hi22_p && upper32 == -1) 1194 need_xor10_p = 1; 1195 1196 /* Does bottom part (after sethi) have bits? */ 1197 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1198 /* No sethi. */ 1199 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1200 /* Need `or' if we didn't set anything else. */ 1201 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1202 need_lo10_p = 1; 1203 } 1204 else 1205 /* Output directly to dst reg if lower 32 bits are all zero. */ 1206 upper_dstreg = dstreg; 1207 } 1208 1209 if (!upper_dstreg && dstreg) 1210 as_warn (_("setx: illegal temporary register g0")); 1211 1212 if (need_hh22_p) 1213 { 1214 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1215 | ((upper32 >> 10) & 0x3fffff)); 1216 the_insn.reloc = (the_insn.exp.X_op != O_constant 1217 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1218 output_insn (insn, &the_insn); 1219 } 1220 1221 if (need_hi22_p) 1222 { 1223 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1224 | (((need_xor10_p ? ~lower32 : lower32) 1225 >> 10) & 0x3fffff)); 1226 the_insn.reloc = (the_insn.exp.X_op != O_constant 1227 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1228 output_insn (insn, &the_insn); 1229 } 1230 1231 if (need_hm10_p) 1232 { 1233 the_insn.opcode = (OR_INSN 1234 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1235 | RD (upper_dstreg) 1236 | IMMED 1237 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1238 the_insn.reloc = (the_insn.exp.X_op != O_constant 1239 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1240 output_insn (insn, &the_insn); 1241 } 1242 1243 if (need_lo10_p) 1244 { 1245 /* FIXME: One nice optimization to do here is to OR the low part 1246 with the highpart if hi22 isn't needed and the low part is 1247 positive. */ 1248 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1249 | RD (dstreg) 1250 | IMMED 1251 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1252 the_insn.reloc = (the_insn.exp.X_op != O_constant 1253 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1254 output_insn (insn, &the_insn); 1255 } 1256 1257 /* If we needed to build the upper part, shift it into place. */ 1258 if (need_hh22_p || need_hm10_p) 1259 { 1260 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1261 | IMMED | 32); 1262 the_insn.reloc = BFD_RELOC_NONE; 1263 output_insn (insn, &the_insn); 1264 } 1265 1266 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1267 if (need_xor10_p) 1268 { 1269 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1270 | 0x1c00 | (lower32 & 0x3ff)); 1271 the_insn.reloc = BFD_RELOC_NONE; 1272 output_insn (insn, &the_insn); 1273 } 1274 1275 /* If we needed to build both upper and lower parts, OR them together. */ 1276 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1277 { 1278 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1279 | RD (dstreg)); 1280 the_insn.reloc = BFD_RELOC_NONE; 1281 output_insn (insn, &the_insn); 1282 } 1283 } 1284 1285 /* Main entry point to assemble one instruction. */ 1286 1287 void 1288 md_assemble (char *str) 1289 { 1290 const struct sparc_opcode *insn; 1291 int special_case; 1292 1293 know (str); 1294 special_case = sparc_ip (str, &insn); 1295 if (insn == NULL) 1296 return; 1297 1298 /* We warn about attempts to put a floating point branch in a delay slot, 1299 unless the delay slot has been annulled. */ 1300 if (last_insn != NULL 1301 && (insn->flags & F_FBR) != 0 1302 && (last_insn->flags & F_DELAYED) != 0 1303 /* ??? This test isn't completely accurate. We assume anything with 1304 F_{UNBR,CONDBR,FBR} set is annullable. */ 1305 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1306 || (last_opcode & ANNUL) == 0)) 1307 as_warn (_("FP branch in delay slot")); 1308 1309 /* SPARC before v9 requires a nop instruction between a floating 1310 point instruction and a floating point branch. We insert one 1311 automatically, with a warning. */ 1312 if (max_architecture < SPARC_OPCODE_ARCH_V9 1313 && last_insn != NULL 1314 && (insn->flags & F_FBR) != 0 1315 && (last_insn->flags & F_FLOAT) != 0) 1316 { 1317 struct sparc_it nop_insn; 1318 1319 nop_insn.opcode = NOP_INSN; 1320 nop_insn.reloc = BFD_RELOC_NONE; 1321 output_insn (insn, &nop_insn); 1322 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1323 } 1324 1325 switch (special_case) 1326 { 1327 case SPECIAL_CASE_NONE: 1328 /* Normal insn. */ 1329 output_insn (insn, &the_insn); 1330 break; 1331 1332 case SPECIAL_CASE_SETSW: 1333 synthetize_setsw (insn); 1334 break; 1335 1336 case SPECIAL_CASE_SET: 1337 synthetize_setuw (insn); 1338 break; 1339 1340 case SPECIAL_CASE_SETX: 1341 synthetize_setx (insn); 1342 break; 1343 1344 case SPECIAL_CASE_FDIV: 1345 { 1346 int rd = (the_insn.opcode >> 25) & 0x1f; 1347 1348 output_insn (insn, &the_insn); 1349 1350 /* According to information leaked from Sun, the "fdiv" instructions 1351 on early SPARC machines would produce incorrect results sometimes. 1352 The workaround is to add an fmovs of the destination register to 1353 itself just after the instruction. This was true on machines 1354 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1355 assert (the_insn.reloc == BFD_RELOC_NONE); 1356 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1357 output_insn (insn, &the_insn); 1358 return; 1359 } 1360 1361 default: 1362 as_fatal (_("failed special case insn sanity check")); 1363 } 1364 } 1365 1366 /* Subroutine of md_assemble to do the actual parsing. */ 1367 1368 static int 1369 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1370 { 1371 char *error_message = ""; 1372 char *s; 1373 const char *args; 1374 char c; 1375 const struct sparc_opcode *insn; 1376 char *argsStart; 1377 unsigned long opcode; 1378 unsigned int mask = 0; 1379 int match = 0; 1380 int comma = 0; 1381 int v9_arg_p; 1382 int special_case = SPECIAL_CASE_NONE; 1383 1384 s = str; 1385 if (ISLOWER (*s)) 1386 { 1387 do 1388 ++s; 1389 while (ISLOWER (*s) || ISDIGIT (*s)); 1390 } 1391 1392 switch (*s) 1393 { 1394 case '\0': 1395 break; 1396 1397 case ',': 1398 comma = 1; 1399 /* Fall through. */ 1400 1401 case ' ': 1402 *s++ = '\0'; 1403 break; 1404 1405 default: 1406 as_bad (_("Unknown opcode: `%s'"), str); 1407 *pinsn = NULL; 1408 return special_case; 1409 } 1410 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1411 *pinsn = insn; 1412 if (insn == NULL) 1413 { 1414 as_bad (_("Unknown opcode: `%s'"), str); 1415 return special_case; 1416 } 1417 if (comma) 1418 { 1419 *--s = ','; 1420 } 1421 1422 argsStart = s; 1423 for (;;) 1424 { 1425 opcode = insn->match; 1426 memset (&the_insn, '\0', sizeof (the_insn)); 1427 the_insn.reloc = BFD_RELOC_NONE; 1428 v9_arg_p = 0; 1429 1430 /* Build the opcode, checking as we go to make sure that the 1431 operands match. */ 1432 for (args = insn->args;; ++args) 1433 { 1434 switch (*args) 1435 { 1436 case 'K': 1437 { 1438 int kmask = 0; 1439 1440 /* Parse a series of masks. */ 1441 if (*s == '#') 1442 { 1443 while (*s == '#') 1444 { 1445 int mask; 1446 1447 if (! parse_keyword_arg (sparc_encode_membar, &s, 1448 &mask)) 1449 { 1450 error_message = _(": invalid membar mask name"); 1451 goto error; 1452 } 1453 kmask |= mask; 1454 while (*s == ' ') 1455 ++s; 1456 if (*s == '|' || *s == '+') 1457 ++s; 1458 while (*s == ' ') 1459 ++s; 1460 } 1461 } 1462 else 1463 { 1464 if (! parse_const_expr_arg (&s, &kmask)) 1465 { 1466 error_message = _(": invalid membar mask expression"); 1467 goto error; 1468 } 1469 if (kmask < 0 || kmask > 127) 1470 { 1471 error_message = _(": invalid membar mask number"); 1472 goto error; 1473 } 1474 } 1475 1476 opcode |= MEMBAR (kmask); 1477 continue; 1478 } 1479 1480 case '3': 1481 { 1482 int smask = 0; 1483 1484 if (! parse_const_expr_arg (&s, &smask)) 1485 { 1486 error_message = _(": invalid siam mode expression"); 1487 goto error; 1488 } 1489 if (smask < 0 || smask > 7) 1490 { 1491 error_message = _(": invalid siam mode number"); 1492 goto error; 1493 } 1494 opcode |= smask; 1495 continue; 1496 } 1497 1498 case '*': 1499 { 1500 int fcn = 0; 1501 1502 /* Parse a prefetch function. */ 1503 if (*s == '#') 1504 { 1505 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1506 { 1507 error_message = _(": invalid prefetch function name"); 1508 goto error; 1509 } 1510 } 1511 else 1512 { 1513 if (! parse_const_expr_arg (&s, &fcn)) 1514 { 1515 error_message = _(": invalid prefetch function expression"); 1516 goto error; 1517 } 1518 if (fcn < 0 || fcn > 31) 1519 { 1520 error_message = _(": invalid prefetch function number"); 1521 goto error; 1522 } 1523 } 1524 opcode |= RD (fcn); 1525 continue; 1526 } 1527 1528 case '!': 1529 case '?': 1530 /* Parse a sparc64 privileged register. */ 1531 if (*s == '%') 1532 { 1533 struct priv_reg_entry *p = priv_reg_table; 1534 unsigned int len = 9999999; /* Init to make gcc happy. */ 1535 1536 s += 1; 1537 while (p->name[0] > s[0]) 1538 p++; 1539 while (p->name[0] == s[0]) 1540 { 1541 len = strlen (p->name); 1542 if (strncmp (p->name, s, len) == 0) 1543 break; 1544 p++; 1545 } 1546 if (p->name[0] != s[0]) 1547 { 1548 error_message = _(": unrecognizable privileged register"); 1549 goto error; 1550 } 1551 if (*args == '?') 1552 opcode |= (p->regnum << 14); 1553 else 1554 opcode |= (p->regnum << 25); 1555 s += len; 1556 continue; 1557 } 1558 else 1559 { 1560 error_message = _(": unrecognizable privileged register"); 1561 goto error; 1562 } 1563 1564 case '$': 1565 case '%': 1566 /* Parse a sparc64 hyperprivileged register. */ 1567 if (*s == '%') 1568 { 1569 struct priv_reg_entry *p = hpriv_reg_table; 1570 unsigned int len = 9999999; /* Init to make gcc happy. */ 1571 1572 s += 1; 1573 while (p->name[0] > s[0]) 1574 p++; 1575 while (p->name[0] == s[0]) 1576 { 1577 len = strlen (p->name); 1578 if (strncmp (p->name, s, len) == 0) 1579 break; 1580 p++; 1581 } 1582 if (p->name[0] != s[0]) 1583 { 1584 error_message = _(": unrecognizable hyperprivileged register"); 1585 goto error; 1586 } 1587 if (*args == '$') 1588 opcode |= (p->regnum << 14); 1589 else 1590 opcode |= (p->regnum << 25); 1591 s += len; 1592 continue; 1593 } 1594 else 1595 { 1596 error_message = _(": unrecognizable hyperprivileged register"); 1597 goto error; 1598 } 1599 1600 case '_': 1601 case '/': 1602 /* Parse a v9a/v9b ancillary state register. */ 1603 if (*s == '%') 1604 { 1605 struct priv_reg_entry *p = v9a_asr_table; 1606 unsigned int len = 9999999; /* Init to make gcc happy. */ 1607 1608 s += 1; 1609 while (p->name[0] > s[0]) 1610 p++; 1611 while (p->name[0] == s[0]) 1612 { 1613 len = strlen (p->name); 1614 if (strncmp (p->name, s, len) == 0) 1615 break; 1616 p++; 1617 } 1618 if (p->name[0] != s[0]) 1619 { 1620 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1621 goto error; 1622 } 1623 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1624 { 1625 error_message = _(": rd on write only ancillary state register"); 1626 goto error; 1627 } 1628 if (p->regnum >= 24 1629 && (insn->architecture 1630 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1631 { 1632 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1633 error_message = _(": unrecognizable v9a ancillary state register"); 1634 goto error; 1635 } 1636 if (*args == '/') 1637 opcode |= (p->regnum << 14); 1638 else 1639 opcode |= (p->regnum << 25); 1640 s += len; 1641 continue; 1642 } 1643 else 1644 { 1645 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1646 goto error; 1647 } 1648 1649 case 'M': 1650 case 'm': 1651 if (strncmp (s, "%asr", 4) == 0) 1652 { 1653 s += 4; 1654 1655 if (ISDIGIT (*s)) 1656 { 1657 long num = 0; 1658 1659 while (ISDIGIT (*s)) 1660 { 1661 num = num * 10 + *s - '0'; 1662 ++s; 1663 } 1664 1665 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1666 { 1667 if (num < 16 || 31 < num) 1668 { 1669 error_message = _(": asr number must be between 16 and 31"); 1670 goto error; 1671 } 1672 } 1673 else 1674 { 1675 if (num < 0 || 31 < num) 1676 { 1677 error_message = _(": asr number must be between 0 and 31"); 1678 goto error; 1679 } 1680 } 1681 1682 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1683 continue; 1684 } 1685 else 1686 { 1687 error_message = _(": expecting %asrN"); 1688 goto error; 1689 } 1690 } /* if %asr */ 1691 break; 1692 1693 case 'I': 1694 the_insn.reloc = BFD_RELOC_SPARC_11; 1695 goto immediate; 1696 1697 case 'j': 1698 the_insn.reloc = BFD_RELOC_SPARC_10; 1699 goto immediate; 1700 1701 case 'X': 1702 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1703 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1704 the_insn.reloc = BFD_RELOC_SPARC_5; 1705 else 1706 the_insn.reloc = BFD_RELOC_SPARC13; 1707 /* These fields are unsigned, but for upward compatibility, 1708 allow negative values as well. */ 1709 goto immediate; 1710 1711 case 'Y': 1712 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1713 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1714 the_insn.reloc = BFD_RELOC_SPARC_6; 1715 else 1716 the_insn.reloc = BFD_RELOC_SPARC13; 1717 /* These fields are unsigned, but for upward compatibility, 1718 allow negative values as well. */ 1719 goto immediate; 1720 1721 case 'k': 1722 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1723 the_insn.pcrel = 1; 1724 goto immediate; 1725 1726 case 'G': 1727 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1728 the_insn.pcrel = 1; 1729 goto immediate; 1730 1731 case 'N': 1732 if (*s == 'p' && s[1] == 'n') 1733 { 1734 s += 2; 1735 continue; 1736 } 1737 break; 1738 1739 case 'T': 1740 if (*s == 'p' && s[1] == 't') 1741 { 1742 s += 2; 1743 continue; 1744 } 1745 break; 1746 1747 case 'z': 1748 if (*s == ' ') 1749 { 1750 ++s; 1751 } 1752 if (strncmp (s, "%icc", 4) == 0) 1753 { 1754 s += 4; 1755 continue; 1756 } 1757 break; 1758 1759 case 'Z': 1760 if (*s == ' ') 1761 { 1762 ++s; 1763 } 1764 if (strncmp (s, "%xcc", 4) == 0) 1765 { 1766 s += 4; 1767 continue; 1768 } 1769 break; 1770 1771 case '6': 1772 if (*s == ' ') 1773 { 1774 ++s; 1775 } 1776 if (strncmp (s, "%fcc0", 5) == 0) 1777 { 1778 s += 5; 1779 continue; 1780 } 1781 break; 1782 1783 case '7': 1784 if (*s == ' ') 1785 { 1786 ++s; 1787 } 1788 if (strncmp (s, "%fcc1", 5) == 0) 1789 { 1790 s += 5; 1791 continue; 1792 } 1793 break; 1794 1795 case '8': 1796 if (*s == ' ') 1797 { 1798 ++s; 1799 } 1800 if (strncmp (s, "%fcc2", 5) == 0) 1801 { 1802 s += 5; 1803 continue; 1804 } 1805 break; 1806 1807 case '9': 1808 if (*s == ' ') 1809 { 1810 ++s; 1811 } 1812 if (strncmp (s, "%fcc3", 5) == 0) 1813 { 1814 s += 5; 1815 continue; 1816 } 1817 break; 1818 1819 case 'P': 1820 if (strncmp (s, "%pc", 3) == 0) 1821 { 1822 s += 3; 1823 continue; 1824 } 1825 break; 1826 1827 case 'W': 1828 if (strncmp (s, "%tick", 5) == 0) 1829 { 1830 s += 5; 1831 continue; 1832 } 1833 break; 1834 1835 case '\0': /* End of args. */ 1836 if (s[0] == ',' && s[1] == '%') 1837 { 1838 static const struct ops 1839 { 1840 /* The name as it appears in assembler. */ 1841 char *name; 1842 /* strlen (name), precomputed for speed */ 1843 int len; 1844 /* The reloc this pseudo-op translates to. */ 1845 int reloc; 1846 /* 1 if tls call. */ 1847 int tls_call; 1848 } 1849 ops[] = 1850 { 1851 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 1852 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 1853 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 1854 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 1855 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 1856 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 1857 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 1858 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, 1859 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, 1860 { NULL, 0, 0, 0 } 1861 }; 1862 const struct ops *o; 1863 char *s1; 1864 int npar = 0; 1865 1866 for (o = ops; o->name; o++) 1867 if (strncmp (s + 2, o->name, o->len) == 0) 1868 break; 1869 if (o->name == NULL) 1870 break; 1871 1872 if (s[o->len + 2] != '(') 1873 { 1874 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1875 return special_case; 1876 } 1877 1878 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) 1879 { 1880 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 1881 o->name); 1882 return special_case; 1883 } 1884 1885 if (o->tls_call 1886 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 1887 || the_insn.exp.X_add_number != 0 1888 || the_insn.exp.X_add_symbol 1889 != symbol_find_or_make ("__tls_get_addr"))) 1890 { 1891 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 1892 o->name); 1893 return special_case; 1894 } 1895 1896 the_insn.reloc = o->reloc; 1897 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 1898 s += o->len + 3; 1899 1900 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 1901 if (*s1 == '(') 1902 npar++; 1903 else if (*s1 == ')') 1904 { 1905 if (!npar) 1906 break; 1907 npar--; 1908 } 1909 1910 if (*s1 != ')') 1911 { 1912 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1913 return special_case; 1914 } 1915 1916 *s1 = '\0'; 1917 (void) get_expression (s); 1918 *s1 = ')'; 1919 s = s1 + 1; 1920 } 1921 if (*s == '\0') 1922 match = 1; 1923 break; 1924 1925 case '+': 1926 if (*s == '+') 1927 { 1928 ++s; 1929 continue; 1930 } 1931 if (*s == '-') 1932 { 1933 continue; 1934 } 1935 break; 1936 1937 case '[': /* These must match exactly. */ 1938 case ']': 1939 case ',': 1940 case ' ': 1941 if (*s++ == *args) 1942 continue; 1943 break; 1944 1945 case '#': /* Must be at least one digit. */ 1946 if (ISDIGIT (*s++)) 1947 { 1948 while (ISDIGIT (*s)) 1949 { 1950 ++s; 1951 } 1952 continue; 1953 } 1954 break; 1955 1956 case 'C': /* Coprocessor state register. */ 1957 if (strncmp (s, "%csr", 4) == 0) 1958 { 1959 s += 4; 1960 continue; 1961 } 1962 break; 1963 1964 case 'b': /* Next operand is a coprocessor register. */ 1965 case 'c': 1966 case 'D': 1967 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 1968 { 1969 mask = *s++; 1970 if (ISDIGIT (*s)) 1971 { 1972 mask = 10 * (mask - '0') + (*s++ - '0'); 1973 if (mask >= 32) 1974 { 1975 break; 1976 } 1977 } 1978 else 1979 { 1980 mask -= '0'; 1981 } 1982 switch (*args) 1983 { 1984 1985 case 'b': 1986 opcode |= mask << 14; 1987 continue; 1988 1989 case 'c': 1990 opcode |= mask; 1991 continue; 1992 1993 case 'D': 1994 opcode |= mask << 25; 1995 continue; 1996 } 1997 } 1998 break; 1999 2000 case 'r': /* next operand must be a register */ 2001 case 'O': 2002 case '1': 2003 case '2': 2004 case 'd': 2005 if (*s++ == '%') 2006 { 2007 switch (c = *s++) 2008 { 2009 2010 case 'f': /* frame pointer */ 2011 if (*s++ == 'p') 2012 { 2013 mask = 0x1e; 2014 break; 2015 } 2016 goto error; 2017 2018 case 'g': /* global register */ 2019 c = *s++; 2020 if (isoctal (c)) 2021 { 2022 mask = c - '0'; 2023 break; 2024 } 2025 goto error; 2026 2027 case 'i': /* in register */ 2028 c = *s++; 2029 if (isoctal (c)) 2030 { 2031 mask = c - '0' + 24; 2032 break; 2033 } 2034 goto error; 2035 2036 case 'l': /* local register */ 2037 c = *s++; 2038 if (isoctal (c)) 2039 { 2040 mask = (c - '0' + 16); 2041 break; 2042 } 2043 goto error; 2044 2045 case 'o': /* out register */ 2046 c = *s++; 2047 if (isoctal (c)) 2048 { 2049 mask = (c - '0' + 8); 2050 break; 2051 } 2052 goto error; 2053 2054 case 's': /* stack pointer */ 2055 if (*s++ == 'p') 2056 { 2057 mask = 0xe; 2058 break; 2059 } 2060 goto error; 2061 2062 case 'r': /* any register */ 2063 if (!ISDIGIT ((c = *s++))) 2064 { 2065 goto error; 2066 } 2067 /* FALLTHROUGH */ 2068 case '0': 2069 case '1': 2070 case '2': 2071 case '3': 2072 case '4': 2073 case '5': 2074 case '6': 2075 case '7': 2076 case '8': 2077 case '9': 2078 if (ISDIGIT (*s)) 2079 { 2080 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2081 { 2082 goto error; 2083 } 2084 } 2085 else 2086 { 2087 c -= '0'; 2088 } 2089 mask = c; 2090 break; 2091 2092 default: 2093 goto error; 2094 } 2095 2096 if ((mask & ~1) == 2 && sparc_arch_size == 64 2097 && no_undeclared_regs && ! globals[mask]) 2098 as_bad (_("detected global register use not covered by .register pseudo-op")); 2099 2100 /* Got the register, now figure out where 2101 it goes in the opcode. */ 2102 switch (*args) 2103 { 2104 case '1': 2105 opcode |= mask << 14; 2106 continue; 2107 2108 case '2': 2109 opcode |= mask; 2110 continue; 2111 2112 case 'd': 2113 opcode |= mask << 25; 2114 continue; 2115 2116 case 'r': 2117 opcode |= (mask << 25) | (mask << 14); 2118 continue; 2119 2120 case 'O': 2121 opcode |= (mask << 25) | (mask << 0); 2122 continue; 2123 } 2124 } 2125 break; 2126 2127 case 'e': /* next operand is a floating point register */ 2128 case 'v': 2129 case 'V': 2130 2131 case 'f': 2132 case 'B': 2133 case 'R': 2134 2135 case 'g': 2136 case 'H': 2137 case 'J': 2138 { 2139 char format; 2140 2141 if (*s++ == '%' 2142 && ((format = *s) == 'f') 2143 && ISDIGIT (*++s)) 2144 { 2145 for (mask = 0; ISDIGIT (*s); ++s) 2146 { 2147 mask = 10 * mask + (*s - '0'); 2148 } /* read the number */ 2149 2150 if ((*args == 'v' 2151 || *args == 'B' 2152 || *args == 'H') 2153 && (mask & 1)) 2154 { 2155 break; 2156 } /* register must be even numbered */ 2157 2158 if ((*args == 'V' 2159 || *args == 'R' 2160 || *args == 'J') 2161 && (mask & 3)) 2162 { 2163 break; 2164 } /* register must be multiple of 4 */ 2165 2166 if (mask >= 64) 2167 { 2168 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2169 error_message = _(": There are only 64 f registers; [0-63]"); 2170 else 2171 error_message = _(": There are only 32 f registers; [0-31]"); 2172 goto error; 2173 } /* on error */ 2174 else if (mask >= 32) 2175 { 2176 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2177 { 2178 if (*args == 'e' || *args == 'f' || *args == 'g') 2179 { 2180 error_message 2181 = _(": There are only 32 single precision f registers; [0-31]"); 2182 goto error; 2183 } 2184 v9_arg_p = 1; 2185 mask -= 31; /* wrap high bit */ 2186 } 2187 else 2188 { 2189 error_message = _(": There are only 32 f registers; [0-31]"); 2190 goto error; 2191 } 2192 } 2193 } 2194 else 2195 { 2196 break; 2197 } /* if not an 'f' register. */ 2198 2199 switch (*args) 2200 { 2201 case 'v': 2202 case 'V': 2203 case 'e': 2204 opcode |= RS1 (mask); 2205 continue; 2206 2207 case 'f': 2208 case 'B': 2209 case 'R': 2210 opcode |= RS2 (mask); 2211 continue; 2212 2213 case 'g': 2214 case 'H': 2215 case 'J': 2216 opcode |= RD (mask); 2217 continue; 2218 } /* Pack it in. */ 2219 2220 know (0); 2221 break; 2222 } /* float arg */ 2223 2224 case 'F': 2225 if (strncmp (s, "%fsr", 4) == 0) 2226 { 2227 s += 4; 2228 continue; 2229 } 2230 break; 2231 2232 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2233 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2234 goto immediate; 2235 2236 case 'l': /* 22 bit PC relative immediate */ 2237 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2238 the_insn.pcrel = 1; 2239 goto immediate; 2240 2241 case 'L': /* 30 bit immediate */ 2242 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2243 the_insn.pcrel = 1; 2244 goto immediate; 2245 2246 case 'h': 2247 case 'n': /* 22 bit immediate */ 2248 the_insn.reloc = BFD_RELOC_SPARC22; 2249 goto immediate; 2250 2251 case 'i': /* 13 bit immediate */ 2252 the_insn.reloc = BFD_RELOC_SPARC13; 2253 2254 /* fallthrough */ 2255 2256 immediate: 2257 if (*s == ' ') 2258 s++; 2259 2260 { 2261 char *s1; 2262 char *op_arg = NULL; 2263 static expressionS op_exp; 2264 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2265 2266 /* Check for %hi, etc. */ 2267 if (*s == '%') 2268 { 2269 static const struct ops { 2270 /* The name as it appears in assembler. */ 2271 char *name; 2272 /* strlen (name), precomputed for speed */ 2273 int len; 2274 /* The reloc this pseudo-op translates to. */ 2275 int reloc; 2276 /* Non-zero if for v9 only. */ 2277 int v9_p; 2278 /* Non-zero if can be used in pc-relative contexts. */ 2279 int pcrel_p;/*FIXME:wip*/ 2280 } ops[] = { 2281 /* hix/lox must appear before hi/lo so %hix won't be 2282 mistaken for %hi. */ 2283 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2284 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2285 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2286 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2287 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, 2288 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, 2289 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2290 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2291 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2292 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2293 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2294 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2295 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2296 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2297 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2298 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2299 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2300 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2301 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2302 0 }, 2303 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2304 0 }, 2305 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2306 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2307 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2308 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2309 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 2310 0, 0 }, 2311 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 2312 0, 0 }, 2313 { NULL, 0, 0, 0, 0 } 2314 }; 2315 const struct ops *o; 2316 2317 for (o = ops; o->name; o++) 2318 if (strncmp (s + 1, o->name, o->len) == 0) 2319 break; 2320 if (o->name == NULL) 2321 break; 2322 2323 if (s[o->len + 1] != '(') 2324 { 2325 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2326 return special_case; 2327 } 2328 2329 op_arg = o->name; 2330 the_insn.reloc = o->reloc; 2331 s += o->len + 2; 2332 v9_arg_p = o->v9_p; 2333 } 2334 2335 /* Note that if the get_expression() fails, we will still 2336 have created U entries in the symbol table for the 2337 'symbols' in the input string. Try not to create U 2338 symbols for registers, etc. */ 2339 2340 /* This stuff checks to see if the expression ends in 2341 +%reg. If it does, it removes the register from 2342 the expression, and re-sets 's' to point to the 2343 right place. */ 2344 2345 if (op_arg) 2346 { 2347 int npar = 0; 2348 2349 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2350 if (*s1 == '(') 2351 npar++; 2352 else if (*s1 == ')') 2353 { 2354 if (!npar) 2355 break; 2356 npar--; 2357 } 2358 2359 if (*s1 != ')') 2360 { 2361 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2362 return special_case; 2363 } 2364 2365 *s1 = '\0'; 2366 (void) get_expression (s); 2367 *s1 = ')'; 2368 s = s1 + 1; 2369 if (*s == ',' || *s == ']' || !*s) 2370 continue; 2371 if (*s != '+' && *s != '-') 2372 { 2373 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2374 return special_case; 2375 } 2376 *s1 = '0'; 2377 s = s1; 2378 op_exp = the_insn.exp; 2379 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2380 } 2381 2382 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2383 ; 2384 2385 if (s1 != s && ISDIGIT (s1[-1])) 2386 { 2387 if (s1[-2] == '%' && s1[-3] == '+') 2388 s1 -= 3; 2389 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2390 s1 -= 4; 2391 else 2392 s1 = NULL; 2393 if (s1) 2394 { 2395 *s1 = '\0'; 2396 if (op_arg && s1 == s + 1) 2397 the_insn.exp.X_op = O_absent; 2398 else 2399 (void) get_expression (s); 2400 *s1 = '+'; 2401 if (op_arg) 2402 *s = ')'; 2403 s = s1; 2404 } 2405 } 2406 else 2407 s1 = NULL; 2408 2409 if (!s1) 2410 { 2411 (void) get_expression (s); 2412 if (op_arg) 2413 *s = ')'; 2414 s = expr_end; 2415 } 2416 2417 if (op_arg) 2418 { 2419 the_insn.exp2 = the_insn.exp; 2420 the_insn.exp = op_exp; 2421 if (the_insn.exp2.X_op == O_absent) 2422 the_insn.exp2.X_op = O_illegal; 2423 else if (the_insn.exp.X_op == O_absent) 2424 { 2425 the_insn.exp = the_insn.exp2; 2426 the_insn.exp2.X_op = O_illegal; 2427 } 2428 else if (the_insn.exp.X_op == O_constant) 2429 { 2430 valueT val = the_insn.exp.X_add_number; 2431 switch (the_insn.reloc) 2432 { 2433 default: 2434 break; 2435 2436 case BFD_RELOC_SPARC_HH22: 2437 val = BSR (val, 32); 2438 /* Fall through. */ 2439 2440 case BFD_RELOC_SPARC_LM22: 2441 case BFD_RELOC_HI22: 2442 val = (val >> 10) & 0x3fffff; 2443 break; 2444 2445 case BFD_RELOC_SPARC_HM10: 2446 val = BSR (val, 32); 2447 /* Fall through. */ 2448 2449 case BFD_RELOC_LO10: 2450 val &= 0x3ff; 2451 break; 2452 2453 case BFD_RELOC_SPARC_H44: 2454 val >>= 22; 2455 val &= 0x3fffff; 2456 break; 2457 2458 case BFD_RELOC_SPARC_M44: 2459 val >>= 12; 2460 val &= 0x3ff; 2461 break; 2462 2463 case BFD_RELOC_SPARC_L44: 2464 val &= 0xfff; 2465 break; 2466 2467 case BFD_RELOC_SPARC_HIX22: 2468 val = ~val; 2469 val = (val >> 10) & 0x3fffff; 2470 break; 2471 2472 case BFD_RELOC_SPARC_LOX10: 2473 val = (val & 0x3ff) | 0x1c00; 2474 break; 2475 } 2476 the_insn.exp = the_insn.exp2; 2477 the_insn.exp.X_add_number += val; 2478 the_insn.exp2.X_op = O_illegal; 2479 the_insn.reloc = old_reloc; 2480 } 2481 else if (the_insn.exp2.X_op != O_constant) 2482 { 2483 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2484 return special_case; 2485 } 2486 else 2487 { 2488 if (old_reloc != BFD_RELOC_SPARC13 2489 || the_insn.reloc != BFD_RELOC_LO10 2490 || sparc_arch_size != 64 2491 || sparc_pic_code) 2492 { 2493 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2494 return special_case; 2495 } 2496 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2497 } 2498 } 2499 } 2500 /* Check for constants that don't require emitting a reloc. */ 2501 if (the_insn.exp.X_op == O_constant 2502 && the_insn.exp.X_add_symbol == 0 2503 && the_insn.exp.X_op_symbol == 0) 2504 { 2505 /* For pc-relative call instructions, we reject 2506 constants to get better code. */ 2507 if (the_insn.pcrel 2508 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2509 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2510 { 2511 error_message = _(": PC-relative operand can't be a constant"); 2512 goto error; 2513 } 2514 2515 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2516 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2517 { 2518 error_message = _(": TLS operand can't be a constant"); 2519 goto error; 2520 } 2521 2522 /* Constants that won't fit are checked in md_apply_fix 2523 and bfd_install_relocation. 2524 ??? It would be preferable to install the constants 2525 into the insn here and save having to create a fixS 2526 for each one. There already exists code to handle 2527 all the various cases (e.g. in md_apply_fix and 2528 bfd_install_relocation) so duplicating all that code 2529 here isn't right. */ 2530 } 2531 2532 continue; 2533 2534 case 'a': 2535 if (*s++ == 'a') 2536 { 2537 opcode |= ANNUL; 2538 continue; 2539 } 2540 break; 2541 2542 case 'A': 2543 { 2544 int asi = 0; 2545 2546 /* Parse an asi. */ 2547 if (*s == '#') 2548 { 2549 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2550 { 2551 error_message = _(": invalid ASI name"); 2552 goto error; 2553 } 2554 } 2555 else 2556 { 2557 if (! parse_const_expr_arg (&s, &asi)) 2558 { 2559 error_message = _(": invalid ASI expression"); 2560 goto error; 2561 } 2562 if (asi < 0 || asi > 255) 2563 { 2564 error_message = _(": invalid ASI number"); 2565 goto error; 2566 } 2567 } 2568 opcode |= ASI (asi); 2569 continue; 2570 } /* Alternate space. */ 2571 2572 case 'p': 2573 if (strncmp (s, "%psr", 4) == 0) 2574 { 2575 s += 4; 2576 continue; 2577 } 2578 break; 2579 2580 case 'q': /* Floating point queue. */ 2581 if (strncmp (s, "%fq", 3) == 0) 2582 { 2583 s += 3; 2584 continue; 2585 } 2586 break; 2587 2588 case 'Q': /* Coprocessor queue. */ 2589 if (strncmp (s, "%cq", 3) == 0) 2590 { 2591 s += 3; 2592 continue; 2593 } 2594 break; 2595 2596 case 'S': 2597 if (strcmp (str, "set") == 0 2598 || strcmp (str, "setuw") == 0) 2599 { 2600 special_case = SPECIAL_CASE_SET; 2601 continue; 2602 } 2603 else if (strcmp (str, "setsw") == 0) 2604 { 2605 special_case = SPECIAL_CASE_SETSW; 2606 continue; 2607 } 2608 else if (strcmp (str, "setx") == 0) 2609 { 2610 special_case = SPECIAL_CASE_SETX; 2611 continue; 2612 } 2613 else if (strncmp (str, "fdiv", 4) == 0) 2614 { 2615 special_case = SPECIAL_CASE_FDIV; 2616 continue; 2617 } 2618 break; 2619 2620 case 'o': 2621 if (strncmp (s, "%asi", 4) != 0) 2622 break; 2623 s += 4; 2624 continue; 2625 2626 case 's': 2627 if (strncmp (s, "%fprs", 5) != 0) 2628 break; 2629 s += 5; 2630 continue; 2631 2632 case 'E': 2633 if (strncmp (s, "%ccr", 4) != 0) 2634 break; 2635 s += 4; 2636 continue; 2637 2638 case 't': 2639 if (strncmp (s, "%tbr", 4) != 0) 2640 break; 2641 s += 4; 2642 continue; 2643 2644 case 'w': 2645 if (strncmp (s, "%wim", 4) != 0) 2646 break; 2647 s += 4; 2648 continue; 2649 2650 case 'x': 2651 { 2652 char *push = input_line_pointer; 2653 expressionS e; 2654 2655 input_line_pointer = s; 2656 expression (&e); 2657 if (e.X_op == O_constant) 2658 { 2659 int n = e.X_add_number; 2660 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2661 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2662 else 2663 opcode |= e.X_add_number << 5; 2664 } 2665 else 2666 as_bad (_("non-immediate OPF operand, ignored")); 2667 s = input_line_pointer; 2668 input_line_pointer = push; 2669 continue; 2670 } 2671 2672 case 'y': 2673 if (strncmp (s, "%y", 2) != 0) 2674 break; 2675 s += 2; 2676 continue; 2677 2678 case 'u': 2679 case 'U': 2680 { 2681 /* Parse a sparclet cpreg. */ 2682 int cpreg; 2683 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2684 { 2685 error_message = _(": invalid cpreg name"); 2686 goto error; 2687 } 2688 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2689 continue; 2690 } 2691 2692 default: 2693 as_fatal (_("failed sanity check.")); 2694 } /* switch on arg code. */ 2695 2696 /* Break out of for() loop. */ 2697 break; 2698 } /* For each arg that we expect. */ 2699 2700 error: 2701 if (match == 0) 2702 { 2703 /* Args don't match. */ 2704 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2705 && (insn->name == insn[1].name 2706 || !strcmp (insn->name, insn[1].name))) 2707 { 2708 ++insn; 2709 s = argsStart; 2710 continue; 2711 } 2712 else 2713 { 2714 as_bad (_("Illegal operands%s"), error_message); 2715 return special_case; 2716 } 2717 } 2718 else 2719 { 2720 /* We have a match. Now see if the architecture is OK. */ 2721 int needed_arch_mask = insn->architecture; 2722 2723 if (v9_arg_p) 2724 { 2725 needed_arch_mask &= 2726 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2727 if (! needed_arch_mask) 2728 needed_arch_mask = 2729 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2730 } 2731 2732 if (needed_arch_mask 2733 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2734 /* OK. */ 2735 ; 2736 /* Can we bump up the architecture? */ 2737 else if (needed_arch_mask 2738 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2739 { 2740 enum sparc_opcode_arch_val needed_architecture = 2741 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2742 & needed_arch_mask); 2743 2744 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2745 if (warn_on_bump 2746 && needed_architecture > warn_after_architecture) 2747 { 2748 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2749 sparc_opcode_archs[current_architecture].name, 2750 sparc_opcode_archs[needed_architecture].name, 2751 str); 2752 warn_after_architecture = needed_architecture; 2753 } 2754 current_architecture = needed_architecture; 2755 } 2756 /* Conflict. */ 2757 /* ??? This seems to be a bit fragile. What if the next entry in 2758 the opcode table is the one we want and it is supported? 2759 It is possible to arrange the table today so that this can't 2760 happen but what about tomorrow? */ 2761 else 2762 { 2763 int arch, printed_one_p = 0; 2764 char *p; 2765 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2766 2767 /* Create a list of the architectures that support the insn. */ 2768 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2769 p = required_archs; 2770 arch = sparc_ffs (needed_arch_mask); 2771 while ((1 << arch) <= needed_arch_mask) 2772 { 2773 if ((1 << arch) & needed_arch_mask) 2774 { 2775 if (printed_one_p) 2776 *p++ = '|'; 2777 strcpy (p, sparc_opcode_archs[arch].name); 2778 p += strlen (p); 2779 printed_one_p = 1; 2780 } 2781 ++arch; 2782 } 2783 2784 as_bad (_("Architecture mismatch on \"%s\"."), str); 2785 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2786 required_archs, 2787 sparc_opcode_archs[max_architecture].name); 2788 return special_case; 2789 } 2790 } /* If no match. */ 2791 2792 break; 2793 } /* Forever looking for a match. */ 2794 2795 the_insn.opcode = opcode; 2796 return special_case; 2797 } 2798 2799 /* Parse an argument that can be expressed as a keyword. 2800 (eg: #StoreStore or %ccfr). 2801 The result is a boolean indicating success. 2802 If successful, INPUT_POINTER is updated. */ 2803 2804 static int 2805 parse_keyword_arg (int (*lookup_fn) (const char *), 2806 char **input_pointerP, 2807 int *valueP) 2808 { 2809 int value; 2810 char c, *p, *q; 2811 2812 p = *input_pointerP; 2813 for (q = p + (*p == '#' || *p == '%'); 2814 ISALNUM (*q) || *q == '_'; 2815 ++q) 2816 continue; 2817 c = *q; 2818 *q = 0; 2819 value = (*lookup_fn) (p); 2820 *q = c; 2821 if (value == -1) 2822 return 0; 2823 *valueP = value; 2824 *input_pointerP = q; 2825 return 1; 2826 } 2827 2828 /* Parse an argument that is a constant expression. 2829 The result is a boolean indicating success. */ 2830 2831 static int 2832 parse_const_expr_arg (char **input_pointerP, int *valueP) 2833 { 2834 char *save = input_line_pointer; 2835 expressionS exp; 2836 2837 input_line_pointer = *input_pointerP; 2838 /* The next expression may be something other than a constant 2839 (say if we're not processing the right variant of the insn). 2840 Don't call expression unless we're sure it will succeed as it will 2841 signal an error (which we want to defer until later). */ 2842 /* FIXME: It might be better to define md_operand and have it recognize 2843 things like %asi, etc. but continuing that route through to the end 2844 is a lot of work. */ 2845 if (*input_line_pointer == '%') 2846 { 2847 input_line_pointer = save; 2848 return 0; 2849 } 2850 expression (&exp); 2851 *input_pointerP = input_line_pointer; 2852 input_line_pointer = save; 2853 if (exp.X_op != O_constant) 2854 return 0; 2855 *valueP = exp.X_add_number; 2856 return 1; 2857 } 2858 2859 /* Subroutine of sparc_ip to parse an expression. */ 2860 2861 static int 2862 get_expression (char *str) 2863 { 2864 char *save_in; 2865 segT seg; 2866 2867 save_in = input_line_pointer; 2868 input_line_pointer = str; 2869 seg = expression (&the_insn.exp); 2870 if (seg != absolute_section 2871 && seg != text_section 2872 && seg != data_section 2873 && seg != bss_section 2874 && seg != undefined_section) 2875 { 2876 the_insn.error = _("bad segment"); 2877 expr_end = input_line_pointer; 2878 input_line_pointer = save_in; 2879 return 1; 2880 } 2881 expr_end = input_line_pointer; 2882 input_line_pointer = save_in; 2883 return 0; 2884 } 2885 2886 /* Subroutine of md_assemble to output one insn. */ 2887 2888 static void 2889 output_insn (const struct sparc_opcode *insn, struct sparc_it *the_insn) 2890 { 2891 char *toP = frag_more (4); 2892 2893 /* Put out the opcode. */ 2894 if (INSN_BIG_ENDIAN) 2895 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2896 else 2897 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2898 2899 /* Put out the symbol-dependent stuff. */ 2900 if (the_insn->reloc != BFD_RELOC_NONE) 2901 { 2902 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2903 (toP - frag_now->fr_literal), /* Where. */ 2904 4, /* Size. */ 2905 &the_insn->exp, 2906 the_insn->pcrel, 2907 the_insn->reloc); 2908 /* Turn off overflow checking in fixup_segment. We'll do our 2909 own overflow checking in md_apply_fix. This is necessary because 2910 the insn size is 4 and fixup_segment will signal an overflow for 2911 large 8 byte quantities. */ 2912 fixP->fx_no_overflow = 1; 2913 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2914 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2915 } 2916 2917 last_insn = insn; 2918 last_opcode = the_insn->opcode; 2919 2920 #ifdef OBJ_ELF 2921 dwarf2_emit_insn (4); 2922 #endif 2923 } 2924 2925 char * 2926 md_atof (int type, char *litP, int *sizeP) 2927 { 2928 return ieee_md_atof (type, litP, sizeP, target_big_endian); 2929 } 2930 2931 /* Write a value out to the object file, using the appropriate 2932 endianness. */ 2933 2934 void 2935 md_number_to_chars (char *buf, valueT val, int n) 2936 { 2937 if (target_big_endian) 2938 number_to_chars_bigendian (buf, val, n); 2939 else if (target_little_endian_data 2940 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 2941 /* Output debug words, which are not in allocated sections, as big 2942 endian. */ 2943 number_to_chars_bigendian (buf, val, n); 2944 else if (target_little_endian_data || ! target_big_endian) 2945 number_to_chars_littleendian (buf, val, n); 2946 } 2947 2948 /* Apply a fixS to the frags, now that we know the value it ought to 2949 hold. */ 2950 2951 void 2952 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 2953 { 2954 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2955 offsetT val = * (offsetT *) valP; 2956 long insn; 2957 2958 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 2959 2960 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 2961 2962 #ifdef OBJ_ELF 2963 /* SPARC ELF relocations don't use an addend in the data field. */ 2964 if (fixP->fx_addsy != NULL) 2965 { 2966 switch (fixP->fx_r_type) 2967 { 2968 case BFD_RELOC_SPARC_TLS_GD_HI22: 2969 case BFD_RELOC_SPARC_TLS_GD_LO10: 2970 case BFD_RELOC_SPARC_TLS_GD_ADD: 2971 case BFD_RELOC_SPARC_TLS_GD_CALL: 2972 case BFD_RELOC_SPARC_TLS_LDM_HI22: 2973 case BFD_RELOC_SPARC_TLS_LDM_LO10: 2974 case BFD_RELOC_SPARC_TLS_LDM_ADD: 2975 case BFD_RELOC_SPARC_TLS_LDM_CALL: 2976 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 2977 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 2978 case BFD_RELOC_SPARC_TLS_LDO_ADD: 2979 case BFD_RELOC_SPARC_TLS_IE_HI22: 2980 case BFD_RELOC_SPARC_TLS_IE_LO10: 2981 case BFD_RELOC_SPARC_TLS_IE_LD: 2982 case BFD_RELOC_SPARC_TLS_IE_LDX: 2983 case BFD_RELOC_SPARC_TLS_IE_ADD: 2984 case BFD_RELOC_SPARC_TLS_LE_HIX22: 2985 case BFD_RELOC_SPARC_TLS_LE_LOX10: 2986 case BFD_RELOC_SPARC_TLS_DTPMOD32: 2987 case BFD_RELOC_SPARC_TLS_DTPMOD64: 2988 case BFD_RELOC_SPARC_TLS_DTPOFF32: 2989 case BFD_RELOC_SPARC_TLS_DTPOFF64: 2990 case BFD_RELOC_SPARC_TLS_TPOFF32: 2991 case BFD_RELOC_SPARC_TLS_TPOFF64: 2992 S_SET_THREAD_LOCAL (fixP->fx_addsy); 2993 2994 default: 2995 break; 2996 } 2997 2998 return; 2999 } 3000 #endif 3001 3002 /* This is a hack. There should be a better way to 3003 handle this. Probably in terms of howto fields, once 3004 we can look at these fixups in terms of howtos. */ 3005 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3006 val += fixP->fx_where + fixP->fx_frag->fr_address; 3007 3008 #ifdef OBJ_AOUT 3009 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3010 generate a reloc, then we just want to let the reloc addend set 3011 the value. We do not want to also stuff the addend into the 3012 object file. Including the addend in the object file works when 3013 doing a static link, because the linker will ignore the object 3014 file contents. However, the dynamic linker does not ignore the 3015 object file contents. */ 3016 if (fixP->fx_addsy != NULL 3017 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3018 val = 0; 3019 3020 /* When generating PIC code, we do not want an addend for a reloc 3021 against a local symbol. We adjust fx_addnumber to cancel out the 3022 value already included in val, and to also cancel out the 3023 adjustment which bfd_install_relocation will create. */ 3024 if (sparc_pic_code 3025 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3026 && fixP->fx_addsy != NULL 3027 && ! S_IS_COMMON (fixP->fx_addsy) 3028 && symbol_section_p (fixP->fx_addsy)) 3029 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3030 3031 /* When generating PIC code, we need to fiddle to get 3032 bfd_install_relocation to do the right thing for a PC relative 3033 reloc against a local symbol which we are going to keep. */ 3034 if (sparc_pic_code 3035 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3036 && fixP->fx_addsy != NULL 3037 && (S_IS_EXTERNAL (fixP->fx_addsy) 3038 || S_IS_WEAK (fixP->fx_addsy)) 3039 && S_IS_DEFINED (fixP->fx_addsy) 3040 && ! S_IS_COMMON (fixP->fx_addsy)) 3041 { 3042 val = 0; 3043 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3044 } 3045 #endif 3046 3047 /* If this is a data relocation, just output VAL. */ 3048 3049 if (fixP->fx_r_type == BFD_RELOC_16 3050 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3051 { 3052 md_number_to_chars (buf, val, 2); 3053 } 3054 else if (fixP->fx_r_type == BFD_RELOC_32 3055 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3056 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3057 { 3058 md_number_to_chars (buf, val, 4); 3059 } 3060 else if (fixP->fx_r_type == BFD_RELOC_64 3061 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3062 { 3063 md_number_to_chars (buf, val, 8); 3064 } 3065 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3066 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3067 { 3068 fixP->fx_done = 0; 3069 return; 3070 } 3071 else 3072 { 3073 /* It's a relocation against an instruction. */ 3074 3075 if (INSN_BIG_ENDIAN) 3076 insn = bfd_getb32 ((unsigned char *) buf); 3077 else 3078 insn = bfd_getl32 ((unsigned char *) buf); 3079 3080 switch (fixP->fx_r_type) 3081 { 3082 case BFD_RELOC_32_PCREL_S2: 3083 val = val >> 2; 3084 /* FIXME: This increment-by-one deserves a comment of why it's 3085 being done! */ 3086 if (! sparc_pic_code 3087 || fixP->fx_addsy == NULL 3088 || symbol_section_p (fixP->fx_addsy)) 3089 ++val; 3090 3091 insn |= val & 0x3fffffff; 3092 3093 /* See if we have a delay slot. */ 3094 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3095 { 3096 #define G0 0 3097 #define O7 15 3098 #define XCC (2 << 20) 3099 #define COND(x) (((x)&0xf)<<25) 3100 #define CONDA COND(0x8) 3101 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3102 #define INSN_BA (F2(0,2) | CONDA) 3103 #define INSN_OR F3(2, 0x2, 0) 3104 #define INSN_NOP F2(0,4) 3105 3106 long delay; 3107 3108 /* If the instruction is a call with either: 3109 restore 3110 arithmetic instruction with rd == %o7 3111 where rs1 != %o7 and rs2 if it is register != %o7 3112 then we can optimize if the call destination is near 3113 by changing the call into a branch always. */ 3114 if (INSN_BIG_ENDIAN) 3115 delay = bfd_getb32 ((unsigned char *) buf + 4); 3116 else 3117 delay = bfd_getl32 ((unsigned char *) buf + 4); 3118 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3119 break; 3120 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3121 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3122 || ((delay & RD (~0)) != RD (O7)))) 3123 break; 3124 if ((delay & RS1 (~0)) == RS1 (O7) 3125 || ((delay & F3I (~0)) == 0 3126 && (delay & RS2 (~0)) == RS2 (O7))) 3127 break; 3128 /* Ensure the branch will fit into simm22. */ 3129 if ((val & 0x3fe00000) 3130 && (val & 0x3fe00000) != 0x3fe00000) 3131 break; 3132 /* Check if the arch is v9 and branch will fit 3133 into simm19. */ 3134 if (((val & 0x3c0000) == 0 3135 || (val & 0x3c0000) == 0x3c0000) 3136 && (sparc_arch_size == 64 3137 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3138 /* ba,pt %xcc */ 3139 insn = INSN_BPA | (val & 0x7ffff); 3140 else 3141 /* ba */ 3142 insn = INSN_BA | (val & 0x3fffff); 3143 if (fixP->fx_where >= 4 3144 && ((delay & (0xffffffff ^ RS1 (~0))) 3145 == (INSN_OR | RD (O7) | RS2 (G0)))) 3146 { 3147 long setter; 3148 int reg; 3149 3150 if (INSN_BIG_ENDIAN) 3151 setter = bfd_getb32 ((unsigned char *) buf - 4); 3152 else 3153 setter = bfd_getl32 ((unsigned char *) buf - 4); 3154 if ((setter & (0xffffffff ^ RD (~0))) 3155 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3156 break; 3157 /* The sequence was 3158 or %o7, %g0, %rN 3159 call foo 3160 or %rN, %g0, %o7 3161 3162 If call foo was replaced with ba, replace 3163 or %rN, %g0, %o7 with nop. */ 3164 reg = (delay & RS1 (~0)) >> 14; 3165 if (reg != ((setter & RD (~0)) >> 25) 3166 || reg == G0 || reg == O7) 3167 break; 3168 3169 if (INSN_BIG_ENDIAN) 3170 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3171 else 3172 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3173 } 3174 } 3175 break; 3176 3177 case BFD_RELOC_SPARC_11: 3178 if (! in_signed_range (val, 0x7ff)) 3179 as_bad_where (fixP->fx_file, fixP->fx_line, 3180 _("relocation overflow")); 3181 insn |= val & 0x7ff; 3182 break; 3183 3184 case BFD_RELOC_SPARC_10: 3185 if (! in_signed_range (val, 0x3ff)) 3186 as_bad_where (fixP->fx_file, fixP->fx_line, 3187 _("relocation overflow")); 3188 insn |= val & 0x3ff; 3189 break; 3190 3191 case BFD_RELOC_SPARC_7: 3192 if (! in_bitfield_range (val, 0x7f)) 3193 as_bad_where (fixP->fx_file, fixP->fx_line, 3194 _("relocation overflow")); 3195 insn |= val & 0x7f; 3196 break; 3197 3198 case BFD_RELOC_SPARC_6: 3199 if (! in_bitfield_range (val, 0x3f)) 3200 as_bad_where (fixP->fx_file, fixP->fx_line, 3201 _("relocation overflow")); 3202 insn |= val & 0x3f; 3203 break; 3204 3205 case BFD_RELOC_SPARC_5: 3206 if (! in_bitfield_range (val, 0x1f)) 3207 as_bad_where (fixP->fx_file, fixP->fx_line, 3208 _("relocation overflow")); 3209 insn |= val & 0x1f; 3210 break; 3211 3212 case BFD_RELOC_SPARC_WDISP16: 3213 if ((val & 3) 3214 || val >= 0x1fffc 3215 || val <= -(offsetT) 0x20008) 3216 as_bad_where (fixP->fx_file, fixP->fx_line, 3217 _("relocation overflow")); 3218 /* FIXME: The +1 deserves a comment. */ 3219 val = (val >> 2) + 1; 3220 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3221 break; 3222 3223 case BFD_RELOC_SPARC_WDISP19: 3224 if ((val & 3) 3225 || val >= 0xffffc 3226 || val <= -(offsetT) 0x100008) 3227 as_bad_where (fixP->fx_file, fixP->fx_line, 3228 _("relocation overflow")); 3229 /* FIXME: The +1 deserves a comment. */ 3230 val = (val >> 2) + 1; 3231 insn |= val & 0x7ffff; 3232 break; 3233 3234 case BFD_RELOC_SPARC_HH22: 3235 val = BSR (val, 32); 3236 /* Fall through. */ 3237 3238 case BFD_RELOC_SPARC_LM22: 3239 case BFD_RELOC_HI22: 3240 if (!fixP->fx_addsy) 3241 insn |= (val >> 10) & 0x3fffff; 3242 else 3243 /* FIXME: Need comment explaining why we do this. */ 3244 insn &= ~0xffff; 3245 break; 3246 3247 case BFD_RELOC_SPARC22: 3248 if (val & ~0x003fffff) 3249 as_bad_where (fixP->fx_file, fixP->fx_line, 3250 _("relocation overflow")); 3251 insn |= (val & 0x3fffff); 3252 break; 3253 3254 case BFD_RELOC_SPARC_HM10: 3255 val = BSR (val, 32); 3256 /* Fall through. */ 3257 3258 case BFD_RELOC_LO10: 3259 if (!fixP->fx_addsy) 3260 insn |= val & 0x3ff; 3261 else 3262 /* FIXME: Need comment explaining why we do this. */ 3263 insn &= ~0xff; 3264 break; 3265 3266 case BFD_RELOC_SPARC_OLO10: 3267 val &= 0x3ff; 3268 val += fixP->tc_fix_data; 3269 /* Fall through. */ 3270 3271 case BFD_RELOC_SPARC13: 3272 if (! in_signed_range (val, 0x1fff)) 3273 as_bad_where (fixP->fx_file, fixP->fx_line, 3274 _("relocation overflow")); 3275 insn |= val & 0x1fff; 3276 break; 3277 3278 case BFD_RELOC_SPARC_WDISP22: 3279 val = (val >> 2) + 1; 3280 /* Fall through. */ 3281 case BFD_RELOC_SPARC_BASE22: 3282 insn |= val & 0x3fffff; 3283 break; 3284 3285 case BFD_RELOC_SPARC_H44: 3286 if (!fixP->fx_addsy) 3287 { 3288 bfd_vma tval = val; 3289 tval >>= 22; 3290 insn |= tval & 0x3fffff; 3291 } 3292 break; 3293 3294 case BFD_RELOC_SPARC_M44: 3295 if (!fixP->fx_addsy) 3296 insn |= (val >> 12) & 0x3ff; 3297 break; 3298 3299 case BFD_RELOC_SPARC_L44: 3300 if (!fixP->fx_addsy) 3301 insn |= val & 0xfff; 3302 break; 3303 3304 case BFD_RELOC_SPARC_HIX22: 3305 if (!fixP->fx_addsy) 3306 { 3307 val ^= ~(offsetT) 0; 3308 insn |= (val >> 10) & 0x3fffff; 3309 } 3310 break; 3311 3312 case BFD_RELOC_SPARC_LOX10: 3313 if (!fixP->fx_addsy) 3314 insn |= 0x1c00 | (val & 0x3ff); 3315 break; 3316 3317 case BFD_RELOC_NONE: 3318 default: 3319 as_bad_where (fixP->fx_file, fixP->fx_line, 3320 _("bad or unhandled relocation type: 0x%02x"), 3321 fixP->fx_r_type); 3322 break; 3323 } 3324 3325 if (INSN_BIG_ENDIAN) 3326 bfd_putb32 (insn, (unsigned char *) buf); 3327 else 3328 bfd_putl32 (insn, (unsigned char *) buf); 3329 } 3330 3331 /* Are we finished with this relocation now? */ 3332 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3333 fixP->fx_done = 1; 3334 } 3335 3336 /* Translate internal representation of relocation info to BFD target 3337 format. */ 3338 3339 arelent ** 3340 tc_gen_reloc (asection *section, fixS *fixp) 3341 { 3342 static arelent *relocs[3]; 3343 arelent *reloc; 3344 bfd_reloc_code_real_type code; 3345 3346 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3347 relocs[1] = NULL; 3348 3349 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3350 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3351 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3352 3353 switch (fixp->fx_r_type) 3354 { 3355 case BFD_RELOC_16: 3356 case BFD_RELOC_32: 3357 case BFD_RELOC_HI22: 3358 case BFD_RELOC_LO10: 3359 case BFD_RELOC_32_PCREL_S2: 3360 case BFD_RELOC_SPARC13: 3361 case BFD_RELOC_SPARC22: 3362 case BFD_RELOC_SPARC_PC22: 3363 case BFD_RELOC_SPARC_PC10: 3364 case BFD_RELOC_SPARC_BASE13: 3365 case BFD_RELOC_SPARC_WDISP16: 3366 case BFD_RELOC_SPARC_WDISP19: 3367 case BFD_RELOC_SPARC_WDISP22: 3368 case BFD_RELOC_64: 3369 case BFD_RELOC_SPARC_5: 3370 case BFD_RELOC_SPARC_6: 3371 case BFD_RELOC_SPARC_7: 3372 case BFD_RELOC_SPARC_10: 3373 case BFD_RELOC_SPARC_11: 3374 case BFD_RELOC_SPARC_HH22: 3375 case BFD_RELOC_SPARC_HM10: 3376 case BFD_RELOC_SPARC_LM22: 3377 case BFD_RELOC_SPARC_PC_HH22: 3378 case BFD_RELOC_SPARC_PC_HM10: 3379 case BFD_RELOC_SPARC_PC_LM22: 3380 case BFD_RELOC_SPARC_H44: 3381 case BFD_RELOC_SPARC_M44: 3382 case BFD_RELOC_SPARC_L44: 3383 case BFD_RELOC_SPARC_HIX22: 3384 case BFD_RELOC_SPARC_LOX10: 3385 case BFD_RELOC_SPARC_REV32: 3386 case BFD_RELOC_SPARC_OLO10: 3387 case BFD_RELOC_SPARC_UA16: 3388 case BFD_RELOC_SPARC_UA32: 3389 case BFD_RELOC_SPARC_UA64: 3390 case BFD_RELOC_8_PCREL: 3391 case BFD_RELOC_16_PCREL: 3392 case BFD_RELOC_32_PCREL: 3393 case BFD_RELOC_64_PCREL: 3394 case BFD_RELOC_SPARC_PLT32: 3395 case BFD_RELOC_SPARC_PLT64: 3396 case BFD_RELOC_VTABLE_ENTRY: 3397 case BFD_RELOC_VTABLE_INHERIT: 3398 case BFD_RELOC_SPARC_TLS_GD_HI22: 3399 case BFD_RELOC_SPARC_TLS_GD_LO10: 3400 case BFD_RELOC_SPARC_TLS_GD_ADD: 3401 case BFD_RELOC_SPARC_TLS_GD_CALL: 3402 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3403 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3404 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3405 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3406 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3407 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3408 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3409 case BFD_RELOC_SPARC_TLS_IE_HI22: 3410 case BFD_RELOC_SPARC_TLS_IE_LO10: 3411 case BFD_RELOC_SPARC_TLS_IE_LD: 3412 case BFD_RELOC_SPARC_TLS_IE_LDX: 3413 case BFD_RELOC_SPARC_TLS_IE_ADD: 3414 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3415 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3416 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3417 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3418 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3419 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3420 case BFD_RELOC_SPARC_GOTDATA_OP: 3421 code = fixp->fx_r_type; 3422 break; 3423 default: 3424 abort (); 3425 return NULL; 3426 } 3427 3428 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3429 /* If we are generating PIC code, we need to generate a different 3430 set of relocs. */ 3431 3432 #ifdef OBJ_ELF 3433 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3434 #else 3435 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3436 #endif 3437 #ifdef TE_VXWORKS 3438 #define GOTT_BASE "__GOTT_BASE__" 3439 #define GOTT_INDEX "__GOTT_INDEX__" 3440 #endif 3441 3442 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3443 3444 if (sparc_pic_code) 3445 { 3446 switch (code) 3447 { 3448 case BFD_RELOC_32_PCREL_S2: 3449 if (generic_force_reloc (fixp)) 3450 code = BFD_RELOC_SPARC_WPLT30; 3451 break; 3452 case BFD_RELOC_HI22: 3453 code = BFD_RELOC_SPARC_GOT22; 3454 if (fixp->fx_addsy != NULL) 3455 { 3456 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3457 code = BFD_RELOC_SPARC_PC22; 3458 #ifdef TE_VXWORKS 3459 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3460 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3461 code = BFD_RELOC_HI22; /* Unchanged. */ 3462 #endif 3463 } 3464 break; 3465 case BFD_RELOC_LO10: 3466 code = BFD_RELOC_SPARC_GOT10; 3467 if (fixp->fx_addsy != NULL) 3468 { 3469 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3470 code = BFD_RELOC_SPARC_PC10; 3471 #ifdef TE_VXWORKS 3472 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3473 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3474 code = BFD_RELOC_LO10; /* Unchanged. */ 3475 #endif 3476 } 3477 break; 3478 case BFD_RELOC_SPARC13: 3479 code = BFD_RELOC_SPARC_GOT13; 3480 break; 3481 default: 3482 break; 3483 } 3484 } 3485 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3486 3487 /* Nothing is aligned in DWARF debugging sections. */ 3488 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3489 switch (code) 3490 { 3491 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3492 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3493 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3494 default: break; 3495 } 3496 3497 if (code == BFD_RELOC_SPARC_OLO10) 3498 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3499 else 3500 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3501 if (reloc->howto == 0) 3502 { 3503 as_bad_where (fixp->fx_file, fixp->fx_line, 3504 _("internal error: can't export reloc type %d (`%s')"), 3505 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3506 xfree (reloc); 3507 relocs[0] = NULL; 3508 return relocs; 3509 } 3510 3511 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3512 #ifdef OBJ_AOUT 3513 3514 if (reloc->howto->pc_relative == 0 3515 || code == BFD_RELOC_SPARC_PC10 3516 || code == BFD_RELOC_SPARC_PC22) 3517 reloc->addend = fixp->fx_addnumber; 3518 else if (sparc_pic_code 3519 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3520 && fixp->fx_addsy != NULL 3521 && (S_IS_EXTERNAL (fixp->fx_addsy) 3522 || S_IS_WEAK (fixp->fx_addsy)) 3523 && S_IS_DEFINED (fixp->fx_addsy) 3524 && ! S_IS_COMMON (fixp->fx_addsy)) 3525 reloc->addend = fixp->fx_addnumber; 3526 else 3527 reloc->addend = fixp->fx_offset - reloc->address; 3528 3529 #else /* elf or coff */ 3530 3531 if (code != BFD_RELOC_32_PCREL_S2 3532 && code != BFD_RELOC_SPARC_WDISP22 3533 && code != BFD_RELOC_SPARC_WDISP16 3534 && code != BFD_RELOC_SPARC_WDISP19 3535 && code != BFD_RELOC_SPARC_WPLT30 3536 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3537 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3538 reloc->addend = fixp->fx_addnumber; 3539 else if (symbol_section_p (fixp->fx_addsy)) 3540 reloc->addend = (section->vma 3541 + fixp->fx_addnumber 3542 + md_pcrel_from (fixp)); 3543 else 3544 reloc->addend = fixp->fx_offset; 3545 #endif 3546 3547 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3548 on the same location. */ 3549 if (code == BFD_RELOC_SPARC_OLO10) 3550 { 3551 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3552 relocs[2] = NULL; 3553 3554 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3555 *reloc->sym_ptr_ptr 3556 = symbol_get_bfdsym (section_symbol (absolute_section)); 3557 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3558 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3559 reloc->addend = fixp->tc_fix_data; 3560 } 3561 3562 return relocs; 3563 } 3564 3565 /* We have no need to default values of symbols. */ 3566 3567 symbolS * 3568 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 3569 { 3570 return 0; 3571 } 3572 3573 /* Round up a section size to the appropriate boundary. */ 3574 3575 valueT 3576 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 3577 { 3578 #ifndef OBJ_ELF 3579 /* This is not right for ELF; a.out wants it, and COFF will force 3580 the alignment anyways. */ 3581 valueT align = ((valueT) 1 3582 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3583 valueT newsize; 3584 3585 /* Turn alignment value into a mask. */ 3586 align--; 3587 newsize = (size + align) & ~align; 3588 return newsize; 3589 #else 3590 return size; 3591 #endif 3592 } 3593 3594 /* Exactly what point is a PC-relative offset relative TO? 3595 On the sparc, they're relative to the address of the offset, plus 3596 its size. This gets us to the following instruction. 3597 (??? Is this right? FIXME-SOON) */ 3598 long 3599 md_pcrel_from (fixS *fixP) 3600 { 3601 long ret; 3602 3603 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3604 if (! sparc_pic_code 3605 || fixP->fx_addsy == NULL 3606 || symbol_section_p (fixP->fx_addsy)) 3607 ret += fixP->fx_size; 3608 return ret; 3609 } 3610 3611 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3612 of two. */ 3613 3614 static int 3615 mylog2 (int value) 3616 { 3617 int shift; 3618 3619 if (value <= 0) 3620 return -1; 3621 3622 for (shift = 0; (value & 1) == 0; value >>= 1) 3623 ++shift; 3624 3625 return (value == 1) ? shift : -1; 3626 } 3627 3628 /* Sort of like s_lcomm. */ 3629 3630 #ifndef OBJ_ELF 3631 static int max_alignment = 15; 3632 #endif 3633 3634 static void 3635 s_reserve (int ignore ATTRIBUTE_UNUSED) 3636 { 3637 char *name; 3638 char *p; 3639 char c; 3640 int align; 3641 int size; 3642 int temp; 3643 symbolS *symbolP; 3644 3645 name = input_line_pointer; 3646 c = get_symbol_end (); 3647 p = input_line_pointer; 3648 *p = c; 3649 SKIP_WHITESPACE (); 3650 3651 if (*input_line_pointer != ',') 3652 { 3653 as_bad (_("Expected comma after name")); 3654 ignore_rest_of_line (); 3655 return; 3656 } 3657 3658 ++input_line_pointer; 3659 3660 if ((size = get_absolute_expression ()) < 0) 3661 { 3662 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3663 ignore_rest_of_line (); 3664 return; 3665 } /* Bad length. */ 3666 3667 *p = 0; 3668 symbolP = symbol_find_or_make (name); 3669 *p = c; 3670 3671 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3672 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3673 { 3674 as_bad (_("bad .reserve segment -- expected BSS segment")); 3675 return; 3676 } 3677 3678 if (input_line_pointer[2] == '.') 3679 input_line_pointer += 7; 3680 else 3681 input_line_pointer += 6; 3682 SKIP_WHITESPACE (); 3683 3684 if (*input_line_pointer == ',') 3685 { 3686 ++input_line_pointer; 3687 3688 SKIP_WHITESPACE (); 3689 if (*input_line_pointer == '\n') 3690 { 3691 as_bad (_("missing alignment")); 3692 ignore_rest_of_line (); 3693 return; 3694 } 3695 3696 align = (int) get_absolute_expression (); 3697 3698 #ifndef OBJ_ELF 3699 if (align > max_alignment) 3700 { 3701 align = max_alignment; 3702 as_warn (_("alignment too large; assuming %d"), align); 3703 } 3704 #endif 3705 3706 if (align < 0) 3707 { 3708 as_bad (_("negative alignment")); 3709 ignore_rest_of_line (); 3710 return; 3711 } 3712 3713 if (align != 0) 3714 { 3715 temp = mylog2 (align); 3716 if (temp < 0) 3717 { 3718 as_bad (_("alignment not a power of 2")); 3719 ignore_rest_of_line (); 3720 return; 3721 } 3722 3723 align = temp; 3724 } 3725 3726 record_alignment (bss_section, align); 3727 } 3728 else 3729 align = 0; 3730 3731 if (!S_IS_DEFINED (symbolP) 3732 #ifdef OBJ_AOUT 3733 && S_GET_OTHER (symbolP) == 0 3734 && S_GET_DESC (symbolP) == 0 3735 #endif 3736 ) 3737 { 3738 if (! need_pass_2) 3739 { 3740 char *pfrag; 3741 segT current_seg = now_seg; 3742 subsegT current_subseg = now_subseg; 3743 3744 /* Switch to bss. */ 3745 subseg_set (bss_section, 1); 3746 3747 if (align) 3748 /* Do alignment. */ 3749 frag_align (align, 0, 0); 3750 3751 /* Detach from old frag. */ 3752 if (S_GET_SEGMENT (symbolP) == bss_section) 3753 symbol_get_frag (symbolP)->fr_symbol = NULL; 3754 3755 symbol_set_frag (symbolP, frag_now); 3756 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3757 (offsetT) size, (char *) 0); 3758 *pfrag = 0; 3759 3760 S_SET_SEGMENT (symbolP, bss_section); 3761 3762 subseg_set (current_seg, current_subseg); 3763 3764 #ifdef OBJ_ELF 3765 S_SET_SIZE (symbolP, size); 3766 #endif 3767 } 3768 } 3769 else 3770 { 3771 as_warn ("Ignoring attempt to re-define symbol %s", 3772 S_GET_NAME (symbolP)); 3773 } /* if not redefining. */ 3774 3775 demand_empty_rest_of_line (); 3776 } 3777 3778 static void 3779 s_common (int ignore ATTRIBUTE_UNUSED) 3780 { 3781 char *name; 3782 char c; 3783 char *p; 3784 offsetT temp, size; 3785 symbolS *symbolP; 3786 3787 name = input_line_pointer; 3788 c = get_symbol_end (); 3789 /* Just after name is now '\0'. */ 3790 p = input_line_pointer; 3791 *p = c; 3792 SKIP_WHITESPACE (); 3793 if (*input_line_pointer != ',') 3794 { 3795 as_bad (_("Expected comma after symbol-name")); 3796 ignore_rest_of_line (); 3797 return; 3798 } 3799 3800 /* Skip ','. */ 3801 input_line_pointer++; 3802 3803 if ((temp = get_absolute_expression ()) < 0) 3804 { 3805 as_bad (_(".COMMon length (%lu) out of range ignored"), 3806 (unsigned long) temp); 3807 ignore_rest_of_line (); 3808 return; 3809 } 3810 size = temp; 3811 *p = 0; 3812 symbolP = symbol_find_or_make (name); 3813 *p = c; 3814 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3815 { 3816 as_bad (_("Ignoring attempt to re-define symbol")); 3817 ignore_rest_of_line (); 3818 return; 3819 } 3820 if (S_GET_VALUE (symbolP) != 0) 3821 { 3822 if (S_GET_VALUE (symbolP) != (valueT) size) 3823 { 3824 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 3825 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 3826 } 3827 } 3828 else 3829 { 3830 #ifndef OBJ_ELF 3831 S_SET_VALUE (symbolP, (valueT) size); 3832 S_SET_EXTERNAL (symbolP); 3833 #endif 3834 } 3835 know (symbol_get_frag (symbolP) == &zero_address_frag); 3836 if (*input_line_pointer != ',') 3837 { 3838 as_bad (_("Expected comma after common length")); 3839 ignore_rest_of_line (); 3840 return; 3841 } 3842 input_line_pointer++; 3843 SKIP_WHITESPACE (); 3844 if (*input_line_pointer != '"') 3845 { 3846 temp = get_absolute_expression (); 3847 3848 #ifndef OBJ_ELF 3849 if (temp > max_alignment) 3850 { 3851 temp = max_alignment; 3852 as_warn (_("alignment too large; assuming %ld"), (long) temp); 3853 } 3854 #endif 3855 3856 if (temp < 0) 3857 { 3858 as_bad (_("negative alignment")); 3859 ignore_rest_of_line (); 3860 return; 3861 } 3862 3863 #ifdef OBJ_ELF 3864 if (symbol_get_obj (symbolP)->local) 3865 { 3866 segT old_sec; 3867 int old_subsec; 3868 char *p; 3869 int align; 3870 3871 old_sec = now_seg; 3872 old_subsec = now_subseg; 3873 3874 if (temp == 0) 3875 align = 0; 3876 else 3877 align = mylog2 (temp); 3878 3879 if (align < 0) 3880 { 3881 as_bad (_("alignment not a power of 2")); 3882 ignore_rest_of_line (); 3883 return; 3884 } 3885 3886 record_alignment (bss_section, align); 3887 subseg_set (bss_section, 0); 3888 if (align) 3889 frag_align (align, 0, 0); 3890 if (S_GET_SEGMENT (symbolP) == bss_section) 3891 symbol_get_frag (symbolP)->fr_symbol = 0; 3892 symbol_set_frag (symbolP, frag_now); 3893 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3894 (offsetT) size, (char *) 0); 3895 *p = 0; 3896 S_SET_SEGMENT (symbolP, bss_section); 3897 S_CLEAR_EXTERNAL (symbolP); 3898 S_SET_SIZE (symbolP, size); 3899 subseg_set (old_sec, old_subsec); 3900 } 3901 else 3902 #endif /* OBJ_ELF */ 3903 { 3904 allocate_common: 3905 S_SET_VALUE (symbolP, (valueT) size); 3906 #ifdef OBJ_ELF 3907 S_SET_ALIGN (symbolP, temp); 3908 S_SET_SIZE (symbolP, size); 3909 #endif 3910 S_SET_EXTERNAL (symbolP); 3911 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 3912 } 3913 } 3914 else 3915 { 3916 input_line_pointer++; 3917 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 3918 if (*input_line_pointer == '.') 3919 input_line_pointer++; 3920 /* @@ Some say data, some say bss. */ 3921 if (strncmp (input_line_pointer, "bss\"", 4) 3922 && strncmp (input_line_pointer, "data\"", 5)) 3923 { 3924 while (*--input_line_pointer != '"') 3925 ; 3926 input_line_pointer--; 3927 goto bad_common_segment; 3928 } 3929 while (*input_line_pointer++ != '"') 3930 ; 3931 goto allocate_common; 3932 } 3933 3934 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 3935 3936 demand_empty_rest_of_line (); 3937 return; 3938 3939 { 3940 bad_common_segment: 3941 p = input_line_pointer; 3942 while (*p && *p != '\n') 3943 p++; 3944 c = *p; 3945 *p = '\0'; 3946 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 3947 *p = c; 3948 input_line_pointer = p; 3949 ignore_rest_of_line (); 3950 return; 3951 } 3952 } 3953 3954 /* Handle the .empty pseudo-op. This suppresses the warnings about 3955 invalid delay slot usage. */ 3956 3957 static void 3958 s_empty (int ignore ATTRIBUTE_UNUSED) 3959 { 3960 /* The easy way to implement is to just forget about the last 3961 instruction. */ 3962 last_insn = NULL; 3963 } 3964 3965 static void 3966 s_seg (int ignore ATTRIBUTE_UNUSED) 3967 { 3968 3969 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 3970 { 3971 input_line_pointer += 6; 3972 s_text (0); 3973 return; 3974 } 3975 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 3976 { 3977 input_line_pointer += 6; 3978 s_data (0); 3979 return; 3980 } 3981 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 3982 { 3983 input_line_pointer += 7; 3984 s_data1 (); 3985 return; 3986 } 3987 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 3988 { 3989 input_line_pointer += 5; 3990 /* We only support 2 segments -- text and data -- for now, so 3991 things in the "bss segment" will have to go into data for now. 3992 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 3993 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 3994 return; 3995 } 3996 as_bad (_("Unknown segment type")); 3997 demand_empty_rest_of_line (); 3998 } 3999 4000 static void 4001 s_data1 (void) 4002 { 4003 subseg_set (data_section, 1); 4004 demand_empty_rest_of_line (); 4005 } 4006 4007 static void 4008 s_proc (int ignore ATTRIBUTE_UNUSED) 4009 { 4010 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4011 { 4012 ++input_line_pointer; 4013 } 4014 ++input_line_pointer; 4015 } 4016 4017 /* This static variable is set by s_uacons to tell sparc_cons_align 4018 that the expression does not need to be aligned. */ 4019 4020 static int sparc_no_align_cons = 0; 4021 4022 /* This static variable is set by sparc_cons to emit requested types 4023 of relocations in cons_fix_new_sparc. */ 4024 4025 static const char *sparc_cons_special_reloc; 4026 4027 /* This handles the unaligned space allocation pseudo-ops, such as 4028 .uaword. .uaword is just like .word, but the value does not need 4029 to be aligned. */ 4030 4031 static void 4032 s_uacons (int bytes) 4033 { 4034 /* Tell sparc_cons_align not to align this value. */ 4035 sparc_no_align_cons = 1; 4036 cons (bytes); 4037 sparc_no_align_cons = 0; 4038 } 4039 4040 /* This handles the native word allocation pseudo-op .nword. 4041 For sparc_arch_size 32 it is equivalent to .word, for 4042 sparc_arch_size 64 it is equivalent to .xword. */ 4043 4044 static void 4045 s_ncons (int bytes ATTRIBUTE_UNUSED) 4046 { 4047 cons (sparc_arch_size == 32 ? 4 : 8); 4048 } 4049 4050 #ifdef OBJ_ELF 4051 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4052 global register. 4053 The syntax is: 4054 4055 .register %g[2367],{#scratch|symbolname|#ignore} 4056 */ 4057 4058 static void 4059 s_register (int ignore ATTRIBUTE_UNUSED) 4060 { 4061 char c; 4062 int reg; 4063 int flags; 4064 const char *regname; 4065 4066 if (input_line_pointer[0] != '%' 4067 || input_line_pointer[1] != 'g' 4068 || ((input_line_pointer[2] & ~1) != '2' 4069 && (input_line_pointer[2] & ~1) != '6') 4070 || input_line_pointer[3] != ',') 4071 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4072 reg = input_line_pointer[2] - '0'; 4073 input_line_pointer += 4; 4074 4075 if (*input_line_pointer == '#') 4076 { 4077 ++input_line_pointer; 4078 regname = input_line_pointer; 4079 c = get_symbol_end (); 4080 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4081 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4082 if (regname[0] == 'i') 4083 regname = NULL; 4084 else 4085 regname = ""; 4086 } 4087 else 4088 { 4089 regname = input_line_pointer; 4090 c = get_symbol_end (); 4091 } 4092 if (sparc_arch_size == 64) 4093 { 4094 if (globals[reg]) 4095 { 4096 if ((regname && globals[reg] != (symbolS *) 1 4097 && strcmp (S_GET_NAME (globals[reg]), regname)) 4098 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4099 as_bad (_("redefinition of global register")); 4100 } 4101 else 4102 { 4103 if (regname == NULL) 4104 globals[reg] = (symbolS *) 1; 4105 else 4106 { 4107 if (*regname) 4108 { 4109 if (symbol_find (regname)) 4110 as_bad (_("Register symbol %s already defined."), 4111 regname); 4112 } 4113 globals[reg] = symbol_make (regname); 4114 flags = symbol_get_bfdsym (globals[reg])->flags; 4115 if (! *regname) 4116 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4117 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4118 flags |= BSF_GLOBAL; 4119 symbol_get_bfdsym (globals[reg])->flags = flags; 4120 S_SET_VALUE (globals[reg], (valueT) reg); 4121 S_SET_ALIGN (globals[reg], reg); 4122 S_SET_SIZE (globals[reg], 0); 4123 /* Although we actually want undefined_section here, 4124 we have to use absolute_section, because otherwise 4125 generic as code will make it a COM section. 4126 We fix this up in sparc_adjust_symtab. */ 4127 S_SET_SEGMENT (globals[reg], absolute_section); 4128 S_SET_OTHER (globals[reg], 0); 4129 elf_symbol (symbol_get_bfdsym (globals[reg])) 4130 ->internal_elf_sym.st_info = 4131 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4132 elf_symbol (symbol_get_bfdsym (globals[reg])) 4133 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4134 } 4135 } 4136 } 4137 4138 *input_line_pointer = c; 4139 4140 demand_empty_rest_of_line (); 4141 } 4142 4143 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4144 symbols which need it. */ 4145 4146 void 4147 sparc_adjust_symtab (void) 4148 { 4149 symbolS *sym; 4150 4151 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4152 { 4153 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4154 ->internal_elf_sym.st_info) != STT_REGISTER) 4155 continue; 4156 4157 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4158 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4159 continue; 4160 4161 S_SET_SEGMENT (sym, undefined_section); 4162 } 4163 } 4164 #endif 4165 4166 /* If the --enforce-aligned-data option is used, we require .word, 4167 et. al., to be aligned correctly. We do it by setting up an 4168 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4169 no unexpected alignment was introduced. 4170 4171 The SunOS and Solaris native assemblers enforce aligned data by 4172 default. We don't want to do that, because gcc can deliberately 4173 generate misaligned data if the packed attribute is used. Instead, 4174 we permit misaligned data by default, and permit the user to set an 4175 option to check for it. */ 4176 4177 void 4178 sparc_cons_align (int nbytes) 4179 { 4180 int nalign; 4181 char *p; 4182 4183 /* Only do this if we are enforcing aligned data. */ 4184 if (! enforce_aligned_data) 4185 return; 4186 4187 /* Don't align if this is an unaligned pseudo-op. */ 4188 if (sparc_no_align_cons) 4189 return; 4190 4191 nalign = mylog2 (nbytes); 4192 if (nalign == 0) 4193 return; 4194 4195 assert (nalign > 0); 4196 4197 if (now_seg == absolute_section) 4198 { 4199 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4200 as_bad (_("misaligned data")); 4201 return; 4202 } 4203 4204 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4205 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4206 4207 record_alignment (now_seg, nalign); 4208 } 4209 4210 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4211 4212 void 4213 sparc_handle_align (fragS *fragp) 4214 { 4215 int count, fix; 4216 char *p; 4217 4218 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4219 4220 switch (fragp->fr_type) 4221 { 4222 case rs_align_test: 4223 if (count != 0) 4224 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4225 break; 4226 4227 case rs_align_code: 4228 p = fragp->fr_literal + fragp->fr_fix; 4229 fix = 0; 4230 4231 if (count & 3) 4232 { 4233 fix = count & 3; 4234 memset (p, 0, fix); 4235 p += fix; 4236 count -= fix; 4237 } 4238 4239 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4240 { 4241 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4242 if (INSN_BIG_ENDIAN) 4243 number_to_chars_bigendian (p, wval, 4); 4244 else 4245 number_to_chars_littleendian (p, wval, 4); 4246 p += 4; 4247 count -= 4; 4248 fix += 4; 4249 } 4250 4251 if (INSN_BIG_ENDIAN) 4252 number_to_chars_bigendian (p, 0x01000000, 4); 4253 else 4254 number_to_chars_littleendian (p, 0x01000000, 4); 4255 4256 fragp->fr_fix += fix; 4257 fragp->fr_var = 4; 4258 break; 4259 4260 default: 4261 break; 4262 } 4263 } 4264 4265 #ifdef OBJ_ELF 4266 /* Some special processing for a Sparc ELF file. */ 4267 4268 void 4269 sparc_elf_final_processing (void) 4270 { 4271 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4272 sort of BFD interface for this. */ 4273 if (sparc_arch_size == 64) 4274 { 4275 switch (sparc_memory_model) 4276 { 4277 case MM_RMO: 4278 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4279 break; 4280 case MM_PSO: 4281 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4282 break; 4283 default: 4284 break; 4285 } 4286 } 4287 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4288 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4289 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4290 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4291 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4292 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4293 } 4294 4295 void 4296 sparc_cons (expressionS *exp, int size) 4297 { 4298 char *save; 4299 4300 SKIP_WHITESPACE (); 4301 sparc_cons_special_reloc = NULL; 4302 save = input_line_pointer; 4303 if (input_line_pointer[0] == '%' 4304 && input_line_pointer[1] == 'r' 4305 && input_line_pointer[2] == '_') 4306 { 4307 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4308 { 4309 input_line_pointer += 7; 4310 sparc_cons_special_reloc = "disp"; 4311 } 4312 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4313 { 4314 if (size != 4 && size != 8) 4315 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4316 else 4317 { 4318 input_line_pointer += 6; 4319 sparc_cons_special_reloc = "plt"; 4320 } 4321 } 4322 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4323 { 4324 if (size != 4 && size != 8) 4325 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4326 else 4327 { 4328 input_line_pointer += 13; 4329 sparc_cons_special_reloc = "tls_dtpoff"; 4330 } 4331 } 4332 if (sparc_cons_special_reloc) 4333 { 4334 int bad = 0; 4335 4336 switch (size) 4337 { 4338 case 1: 4339 if (*input_line_pointer != '8') 4340 bad = 1; 4341 input_line_pointer--; 4342 break; 4343 case 2: 4344 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4345 bad = 1; 4346 break; 4347 case 4: 4348 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4349 bad = 1; 4350 break; 4351 case 8: 4352 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4353 bad = 1; 4354 break; 4355 default: 4356 bad = 1; 4357 break; 4358 } 4359 4360 if (bad) 4361 { 4362 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4363 sparc_cons_special_reloc, size * 8, size); 4364 } 4365 else 4366 { 4367 input_line_pointer += 2; 4368 if (*input_line_pointer != '(') 4369 { 4370 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4371 sparc_cons_special_reloc, size * 8); 4372 bad = 1; 4373 } 4374 } 4375 4376 if (bad) 4377 { 4378 input_line_pointer = save; 4379 sparc_cons_special_reloc = NULL; 4380 } 4381 else 4382 { 4383 int c; 4384 char *end = ++input_line_pointer; 4385 int npar = 0; 4386 4387 while (! is_end_of_line[(c = *end)]) 4388 { 4389 if (c == '(') 4390 npar++; 4391 else if (c == ')') 4392 { 4393 if (!npar) 4394 break; 4395 npar--; 4396 } 4397 end++; 4398 } 4399 4400 if (c != ')') 4401 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4402 sparc_cons_special_reloc, size * 8); 4403 else 4404 { 4405 *end = '\0'; 4406 expression (exp); 4407 *end = c; 4408 if (input_line_pointer != end) 4409 { 4410 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4411 sparc_cons_special_reloc, size * 8); 4412 } 4413 else 4414 { 4415 input_line_pointer++; 4416 SKIP_WHITESPACE (); 4417 c = *input_line_pointer; 4418 if (! is_end_of_line[c] && c != ',') 4419 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4420 sparc_cons_special_reloc, size * 8); 4421 } 4422 } 4423 } 4424 } 4425 } 4426 if (sparc_cons_special_reloc == NULL) 4427 expression (exp); 4428 } 4429 4430 #endif 4431 4432 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4433 reloc for a cons. We could use the definition there, except that 4434 we want to handle little endian relocs specially. */ 4435 4436 void 4437 cons_fix_new_sparc (fragS *frag, 4438 int where, 4439 unsigned int nbytes, 4440 expressionS *exp) 4441 { 4442 bfd_reloc_code_real_type r; 4443 4444 r = (nbytes == 1 ? BFD_RELOC_8 : 4445 (nbytes == 2 ? BFD_RELOC_16 : 4446 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4447 4448 if (target_little_endian_data 4449 && nbytes == 4 4450 && now_seg->flags & SEC_ALLOC) 4451 r = BFD_RELOC_SPARC_REV32; 4452 4453 if (sparc_cons_special_reloc) 4454 { 4455 if (*sparc_cons_special_reloc == 'd') 4456 switch (nbytes) 4457 { 4458 case 1: r = BFD_RELOC_8_PCREL; break; 4459 case 2: r = BFD_RELOC_16_PCREL; break; 4460 case 4: r = BFD_RELOC_32_PCREL; break; 4461 case 8: r = BFD_RELOC_64_PCREL; break; 4462 default: abort (); 4463 } 4464 else if (*sparc_cons_special_reloc == 'p') 4465 switch (nbytes) 4466 { 4467 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4468 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4469 } 4470 else 4471 switch (nbytes) 4472 { 4473 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4474 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4475 } 4476 } 4477 else if (sparc_no_align_cons) 4478 { 4479 switch (nbytes) 4480 { 4481 case 2: r = BFD_RELOC_SPARC_UA16; break; 4482 case 4: r = BFD_RELOC_SPARC_UA32; break; 4483 case 8: r = BFD_RELOC_SPARC_UA64; break; 4484 default: abort (); 4485 } 4486 } 4487 4488 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4489 sparc_cons_special_reloc = NULL; 4490 } 4491 4492 void 4493 sparc_cfi_frame_initial_instructions (void) 4494 { 4495 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4496 } 4497 4498 int 4499 sparc_regname_to_dw2regnum (char *regname) 4500 { 4501 char *p, *q; 4502 4503 if (!regname[0]) 4504 return -1; 4505 4506 q = "goli"; 4507 p = strchr (q, regname[0]); 4508 if (p) 4509 { 4510 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4511 return -1; 4512 return (p - q) * 8 + regname[1] - '0'; 4513 } 4514 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4515 return 14; 4516 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4517 return 30; 4518 if (regname[0] == 'f' || regname[0] == 'r') 4519 { 4520 unsigned int regnum; 4521 4522 regnum = strtoul (regname + 1, &q, 10); 4523 if (p == q || *q) 4524 return -1; 4525 if (regnum >= ((regname[0] == 'f' 4526 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4527 ? 64 : 32)) 4528 return -1; 4529 if (regname[0] == 'f') 4530 { 4531 regnum += 32; 4532 if (regnum >= 64 && (regnum & 1)) 4533 return -1; 4534 } 4535 return regnum; 4536 } 4537 return -1; 4538 } 4539 4540 void 4541 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4542 { 4543 sparc_cons_special_reloc = "disp"; 4544 sparc_no_align_cons = 1; 4545 emit_expr (exp, nbytes); 4546 sparc_no_align_cons = 0; 4547 sparc_cons_special_reloc = NULL; 4548 } 4549