1 /* tc-xtensa.c -- Assemble Xtensa instructions. 2 Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include <limits.h> 22 #include "as.h" 23 #include "sb.h" 24 #include "safe-ctype.h" 25 #include "tc-xtensa.h" 26 #include "subsegs.h" 27 #include "xtensa-relax.h" 28 #include "dwarf2dbg.h" 29 #include "xtensa-istack.h" 30 #include "struc-symbol.h" 31 #include "xtensa-config.h" 32 33 /* Provide default values for new configuration settings. */ 34 #ifndef XSHAL_ABI 35 #define XSHAL_ABI 0 36 #endif 37 38 #ifndef uint32 39 #define uint32 unsigned int 40 #endif 41 #ifndef int32 42 #define int32 signed int 43 #endif 44 45 /* Notes: 46 47 Naming conventions (used somewhat inconsistently): 48 The xtensa_ functions are exported 49 The xg_ functions are internal 50 51 We also have a couple of different extensibility mechanisms. 52 1) The idiom replacement: 53 This is used when a line is first parsed to 54 replace an instruction pattern with another instruction 55 It is currently limited to replacements of instructions 56 with constant operands. 57 2) The xtensa-relax.c mechanism that has stronger instruction 58 replacement patterns. When an instruction's immediate field 59 does not fit the next instruction sequence is attempted. 60 In addition, "narrow" opcodes are supported this way. */ 61 62 63 /* Define characters with special meanings to GAS. */ 64 const char comment_chars[] = "#"; 65 const char line_comment_chars[] = "#"; 66 const char line_separator_chars[] = ";"; 67 const char EXP_CHARS[] = "eE"; 68 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 69 70 71 /* Flags to indicate whether the hardware supports the density and 72 absolute literals options. */ 73 74 bfd_boolean density_supported = XCHAL_HAVE_DENSITY; 75 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; 76 77 /* Maximum width we would pad an unreachable frag to get alignment. */ 78 #define UNREACHABLE_MAX_WIDTH 8 79 80 static vliw_insn cur_vinsn; 81 82 unsigned xtensa_num_pipe_stages; 83 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; 84 85 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; 86 87 /* Some functions are only valid in the front end. This variable 88 allows us to assert that we haven't crossed over into the 89 back end. */ 90 static bfd_boolean past_xtensa_end = FALSE; 91 92 /* Flags for properties of the last instruction in a segment. */ 93 #define FLAG_IS_A0_WRITER 0x1 94 #define FLAG_IS_BAD_LOOPEND 0x2 95 96 97 /* We define a special segment names ".literal" to place literals 98 into. The .fini and .init sections are special because they 99 contain code that is moved together by the linker. We give them 100 their own special .fini.literal and .init.literal sections. */ 101 102 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") 103 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") 104 #define INIT_SECTION_NAME xtensa_section_rename (".init") 105 #define FINI_SECTION_NAME xtensa_section_rename (".fini") 106 107 108 /* This type is used for the directive_stack to keep track of the 109 state of the literal collection pools. If lit_prefix is set, it is 110 used to determine the literal section names; otherwise, the literal 111 sections are determined based on the current text section. The 112 lit_seg and lit4_seg fields cache these literal sections, with the 113 current_text_seg field used a tag to indicate whether the cached 114 values are valid. */ 115 116 typedef struct lit_state_struct 117 { 118 char *lit_prefix; 119 segT current_text_seg; 120 segT lit_seg; 121 segT lit4_seg; 122 } lit_state; 123 124 static lit_state default_lit_sections; 125 126 127 /* We keep a list of literal segments. The seg_list type is the node 128 for this list. The literal_head pointer is the head of the list, 129 with the literal_head_h dummy node at the start. */ 130 131 typedef struct seg_list_struct 132 { 133 struct seg_list_struct *next; 134 segT seg; 135 } seg_list; 136 137 static seg_list literal_head_h; 138 static seg_list *literal_head = &literal_head_h; 139 140 141 /* Lists of symbols. We keep a list of symbols that label the current 142 instruction, so that we can adjust the symbols when inserting alignment 143 for various instructions. We also keep a list of all the symbols on 144 literals, so that we can fix up those symbols when the literals are 145 later moved into the text sections. */ 146 147 typedef struct sym_list_struct 148 { 149 struct sym_list_struct *next; 150 symbolS *sym; 151 } sym_list; 152 153 static sym_list *insn_labels = NULL; 154 static sym_list *free_insn_labels = NULL; 155 static sym_list *saved_insn_labels = NULL; 156 157 static sym_list *literal_syms; 158 159 160 /* Flags to determine whether to prefer const16 or l32r 161 if both options are available. */ 162 int prefer_const16 = 0; 163 int prefer_l32r = 0; 164 165 /* Global flag to indicate when we are emitting literals. */ 166 int generating_literals = 0; 167 168 /* The following PROPERTY table definitions are copied from 169 <elf/xtensa.h> and must be kept in sync with the code there. */ 170 171 /* Flags in the property tables to specify whether blocks of memory 172 are literals, instructions, data, or unreachable. For 173 instructions, blocks that begin loop targets and branch targets are 174 designated. Blocks that do not allow density, instruction 175 reordering or transformation are also specified. Finally, for 176 branch targets, branch target alignment priority is included. 177 Alignment of the next block is specified in the current block 178 and the size of the current block does not include any fill required 179 to align to the next block. */ 180 181 #define XTENSA_PROP_LITERAL 0x00000001 182 #define XTENSA_PROP_INSN 0x00000002 183 #define XTENSA_PROP_DATA 0x00000004 184 #define XTENSA_PROP_UNREACHABLE 0x00000008 185 /* Instruction only properties at beginning of code. */ 186 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 187 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 188 /* Instruction only properties about code. */ 189 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 190 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 191 /* Historically, NO_TRANSFORM was a property of instructions, 192 but it should apply to literals under certain circumstances. */ 193 #define XTENSA_PROP_NO_TRANSFORM 0x00000100 194 195 /* Branch target alignment information. This transmits information 196 to the linker optimization about the priority of aligning a 197 particular block for branch target alignment: None, low priority, 198 high priority, or required. These only need to be checked in 199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 200 Common usage is 201 202 switch (GET_XTENSA_PROP_BT_ALIGN (flags)) 203 case XTENSA_PROP_BT_ALIGN_NONE: 204 case XTENSA_PROP_BT_ALIGN_LOW: 205 case XTENSA_PROP_BT_ALIGN_HIGH: 206 case XTENSA_PROP_BT_ALIGN_REQUIRE: 207 */ 208 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 209 210 /* No branch target alignment. */ 211 #define XTENSA_PROP_BT_ALIGN_NONE 0x0 212 /* Low priority branch target alignment. */ 213 #define XTENSA_PROP_BT_ALIGN_LOW 0x1 214 /* High priority branch target alignment. */ 215 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 216 /* Required branch target alignment. */ 217 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 218 219 #define GET_XTENSA_PROP_BT_ALIGN(flag) \ 220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) 221 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 224 225 226 /* Alignment is specified in the block BEFORE the one that needs 227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 228 get the required alignment specified as a power of 2. Use 229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 230 alignment. Be careful of side effects since the SET will evaluate 231 flags twice. Also, note that the SIZE of a block in the property 232 table does not include the alignment size, so the alignment fill 233 must be calculated to determine if two blocks are contiguous. 234 TEXT_ALIGN is not currently implemented but is a placeholder for a 235 possible future implementation. */ 236 237 #define XTENSA_PROP_ALIGN 0x00000800 238 239 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 240 241 #define GET_XTENSA_PROP_ALIGNMENT(flag) \ 242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) 243 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 246 247 #define XTENSA_PROP_INSN_ABSLIT 0x00020000 248 249 250 /* Structure for saving instruction and alignment per-fragment data 251 that will be written to the object file. This structure is 252 equivalent to the actual data that will be written out to the file 253 but is easier to use. We provide a conversion to file flags 254 in frag_flags_to_number. */ 255 256 typedef struct frag_flags_struct frag_flags; 257 258 struct frag_flags_struct 259 { 260 /* is_literal should only be used after xtensa_move_literals. 261 If you need to check if you are generating a literal fragment, 262 then use the generating_literals global. */ 263 264 unsigned is_literal : 1; 265 unsigned is_insn : 1; 266 unsigned is_data : 1; 267 unsigned is_unreachable : 1; 268 269 /* is_specific_opcode implies no_transform. */ 270 unsigned is_no_transform : 1; 271 272 struct 273 { 274 unsigned is_loop_target : 1; 275 unsigned is_branch_target : 1; /* Branch targets have a priority. */ 276 unsigned bt_align_priority : 2; 277 278 unsigned is_no_density : 1; 279 /* no_longcalls flag does not need to be placed in the object file. */ 280 281 unsigned is_no_reorder : 1; 282 283 /* Uses absolute literal addressing for l32r. */ 284 unsigned is_abslit : 1; 285 } insn; 286 unsigned is_align : 1; 287 unsigned alignment : 5; 288 }; 289 290 291 /* Structure for saving information about a block of property data 292 for frags that have the same flags. */ 293 struct xtensa_block_info_struct 294 { 295 segT sec; 296 bfd_vma offset; 297 size_t size; 298 frag_flags flags; 299 struct xtensa_block_info_struct *next; 300 }; 301 302 303 /* Structure for saving the current state before emitting literals. */ 304 typedef struct emit_state_struct 305 { 306 const char *name; 307 segT now_seg; 308 subsegT now_subseg; 309 int generating_literals; 310 } emit_state; 311 312 313 /* Opcode placement information */ 314 315 typedef unsigned long long bitfield; 316 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) 317 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) 318 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) 319 320 #define MAX_FORMATS 32 321 322 typedef struct op_placement_info_struct 323 { 324 int num_formats; 325 /* A number describing how restrictive the issue is for this 326 opcode. For example, an opcode that fits lots of different 327 formats has a high freedom, as does an opcode that fits 328 only one format but many slots in that format. The most 329 restrictive is the opcode that fits only one slot in one 330 format. */ 331 int issuef; 332 xtensa_format narrowest; 333 char narrowest_size; 334 char narrowest_slot; 335 336 /* formats is a bitfield with the Nth bit set 337 if the opcode fits in the Nth xtensa_format. */ 338 bitfield formats; 339 340 /* slots[N]'s Mth bit is set if the op fits in the 341 Mth slot of the Nth xtensa_format. */ 342 bitfield slots[MAX_FORMATS]; 343 344 /* A count of the number of slots in a given format 345 an op can fit (i.e., the bitcount of the slot field above). */ 346 char slots_in_format[MAX_FORMATS]; 347 348 } op_placement_info, *op_placement_info_table; 349 350 op_placement_info_table op_placement_table; 351 352 353 /* Extra expression types. */ 354 355 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ 356 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ 357 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ 358 #define O_pcrel O_md4 /* value is a PC-relative offset */ 359 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ 360 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ 361 #define O_tlscall O_md7 /* TLS_CALL relocation */ 362 #define O_tpoff O_md8 /* TPOFF relocation */ 363 #define O_dtpoff O_md9 /* DTPOFF relocation */ 364 365 struct suffix_reloc_map 366 { 367 char *suffix; 368 int length; 369 bfd_reloc_code_real_type reloc; 370 unsigned char operator; 371 }; 372 373 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } 374 375 static struct suffix_reloc_map suffix_relocs[] = 376 { 377 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), 378 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), 379 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), 380 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), 381 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), 382 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), 383 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), 384 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), 385 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), 386 { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } 387 }; 388 389 390 /* Directives. */ 391 392 typedef enum 393 { 394 directive_none = 0, 395 directive_literal, 396 directive_density, 397 directive_transform, 398 directive_freeregs, 399 directive_longcalls, 400 directive_literal_prefix, 401 directive_schedule, 402 directive_absolute_literals, 403 directive_last_directive 404 } directiveE; 405 406 typedef struct 407 { 408 const char *name; 409 bfd_boolean can_be_negated; 410 } directive_infoS; 411 412 const directive_infoS directive_info[] = 413 { 414 { "none", FALSE }, 415 { "literal", FALSE }, 416 { "density", TRUE }, 417 { "transform", TRUE }, 418 { "freeregs", FALSE }, 419 { "longcalls", TRUE }, 420 { "literal_prefix", FALSE }, 421 { "schedule", TRUE }, 422 { "absolute-literals", TRUE } 423 }; 424 425 bfd_boolean directive_state[] = 426 { 427 FALSE, /* none */ 428 FALSE, /* literal */ 429 #if !XCHAL_HAVE_DENSITY 430 FALSE, /* density */ 431 #else 432 TRUE, /* density */ 433 #endif 434 TRUE, /* transform */ 435 FALSE, /* freeregs */ 436 FALSE, /* longcalls */ 437 FALSE, /* literal_prefix */ 438 FALSE, /* schedule */ 439 #if XSHAL_USE_ABSOLUTE_LITERALS 440 TRUE /* absolute_literals */ 441 #else 442 FALSE /* absolute_literals */ 443 #endif 444 }; 445 446 447 /* Directive functions. */ 448 449 static void xtensa_begin_directive (int); 450 static void xtensa_end_directive (int); 451 static void xtensa_literal_prefix (void); 452 static void xtensa_literal_position (int); 453 static void xtensa_literal_pseudo (int); 454 static void xtensa_frequency_pseudo (int); 455 static void xtensa_elf_cons (int); 456 static void xtensa_leb128 (int); 457 458 /* Parsing and Idiom Translation. */ 459 460 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); 461 462 /* Various Other Internal Functions. */ 463 464 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); 465 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); 466 static void xtensa_mark_literal_pool_location (void); 467 static addressT get_expanded_loop_offset (xtensa_opcode); 468 static fragS *get_literal_pool_location (segT); 469 static void set_literal_pool_location (segT, fragS *); 470 static void xtensa_set_frag_assembly_state (fragS *); 471 static void finish_vinsn (vliw_insn *); 472 static bfd_boolean emit_single_op (TInsn *); 473 static int total_frag_text_expansion (fragS *); 474 475 /* Alignment Functions. */ 476 477 static int get_text_align_power (unsigned); 478 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); 479 static int branch_align_power (segT); 480 481 /* Helpers for xtensa_relax_frag(). */ 482 483 static long relax_frag_add_nop (fragS *); 484 485 /* Accessors for additional per-subsegment information. */ 486 487 static unsigned get_last_insn_flags (segT, subsegT); 488 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); 489 static float get_subseg_total_freq (segT, subsegT); 490 static float get_subseg_target_freq (segT, subsegT); 491 static void set_subseg_freq (segT, subsegT, float, float); 492 493 /* Segment list functions. */ 494 495 static void xtensa_move_literals (void); 496 static void xtensa_reorder_segments (void); 497 static void xtensa_switch_to_literal_fragment (emit_state *); 498 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); 499 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); 500 static void xtensa_restore_emit_state (emit_state *); 501 static segT cache_literal_section (bfd_boolean); 502 503 /* Import from elf32-xtensa.c in BFD library. */ 504 505 extern asection *xtensa_make_property_section (asection *, const char *); 506 507 /* op_placement_info functions. */ 508 509 static void init_op_placement_info_table (void); 510 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); 511 static int xg_get_single_size (xtensa_opcode); 512 static xtensa_format xg_get_single_format (xtensa_opcode); 513 static int xg_get_single_slot (xtensa_opcode); 514 515 /* TInsn and IStack functions. */ 516 517 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); 518 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); 519 static bfd_boolean tinsn_has_complex_operands (const TInsn *); 520 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); 521 static bfd_boolean tinsn_check_arguments (const TInsn *); 522 static void tinsn_from_chars (TInsn *, char *, int); 523 static void tinsn_immed_from_frag (TInsn *, fragS *, int); 524 static int get_num_stack_text_bytes (IStack *); 525 static int get_num_stack_literal_bytes (IStack *); 526 527 /* vliw_insn functions. */ 528 529 static void xg_init_vinsn (vliw_insn *); 530 static void xg_clear_vinsn (vliw_insn *); 531 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); 532 static void xg_free_vinsn (vliw_insn *); 533 static bfd_boolean vinsn_to_insnbuf 534 (vliw_insn *, char *, fragS *, bfd_boolean); 535 static void vinsn_from_chars (vliw_insn *, char *); 536 537 /* Expression Utilities. */ 538 539 bfd_boolean expr_is_const (const expressionS *); 540 offsetT get_expr_const (const expressionS *); 541 void set_expr_const (expressionS *, offsetT); 542 bfd_boolean expr_is_register (const expressionS *); 543 offsetT get_expr_register (const expressionS *); 544 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); 545 bfd_boolean expr_is_equal (expressionS *, expressionS *); 546 static void copy_expr (expressionS *, const expressionS *); 547 548 /* Section renaming. */ 549 550 static void build_section_rename (const char *); 551 552 553 /* ISA imported from bfd. */ 554 extern xtensa_isa xtensa_default_isa; 555 556 extern int target_big_endian; 557 558 static xtensa_opcode xtensa_addi_opcode; 559 static xtensa_opcode xtensa_addmi_opcode; 560 static xtensa_opcode xtensa_call0_opcode; 561 static xtensa_opcode xtensa_call4_opcode; 562 static xtensa_opcode xtensa_call8_opcode; 563 static xtensa_opcode xtensa_call12_opcode; 564 static xtensa_opcode xtensa_callx0_opcode; 565 static xtensa_opcode xtensa_callx4_opcode; 566 static xtensa_opcode xtensa_callx8_opcode; 567 static xtensa_opcode xtensa_callx12_opcode; 568 static xtensa_opcode xtensa_const16_opcode; 569 static xtensa_opcode xtensa_entry_opcode; 570 static xtensa_opcode xtensa_extui_opcode; 571 static xtensa_opcode xtensa_movi_opcode; 572 static xtensa_opcode xtensa_movi_n_opcode; 573 static xtensa_opcode xtensa_isync_opcode; 574 static xtensa_opcode xtensa_jx_opcode; 575 static xtensa_opcode xtensa_l32r_opcode; 576 static xtensa_opcode xtensa_loop_opcode; 577 static xtensa_opcode xtensa_loopnez_opcode; 578 static xtensa_opcode xtensa_loopgtz_opcode; 579 static xtensa_opcode xtensa_nop_opcode; 580 static xtensa_opcode xtensa_nop_n_opcode; 581 static xtensa_opcode xtensa_or_opcode; 582 static xtensa_opcode xtensa_ret_opcode; 583 static xtensa_opcode xtensa_ret_n_opcode; 584 static xtensa_opcode xtensa_retw_opcode; 585 static xtensa_opcode xtensa_retw_n_opcode; 586 static xtensa_opcode xtensa_rsr_lcount_opcode; 587 static xtensa_opcode xtensa_waiti_opcode; 588 589 590 /* Command-line Options. */ 591 592 bfd_boolean use_literal_section = TRUE; 593 static bfd_boolean align_targets = TRUE; 594 static bfd_boolean warn_unaligned_branch_targets = FALSE; 595 static bfd_boolean has_a0_b_retw = FALSE; 596 static bfd_boolean workaround_a0_b_retw = FALSE; 597 static bfd_boolean workaround_b_j_loop_end = FALSE; 598 static bfd_boolean workaround_short_loop = FALSE; 599 static bfd_boolean maybe_has_short_loop = FALSE; 600 static bfd_boolean workaround_close_loop_end = FALSE; 601 static bfd_boolean maybe_has_close_loop_end = FALSE; 602 static bfd_boolean enforce_three_byte_loop_align = FALSE; 603 604 /* When workaround_short_loops is TRUE, all loops with early exits must 605 have at least 3 instructions. workaround_all_short_loops is a modifier 606 to the workaround_short_loop flag. In addition to the 607 workaround_short_loop actions, all straightline loopgtz and loopnez 608 must have at least 3 instructions. */ 609 610 static bfd_boolean workaround_all_short_loops = FALSE; 611 612 613 static void 614 xtensa_setup_hw_workarounds (int earliest, int latest) 615 { 616 if (earliest > latest) 617 as_fatal (_("illegal range of target hardware versions")); 618 619 /* Enable all workarounds for pre-T1050.0 hardware. */ 620 if (earliest < 105000 || latest < 105000) 621 { 622 workaround_a0_b_retw |= TRUE; 623 workaround_b_j_loop_end |= TRUE; 624 workaround_short_loop |= TRUE; 625 workaround_close_loop_end |= TRUE; 626 workaround_all_short_loops |= TRUE; 627 enforce_three_byte_loop_align = TRUE; 628 } 629 } 630 631 632 enum 633 { 634 option_density = OPTION_MD_BASE, 635 option_no_density, 636 637 option_relax, 638 option_no_relax, 639 640 option_link_relax, 641 option_no_link_relax, 642 643 option_generics, 644 option_no_generics, 645 646 option_transform, 647 option_no_transform, 648 649 option_text_section_literals, 650 option_no_text_section_literals, 651 652 option_absolute_literals, 653 option_no_absolute_literals, 654 655 option_align_targets, 656 option_no_align_targets, 657 658 option_warn_unaligned_targets, 659 660 option_longcalls, 661 option_no_longcalls, 662 663 option_workaround_a0_b_retw, 664 option_no_workaround_a0_b_retw, 665 666 option_workaround_b_j_loop_end, 667 option_no_workaround_b_j_loop_end, 668 669 option_workaround_short_loop, 670 option_no_workaround_short_loop, 671 672 option_workaround_all_short_loops, 673 option_no_workaround_all_short_loops, 674 675 option_workaround_close_loop_end, 676 option_no_workaround_close_loop_end, 677 678 option_no_workarounds, 679 680 option_rename_section_name, 681 682 option_prefer_l32r, 683 option_prefer_const16, 684 685 option_target_hardware 686 }; 687 688 const char *md_shortopts = ""; 689 690 struct option md_longopts[] = 691 { 692 { "density", no_argument, NULL, option_density }, 693 { "no-density", no_argument, NULL, option_no_density }, 694 695 /* Both "relax" and "generics" are deprecated and treated as equivalent 696 to the "transform" option. */ 697 { "relax", no_argument, NULL, option_relax }, 698 { "no-relax", no_argument, NULL, option_no_relax }, 699 { "generics", no_argument, NULL, option_generics }, 700 { "no-generics", no_argument, NULL, option_no_generics }, 701 702 { "transform", no_argument, NULL, option_transform }, 703 { "no-transform", no_argument, NULL, option_no_transform }, 704 { "text-section-literals", no_argument, NULL, option_text_section_literals }, 705 { "no-text-section-literals", no_argument, NULL, 706 option_no_text_section_literals }, 707 { "absolute-literals", no_argument, NULL, option_absolute_literals }, 708 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, 709 /* This option was changed from -align-target to -target-align 710 because it conflicted with the "-al" option. */ 711 { "target-align", no_argument, NULL, option_align_targets }, 712 { "no-target-align", no_argument, NULL, option_no_align_targets }, 713 { "warn-unaligned-targets", no_argument, NULL, 714 option_warn_unaligned_targets }, 715 { "longcalls", no_argument, NULL, option_longcalls }, 716 { "no-longcalls", no_argument, NULL, option_no_longcalls }, 717 718 { "no-workaround-a0-b-retw", no_argument, NULL, 719 option_no_workaround_a0_b_retw }, 720 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, 721 722 { "no-workaround-b-j-loop-end", no_argument, NULL, 723 option_no_workaround_b_j_loop_end }, 724 { "workaround-b-j-loop-end", no_argument, NULL, 725 option_workaround_b_j_loop_end }, 726 727 { "no-workaround-short-loops", no_argument, NULL, 728 option_no_workaround_short_loop }, 729 { "workaround-short-loops", no_argument, NULL, 730 option_workaround_short_loop }, 731 732 { "no-workaround-all-short-loops", no_argument, NULL, 733 option_no_workaround_all_short_loops }, 734 { "workaround-all-short-loop", no_argument, NULL, 735 option_workaround_all_short_loops }, 736 737 { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, 738 { "prefer-const16", no_argument, NULL, option_prefer_const16 }, 739 740 { "no-workarounds", no_argument, NULL, option_no_workarounds }, 741 742 { "no-workaround-close-loop-end", no_argument, NULL, 743 option_no_workaround_close_loop_end }, 744 { "workaround-close-loop-end", no_argument, NULL, 745 option_workaround_close_loop_end }, 746 747 { "rename-section", required_argument, NULL, option_rename_section_name }, 748 749 { "link-relax", no_argument, NULL, option_link_relax }, 750 { "no-link-relax", no_argument, NULL, option_no_link_relax }, 751 752 { "target-hardware", required_argument, NULL, option_target_hardware }, 753 754 { NULL, no_argument, NULL, 0 } 755 }; 756 757 size_t md_longopts_size = sizeof md_longopts; 758 759 760 int 761 md_parse_option (int c, char *arg) 762 { 763 switch (c) 764 { 765 case option_density: 766 as_warn (_("--density option is ignored")); 767 return 1; 768 case option_no_density: 769 as_warn (_("--no-density option is ignored")); 770 return 1; 771 case option_link_relax: 772 linkrelax = 1; 773 return 1; 774 case option_no_link_relax: 775 linkrelax = 0; 776 return 1; 777 case option_generics: 778 as_warn (_("--generics is deprecated; use --transform instead")); 779 return md_parse_option (option_transform, arg); 780 case option_no_generics: 781 as_warn (_("--no-generics is deprecated; use --no-transform instead")); 782 return md_parse_option (option_no_transform, arg); 783 case option_relax: 784 as_warn (_("--relax is deprecated; use --transform instead")); 785 return md_parse_option (option_transform, arg); 786 case option_no_relax: 787 as_warn (_("--no-relax is deprecated; use --no-transform instead")); 788 return md_parse_option (option_no_transform, arg); 789 case option_longcalls: 790 directive_state[directive_longcalls] = TRUE; 791 return 1; 792 case option_no_longcalls: 793 directive_state[directive_longcalls] = FALSE; 794 return 1; 795 case option_text_section_literals: 796 use_literal_section = FALSE; 797 return 1; 798 case option_no_text_section_literals: 799 use_literal_section = TRUE; 800 return 1; 801 case option_absolute_literals: 802 if (!absolute_literals_supported) 803 { 804 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); 805 return 0; 806 } 807 directive_state[directive_absolute_literals] = TRUE; 808 return 1; 809 case option_no_absolute_literals: 810 directive_state[directive_absolute_literals] = FALSE; 811 return 1; 812 813 case option_workaround_a0_b_retw: 814 workaround_a0_b_retw = TRUE; 815 return 1; 816 case option_no_workaround_a0_b_retw: 817 workaround_a0_b_retw = FALSE; 818 return 1; 819 case option_workaround_b_j_loop_end: 820 workaround_b_j_loop_end = TRUE; 821 return 1; 822 case option_no_workaround_b_j_loop_end: 823 workaround_b_j_loop_end = FALSE; 824 return 1; 825 826 case option_workaround_short_loop: 827 workaround_short_loop = TRUE; 828 return 1; 829 case option_no_workaround_short_loop: 830 workaround_short_loop = FALSE; 831 return 1; 832 833 case option_workaround_all_short_loops: 834 workaround_all_short_loops = TRUE; 835 return 1; 836 case option_no_workaround_all_short_loops: 837 workaround_all_short_loops = FALSE; 838 return 1; 839 840 case option_workaround_close_loop_end: 841 workaround_close_loop_end = TRUE; 842 return 1; 843 case option_no_workaround_close_loop_end: 844 workaround_close_loop_end = FALSE; 845 return 1; 846 847 case option_no_workarounds: 848 workaround_a0_b_retw = FALSE; 849 workaround_b_j_loop_end = FALSE; 850 workaround_short_loop = FALSE; 851 workaround_all_short_loops = FALSE; 852 workaround_close_loop_end = FALSE; 853 return 1; 854 855 case option_align_targets: 856 align_targets = TRUE; 857 return 1; 858 case option_no_align_targets: 859 align_targets = FALSE; 860 return 1; 861 862 case option_warn_unaligned_targets: 863 warn_unaligned_branch_targets = TRUE; 864 return 1; 865 866 case option_rename_section_name: 867 build_section_rename (arg); 868 return 1; 869 870 case 'Q': 871 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 872 should be emitted or not. FIXME: Not implemented. */ 873 return 1; 874 875 case option_prefer_l32r: 876 if (prefer_const16) 877 as_fatal (_("prefer-l32r conflicts with prefer-const16")); 878 prefer_l32r = 1; 879 return 1; 880 881 case option_prefer_const16: 882 if (prefer_l32r) 883 as_fatal (_("prefer-const16 conflicts with prefer-l32r")); 884 prefer_const16 = 1; 885 return 1; 886 887 case option_target_hardware: 888 { 889 int earliest, latest = 0; 890 if (*arg == 0 || *arg == '-') 891 as_fatal (_("invalid target hardware version")); 892 893 earliest = strtol (arg, &arg, 0); 894 895 if (*arg == 0) 896 latest = earliest; 897 else if (*arg == '-') 898 { 899 if (*++arg == 0) 900 as_fatal (_("invalid target hardware version")); 901 latest = strtol (arg, &arg, 0); 902 } 903 if (*arg != 0) 904 as_fatal (_("invalid target hardware version")); 905 906 xtensa_setup_hw_workarounds (earliest, latest); 907 return 1; 908 } 909 910 case option_transform: 911 /* This option has no affect other than to use the defaults, 912 which are already set. */ 913 return 1; 914 915 case option_no_transform: 916 /* This option turns off all transformations of any kind. 917 However, because we want to preserve the state of other 918 directives, we only change its own field. Thus, before 919 you perform any transformation, always check if transform 920 is available. If you use the functions we provide for this 921 purpose, you will be ok. */ 922 directive_state[directive_transform] = FALSE; 923 return 1; 924 925 default: 926 return 0; 927 } 928 } 929 930 931 void 932 md_show_usage (FILE *stream) 933 { 934 fputs ("\n\ 935 Xtensa options:\n\ 936 --[no-]text-section-literals\n\ 937 [Do not] put literals in the text section\n\ 938 --[no-]absolute-literals\n\ 939 [Do not] default to use non-PC-relative literals\n\ 940 --[no-]target-align [Do not] try to align branch targets\n\ 941 --[no-]longcalls [Do not] emit 32-bit call sequences\n\ 942 --[no-]transform [Do not] transform instructions\n\ 943 --rename-section old=new Rename section 'old' to 'new'\n", stream); 944 } 945 946 947 /* Functions related to the list of current label symbols. */ 948 949 static void 950 xtensa_add_insn_label (symbolS *sym) 951 { 952 sym_list *l; 953 954 if (!free_insn_labels) 955 l = (sym_list *) xmalloc (sizeof (sym_list)); 956 else 957 { 958 l = free_insn_labels; 959 free_insn_labels = l->next; 960 } 961 962 l->sym = sym; 963 l->next = insn_labels; 964 insn_labels = l; 965 } 966 967 968 static void 969 xtensa_clear_insn_labels (void) 970 { 971 sym_list **pl; 972 973 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 974 ; 975 *pl = insn_labels; 976 insn_labels = NULL; 977 } 978 979 980 static void 981 xtensa_move_labels (fragS *new_frag, valueT new_offset) 982 { 983 sym_list *lit; 984 985 for (lit = insn_labels; lit; lit = lit->next) 986 { 987 symbolS *lit_sym = lit->sym; 988 S_SET_VALUE (lit_sym, new_offset); 989 symbol_set_frag (lit_sym, new_frag); 990 } 991 } 992 993 994 /* Directive data and functions. */ 995 996 typedef struct state_stackS_struct 997 { 998 directiveE directive; 999 bfd_boolean negated; 1000 bfd_boolean old_state; 1001 const char *file; 1002 unsigned int line; 1003 const void *datum; 1004 struct state_stackS_struct *prev; 1005 } state_stackS; 1006 1007 state_stackS *directive_state_stack; 1008 1009 const pseudo_typeS md_pseudo_table[] = 1010 { 1011 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ 1012 { "literal_position", xtensa_literal_position, 0 }, 1013 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ 1014 { "long", xtensa_elf_cons, 4 }, 1015 { "word", xtensa_elf_cons, 4 }, 1016 { "4byte", xtensa_elf_cons, 4 }, 1017 { "short", xtensa_elf_cons, 2 }, 1018 { "2byte", xtensa_elf_cons, 2 }, 1019 { "sleb128", xtensa_leb128, 1}, 1020 { "uleb128", xtensa_leb128, 0}, 1021 { "begin", xtensa_begin_directive, 0 }, 1022 { "end", xtensa_end_directive, 0 }, 1023 { "literal", xtensa_literal_pseudo, 0 }, 1024 { "frequency", xtensa_frequency_pseudo, 0 }, 1025 { NULL, 0, 0 }, 1026 }; 1027 1028 1029 static bfd_boolean 1030 use_transform (void) 1031 { 1032 /* After md_end, you should be checking frag by frag, rather 1033 than state directives. */ 1034 assert (!past_xtensa_end); 1035 return directive_state[directive_transform]; 1036 } 1037 1038 1039 static bfd_boolean 1040 do_align_targets (void) 1041 { 1042 /* Do not use this function after md_end; just look at align_targets 1043 instead. There is no target-align directive, so alignment is either 1044 enabled for all frags or not done at all. */ 1045 assert (!past_xtensa_end); 1046 return align_targets && use_transform (); 1047 } 1048 1049 1050 static void 1051 directive_push (directiveE directive, bfd_boolean negated, const void *datum) 1052 { 1053 char *file; 1054 unsigned int line; 1055 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); 1056 1057 as_where (&file, &line); 1058 1059 stack->directive = directive; 1060 stack->negated = negated; 1061 stack->old_state = directive_state[directive]; 1062 stack->file = file; 1063 stack->line = line; 1064 stack->datum = datum; 1065 stack->prev = directive_state_stack; 1066 directive_state_stack = stack; 1067 1068 directive_state[directive] = !negated; 1069 } 1070 1071 1072 static void 1073 directive_pop (directiveE *directive, 1074 bfd_boolean *negated, 1075 const char **file, 1076 unsigned int *line, 1077 const void **datum) 1078 { 1079 state_stackS *top = directive_state_stack; 1080 1081 if (!directive_state_stack) 1082 { 1083 as_bad (_("unmatched end directive")); 1084 *directive = directive_none; 1085 return; 1086 } 1087 1088 directive_state[directive_state_stack->directive] = top->old_state; 1089 *directive = top->directive; 1090 *negated = top->negated; 1091 *file = top->file; 1092 *line = top->line; 1093 *datum = top->datum; 1094 directive_state_stack = top->prev; 1095 free (top); 1096 } 1097 1098 1099 static void 1100 directive_balance (void) 1101 { 1102 while (directive_state_stack) 1103 { 1104 directiveE directive; 1105 bfd_boolean negated; 1106 const char *file; 1107 unsigned int line; 1108 const void *datum; 1109 1110 directive_pop (&directive, &negated, &file, &line, &datum); 1111 as_warn_where ((char *) file, line, 1112 _(".begin directive with no matching .end directive")); 1113 } 1114 } 1115 1116 1117 static bfd_boolean 1118 inside_directive (directiveE dir) 1119 { 1120 state_stackS *top = directive_state_stack; 1121 1122 while (top && top->directive != dir) 1123 top = top->prev; 1124 1125 return (top != NULL); 1126 } 1127 1128 1129 static void 1130 get_directive (directiveE *directive, bfd_boolean *negated) 1131 { 1132 int len; 1133 unsigned i; 1134 char *directive_string; 1135 1136 if (strncmp (input_line_pointer, "no-", 3) != 0) 1137 *negated = FALSE; 1138 else 1139 { 1140 *negated = TRUE; 1141 input_line_pointer += 3; 1142 } 1143 1144 len = strspn (input_line_pointer, 1145 "abcdefghijklmnopqrstuvwxyz_-/0123456789."); 1146 1147 /* This code is a hack to make .begin [no-][generics|relax] exactly 1148 equivalent to .begin [no-]transform. We should remove it when 1149 we stop accepting those options. */ 1150 1151 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) 1152 { 1153 as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); 1154 directive_string = "transform"; 1155 } 1156 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) 1157 { 1158 as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); 1159 directive_string = "transform"; 1160 } 1161 else 1162 directive_string = input_line_pointer; 1163 1164 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) 1165 { 1166 if (strncmp (directive_string, directive_info[i].name, len) == 0) 1167 { 1168 input_line_pointer += len; 1169 *directive = (directiveE) i; 1170 if (*negated && !directive_info[i].can_be_negated) 1171 as_bad (_("directive %s cannot be negated"), 1172 directive_info[i].name); 1173 return; 1174 } 1175 } 1176 1177 as_bad (_("unknown directive")); 1178 *directive = (directiveE) XTENSA_UNDEFINED; 1179 } 1180 1181 1182 static void 1183 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) 1184 { 1185 directiveE directive; 1186 bfd_boolean negated; 1187 emit_state *state; 1188 lit_state *ls; 1189 1190 get_directive (&directive, &negated); 1191 if (directive == (directiveE) XTENSA_UNDEFINED) 1192 { 1193 discard_rest_of_line (); 1194 return; 1195 } 1196 1197 if (cur_vinsn.inside_bundle) 1198 as_bad (_("directives are not valid inside bundles")); 1199 1200 switch (directive) 1201 { 1202 case directive_literal: 1203 if (!inside_directive (directive_literal)) 1204 { 1205 /* Previous labels go with whatever follows this directive, not with 1206 the literal, so save them now. */ 1207 saved_insn_labels = insn_labels; 1208 insn_labels = NULL; 1209 } 1210 as_warn (_(".begin literal is deprecated; use .literal instead")); 1211 state = (emit_state *) xmalloc (sizeof (emit_state)); 1212 xtensa_switch_to_literal_fragment (state); 1213 directive_push (directive_literal, negated, state); 1214 break; 1215 1216 case directive_literal_prefix: 1217 /* Have to flush pending output because a movi relaxed to an l32r 1218 might produce a literal. */ 1219 md_flush_pending_output (); 1220 /* Check to see if the current fragment is a literal 1221 fragment. If it is, then this operation is not allowed. */ 1222 if (generating_literals) 1223 { 1224 as_bad (_("cannot set literal_prefix inside literal fragment")); 1225 return; 1226 } 1227 1228 /* Allocate the literal state for this section and push 1229 onto the directive stack. */ 1230 ls = xmalloc (sizeof (lit_state)); 1231 assert (ls); 1232 1233 *ls = default_lit_sections; 1234 directive_push (directive_literal_prefix, negated, ls); 1235 1236 /* Process the new prefix. */ 1237 xtensa_literal_prefix (); 1238 break; 1239 1240 case directive_freeregs: 1241 /* This information is currently unused, but we'll accept the statement 1242 and just discard the rest of the line. This won't check the syntax, 1243 but it will accept every correct freeregs directive. */ 1244 input_line_pointer += strcspn (input_line_pointer, "\n"); 1245 directive_push (directive_freeregs, negated, 0); 1246 break; 1247 1248 case directive_schedule: 1249 md_flush_pending_output (); 1250 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 1251 frag_now->fr_symbol, frag_now->fr_offset, NULL); 1252 directive_push (directive_schedule, negated, 0); 1253 xtensa_set_frag_assembly_state (frag_now); 1254 break; 1255 1256 case directive_density: 1257 as_warn (_(".begin [no-]density is ignored")); 1258 break; 1259 1260 case directive_absolute_literals: 1261 md_flush_pending_output (); 1262 if (!absolute_literals_supported && !negated) 1263 { 1264 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1265 break; 1266 } 1267 xtensa_set_frag_assembly_state (frag_now); 1268 directive_push (directive, negated, 0); 1269 break; 1270 1271 default: 1272 md_flush_pending_output (); 1273 xtensa_set_frag_assembly_state (frag_now); 1274 directive_push (directive, negated, 0); 1275 break; 1276 } 1277 1278 demand_empty_rest_of_line (); 1279 } 1280 1281 1282 static void 1283 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) 1284 { 1285 directiveE begin_directive, end_directive; 1286 bfd_boolean begin_negated, end_negated; 1287 const char *file; 1288 unsigned int line; 1289 emit_state *state; 1290 emit_state **state_ptr; 1291 lit_state *s; 1292 1293 if (cur_vinsn.inside_bundle) 1294 as_bad (_("directives are not valid inside bundles")); 1295 1296 get_directive (&end_directive, &end_negated); 1297 1298 md_flush_pending_output (); 1299 1300 switch (end_directive) 1301 { 1302 case (directiveE) XTENSA_UNDEFINED: 1303 discard_rest_of_line (); 1304 return; 1305 1306 case directive_density: 1307 as_warn (_(".end [no-]density is ignored")); 1308 demand_empty_rest_of_line (); 1309 break; 1310 1311 case directive_absolute_literals: 1312 if (!absolute_literals_supported && !end_negated) 1313 { 1314 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1315 demand_empty_rest_of_line (); 1316 return; 1317 } 1318 break; 1319 1320 default: 1321 break; 1322 } 1323 1324 state_ptr = &state; /* use state_ptr to avoid type-punning warning */ 1325 directive_pop (&begin_directive, &begin_negated, &file, &line, 1326 (const void **) state_ptr); 1327 1328 if (begin_directive != directive_none) 1329 { 1330 if (begin_directive != end_directive || begin_negated != end_negated) 1331 { 1332 as_bad (_("does not match begin %s%s at %s:%d"), 1333 begin_negated ? "no-" : "", 1334 directive_info[begin_directive].name, file, line); 1335 } 1336 else 1337 { 1338 switch (end_directive) 1339 { 1340 case directive_literal: 1341 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); 1342 xtensa_restore_emit_state (state); 1343 xtensa_set_frag_assembly_state (frag_now); 1344 free (state); 1345 if (!inside_directive (directive_literal)) 1346 { 1347 /* Restore the list of current labels. */ 1348 xtensa_clear_insn_labels (); 1349 insn_labels = saved_insn_labels; 1350 } 1351 break; 1352 1353 case directive_literal_prefix: 1354 /* Restore the default collection sections from saved state. */ 1355 s = (lit_state *) state; 1356 assert (s); 1357 default_lit_sections = *s; 1358 1359 /* Free the state storage. */ 1360 free (s->lit_prefix); 1361 free (s); 1362 break; 1363 1364 case directive_schedule: 1365 case directive_freeregs: 1366 break; 1367 1368 default: 1369 xtensa_set_frag_assembly_state (frag_now); 1370 break; 1371 } 1372 } 1373 } 1374 1375 demand_empty_rest_of_line (); 1376 } 1377 1378 1379 /* Place an aligned literal fragment at the current location. */ 1380 1381 static void 1382 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) 1383 { 1384 md_flush_pending_output (); 1385 1386 if (inside_directive (directive_literal)) 1387 as_warn (_(".literal_position inside literal directive; ignoring")); 1388 xtensa_mark_literal_pool_location (); 1389 1390 demand_empty_rest_of_line (); 1391 xtensa_clear_insn_labels (); 1392 } 1393 1394 1395 /* Support .literal label, expr, ... */ 1396 1397 static void 1398 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) 1399 { 1400 emit_state state; 1401 char *p, *base_name; 1402 char c; 1403 segT dest_seg; 1404 1405 if (inside_directive (directive_literal)) 1406 { 1407 as_bad (_(".literal not allowed inside .begin literal region")); 1408 ignore_rest_of_line (); 1409 return; 1410 } 1411 1412 md_flush_pending_output (); 1413 1414 /* Previous labels go with whatever follows this directive, not with 1415 the literal, so save them now. */ 1416 saved_insn_labels = insn_labels; 1417 insn_labels = NULL; 1418 1419 /* If we are using text-section literals, then this is the right value... */ 1420 dest_seg = now_seg; 1421 1422 base_name = input_line_pointer; 1423 1424 xtensa_switch_to_literal_fragment (&state); 1425 1426 /* ...but if we aren't using text-section-literals, then we 1427 need to put them in the section we just switched to. */ 1428 if (use_literal_section || directive_state[directive_absolute_literals]) 1429 dest_seg = now_seg; 1430 1431 /* All literals are aligned to four-byte boundaries. */ 1432 frag_align (2, 0, 0); 1433 record_alignment (now_seg, 2); 1434 1435 c = get_symbol_end (); 1436 /* Just after name is now '\0'. */ 1437 p = input_line_pointer; 1438 *p = c; 1439 SKIP_WHITESPACE (); 1440 1441 if (*input_line_pointer != ',' && *input_line_pointer != ':') 1442 { 1443 as_bad (_("expected comma or colon after symbol name; " 1444 "rest of line ignored")); 1445 ignore_rest_of_line (); 1446 xtensa_restore_emit_state (&state); 1447 return; 1448 } 1449 *p = 0; 1450 1451 colon (base_name); 1452 1453 *p = c; 1454 input_line_pointer++; /* skip ',' or ':' */ 1455 1456 xtensa_elf_cons (4); 1457 1458 xtensa_restore_emit_state (&state); 1459 1460 /* Restore the list of current labels. */ 1461 xtensa_clear_insn_labels (); 1462 insn_labels = saved_insn_labels; 1463 } 1464 1465 1466 static void 1467 xtensa_literal_prefix (void) 1468 { 1469 char *name; 1470 int len; 1471 1472 /* Parse the new prefix from the input_line_pointer. */ 1473 SKIP_WHITESPACE (); 1474 len = strspn (input_line_pointer, 1475 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1476 "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); 1477 1478 /* Get a null-terminated copy of the name. */ 1479 name = xmalloc (len + 1); 1480 assert (name); 1481 strncpy (name, input_line_pointer, len); 1482 name[len] = 0; 1483 1484 /* Skip the name in the input line. */ 1485 input_line_pointer += len; 1486 1487 default_lit_sections.lit_prefix = name; 1488 1489 /* Clear cached literal sections, since the prefix has changed. */ 1490 default_lit_sections.lit_seg = NULL; 1491 default_lit_sections.lit4_seg = NULL; 1492 } 1493 1494 1495 /* Support ".frequency branch_target_frequency fall_through_frequency". */ 1496 1497 static void 1498 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) 1499 { 1500 float fall_through_f, target_f; 1501 1502 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); 1503 if (fall_through_f < 0) 1504 { 1505 as_bad (_("fall through frequency must be greater than 0")); 1506 ignore_rest_of_line (); 1507 return; 1508 } 1509 1510 target_f = (float) strtod (input_line_pointer, &input_line_pointer); 1511 if (target_f < 0) 1512 { 1513 as_bad (_("branch target frequency must be greater than 0")); 1514 ignore_rest_of_line (); 1515 return; 1516 } 1517 1518 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); 1519 1520 demand_empty_rest_of_line (); 1521 } 1522 1523 1524 /* Like normal .long/.short/.word, except support @plt, etc. 1525 Clobbers input_line_pointer, checks end-of-line. */ 1526 1527 static void 1528 xtensa_elf_cons (int nbytes) 1529 { 1530 expressionS exp; 1531 bfd_reloc_code_real_type reloc; 1532 1533 md_flush_pending_output (); 1534 1535 if (cur_vinsn.inside_bundle) 1536 as_bad (_("directives are not valid inside bundles")); 1537 1538 if (is_it_end_of_statement ()) 1539 { 1540 demand_empty_rest_of_line (); 1541 return; 1542 } 1543 1544 do 1545 { 1546 expression (&exp); 1547 if (exp.X_op == O_symbol 1548 && *input_line_pointer == '@' 1549 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) 1550 != BFD_RELOC_NONE)) 1551 { 1552 reloc_howto_type *reloc_howto = 1553 bfd_reloc_type_lookup (stdoutput, reloc); 1554 1555 if (reloc == BFD_RELOC_UNUSED || !reloc_howto) 1556 as_bad (_("unsupported relocation")); 1557 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP 1558 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 1559 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 1560 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) 1561 as_bad (_("opcode-specific %s relocation used outside " 1562 "an instruction"), reloc_howto->name); 1563 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) 1564 as_bad (_("%s relocations do not fit in %d bytes"), 1565 reloc_howto->name, nbytes); 1566 else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC 1567 || reloc == BFD_RELOC_XTENSA_TLS_ARG 1568 || reloc == BFD_RELOC_XTENSA_TLS_CALL) 1569 as_bad (_("invalid use of %s relocation"), reloc_howto->name); 1570 else 1571 { 1572 char *p = frag_more ((int) nbytes); 1573 xtensa_set_frag_assembly_state (frag_now); 1574 fix_new_exp (frag_now, p - frag_now->fr_literal, 1575 nbytes, &exp, reloc_howto->pc_relative, reloc); 1576 } 1577 } 1578 else 1579 { 1580 xtensa_set_frag_assembly_state (frag_now); 1581 emit_expr (&exp, (unsigned int) nbytes); 1582 } 1583 } 1584 while (*input_line_pointer++ == ','); 1585 1586 input_line_pointer--; /* Put terminator back into stream. */ 1587 demand_empty_rest_of_line (); 1588 } 1589 1590 static bfd_boolean is_leb128_expr; 1591 1592 static void 1593 xtensa_leb128 (int sign) 1594 { 1595 is_leb128_expr = TRUE; 1596 s_leb128 (sign); 1597 is_leb128_expr = FALSE; 1598 } 1599 1600 1601 /* Parsing and Idiom Translation. */ 1602 1603 /* Parse @plt, etc. and return the desired relocation. */ 1604 static bfd_reloc_code_real_type 1605 xtensa_elf_suffix (char **str_p, expressionS *exp_p) 1606 { 1607 char ident[20]; 1608 char *str = *str_p; 1609 char *str2; 1610 int ch; 1611 int len; 1612 struct suffix_reloc_map *ptr; 1613 1614 if (*str++ != '@') 1615 return BFD_RELOC_NONE; 1616 1617 for (ch = *str, str2 = ident; 1618 (str2 < ident + sizeof (ident) - 1 1619 && (ISALNUM (ch) || ch == '@')); 1620 ch = *++str) 1621 { 1622 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); 1623 } 1624 1625 *str2 = '\0'; 1626 len = str2 - ident; 1627 1628 ch = ident[0]; 1629 for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) 1630 if (ch == ptr->suffix[0] 1631 && len == ptr->length 1632 && memcmp (ident, ptr->suffix, ptr->length) == 0) 1633 { 1634 /* Now check for "identifier@suffix+constant". */ 1635 if (*str == '-' || *str == '+') 1636 { 1637 char *orig_line = input_line_pointer; 1638 expressionS new_exp; 1639 1640 input_line_pointer = str; 1641 expression (&new_exp); 1642 if (new_exp.X_op == O_constant) 1643 { 1644 exp_p->X_add_number += new_exp.X_add_number; 1645 str = input_line_pointer; 1646 } 1647 1648 if (&input_line_pointer != str_p) 1649 input_line_pointer = orig_line; 1650 } 1651 1652 *str_p = str; 1653 return ptr->reloc; 1654 } 1655 1656 return BFD_RELOC_UNUSED; 1657 } 1658 1659 1660 /* Find the matching operator type. */ 1661 static unsigned char 1662 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) 1663 { 1664 struct suffix_reloc_map *sfx; 1665 unsigned char operator = (unsigned char) -1; 1666 1667 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) 1668 { 1669 if (sfx->reloc == reloc) 1670 { 1671 operator = sfx->operator; 1672 break; 1673 } 1674 } 1675 assert (operator != (unsigned char) -1); 1676 return operator; 1677 } 1678 1679 1680 /* Find the matching reloc type. */ 1681 static bfd_reloc_code_real_type 1682 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) 1683 { 1684 struct suffix_reloc_map *sfx; 1685 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; 1686 1687 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) 1688 { 1689 if (sfx->operator == operator) 1690 { 1691 reloc = sfx->reloc; 1692 break; 1693 } 1694 } 1695 1696 if (is_literal) 1697 { 1698 if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) 1699 return BFD_RELOC_XTENSA_TLSDESC_FN; 1700 else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) 1701 return BFD_RELOC_XTENSA_TLSDESC_ARG; 1702 } 1703 1704 if (reloc == BFD_RELOC_UNUSED) 1705 return BFD_RELOC_32; 1706 1707 return reloc; 1708 } 1709 1710 1711 static const char * 1712 expression_end (const char *name) 1713 { 1714 while (1) 1715 { 1716 switch (*name) 1717 { 1718 case '}': 1719 case ';': 1720 case '\0': 1721 case ',': 1722 case ':': 1723 return name; 1724 case ' ': 1725 case '\t': 1726 ++name; 1727 continue; 1728 default: 1729 return 0; 1730 } 1731 } 1732 } 1733 1734 1735 #define ERROR_REG_NUM ((unsigned) -1) 1736 1737 static unsigned 1738 tc_get_register (const char *prefix) 1739 { 1740 unsigned reg; 1741 const char *next_expr; 1742 const char *old_line_pointer; 1743 1744 SKIP_WHITESPACE (); 1745 old_line_pointer = input_line_pointer; 1746 1747 if (*input_line_pointer == '$') 1748 ++input_line_pointer; 1749 1750 /* Accept "sp" as a synonym for "a1". */ 1751 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' 1752 && expression_end (input_line_pointer + 2)) 1753 { 1754 input_line_pointer += 2; 1755 return 1; /* AR[1] */ 1756 } 1757 1758 while (*input_line_pointer++ == *prefix++) 1759 ; 1760 --input_line_pointer; 1761 --prefix; 1762 1763 if (*prefix) 1764 { 1765 as_bad (_("bad register name: %s"), old_line_pointer); 1766 return ERROR_REG_NUM; 1767 } 1768 1769 if (!ISDIGIT ((unsigned char) *input_line_pointer)) 1770 { 1771 as_bad (_("bad register number: %s"), input_line_pointer); 1772 return ERROR_REG_NUM; 1773 } 1774 1775 reg = 0; 1776 1777 while (ISDIGIT ((int) *input_line_pointer)) 1778 reg = reg * 10 + *input_line_pointer++ - '0'; 1779 1780 if (!(next_expr = expression_end (input_line_pointer))) 1781 { 1782 as_bad (_("bad register name: %s"), old_line_pointer); 1783 return ERROR_REG_NUM; 1784 } 1785 1786 input_line_pointer = (char *) next_expr; 1787 1788 return reg; 1789 } 1790 1791 1792 static void 1793 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) 1794 { 1795 xtensa_isa isa = xtensa_default_isa; 1796 1797 /* Check if this is an immediate operand. */ 1798 if (xtensa_operand_is_register (isa, opc, opnd) == 0) 1799 { 1800 bfd_reloc_code_real_type reloc; 1801 segT t = expression (tok); 1802 if (t == absolute_section 1803 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) 1804 { 1805 assert (tok->X_op == O_constant); 1806 tok->X_op = O_symbol; 1807 tok->X_add_symbol = &abs_symbol; 1808 } 1809 1810 if ((tok->X_op == O_constant || tok->X_op == O_symbol) 1811 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 1812 != BFD_RELOC_NONE)) 1813 { 1814 switch (reloc) 1815 { 1816 case BFD_RELOC_LO16: 1817 if (tok->X_op == O_constant) 1818 { 1819 tok->X_add_number &= 0xffff; 1820 return; 1821 } 1822 break; 1823 case BFD_RELOC_HI16: 1824 if (tok->X_op == O_constant) 1825 { 1826 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; 1827 return; 1828 } 1829 break; 1830 case BFD_RELOC_UNUSED: 1831 as_bad (_("unsupported relocation")); 1832 return; 1833 case BFD_RELOC_32_PCREL: 1834 as_bad (_("pcrel relocation not allowed in an instruction")); 1835 return; 1836 default: 1837 break; 1838 } 1839 tok->X_op = map_suffix_reloc_to_operator (reloc); 1840 } 1841 } 1842 else 1843 { 1844 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); 1845 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); 1846 1847 if (reg != ERROR_REG_NUM) /* Already errored */ 1848 { 1849 uint32 buf = reg; 1850 if (xtensa_operand_encode (isa, opc, opnd, &buf)) 1851 as_bad (_("register number out of range")); 1852 } 1853 1854 tok->X_op = O_register; 1855 tok->X_add_symbol = 0; 1856 tok->X_add_number = reg; 1857 } 1858 } 1859 1860 1861 /* Split up the arguments for an opcode or pseudo-op. */ 1862 1863 static int 1864 tokenize_arguments (char **args, char *str) 1865 { 1866 char *old_input_line_pointer; 1867 bfd_boolean saw_comma = FALSE; 1868 bfd_boolean saw_arg = FALSE; 1869 bfd_boolean saw_colon = FALSE; 1870 int num_args = 0; 1871 char *arg_end, *arg; 1872 int arg_len; 1873 1874 /* Save and restore input_line_pointer around this function. */ 1875 old_input_line_pointer = input_line_pointer; 1876 input_line_pointer = str; 1877 1878 while (*input_line_pointer) 1879 { 1880 SKIP_WHITESPACE (); 1881 switch (*input_line_pointer) 1882 { 1883 case '\0': 1884 case '}': 1885 goto fini; 1886 1887 case ':': 1888 input_line_pointer++; 1889 if (saw_comma || saw_colon || !saw_arg) 1890 goto err; 1891 saw_colon = TRUE; 1892 break; 1893 1894 case ',': 1895 input_line_pointer++; 1896 if (saw_comma || saw_colon || !saw_arg) 1897 goto err; 1898 saw_comma = TRUE; 1899 break; 1900 1901 default: 1902 if (!saw_comma && !saw_colon && saw_arg) 1903 goto err; 1904 1905 arg_end = input_line_pointer + 1; 1906 while (!expression_end (arg_end)) 1907 arg_end += 1; 1908 1909 arg_len = arg_end - input_line_pointer; 1910 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); 1911 args[num_args] = arg; 1912 1913 if (saw_colon) 1914 *arg++ = ':'; 1915 strncpy (arg, input_line_pointer, arg_len); 1916 arg[arg_len] = '\0'; 1917 1918 input_line_pointer = arg_end; 1919 num_args += 1; 1920 saw_comma = FALSE; 1921 saw_colon = FALSE; 1922 saw_arg = TRUE; 1923 break; 1924 } 1925 } 1926 1927 fini: 1928 if (saw_comma || saw_colon) 1929 goto err; 1930 input_line_pointer = old_input_line_pointer; 1931 return num_args; 1932 1933 err: 1934 if (saw_comma) 1935 as_bad (_("extra comma")); 1936 else if (saw_colon) 1937 as_bad (_("extra colon")); 1938 else if (!saw_arg) 1939 as_bad (_("missing argument")); 1940 else 1941 as_bad (_("missing comma or colon")); 1942 input_line_pointer = old_input_line_pointer; 1943 return -1; 1944 } 1945 1946 1947 /* Parse the arguments to an opcode. Return TRUE on error. */ 1948 1949 static bfd_boolean 1950 parse_arguments (TInsn *insn, int num_args, char **arg_strings) 1951 { 1952 expressionS *tok, *last_tok; 1953 xtensa_opcode opcode = insn->opcode; 1954 bfd_boolean had_error = TRUE; 1955 xtensa_isa isa = xtensa_default_isa; 1956 int n, num_regs = 0; 1957 int opcode_operand_count; 1958 int opnd_cnt, last_opnd_cnt; 1959 unsigned int next_reg = 0; 1960 char *old_input_line_pointer; 1961 1962 if (insn->insn_type == ITYPE_LITERAL) 1963 opcode_operand_count = 1; 1964 else 1965 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); 1966 1967 tok = insn->tok; 1968 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); 1969 1970 /* Save and restore input_line_pointer around this function. */ 1971 old_input_line_pointer = input_line_pointer; 1972 1973 last_tok = 0; 1974 last_opnd_cnt = -1; 1975 opnd_cnt = 0; 1976 1977 /* Skip invisible operands. */ 1978 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) 1979 { 1980 opnd_cnt += 1; 1981 tok++; 1982 } 1983 1984 for (n = 0; n < num_args; n++) 1985 { 1986 input_line_pointer = arg_strings[n]; 1987 if (*input_line_pointer == ':') 1988 { 1989 xtensa_regfile opnd_rf; 1990 input_line_pointer++; 1991 if (num_regs == 0) 1992 goto err; 1993 assert (opnd_cnt > 0); 1994 num_regs--; 1995 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); 1996 if (next_reg 1997 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) 1998 as_warn (_("incorrect register number, ignoring")); 1999 next_reg++; 2000 } 2001 else 2002 { 2003 if (opnd_cnt >= opcode_operand_count) 2004 { 2005 as_warn (_("too many arguments")); 2006 goto err; 2007 } 2008 assert (opnd_cnt < MAX_INSN_ARGS); 2009 2010 expression_maybe_register (opcode, opnd_cnt, tok); 2011 next_reg = tok->X_add_number + 1; 2012 2013 if (tok->X_op == O_illegal || tok->X_op == O_absent) 2014 goto err; 2015 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) 2016 { 2017 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; 2018 /* minus 1 because we are seeing one right now */ 2019 } 2020 else 2021 num_regs = 0; 2022 2023 last_tok = tok; 2024 last_opnd_cnt = opnd_cnt; 2025 2026 do 2027 { 2028 opnd_cnt += 1; 2029 tok++; 2030 } 2031 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); 2032 } 2033 } 2034 2035 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) 2036 goto err; 2037 2038 insn->ntok = tok - insn->tok; 2039 had_error = FALSE; 2040 2041 err: 2042 input_line_pointer = old_input_line_pointer; 2043 return had_error; 2044 } 2045 2046 2047 static int 2048 get_invisible_operands (TInsn *insn) 2049 { 2050 xtensa_isa isa = xtensa_default_isa; 2051 static xtensa_insnbuf slotbuf = NULL; 2052 xtensa_format fmt; 2053 xtensa_opcode opc = insn->opcode; 2054 int slot, opnd, fmt_found; 2055 unsigned val; 2056 2057 if (!slotbuf) 2058 slotbuf = xtensa_insnbuf_alloc (isa); 2059 2060 /* Find format/slot where this can be encoded. */ 2061 fmt_found = 0; 2062 slot = 0; 2063 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 2064 { 2065 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 2066 { 2067 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) 2068 { 2069 fmt_found = 1; 2070 break; 2071 } 2072 } 2073 if (fmt_found) break; 2074 } 2075 2076 if (!fmt_found) 2077 { 2078 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); 2079 return -1; 2080 } 2081 2082 /* First encode all the visible operands 2083 (to deal with shared field operands). */ 2084 for (opnd = 0; opnd < insn->ntok; opnd++) 2085 { 2086 if (xtensa_operand_is_visible (isa, opc, opnd) == 1 2087 && (insn->tok[opnd].X_op == O_register 2088 || insn->tok[opnd].X_op == O_constant)) 2089 { 2090 val = insn->tok[opnd].X_add_number; 2091 xtensa_operand_encode (isa, opc, opnd, &val); 2092 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); 2093 } 2094 } 2095 2096 /* Then pull out the values for the invisible ones. */ 2097 for (opnd = 0; opnd < insn->ntok; opnd++) 2098 { 2099 if (xtensa_operand_is_visible (isa, opc, opnd) == 0) 2100 { 2101 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); 2102 xtensa_operand_decode (isa, opc, opnd, &val); 2103 insn->tok[opnd].X_add_number = val; 2104 if (xtensa_operand_is_register (isa, opc, opnd) == 1) 2105 insn->tok[opnd].X_op = O_register; 2106 else 2107 insn->tok[opnd].X_op = O_constant; 2108 } 2109 } 2110 2111 return 0; 2112 } 2113 2114 2115 static void 2116 xg_reverse_shift_count (char **cnt_argp) 2117 { 2118 char *cnt_arg, *new_arg; 2119 cnt_arg = *cnt_argp; 2120 2121 /* replace the argument with "31-(argument)" */ 2122 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); 2123 sprintf (new_arg, "31-(%s)", cnt_arg); 2124 2125 free (cnt_arg); 2126 *cnt_argp = new_arg; 2127 } 2128 2129 2130 /* If "arg" is a constant expression, return non-zero with the value 2131 in *valp. */ 2132 2133 static int 2134 xg_arg_is_constant (char *arg, offsetT *valp) 2135 { 2136 expressionS exp; 2137 char *save_ptr = input_line_pointer; 2138 2139 input_line_pointer = arg; 2140 expression (&exp); 2141 input_line_pointer = save_ptr; 2142 2143 if (exp.X_op == O_constant) 2144 { 2145 *valp = exp.X_add_number; 2146 return 1; 2147 } 2148 2149 return 0; 2150 } 2151 2152 2153 static void 2154 xg_replace_opname (char **popname, char *newop) 2155 { 2156 free (*popname); 2157 *popname = (char *) xmalloc (strlen (newop) + 1); 2158 strcpy (*popname, newop); 2159 } 2160 2161 2162 static int 2163 xg_check_num_args (int *pnum_args, 2164 int expected_num, 2165 char *opname, 2166 char **arg_strings) 2167 { 2168 int num_args = *pnum_args; 2169 2170 if (num_args < expected_num) 2171 { 2172 as_bad (_("not enough operands (%d) for '%s'; expected %d"), 2173 num_args, opname, expected_num); 2174 return -1; 2175 } 2176 2177 if (num_args > expected_num) 2178 { 2179 as_warn (_("too many operands (%d) for '%s'; expected %d"), 2180 num_args, opname, expected_num); 2181 while (num_args-- > expected_num) 2182 { 2183 free (arg_strings[num_args]); 2184 arg_strings[num_args] = 0; 2185 } 2186 *pnum_args = expected_num; 2187 return -1; 2188 } 2189 2190 return 0; 2191 } 2192 2193 2194 /* If the register is not specified as part of the opcode, 2195 then get it from the operand and move it to the opcode. */ 2196 2197 static int 2198 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) 2199 { 2200 xtensa_isa isa = xtensa_default_isa; 2201 xtensa_sysreg sr; 2202 char *opname, *new_opname; 2203 const char *sr_name; 2204 int is_user, is_write; 2205 2206 opname = *popname; 2207 if (*opname == '_') 2208 opname += 1; 2209 is_user = (opname[1] == 'u'); 2210 is_write = (opname[0] == 'w'); 2211 2212 /* Opname == [rw]ur or [rwx]sr... */ 2213 2214 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2215 return -1; 2216 2217 /* Check if the argument is a symbolic register name. */ 2218 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); 2219 /* Handle WSR to "INTSET" as a special case. */ 2220 if (sr == XTENSA_UNDEFINED && is_write && !is_user 2221 && !strcasecmp (arg_strings[1], "intset")) 2222 sr = xtensa_sysreg_lookup_name (isa, "interrupt"); 2223 if (sr == XTENSA_UNDEFINED 2224 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) 2225 { 2226 /* Maybe it's a register number.... */ 2227 offsetT val; 2228 if (!xg_arg_is_constant (arg_strings[1], &val)) 2229 { 2230 as_bad (_("invalid register '%s' for '%s' instruction"), 2231 arg_strings[1], opname); 2232 return -1; 2233 } 2234 sr = xtensa_sysreg_lookup (isa, val, is_user); 2235 if (sr == XTENSA_UNDEFINED) 2236 { 2237 as_bad (_("invalid register number (%ld) for '%s' instruction"), 2238 (long) val, opname); 2239 return -1; 2240 } 2241 } 2242 2243 /* Remove the last argument, which is now part of the opcode. */ 2244 free (arg_strings[1]); 2245 arg_strings[1] = 0; 2246 *pnum_args = 1; 2247 2248 /* Translate the opcode. */ 2249 sr_name = xtensa_sysreg_name (isa, sr); 2250 /* Another special case for "WSR.INTSET".... */ 2251 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) 2252 sr_name = "intset"; 2253 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2254 sprintf (new_opname, "%s.%s", *popname, sr_name); 2255 free (*popname); 2256 *popname = new_opname; 2257 2258 return 0; 2259 } 2260 2261 2262 static int 2263 xtensa_translate_old_userreg_ops (char **popname) 2264 { 2265 xtensa_isa isa = xtensa_default_isa; 2266 xtensa_sysreg sr; 2267 char *opname, *new_opname; 2268 const char *sr_name; 2269 bfd_boolean has_underbar = FALSE; 2270 2271 opname = *popname; 2272 if (opname[0] == '_') 2273 { 2274 has_underbar = TRUE; 2275 opname += 1; 2276 } 2277 2278 sr = xtensa_sysreg_lookup_name (isa, opname + 1); 2279 if (sr != XTENSA_UNDEFINED) 2280 { 2281 /* The new default name ("nnn") is different from the old default 2282 name ("URnnn"). The old default is handled below, and we don't 2283 want to recognize [RW]nnn, so do nothing if the name is the (new) 2284 default. */ 2285 static char namebuf[10]; 2286 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); 2287 if (strcmp (namebuf, opname + 1) == 0) 2288 return 0; 2289 } 2290 else 2291 { 2292 offsetT val; 2293 char *end; 2294 2295 /* Only continue if the reg name is "URnnn". */ 2296 if (opname[1] != 'u' || opname[2] != 'r') 2297 return 0; 2298 val = strtoul (opname + 3, &end, 10); 2299 if (*end != '\0') 2300 return 0; 2301 2302 sr = xtensa_sysreg_lookup (isa, val, 1); 2303 if (sr == XTENSA_UNDEFINED) 2304 { 2305 as_bad (_("invalid register number (%ld) for '%s'"), 2306 (long) val, opname); 2307 return -1; 2308 } 2309 } 2310 2311 /* Translate the opcode. */ 2312 sr_name = xtensa_sysreg_name (isa, sr); 2313 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2314 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), 2315 opname[0], sr_name); 2316 free (*popname); 2317 *popname = new_opname; 2318 2319 return 0; 2320 } 2321 2322 2323 static int 2324 xtensa_translate_zero_immed (char *old_op, 2325 char *new_op, 2326 char **popname, 2327 int *pnum_args, 2328 char **arg_strings) 2329 { 2330 char *opname; 2331 offsetT val; 2332 2333 opname = *popname; 2334 assert (opname[0] != '_'); 2335 2336 if (strcmp (opname, old_op) != 0) 2337 return 0; 2338 2339 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2340 return -1; 2341 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) 2342 { 2343 xg_replace_opname (popname, new_op); 2344 free (arg_strings[1]); 2345 arg_strings[1] = arg_strings[2]; 2346 arg_strings[2] = 0; 2347 *pnum_args = 2; 2348 } 2349 2350 return 0; 2351 } 2352 2353 2354 /* If the instruction is an idiom (i.e., a built-in macro), translate it. 2355 Returns non-zero if an error was found. */ 2356 2357 static int 2358 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) 2359 { 2360 char *opname = *popname; 2361 bfd_boolean has_underbar = FALSE; 2362 2363 if (*opname == '_') 2364 { 2365 has_underbar = TRUE; 2366 opname += 1; 2367 } 2368 2369 if (strcmp (opname, "mov") == 0) 2370 { 2371 if (use_transform () && !has_underbar && density_supported) 2372 xg_replace_opname (popname, "mov.n"); 2373 else 2374 { 2375 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2376 return -1; 2377 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2378 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); 2379 strcpy (arg_strings[2], arg_strings[1]); 2380 *pnum_args = 3; 2381 } 2382 return 0; 2383 } 2384 2385 if (strcmp (opname, "bbsi.l") == 0) 2386 { 2387 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2388 return -1; 2389 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); 2390 if (target_big_endian) 2391 xg_reverse_shift_count (&arg_strings[1]); 2392 return 0; 2393 } 2394 2395 if (strcmp (opname, "bbci.l") == 0) 2396 { 2397 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2398 return -1; 2399 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); 2400 if (target_big_endian) 2401 xg_reverse_shift_count (&arg_strings[1]); 2402 return 0; 2403 } 2404 2405 /* Don't do anything special with NOPs inside FLIX instructions. They 2406 are handled elsewhere. Real NOP instructions are always available 2407 in configurations with FLIX, so this should never be an issue but 2408 check for it anyway. */ 2409 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED 2410 && strcmp (opname, "nop") == 0) 2411 { 2412 if (use_transform () && !has_underbar && density_supported) 2413 xg_replace_opname (popname, "nop.n"); 2414 else 2415 { 2416 if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) 2417 return -1; 2418 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2419 arg_strings[0] = (char *) xmalloc (3); 2420 arg_strings[1] = (char *) xmalloc (3); 2421 arg_strings[2] = (char *) xmalloc (3); 2422 strcpy (arg_strings[0], "a1"); 2423 strcpy (arg_strings[1], "a1"); 2424 strcpy (arg_strings[2], "a1"); 2425 *pnum_args = 3; 2426 } 2427 return 0; 2428 } 2429 2430 /* Recognize [RW]UR and [RWX]SR. */ 2431 if ((((opname[0] == 'r' || opname[0] == 'w') 2432 && (opname[1] == 'u' || opname[1] == 's')) 2433 || (opname[0] == 'x' && opname[1] == 's')) 2434 && opname[2] == 'r' 2435 && opname[3] == '\0') 2436 return xg_translate_sysreg_op (popname, pnum_args, arg_strings); 2437 2438 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and 2439 [RW]<name> if <name> is the non-default name of a user register. */ 2440 if ((opname[0] == 'r' || opname[0] == 'w') 2441 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) 2442 return xtensa_translate_old_userreg_ops (popname); 2443 2444 /* Relax branches that don't allow comparisons against an immediate value 2445 of zero to the corresponding branches with implicit zero immediates. */ 2446 if (!has_underbar && use_transform ()) 2447 { 2448 if (xtensa_translate_zero_immed ("bnei", "bnez", popname, 2449 pnum_args, arg_strings)) 2450 return -1; 2451 2452 if (xtensa_translate_zero_immed ("beqi", "beqz", popname, 2453 pnum_args, arg_strings)) 2454 return -1; 2455 2456 if (xtensa_translate_zero_immed ("bgei", "bgez", popname, 2457 pnum_args, arg_strings)) 2458 return -1; 2459 2460 if (xtensa_translate_zero_immed ("blti", "bltz", popname, 2461 pnum_args, arg_strings)) 2462 return -1; 2463 } 2464 2465 return 0; 2466 } 2467 2468 2469 /* Functions for dealing with the Xtensa ISA. */ 2470 2471 /* Currently the assembler only allows us to use a single target per 2472 fragment. Because of this, only one operand for a given 2473 instruction may be symbolic. If there is a PC-relative operand, 2474 the last one is chosen. Otherwise, the result is the number of the 2475 last immediate operand, and if there are none of those, we fail and 2476 return -1. */ 2477 2478 static int 2479 get_relaxable_immed (xtensa_opcode opcode) 2480 { 2481 int last_immed = -1; 2482 int noperands, opi; 2483 2484 if (opcode == XTENSA_UNDEFINED) 2485 return -1; 2486 2487 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); 2488 for (opi = noperands - 1; opi >= 0; opi--) 2489 { 2490 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) 2491 continue; 2492 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) 2493 return opi; 2494 if (last_immed == -1 2495 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) 2496 last_immed = opi; 2497 } 2498 return last_immed; 2499 } 2500 2501 2502 static xtensa_opcode 2503 get_opcode_from_buf (const char *buf, int slot) 2504 { 2505 static xtensa_insnbuf insnbuf = NULL; 2506 static xtensa_insnbuf slotbuf = NULL; 2507 xtensa_isa isa = xtensa_default_isa; 2508 xtensa_format fmt; 2509 2510 if (!insnbuf) 2511 { 2512 insnbuf = xtensa_insnbuf_alloc (isa); 2513 slotbuf = xtensa_insnbuf_alloc (isa); 2514 } 2515 2516 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); 2517 fmt = xtensa_format_decode (isa, insnbuf); 2518 if (fmt == XTENSA_UNDEFINED) 2519 return XTENSA_UNDEFINED; 2520 2521 if (slot >= xtensa_format_num_slots (isa, fmt)) 2522 return XTENSA_UNDEFINED; 2523 2524 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 2525 return xtensa_opcode_decode (isa, fmt, slot, slotbuf); 2526 } 2527 2528 2529 #ifdef TENSILICA_DEBUG 2530 2531 /* For debugging, print out the mapping of opcode numbers to opcodes. */ 2532 2533 static void 2534 xtensa_print_insn_table (void) 2535 { 2536 int num_opcodes, num_operands; 2537 xtensa_opcode opcode; 2538 xtensa_isa isa = xtensa_default_isa; 2539 2540 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); 2541 for (opcode = 0; opcode < num_opcodes; opcode++) 2542 { 2543 int opn; 2544 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); 2545 num_operands = xtensa_opcode_num_operands (isa, opcode); 2546 for (opn = 0; opn < num_operands; opn++) 2547 { 2548 if (xtensa_operand_is_visible (isa, opcode, opn) == 0) 2549 continue; 2550 if (xtensa_operand_is_register (isa, opcode, opn) == 1) 2551 { 2552 xtensa_regfile opnd_rf = 2553 xtensa_operand_regfile (isa, opcode, opn); 2554 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); 2555 } 2556 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) 2557 fputs ("[lLr] ", stderr); 2558 else 2559 fputs ("i ", stderr); 2560 } 2561 fprintf (stderr, "\n"); 2562 } 2563 } 2564 2565 2566 static void 2567 print_vliw_insn (xtensa_insnbuf vbuf) 2568 { 2569 xtensa_isa isa = xtensa_default_isa; 2570 xtensa_format f = xtensa_format_decode (isa, vbuf); 2571 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); 2572 int op; 2573 2574 fprintf (stderr, "format = %d\n", f); 2575 2576 for (op = 0; op < xtensa_format_num_slots (isa, f); op++) 2577 { 2578 xtensa_opcode opcode; 2579 const char *opname; 2580 int operands; 2581 2582 xtensa_format_get_slot (isa, f, op, vbuf, sbuf); 2583 opcode = xtensa_opcode_decode (isa, f, op, sbuf); 2584 opname = xtensa_opcode_name (isa, opcode); 2585 2586 fprintf (stderr, "op in slot %i is %s;\n", op, opname); 2587 fprintf (stderr, " operands = "); 2588 for (operands = 0; 2589 operands < xtensa_opcode_num_operands (isa, opcode); 2590 operands++) 2591 { 2592 unsigned int val; 2593 if (xtensa_operand_is_visible (isa, opcode, operands) == 0) 2594 continue; 2595 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); 2596 xtensa_operand_decode (isa, opcode, operands, &val); 2597 fprintf (stderr, "%d ", val); 2598 } 2599 fprintf (stderr, "\n"); 2600 } 2601 xtensa_insnbuf_free (isa, sbuf); 2602 } 2603 2604 #endif /* TENSILICA_DEBUG */ 2605 2606 2607 static bfd_boolean 2608 is_direct_call_opcode (xtensa_opcode opcode) 2609 { 2610 xtensa_isa isa = xtensa_default_isa; 2611 int n, num_operands; 2612 2613 if (xtensa_opcode_is_call (isa, opcode) != 1) 2614 return FALSE; 2615 2616 num_operands = xtensa_opcode_num_operands (isa, opcode); 2617 for (n = 0; n < num_operands; n++) 2618 { 2619 if (xtensa_operand_is_register (isa, opcode, n) == 0 2620 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) 2621 return TRUE; 2622 } 2623 return FALSE; 2624 } 2625 2626 2627 /* Convert from BFD relocation type code to slot and operand number. 2628 Returns non-zero on failure. */ 2629 2630 static int 2631 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) 2632 { 2633 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP 2634 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 2635 { 2636 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; 2637 *is_alt = FALSE; 2638 } 2639 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 2640 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) 2641 { 2642 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; 2643 *is_alt = TRUE; 2644 } 2645 else 2646 return -1; 2647 2648 return 0; 2649 } 2650 2651 2652 /* Convert from slot number to BFD relocation type code for the 2653 standard PC-relative relocations. Return BFD_RELOC_NONE on 2654 failure. */ 2655 2656 static bfd_reloc_code_real_type 2657 encode_reloc (int slot) 2658 { 2659 if (slot < 0 || slot > 14) 2660 return BFD_RELOC_NONE; 2661 2662 return BFD_RELOC_XTENSA_SLOT0_OP + slot; 2663 } 2664 2665 2666 /* Convert from slot numbers to BFD relocation type code for the 2667 "alternate" relocations. Return BFD_RELOC_NONE on failure. */ 2668 2669 static bfd_reloc_code_real_type 2670 encode_alt_reloc (int slot) 2671 { 2672 if (slot < 0 || slot > 14) 2673 return BFD_RELOC_NONE; 2674 2675 return BFD_RELOC_XTENSA_SLOT0_ALT + slot; 2676 } 2677 2678 2679 static void 2680 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, 2681 xtensa_format fmt, 2682 int slot, 2683 xtensa_opcode opcode, 2684 int operand, 2685 uint32 value, 2686 const char *file, 2687 unsigned int line) 2688 { 2689 uint32 valbuf = value; 2690 2691 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 2692 { 2693 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) 2694 == 1) 2695 as_bad_where ((char *) file, line, 2696 _("operand %d of '%s' has out of range value '%u'"), 2697 operand + 1, 2698 xtensa_opcode_name (xtensa_default_isa, opcode), 2699 value); 2700 else 2701 as_bad_where ((char *) file, line, 2702 _("operand %d of '%s' has invalid value '%u'"), 2703 operand + 1, 2704 xtensa_opcode_name (xtensa_default_isa, opcode), 2705 value); 2706 return; 2707 } 2708 2709 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, 2710 slotbuf, valbuf); 2711 } 2712 2713 2714 static uint32 2715 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, 2716 xtensa_format fmt, 2717 int slot, 2718 xtensa_opcode opcode, 2719 int opnum) 2720 { 2721 uint32 val = 0; 2722 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, 2723 fmt, slot, slotbuf, &val); 2724 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); 2725 return val; 2726 } 2727 2728 2729 /* Checks for rules from xtensa-relax tables. */ 2730 2731 /* The routine xg_instruction_matches_option_term must return TRUE 2732 when a given option term is true. The meaning of all of the option 2733 terms is given interpretation by this function. This is needed when 2734 an option depends on the state of a directive, but there are no such 2735 options in use right now. */ 2736 2737 static bfd_boolean 2738 xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, 2739 const ReqOrOption *option) 2740 { 2741 if (strcmp (option->option_name, "realnop") == 0 2742 || strncmp (option->option_name, "IsaUse", 6) == 0) 2743 { 2744 /* These conditions were evaluated statically when building the 2745 relaxation table. There's no need to reevaluate them now. */ 2746 return TRUE; 2747 } 2748 else 2749 { 2750 as_fatal (_("internal error: unknown option name '%s'"), 2751 option->option_name); 2752 } 2753 } 2754 2755 2756 static bfd_boolean 2757 xg_instruction_matches_or_options (TInsn *insn, 2758 const ReqOrOptionList *or_option) 2759 { 2760 const ReqOrOption *option; 2761 /* Must match each of the AND terms. */ 2762 for (option = or_option; option != NULL; option = option->next) 2763 { 2764 if (xg_instruction_matches_option_term (insn, option)) 2765 return TRUE; 2766 } 2767 return FALSE; 2768 } 2769 2770 2771 static bfd_boolean 2772 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) 2773 { 2774 const ReqOption *req_options; 2775 /* Must match each of the AND terms. */ 2776 for (req_options = options; 2777 req_options != NULL; 2778 req_options = req_options->next) 2779 { 2780 /* Must match one of the OR clauses. */ 2781 if (!xg_instruction_matches_or_options (insn, 2782 req_options->or_option_terms)) 2783 return FALSE; 2784 } 2785 return TRUE; 2786 } 2787 2788 2789 /* Return the transition rule that matches or NULL if none matches. */ 2790 2791 static bfd_boolean 2792 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) 2793 { 2794 PreconditionList *condition_l; 2795 2796 if (rule->opcode != insn->opcode) 2797 return FALSE; 2798 2799 for (condition_l = rule->conditions; 2800 condition_l != NULL; 2801 condition_l = condition_l->next) 2802 { 2803 expressionS *exp1; 2804 expressionS *exp2; 2805 Precondition *cond = condition_l->precond; 2806 2807 switch (cond->typ) 2808 { 2809 case OP_CONSTANT: 2810 /* The expression must be the constant. */ 2811 assert (cond->op_num < insn->ntok); 2812 exp1 = &insn->tok[cond->op_num]; 2813 if (expr_is_const (exp1)) 2814 { 2815 switch (cond->cmp) 2816 { 2817 case OP_EQUAL: 2818 if (get_expr_const (exp1) != cond->op_data) 2819 return FALSE; 2820 break; 2821 case OP_NOTEQUAL: 2822 if (get_expr_const (exp1) == cond->op_data) 2823 return FALSE; 2824 break; 2825 default: 2826 return FALSE; 2827 } 2828 } 2829 else if (expr_is_register (exp1)) 2830 { 2831 switch (cond->cmp) 2832 { 2833 case OP_EQUAL: 2834 if (get_expr_register (exp1) != cond->op_data) 2835 return FALSE; 2836 break; 2837 case OP_NOTEQUAL: 2838 if (get_expr_register (exp1) == cond->op_data) 2839 return FALSE; 2840 break; 2841 default: 2842 return FALSE; 2843 } 2844 } 2845 else 2846 return FALSE; 2847 break; 2848 2849 case OP_OPERAND: 2850 assert (cond->op_num < insn->ntok); 2851 assert (cond->op_data < insn->ntok); 2852 exp1 = &insn->tok[cond->op_num]; 2853 exp2 = &insn->tok[cond->op_data]; 2854 2855 switch (cond->cmp) 2856 { 2857 case OP_EQUAL: 2858 if (!expr_is_equal (exp1, exp2)) 2859 return FALSE; 2860 break; 2861 case OP_NOTEQUAL: 2862 if (expr_is_equal (exp1, exp2)) 2863 return FALSE; 2864 break; 2865 } 2866 break; 2867 2868 case OP_LITERAL: 2869 case OP_LABEL: 2870 default: 2871 return FALSE; 2872 } 2873 } 2874 if (!xg_instruction_matches_options (insn, rule->options)) 2875 return FALSE; 2876 2877 return TRUE; 2878 } 2879 2880 2881 static int 2882 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) 2883 { 2884 bfd_boolean a_greater = FALSE; 2885 bfd_boolean b_greater = FALSE; 2886 2887 ReqOptionList *l_a = a->options; 2888 ReqOptionList *l_b = b->options; 2889 2890 /* We only care if they both are the same except for 2891 a const16 vs. an l32r. */ 2892 2893 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2894 { 2895 ReqOrOptionList *l_or_a = l_a->or_option_terms; 2896 ReqOrOptionList *l_or_b = l_b->or_option_terms; 2897 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2898 { 2899 if (l_or_a->is_true != l_or_b->is_true) 2900 return 0; 2901 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) 2902 { 2903 /* This is the case we care about. */ 2904 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 2905 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) 2906 { 2907 if (prefer_const16) 2908 a_greater = TRUE; 2909 else 2910 b_greater = TRUE; 2911 } 2912 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 2913 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) 2914 { 2915 if (prefer_const16) 2916 b_greater = TRUE; 2917 else 2918 a_greater = TRUE; 2919 } 2920 else 2921 return 0; 2922 } 2923 l_or_a = l_or_a->next; 2924 l_or_b = l_or_b->next; 2925 } 2926 if (l_or_a || l_or_b) 2927 return 0; 2928 2929 l_a = l_a->next; 2930 l_b = l_b->next; 2931 } 2932 if (l_a || l_b) 2933 return 0; 2934 2935 /* Incomparable if the substitution was used differently in two cases. */ 2936 if (a_greater && b_greater) 2937 return 0; 2938 2939 if (b_greater) 2940 return 1; 2941 if (a_greater) 2942 return -1; 2943 2944 return 0; 2945 } 2946 2947 2948 static TransitionRule * 2949 xg_instruction_match (TInsn *insn) 2950 { 2951 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); 2952 TransitionList *l; 2953 assert (insn->opcode < table->num_opcodes); 2954 2955 /* Walk through all of the possible transitions. */ 2956 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 2957 { 2958 TransitionRule *rule = l->rule; 2959 if (xg_instruction_matches_rule (insn, rule)) 2960 return rule; 2961 } 2962 return NULL; 2963 } 2964 2965 2966 /* Various Other Internal Functions. */ 2967 2968 static bfd_boolean 2969 is_unique_insn_expansion (TransitionRule *r) 2970 { 2971 if (!r->to_instr || r->to_instr->next != NULL) 2972 return FALSE; 2973 if (r->to_instr->typ != INSTR_INSTR) 2974 return FALSE; 2975 return TRUE; 2976 } 2977 2978 2979 /* Check if there is exactly one relaxation for INSN that converts it to 2980 another instruction of equal or larger size. If so, and if TARG is 2981 non-null, go ahead and generate the relaxed instruction into TARG. If 2982 NARROW_ONLY is true, then only consider relaxations that widen a narrow 2983 instruction, i.e., ignore relaxations that convert to an instruction of 2984 equal size. In some contexts where this function is used, only 2985 a single widening is allowed and the NARROW_ONLY argument is used to 2986 exclude cases like ADDI being "widened" to an ADDMI, which may 2987 later be relaxed to an ADDMI/ADDI pair. */ 2988 2989 bfd_boolean 2990 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) 2991 { 2992 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 2993 TransitionList *l; 2994 TransitionRule *match = 0; 2995 2996 assert (insn->insn_type == ITYPE_INSN); 2997 assert (insn->opcode < table->num_opcodes); 2998 2999 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3000 { 3001 TransitionRule *rule = l->rule; 3002 3003 if (xg_instruction_matches_rule (insn, rule) 3004 && is_unique_insn_expansion (rule) 3005 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) 3006 <= xg_get_single_size (rule->to_instr->opcode))) 3007 { 3008 if (match) 3009 return FALSE; 3010 match = rule; 3011 } 3012 } 3013 if (!match) 3014 return FALSE; 3015 3016 if (targ) 3017 xg_build_to_insn (targ, insn, match->to_instr); 3018 return TRUE; 3019 } 3020 3021 3022 /* Return the maximum number of bytes this opcode can expand to. */ 3023 3024 static int 3025 xg_get_max_insn_widen_size (xtensa_opcode opcode) 3026 { 3027 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3028 TransitionList *l; 3029 int max_size = xg_get_single_size (opcode); 3030 3031 assert (opcode < table->num_opcodes); 3032 3033 for (l = table->table[opcode]; l != NULL; l = l->next) 3034 { 3035 TransitionRule *rule = l->rule; 3036 BuildInstr *build_list; 3037 int this_size = 0; 3038 3039 if (!rule) 3040 continue; 3041 build_list = rule->to_instr; 3042 if (is_unique_insn_expansion (rule)) 3043 { 3044 assert (build_list->typ == INSTR_INSTR); 3045 this_size = xg_get_max_insn_widen_size (build_list->opcode); 3046 } 3047 else 3048 for (; build_list != NULL; build_list = build_list->next) 3049 { 3050 switch (build_list->typ) 3051 { 3052 case INSTR_INSTR: 3053 this_size += xg_get_single_size (build_list->opcode); 3054 break; 3055 case INSTR_LITERAL_DEF: 3056 case INSTR_LABEL_DEF: 3057 default: 3058 break; 3059 } 3060 } 3061 if (this_size > max_size) 3062 max_size = this_size; 3063 } 3064 return max_size; 3065 } 3066 3067 3068 /* Return the maximum number of literal bytes this opcode can generate. */ 3069 3070 static int 3071 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) 3072 { 3073 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3074 TransitionList *l; 3075 int max_size = 0; 3076 3077 assert (opcode < table->num_opcodes); 3078 3079 for (l = table->table[opcode]; l != NULL; l = l->next) 3080 { 3081 TransitionRule *rule = l->rule; 3082 BuildInstr *build_list; 3083 int this_size = 0; 3084 3085 if (!rule) 3086 continue; 3087 build_list = rule->to_instr; 3088 if (is_unique_insn_expansion (rule)) 3089 { 3090 assert (build_list->typ == INSTR_INSTR); 3091 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); 3092 } 3093 else 3094 for (; build_list != NULL; build_list = build_list->next) 3095 { 3096 switch (build_list->typ) 3097 { 3098 case INSTR_LITERAL_DEF: 3099 /* Hard-coded 4-byte literal. */ 3100 this_size += 4; 3101 break; 3102 case INSTR_INSTR: 3103 case INSTR_LABEL_DEF: 3104 default: 3105 break; 3106 } 3107 } 3108 if (this_size > max_size) 3109 max_size = this_size; 3110 } 3111 return max_size; 3112 } 3113 3114 3115 static bfd_boolean 3116 xg_is_relaxable_insn (TInsn *insn, int lateral_steps) 3117 { 3118 int steps_taken = 0; 3119 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3120 TransitionList *l; 3121 3122 assert (insn->insn_type == ITYPE_INSN); 3123 assert (insn->opcode < table->num_opcodes); 3124 3125 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3126 { 3127 TransitionRule *rule = l->rule; 3128 3129 if (xg_instruction_matches_rule (insn, rule)) 3130 { 3131 if (steps_taken == lateral_steps) 3132 return TRUE; 3133 steps_taken++; 3134 } 3135 } 3136 return FALSE; 3137 } 3138 3139 3140 static symbolS * 3141 get_special_literal_symbol (void) 3142 { 3143 static symbolS *sym = NULL; 3144 3145 if (sym == NULL) 3146 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); 3147 return sym; 3148 } 3149 3150 3151 static symbolS * 3152 get_special_label_symbol (void) 3153 { 3154 static symbolS *sym = NULL; 3155 3156 if (sym == NULL) 3157 sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); 3158 return sym; 3159 } 3160 3161 3162 static bfd_boolean 3163 xg_valid_literal_expression (const expressionS *exp) 3164 { 3165 switch (exp->X_op) 3166 { 3167 case O_constant: 3168 case O_symbol: 3169 case O_big: 3170 case O_uminus: 3171 case O_subtract: 3172 case O_pltrel: 3173 case O_pcrel: 3174 case O_tlsfunc: 3175 case O_tlsarg: 3176 case O_tpoff: 3177 case O_dtpoff: 3178 return TRUE; 3179 default: 3180 return FALSE; 3181 } 3182 } 3183 3184 3185 /* This will check to see if the value can be converted into the 3186 operand type. It will return TRUE if it does not fit. */ 3187 3188 static bfd_boolean 3189 xg_check_operand (int32 value, xtensa_opcode opcode, int operand) 3190 { 3191 uint32 valbuf = value; 3192 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 3193 return TRUE; 3194 return FALSE; 3195 } 3196 3197 3198 /* Assumes: All immeds are constants. Check that all constants fit 3199 into their immeds; return FALSE if not. */ 3200 3201 static bfd_boolean 3202 xg_immeds_fit (const TInsn *insn) 3203 { 3204 xtensa_isa isa = xtensa_default_isa; 3205 int i; 3206 3207 int n = insn->ntok; 3208 assert (insn->insn_type == ITYPE_INSN); 3209 for (i = 0; i < n; ++i) 3210 { 3211 const expressionS *expr = &insn->tok[i]; 3212 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3213 continue; 3214 3215 switch (expr->X_op) 3216 { 3217 case O_register: 3218 case O_constant: 3219 if (xg_check_operand (expr->X_add_number, insn->opcode, i)) 3220 return FALSE; 3221 break; 3222 3223 default: 3224 /* The symbol should have a fixup associated with it. */ 3225 assert (FALSE); 3226 break; 3227 } 3228 } 3229 return TRUE; 3230 } 3231 3232 3233 /* This should only be called after we have an initial 3234 estimate of the addresses. */ 3235 3236 static bfd_boolean 3237 xg_symbolic_immeds_fit (const TInsn *insn, 3238 segT pc_seg, 3239 fragS *pc_frag, 3240 offsetT pc_offset, 3241 long stretch) 3242 { 3243 xtensa_isa isa = xtensa_default_isa; 3244 symbolS *symbolP; 3245 fragS *sym_frag; 3246 offsetT target, pc; 3247 uint32 new_offset; 3248 int i; 3249 int n = insn->ntok; 3250 3251 assert (insn->insn_type == ITYPE_INSN); 3252 3253 for (i = 0; i < n; ++i) 3254 { 3255 const expressionS *expr = &insn->tok[i]; 3256 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3257 continue; 3258 3259 switch (expr->X_op) 3260 { 3261 case O_register: 3262 case O_constant: 3263 if (xg_check_operand (expr->X_add_number, insn->opcode, i)) 3264 return FALSE; 3265 break; 3266 3267 case O_lo16: 3268 case O_hi16: 3269 /* Check for the worst case. */ 3270 if (xg_check_operand (0xffff, insn->opcode, i)) 3271 return FALSE; 3272 break; 3273 3274 case O_symbol: 3275 /* We only allow symbols for PC-relative references. 3276 If pc_frag == 0, then we don't have frag locations yet. */ 3277 if (pc_frag == 0 3278 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) 3279 return FALSE; 3280 3281 /* If it is a weak symbol or a symbol in a different section, 3282 it cannot be known to fit at assembly time. */ 3283 if (S_IS_WEAK (expr->X_add_symbol) 3284 || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) 3285 { 3286 /* For a direct call with --no-longcalls, be optimistic and 3287 assume it will be in range. If the symbol is weak and 3288 undefined, it may remain undefined at link-time, in which 3289 case it will have a zero value and almost certainly be out 3290 of range for a direct call; thus, relax for undefined weak 3291 symbols even if longcalls is not enabled. */ 3292 if (is_direct_call_opcode (insn->opcode) 3293 && ! pc_frag->tc_frag_data.use_longcalls 3294 && (! S_IS_WEAK (expr->X_add_symbol) 3295 || S_IS_DEFINED (expr->X_add_symbol))) 3296 return TRUE; 3297 3298 return FALSE; 3299 } 3300 3301 symbolP = expr->X_add_symbol; 3302 sym_frag = symbol_get_frag (symbolP); 3303 target = S_GET_VALUE (symbolP) + expr->X_add_number; 3304 pc = pc_frag->fr_address + pc_offset; 3305 3306 /* If frag has yet to be reached on this pass, assume it 3307 will move by STRETCH just as we did. If this is not so, 3308 it will be because some frag between grows, and that will 3309 force another pass. Beware zero-length frags. There 3310 should be a faster way to do this. */ 3311 3312 if (stretch != 0 3313 && sym_frag->relax_marker != pc_frag->relax_marker 3314 && S_GET_SEGMENT (symbolP) == pc_seg) 3315 { 3316 target += stretch; 3317 } 3318 3319 new_offset = target; 3320 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); 3321 if (xg_check_operand (new_offset, insn->opcode, i)) 3322 return FALSE; 3323 break; 3324 3325 default: 3326 /* The symbol should have a fixup associated with it. */ 3327 return FALSE; 3328 } 3329 } 3330 3331 return TRUE; 3332 } 3333 3334 3335 /* Return TRUE on success. */ 3336 3337 static bfd_boolean 3338 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) 3339 { 3340 BuildOp *op; 3341 symbolS *sym; 3342 3343 tinsn_init (targ); 3344 targ->debug_line = insn->debug_line; 3345 targ->loc_directive_seen = insn->loc_directive_seen; 3346 switch (bi->typ) 3347 { 3348 case INSTR_INSTR: 3349 op = bi->ops; 3350 targ->opcode = bi->opcode; 3351 targ->insn_type = ITYPE_INSN; 3352 targ->is_specific_opcode = FALSE; 3353 3354 for (; op != NULL; op = op->next) 3355 { 3356 int op_num = op->op_num; 3357 int op_data = op->op_data; 3358 3359 assert (op->op_num < MAX_INSN_ARGS); 3360 3361 if (targ->ntok <= op_num) 3362 targ->ntok = op_num + 1; 3363 3364 switch (op->typ) 3365 { 3366 case OP_CONSTANT: 3367 set_expr_const (&targ->tok[op_num], op_data); 3368 break; 3369 case OP_OPERAND: 3370 assert (op_data < insn->ntok); 3371 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3372 break; 3373 case OP_LITERAL: 3374 sym = get_special_literal_symbol (); 3375 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3376 if (insn->tok[op_data].X_op == O_tlsfunc 3377 || insn->tok[op_data].X_op == O_tlsarg) 3378 copy_expr (&targ->tls_reloc, &insn->tok[op_data]); 3379 break; 3380 case OP_LABEL: 3381 sym = get_special_label_symbol (); 3382 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3383 break; 3384 case OP_OPERAND_HI16U: 3385 case OP_OPERAND_LOW16U: 3386 assert (op_data < insn->ntok); 3387 if (expr_is_const (&insn->tok[op_data])) 3388 { 3389 long val; 3390 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3391 val = xg_apply_userdef_op_fn (op->typ, 3392 targ->tok[op_num]. 3393 X_add_number); 3394 targ->tok[op_num].X_add_number = val; 3395 } 3396 else 3397 { 3398 /* For const16 we can create relocations for these. */ 3399 if (targ->opcode == XTENSA_UNDEFINED 3400 || (targ->opcode != xtensa_const16_opcode)) 3401 return FALSE; 3402 assert (op_data < insn->ntok); 3403 /* Need to build a O_lo16 or O_hi16. */ 3404 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3405 if (targ->tok[op_num].X_op == O_symbol) 3406 { 3407 if (op->typ == OP_OPERAND_HI16U) 3408 targ->tok[op_num].X_op = O_hi16; 3409 else if (op->typ == OP_OPERAND_LOW16U) 3410 targ->tok[op_num].X_op = O_lo16; 3411 else 3412 return FALSE; 3413 } 3414 } 3415 break; 3416 default: 3417 /* currently handles: 3418 OP_OPERAND_LOW8 3419 OP_OPERAND_HI24S 3420 OP_OPERAND_F32MINUS */ 3421 if (xg_has_userdef_op_fn (op->typ)) 3422 { 3423 assert (op_data < insn->ntok); 3424 if (expr_is_const (&insn->tok[op_data])) 3425 { 3426 long val; 3427 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3428 val = xg_apply_userdef_op_fn (op->typ, 3429 targ->tok[op_num]. 3430 X_add_number); 3431 targ->tok[op_num].X_add_number = val; 3432 } 3433 else 3434 return FALSE; /* We cannot use a relocation for this. */ 3435 break; 3436 } 3437 assert (0); 3438 break; 3439 } 3440 } 3441 break; 3442 3443 case INSTR_LITERAL_DEF: 3444 op = bi->ops; 3445 targ->opcode = XTENSA_UNDEFINED; 3446 targ->insn_type = ITYPE_LITERAL; 3447 targ->is_specific_opcode = FALSE; 3448 for (; op != NULL; op = op->next) 3449 { 3450 int op_num = op->op_num; 3451 int op_data = op->op_data; 3452 assert (op->op_num < MAX_INSN_ARGS); 3453 3454 if (targ->ntok <= op_num) 3455 targ->ntok = op_num + 1; 3456 3457 switch (op->typ) 3458 { 3459 case OP_OPERAND: 3460 assert (op_data < insn->ntok); 3461 /* We can only pass resolvable literals through. */ 3462 if (!xg_valid_literal_expression (&insn->tok[op_data])) 3463 return FALSE; 3464 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3465 break; 3466 case OP_LITERAL: 3467 case OP_CONSTANT: 3468 case OP_LABEL: 3469 default: 3470 assert (0); 3471 break; 3472 } 3473 } 3474 break; 3475 3476 case INSTR_LABEL_DEF: 3477 op = bi->ops; 3478 targ->opcode = XTENSA_UNDEFINED; 3479 targ->insn_type = ITYPE_LABEL; 3480 targ->is_specific_opcode = FALSE; 3481 /* Literal with no ops is a label? */ 3482 assert (op == NULL); 3483 break; 3484 3485 default: 3486 assert (0); 3487 } 3488 3489 return TRUE; 3490 } 3491 3492 3493 /* Return TRUE on success. */ 3494 3495 static bfd_boolean 3496 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) 3497 { 3498 for (; bi != NULL; bi = bi->next) 3499 { 3500 TInsn *next_insn = istack_push_space (istack); 3501 3502 if (!xg_build_to_insn (next_insn, insn, bi)) 3503 return FALSE; 3504 } 3505 return TRUE; 3506 } 3507 3508 3509 /* Return TRUE on valid expansion. */ 3510 3511 static bfd_boolean 3512 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) 3513 { 3514 int stack_size = istack->ninsn; 3515 int steps_taken = 0; 3516 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3517 TransitionList *l; 3518 3519 assert (insn->insn_type == ITYPE_INSN); 3520 assert (insn->opcode < table->num_opcodes); 3521 3522 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3523 { 3524 TransitionRule *rule = l->rule; 3525 3526 if (xg_instruction_matches_rule (insn, rule)) 3527 { 3528 if (lateral_steps == steps_taken) 3529 { 3530 int i; 3531 3532 /* This is it. Expand the rule to the stack. */ 3533 if (!xg_build_to_stack (istack, insn, rule->to_instr)) 3534 return FALSE; 3535 3536 /* Check to see if it fits. */ 3537 for (i = stack_size; i < istack->ninsn; i++) 3538 { 3539 TInsn *insn = &istack->insn[i]; 3540 3541 if (insn->insn_type == ITYPE_INSN 3542 && !tinsn_has_symbolic_operands (insn) 3543 && !xg_immeds_fit (insn)) 3544 { 3545 istack->ninsn = stack_size; 3546 return FALSE; 3547 } 3548 } 3549 return TRUE; 3550 } 3551 steps_taken++; 3552 } 3553 } 3554 return FALSE; 3555 } 3556 3557 3558 /* Relax the assembly instruction at least "min_steps". 3559 Return the number of steps taken. 3560 3561 For relaxation to correctly terminate, every relaxation chain must 3562 terminate in one of two ways: 3563 3564 1. If the chain from one instruction to the next consists entirely of 3565 single instructions, then the chain *must* handle all possible 3566 immediates without failing. It must not ever fail because an 3567 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation 3568 chain is one example. L32R loads 32 bits, and there cannot be an 3569 immediate larger than 32 bits, so it satisfies this condition. 3570 Single instruction relaxation chains are as defined by 3571 xg_is_single_relaxable_instruction. 3572 3573 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., 3574 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J 3575 3576 Strictly speaking, in most cases you can violate condition 1 and be OK 3577 -- in particular when the last two instructions have the same single 3578 size. But nevertheless, you should guarantee the above two conditions. 3579 3580 We could fix this so that single-instruction expansions correctly 3581 terminate when they can't handle the range, but the error messages are 3582 worse, and it actually turns out that in every case but one (18-bit wide 3583 branches), you need a multi-instruction expansion to get the full range 3584 anyway. And because 18-bit branches are handled identically to 15-bit 3585 branches, there isn't any point in changing it. */ 3586 3587 static int 3588 xg_assembly_relax (IStack *istack, 3589 TInsn *insn, 3590 segT pc_seg, 3591 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ 3592 offsetT pc_offset, /* offset in fragment */ 3593 int min_steps, /* minimum conversion steps */ 3594 long stretch) /* number of bytes stretched so far */ 3595 { 3596 int steps_taken = 0; 3597 3598 /* Some of its immeds don't fit. Try to build a relaxed version. 3599 This may go through a couple of stages of single instruction 3600 transformations before we get there. */ 3601 3602 TInsn single_target; 3603 TInsn current_insn; 3604 int lateral_steps = 0; 3605 int istack_size = istack->ninsn; 3606 3607 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) 3608 && steps_taken >= min_steps) 3609 { 3610 istack_push (istack, insn); 3611 return steps_taken; 3612 } 3613 current_insn = *insn; 3614 3615 /* Walk through all of the single instruction expansions. */ 3616 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) 3617 { 3618 steps_taken++; 3619 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, 3620 stretch)) 3621 { 3622 if (steps_taken >= min_steps) 3623 { 3624 istack_push (istack, &single_target); 3625 return steps_taken; 3626 } 3627 } 3628 current_insn = single_target; 3629 } 3630 3631 /* Now check for a multi-instruction expansion. */ 3632 while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) 3633 { 3634 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, 3635 stretch)) 3636 { 3637 if (steps_taken >= min_steps) 3638 { 3639 istack_push (istack, ¤t_insn); 3640 return steps_taken; 3641 } 3642 } 3643 steps_taken++; 3644 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) 3645 { 3646 if (steps_taken >= min_steps) 3647 return steps_taken; 3648 } 3649 lateral_steps++; 3650 istack->ninsn = istack_size; 3651 } 3652 3653 /* It's not going to work -- use the original. */ 3654 istack_push (istack, insn); 3655 return steps_taken; 3656 } 3657 3658 3659 static void 3660 xg_finish_frag (char *last_insn, 3661 enum xtensa_relax_statesE frag_state, 3662 enum xtensa_relax_statesE slot0_state, 3663 int max_growth, 3664 bfd_boolean is_insn) 3665 { 3666 /* Finish off this fragment so that it has at LEAST the desired 3667 max_growth. If it doesn't fit in this fragment, close this one 3668 and start a new one. In either case, return a pointer to the 3669 beginning of the growth area. */ 3670 3671 fragS *old_frag; 3672 3673 frag_grow (max_growth); 3674 old_frag = frag_now; 3675 3676 frag_now->fr_opcode = last_insn; 3677 if (is_insn) 3678 frag_now->tc_frag_data.is_insn = TRUE; 3679 3680 frag_var (rs_machine_dependent, max_growth, max_growth, 3681 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); 3682 3683 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; 3684 xtensa_set_frag_assembly_state (frag_now); 3685 3686 /* Just to make sure that we did not split it up. */ 3687 assert (old_frag->fr_next == frag_now); 3688 } 3689 3690 3691 /* Return TRUE if the target frag is one of the next non-empty frags. */ 3692 3693 static bfd_boolean 3694 is_next_frag_target (const fragS *fragP, const fragS *target) 3695 { 3696 if (fragP == NULL) 3697 return FALSE; 3698 3699 for (; fragP; fragP = fragP->fr_next) 3700 { 3701 if (fragP == target) 3702 return TRUE; 3703 if (fragP->fr_fix != 0) 3704 return FALSE; 3705 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) 3706 return FALSE; 3707 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) 3708 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) 3709 return FALSE; 3710 if (fragP->fr_type == rs_space) 3711 return FALSE; 3712 } 3713 return FALSE; 3714 } 3715 3716 3717 static bfd_boolean 3718 is_branch_jmp_to_next (TInsn *insn, fragS *fragP) 3719 { 3720 xtensa_isa isa = xtensa_default_isa; 3721 int i; 3722 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3723 int target_op = -1; 3724 symbolS *sym; 3725 fragS *target_frag; 3726 3727 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 3728 && xtensa_opcode_is_jump (isa, insn->opcode) != 1) 3729 return FALSE; 3730 3731 for (i = 0; i < num_ops; i++) 3732 { 3733 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) 3734 { 3735 target_op = i; 3736 break; 3737 } 3738 } 3739 if (target_op == -1) 3740 return FALSE; 3741 3742 if (insn->ntok <= target_op) 3743 return FALSE; 3744 3745 if (insn->tok[target_op].X_op != O_symbol) 3746 return FALSE; 3747 3748 sym = insn->tok[target_op].X_add_symbol; 3749 if (sym == NULL) 3750 return FALSE; 3751 3752 if (insn->tok[target_op].X_add_number != 0) 3753 return FALSE; 3754 3755 target_frag = symbol_get_frag (sym); 3756 if (target_frag == NULL) 3757 return FALSE; 3758 3759 if (is_next_frag_target (fragP->fr_next, target_frag) 3760 && S_GET_VALUE (sym) == target_frag->fr_address) 3761 return TRUE; 3762 3763 return FALSE; 3764 } 3765 3766 3767 static void 3768 xg_add_branch_and_loop_targets (TInsn *insn) 3769 { 3770 xtensa_isa isa = xtensa_default_isa; 3771 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3772 3773 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3774 { 3775 int i = 1; 3776 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3777 && insn->tok[i].X_op == O_symbol) 3778 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; 3779 return; 3780 } 3781 3782 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 3783 || xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3784 { 3785 int i; 3786 3787 for (i = 0; i < insn->ntok && i < num_ops; i++) 3788 { 3789 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3790 && insn->tok[i].X_op == O_symbol) 3791 { 3792 symbolS *sym = insn->tok[i].X_add_symbol; 3793 symbol_get_tc (sym)->is_branch_target = TRUE; 3794 if (S_IS_DEFINED (sym)) 3795 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 3796 } 3797 } 3798 } 3799 } 3800 3801 3802 /* Return FALSE if no error. */ 3803 3804 static bfd_boolean 3805 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) 3806 { 3807 int num_ops = 0; 3808 BuildOp *b_op; 3809 3810 switch (instr_spec->typ) 3811 { 3812 case INSTR_INSTR: 3813 new_insn->insn_type = ITYPE_INSN; 3814 new_insn->opcode = instr_spec->opcode; 3815 break; 3816 case INSTR_LITERAL_DEF: 3817 new_insn->insn_type = ITYPE_LITERAL; 3818 new_insn->opcode = XTENSA_UNDEFINED; 3819 break; 3820 case INSTR_LABEL_DEF: 3821 abort (); 3822 } 3823 new_insn->is_specific_opcode = FALSE; 3824 new_insn->debug_line = old_insn->debug_line; 3825 new_insn->loc_directive_seen = old_insn->loc_directive_seen; 3826 3827 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) 3828 { 3829 expressionS *exp; 3830 const expressionS *src_exp; 3831 3832 num_ops++; 3833 switch (b_op->typ) 3834 { 3835 case OP_CONSTANT: 3836 /* The expression must be the constant. */ 3837 assert (b_op->op_num < MAX_INSN_ARGS); 3838 exp = &new_insn->tok[b_op->op_num]; 3839 set_expr_const (exp, b_op->op_data); 3840 break; 3841 3842 case OP_OPERAND: 3843 assert (b_op->op_num < MAX_INSN_ARGS); 3844 assert (b_op->op_data < (unsigned) old_insn->ntok); 3845 src_exp = &old_insn->tok[b_op->op_data]; 3846 exp = &new_insn->tok[b_op->op_num]; 3847 copy_expr (exp, src_exp); 3848 break; 3849 3850 case OP_LITERAL: 3851 case OP_LABEL: 3852 as_bad (_("can't handle generation of literal/labels yet")); 3853 assert (0); 3854 3855 default: 3856 as_bad (_("can't handle undefined OP TYPE")); 3857 assert (0); 3858 } 3859 } 3860 3861 new_insn->ntok = num_ops; 3862 return FALSE; 3863 } 3864 3865 3866 /* Return TRUE if it was simplified. */ 3867 3868 static bfd_boolean 3869 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) 3870 { 3871 TransitionRule *rule; 3872 BuildInstr *insn_spec; 3873 3874 if (old_insn->is_specific_opcode || !density_supported) 3875 return FALSE; 3876 3877 rule = xg_instruction_match (old_insn); 3878 if (rule == NULL) 3879 return FALSE; 3880 3881 insn_spec = rule->to_instr; 3882 /* There should only be one. */ 3883 assert (insn_spec != NULL); 3884 assert (insn_spec->next == NULL); 3885 if (insn_spec->next != NULL) 3886 return FALSE; 3887 3888 xg_build_token_insn (insn_spec, old_insn, new_insn); 3889 3890 return TRUE; 3891 } 3892 3893 3894 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> 3895 l32i.n. (2) Check the number of operands. (3) Place the instruction 3896 tokens into the stack or relax it and place multiple 3897 instructions/literals onto the stack. Return FALSE if no error. */ 3898 3899 static bfd_boolean 3900 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) 3901 { 3902 int noperands; 3903 TInsn new_insn; 3904 bfd_boolean do_expand; 3905 3906 tinsn_init (&new_insn); 3907 3908 /* Narrow it if we can. xg_simplify_insn now does all the 3909 appropriate checking (e.g., for the density option). */ 3910 if (xg_simplify_insn (orig_insn, &new_insn)) 3911 orig_insn = &new_insn; 3912 3913 noperands = xtensa_opcode_num_operands (xtensa_default_isa, 3914 orig_insn->opcode); 3915 if (orig_insn->ntok < noperands) 3916 { 3917 as_bad (_("found %d operands for '%s': Expected %d"), 3918 orig_insn->ntok, 3919 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3920 noperands); 3921 return TRUE; 3922 } 3923 if (orig_insn->ntok > noperands) 3924 as_warn (_("found too many (%d) operands for '%s': Expected %d"), 3925 orig_insn->ntok, 3926 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3927 noperands); 3928 3929 /* If there are not enough operands, we will assert above. If there 3930 are too many, just cut out the extras here. */ 3931 orig_insn->ntok = noperands; 3932 3933 if (tinsn_has_invalid_symbolic_operands (orig_insn)) 3934 return TRUE; 3935 3936 /* Special case for extui opcode which has constraints not handled 3937 by the ordinary operand encoding checks. The number of operands 3938 and related syntax issues have already been checked. */ 3939 if (orig_insn->opcode == xtensa_extui_opcode) 3940 { 3941 int shiftimm = orig_insn->tok[2].X_add_number; 3942 int maskimm = orig_insn->tok[3].X_add_number; 3943 if (shiftimm + maskimm > 32) 3944 { 3945 as_bad (_("immediate operands sum to greater than 32")); 3946 return TRUE; 3947 } 3948 } 3949 3950 /* If the instruction will definitely need to be relaxed, it is better 3951 to expand it now for better scheduling. Decide whether to expand 3952 now.... */ 3953 do_expand = (!orig_insn->is_specific_opcode && use_transform ()); 3954 3955 /* Calls should be expanded to longcalls only in the backend relaxation 3956 so that the assembly scheduler will keep the L32R/CALLX instructions 3957 adjacent. */ 3958 if (is_direct_call_opcode (orig_insn->opcode)) 3959 do_expand = FALSE; 3960 3961 if (tinsn_has_symbolic_operands (orig_insn)) 3962 { 3963 /* The values of symbolic operands are not known yet, so only expand 3964 now if an operand is "complex" (e.g., difference of symbols) and 3965 will have to be stored as a literal regardless of the value. */ 3966 if (!tinsn_has_complex_operands (orig_insn)) 3967 do_expand = FALSE; 3968 } 3969 else if (xg_immeds_fit (orig_insn)) 3970 do_expand = FALSE; 3971 3972 if (do_expand) 3973 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); 3974 else 3975 istack_push (istack, orig_insn); 3976 3977 return FALSE; 3978 } 3979 3980 3981 /* Return TRUE if the section flags are marked linkonce 3982 or the name is .gnu.linkonce.*. */ 3983 3984 static int linkonce_len = sizeof (".gnu.linkonce.") - 1; 3985 3986 static bfd_boolean 3987 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) 3988 { 3989 flagword flags, link_once_flags; 3990 3991 flags = bfd_get_section_flags (abfd, sec); 3992 link_once_flags = (flags & SEC_LINK_ONCE); 3993 3994 /* Flags might not be set yet. */ 3995 if (!link_once_flags 3996 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) 3997 link_once_flags = SEC_LINK_ONCE; 3998 3999 return (link_once_flags != 0); 4000 } 4001 4002 4003 static void 4004 xtensa_add_literal_sym (symbolS *sym) 4005 { 4006 sym_list *l; 4007 4008 l = (sym_list *) xmalloc (sizeof (sym_list)); 4009 l->sym = sym; 4010 l->next = literal_syms; 4011 literal_syms = l; 4012 } 4013 4014 4015 static symbolS * 4016 xtensa_create_literal_symbol (segT sec, fragS *frag) 4017 { 4018 static int lit_num = 0; 4019 static char name[256]; 4020 symbolS *symbolP; 4021 4022 sprintf (name, ".L_lit_sym%d", lit_num); 4023 4024 /* Create a local symbol. If it is in a linkonce section, we have to 4025 be careful to make sure that if it is used in a relocation that the 4026 symbol will be in the output file. */ 4027 if (get_is_linkonce_section (stdoutput, sec)) 4028 { 4029 symbolP = symbol_new (name, sec, 0, frag); 4030 S_CLEAR_EXTERNAL (symbolP); 4031 /* symbolP->local = 1; */ 4032 } 4033 else 4034 symbolP = symbol_new (name, sec, 0, frag); 4035 4036 xtensa_add_literal_sym (symbolP); 4037 4038 lit_num++; 4039 return symbolP; 4040 } 4041 4042 4043 /* Currently all literals that are generated here are 32-bit L32R targets. */ 4044 4045 static symbolS * 4046 xg_assemble_literal (/* const */ TInsn *insn) 4047 { 4048 emit_state state; 4049 symbolS *lit_sym = NULL; 4050 bfd_reloc_code_real_type reloc; 4051 bfd_boolean pcrel = FALSE; 4052 char *p; 4053 4054 /* size = 4 for L32R. It could easily be larger when we move to 4055 larger constants. Add a parameter later. */ 4056 offsetT litsize = 4; 4057 offsetT litalign = 2; /* 2^2 = 4 */ 4058 expressionS saved_loc; 4059 expressionS * emit_val; 4060 4061 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); 4062 4063 assert (insn->insn_type == ITYPE_LITERAL); 4064 assert (insn->ntok == 1); /* must be only one token here */ 4065 4066 xtensa_switch_to_literal_fragment (&state); 4067 4068 emit_val = &insn->tok[0]; 4069 if (emit_val->X_op == O_big) 4070 { 4071 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; 4072 if (size > litsize) 4073 { 4074 /* This happens when someone writes a "movi a2, big_number". */ 4075 as_bad_where (frag_now->fr_file, frag_now->fr_line, 4076 _("invalid immediate")); 4077 xtensa_restore_emit_state (&state); 4078 return NULL; 4079 } 4080 } 4081 4082 /* Force a 4-byte align here. Note that this opens a new frag, so all 4083 literals done with this function have a frag to themselves. That's 4084 important for the way text section literals work. */ 4085 frag_align (litalign, 0, 0); 4086 record_alignment (now_seg, litalign); 4087 4088 switch (emit_val->X_op) 4089 { 4090 case O_pcrel: 4091 pcrel = TRUE; 4092 /* fall through */ 4093 case O_pltrel: 4094 case O_tlsfunc: 4095 case O_tlsarg: 4096 case O_tpoff: 4097 case O_dtpoff: 4098 p = frag_more (litsize); 4099 xtensa_set_frag_assembly_state (frag_now); 4100 reloc = map_operator_to_reloc (emit_val->X_op, TRUE); 4101 if (emit_val->X_add_symbol) 4102 emit_val->X_op = O_symbol; 4103 else 4104 emit_val->X_op = O_constant; 4105 fix_new_exp (frag_now, p - frag_now->fr_literal, 4106 litsize, emit_val, pcrel, reloc); 4107 break; 4108 4109 default: 4110 emit_expr (emit_val, litsize); 4111 break; 4112 } 4113 4114 assert (frag_now->tc_frag_data.literal_frag == NULL); 4115 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4116 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4117 lit_sym = frag_now->fr_symbol; 4118 4119 /* Go back. */ 4120 xtensa_restore_emit_state (&state); 4121 return lit_sym; 4122 } 4123 4124 4125 static void 4126 xg_assemble_literal_space (/* const */ int size, int slot) 4127 { 4128 emit_state state; 4129 /* We might have to do something about this alignment. It only 4130 takes effect if something is placed here. */ 4131 offsetT litalign = 2; /* 2^2 = 4 */ 4132 fragS *lit_saved_frag; 4133 4134 assert (size % 4 == 0); 4135 4136 xtensa_switch_to_literal_fragment (&state); 4137 4138 /* Force a 4-byte align here. */ 4139 frag_align (litalign, 0, 0); 4140 record_alignment (now_seg, litalign); 4141 4142 frag_grow (size); 4143 4144 lit_saved_frag = frag_now; 4145 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4146 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4147 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); 4148 4149 /* Go back. */ 4150 xtensa_restore_emit_state (&state); 4151 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; 4152 } 4153 4154 4155 /* Put in a fixup record based on the opcode. 4156 Return TRUE on success. */ 4157 4158 static bfd_boolean 4159 xg_add_opcode_fix (TInsn *tinsn, 4160 int opnum, 4161 xtensa_format fmt, 4162 int slot, 4163 expressionS *expr, 4164 fragS *fragP, 4165 offsetT offset) 4166 { 4167 xtensa_opcode opcode = tinsn->opcode; 4168 bfd_reloc_code_real_type reloc; 4169 reloc_howto_type *howto; 4170 int fmt_length; 4171 fixS *the_fix; 4172 4173 reloc = BFD_RELOC_NONE; 4174 4175 /* First try the special cases for "alternate" relocs. */ 4176 if (opcode == xtensa_l32r_opcode) 4177 { 4178 if (fragP->tc_frag_data.use_absolute_literals) 4179 reloc = encode_alt_reloc (slot); 4180 } 4181 else if (opcode == xtensa_const16_opcode) 4182 { 4183 if (expr->X_op == O_lo16) 4184 { 4185 reloc = encode_reloc (slot); 4186 expr->X_op = O_symbol; 4187 } 4188 else if (expr->X_op == O_hi16) 4189 { 4190 reloc = encode_alt_reloc (slot); 4191 expr->X_op = O_symbol; 4192 } 4193 } 4194 4195 if (opnum != get_relaxable_immed (opcode)) 4196 { 4197 as_bad (_("invalid relocation for operand %i of '%s'"), 4198 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4199 return FALSE; 4200 } 4201 4202 /* Handle erroneous "@h" and "@l" expressions here before they propagate 4203 into the symbol table where the generic portions of the assembler 4204 won't know what to do with them. */ 4205 if (expr->X_op == O_lo16 || expr->X_op == O_hi16) 4206 { 4207 as_bad (_("invalid expression for operand %i of '%s'"), 4208 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4209 return FALSE; 4210 } 4211 4212 /* Next try the generic relocs. */ 4213 if (reloc == BFD_RELOC_NONE) 4214 reloc = encode_reloc (slot); 4215 if (reloc == BFD_RELOC_NONE) 4216 { 4217 as_bad (_("invalid relocation in instruction slot %i"), slot); 4218 return FALSE; 4219 } 4220 4221 howto = bfd_reloc_type_lookup (stdoutput, reloc); 4222 if (!howto) 4223 { 4224 as_bad (_("undefined symbol for opcode \"%s\""), 4225 xtensa_opcode_name (xtensa_default_isa, opcode)); 4226 return FALSE; 4227 } 4228 4229 fmt_length = xtensa_format_length (xtensa_default_isa, fmt); 4230 the_fix = fix_new_exp (fragP, offset, fmt_length, expr, 4231 howto->pc_relative, reloc); 4232 the_fix->fx_no_overflow = 1; 4233 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; 4234 the_fix->tc_fix_data.X_add_number = expr->X_add_number; 4235 the_fix->tc_fix_data.slot = slot; 4236 4237 return TRUE; 4238 } 4239 4240 4241 static bfd_boolean 4242 xg_emit_insn_to_buf (TInsn *tinsn, 4243 char *buf, 4244 fragS *fragP, 4245 offsetT offset, 4246 bfd_boolean build_fix) 4247 { 4248 static xtensa_insnbuf insnbuf = NULL; 4249 bfd_boolean has_symbolic_immed = FALSE; 4250 bfd_boolean ok = TRUE; 4251 4252 if (!insnbuf) 4253 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4254 4255 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); 4256 if (has_symbolic_immed && build_fix) 4257 { 4258 /* Add a fixup. */ 4259 xtensa_format fmt = xg_get_single_format (tinsn->opcode); 4260 int slot = xg_get_single_slot (tinsn->opcode); 4261 int opnum = get_relaxable_immed (tinsn->opcode); 4262 expressionS *exp = &tinsn->tok[opnum]; 4263 4264 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) 4265 ok = FALSE; 4266 } 4267 fragP->tc_frag_data.is_insn = TRUE; 4268 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4269 (unsigned char *) buf, 0); 4270 return ok; 4271 } 4272 4273 4274 static void 4275 xg_resolve_literals (TInsn *insn, symbolS *lit_sym) 4276 { 4277 symbolS *sym = get_special_literal_symbol (); 4278 int i; 4279 if (lit_sym == 0) 4280 return; 4281 assert (insn->insn_type == ITYPE_INSN); 4282 for (i = 0; i < insn->ntok; i++) 4283 if (insn->tok[i].X_add_symbol == sym) 4284 insn->tok[i].X_add_symbol = lit_sym; 4285 4286 } 4287 4288 4289 static void 4290 xg_resolve_labels (TInsn *insn, symbolS *label_sym) 4291 { 4292 symbolS *sym = get_special_label_symbol (); 4293 int i; 4294 for (i = 0; i < insn->ntok; i++) 4295 if (insn->tok[i].X_add_symbol == sym) 4296 insn->tok[i].X_add_symbol = label_sym; 4297 4298 } 4299 4300 4301 /* Return TRUE if the instruction can write to the specified 4302 integer register. */ 4303 4304 static bfd_boolean 4305 is_register_writer (const TInsn *insn, const char *regset, int regnum) 4306 { 4307 int i; 4308 int num_ops; 4309 xtensa_isa isa = xtensa_default_isa; 4310 4311 num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 4312 4313 for (i = 0; i < num_ops; i++) 4314 { 4315 char inout; 4316 inout = xtensa_operand_inout (isa, insn->opcode, i); 4317 if ((inout == 'o' || inout == 'm') 4318 && xtensa_operand_is_register (isa, insn->opcode, i) == 1) 4319 { 4320 xtensa_regfile opnd_rf = 4321 xtensa_operand_regfile (isa, insn->opcode, i); 4322 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) 4323 { 4324 if ((insn->tok[i].X_op == O_register) 4325 && (insn->tok[i].X_add_number == regnum)) 4326 return TRUE; 4327 } 4328 } 4329 } 4330 return FALSE; 4331 } 4332 4333 4334 static bfd_boolean 4335 is_bad_loopend_opcode (const TInsn *tinsn) 4336 { 4337 xtensa_opcode opcode = tinsn->opcode; 4338 4339 if (opcode == XTENSA_UNDEFINED) 4340 return FALSE; 4341 4342 if (opcode == xtensa_call0_opcode 4343 || opcode == xtensa_callx0_opcode 4344 || opcode == xtensa_call4_opcode 4345 || opcode == xtensa_callx4_opcode 4346 || opcode == xtensa_call8_opcode 4347 || opcode == xtensa_callx8_opcode 4348 || opcode == xtensa_call12_opcode 4349 || opcode == xtensa_callx12_opcode 4350 || opcode == xtensa_isync_opcode 4351 || opcode == xtensa_ret_opcode 4352 || opcode == xtensa_ret_n_opcode 4353 || opcode == xtensa_retw_opcode 4354 || opcode == xtensa_retw_n_opcode 4355 || opcode == xtensa_waiti_opcode 4356 || opcode == xtensa_rsr_lcount_opcode) 4357 return TRUE; 4358 4359 return FALSE; 4360 } 4361 4362 4363 /* Labels that begin with ".Ln" or ".LM" are unaligned. 4364 This allows the debugger to add unaligned labels. 4365 Also, the assembler generates stabs labels that need 4366 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ 4367 4368 static bfd_boolean 4369 is_unaligned_label (symbolS *sym) 4370 { 4371 const char *name = S_GET_NAME (sym); 4372 static size_t fake_size = 0; 4373 4374 if (name 4375 && name[0] == '.' 4376 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) 4377 return TRUE; 4378 4379 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ 4380 if (fake_size == 0) 4381 fake_size = strlen (FAKE_LABEL_NAME); 4382 4383 if (name 4384 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 4385 && (name[fake_size] == 'F' 4386 || name[fake_size] == 'L' 4387 || (name[fake_size] == 'e' 4388 && strncmp ("endfunc", name+fake_size, 7) == 0))) 4389 return TRUE; 4390 4391 return FALSE; 4392 } 4393 4394 4395 static fragS * 4396 next_non_empty_frag (const fragS *fragP) 4397 { 4398 fragS *next_fragP = fragP->fr_next; 4399 4400 /* Sometimes an empty will end up here due storage allocation issues. 4401 So we have to skip until we find something legit. */ 4402 while (next_fragP && next_fragP->fr_fix == 0) 4403 next_fragP = next_fragP->fr_next; 4404 4405 if (next_fragP == NULL || next_fragP->fr_fix == 0) 4406 return NULL; 4407 4408 return next_fragP; 4409 } 4410 4411 4412 static bfd_boolean 4413 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) 4414 { 4415 xtensa_opcode out_opcode; 4416 const fragS *next_fragP = next_non_empty_frag (fragP); 4417 4418 if (next_fragP == NULL) 4419 return FALSE; 4420 4421 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); 4422 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) 4423 { 4424 *opcode = out_opcode; 4425 return TRUE; 4426 } 4427 return FALSE; 4428 } 4429 4430 4431 static int 4432 frag_format_size (const fragS *fragP) 4433 { 4434 static xtensa_insnbuf insnbuf = NULL; 4435 xtensa_isa isa = xtensa_default_isa; 4436 xtensa_format fmt; 4437 int fmt_size; 4438 4439 if (!insnbuf) 4440 insnbuf = xtensa_insnbuf_alloc (isa); 4441 4442 if (fragP == NULL) 4443 return XTENSA_UNDEFINED; 4444 4445 xtensa_insnbuf_from_chars (isa, insnbuf, 4446 (unsigned char *) fragP->fr_literal, 0); 4447 4448 fmt = xtensa_format_decode (isa, insnbuf); 4449 if (fmt == XTENSA_UNDEFINED) 4450 return XTENSA_UNDEFINED; 4451 fmt_size = xtensa_format_length (isa, fmt); 4452 4453 /* If the next format won't be changing due to relaxation, just 4454 return the length of the first format. */ 4455 if (fragP->fr_opcode != fragP->fr_literal) 4456 return fmt_size; 4457 4458 /* If during relaxation we have to pull an instruction out of a 4459 multi-slot instruction, we will return the more conservative 4460 number. This works because alignment on bigger instructions 4461 is more restrictive than alignment on smaller instructions. 4462 This is more conservative than we would like, but it happens 4463 infrequently. */ 4464 4465 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) 4466 return fmt_size; 4467 4468 /* If we aren't doing one of our own relaxations or it isn't 4469 slot-based, then the insn size won't change. */ 4470 if (fragP->fr_type != rs_machine_dependent) 4471 return fmt_size; 4472 if (fragP->fr_subtype != RELAX_SLOTS) 4473 return fmt_size; 4474 4475 /* If an instruction is about to grow, return the longer size. */ 4476 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 4477 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 4478 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) 4479 { 4480 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first 4481 instruction in the relaxed version is of length 3. (The case 4482 where we have to pull the instruction out of a FLIX bundle 4483 is handled conservatively above.) However, frags with opcodes 4484 that are expanding to wide branches end up having formats that 4485 are not determinable by the RELAX_IMMED_STEPX enumeration, and 4486 we can't tell directly what format the relaxer picked. This 4487 is a wart in the design of the relaxer that should someday be 4488 fixed, but would require major changes, or at least should 4489 be accompanied by major changes to make use of that data. 4490 4491 In any event, we can tell that we are expanding from a single-slot 4492 three-byte format to a wider one with the logic below. */ 4493 4494 if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3) 4495 return 3 + fragP->tc_frag_data.text_expansion[0]; 4496 else 4497 return 3; 4498 } 4499 4500 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 4501 return 2 + fragP->tc_frag_data.text_expansion[0]; 4502 4503 return fmt_size; 4504 } 4505 4506 4507 static int 4508 next_frag_format_size (const fragS *fragP) 4509 { 4510 const fragS *next_fragP = next_non_empty_frag (fragP); 4511 return frag_format_size (next_fragP); 4512 } 4513 4514 4515 /* In early Xtensa Processors, for reasons that are unclear, the ISA 4516 required two-byte instructions to be treated as three-byte instructions 4517 for loop instruction alignment. This restriction was removed beginning 4518 with Xtensa LX. Now the only requirement on loop instruction alignment 4519 is that the first instruction of the loop must appear at an address that 4520 does not cross a fetch boundary. */ 4521 4522 static int 4523 get_loop_align_size (int insn_size) 4524 { 4525 if (insn_size == XTENSA_UNDEFINED) 4526 return xtensa_fetch_width; 4527 4528 if (enforce_three_byte_loop_align && insn_size == 2) 4529 return 3; 4530 4531 return insn_size; 4532 } 4533 4534 4535 /* If the next legit fragment is an end-of-loop marker, 4536 switch its state so it will instantiate a NOP. */ 4537 4538 static void 4539 update_next_frag_state (fragS *fragP) 4540 { 4541 fragS *next_fragP = fragP->fr_next; 4542 fragS *new_target = NULL; 4543 4544 if (align_targets) 4545 { 4546 /* We are guaranteed there will be one of these... */ 4547 while (!(next_fragP->fr_type == rs_machine_dependent 4548 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4549 || next_fragP->fr_subtype == RELAX_UNREACHABLE))) 4550 next_fragP = next_fragP->fr_next; 4551 4552 assert (next_fragP->fr_type == rs_machine_dependent 4553 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4554 || next_fragP->fr_subtype == RELAX_UNREACHABLE)); 4555 4556 /* ...and one of these. */ 4557 new_target = next_fragP->fr_next; 4558 while (!(new_target->fr_type == rs_machine_dependent 4559 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4560 || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) 4561 new_target = new_target->fr_next; 4562 4563 assert (new_target->fr_type == rs_machine_dependent 4564 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4565 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); 4566 } 4567 4568 while (next_fragP && next_fragP->fr_fix == 0) 4569 { 4570 if (next_fragP->fr_type == rs_machine_dependent 4571 && next_fragP->fr_subtype == RELAX_LOOP_END) 4572 { 4573 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; 4574 return; 4575 } 4576 4577 next_fragP = next_fragP->fr_next; 4578 } 4579 } 4580 4581 4582 static bfd_boolean 4583 next_frag_is_branch_target (const fragS *fragP) 4584 { 4585 /* Sometimes an empty will end up here due to storage allocation issues, 4586 so we have to skip until we find something legit. */ 4587 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4588 { 4589 if (fragP->tc_frag_data.is_branch_target) 4590 return TRUE; 4591 if (fragP->fr_fix != 0) 4592 break; 4593 } 4594 return FALSE; 4595 } 4596 4597 4598 static bfd_boolean 4599 next_frag_is_loop_target (const fragS *fragP) 4600 { 4601 /* Sometimes an empty will end up here due storage allocation issues. 4602 So we have to skip until we find something legit. */ 4603 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4604 { 4605 if (fragP->tc_frag_data.is_loop_target) 4606 return TRUE; 4607 if (fragP->fr_fix != 0) 4608 break; 4609 } 4610 return FALSE; 4611 } 4612 4613 4614 static addressT 4615 next_frag_pre_opcode_bytes (const fragS *fragp) 4616 { 4617 const fragS *next_fragp = fragp->fr_next; 4618 xtensa_opcode next_opcode; 4619 4620 if (!next_frag_opcode_is_loop (fragp, &next_opcode)) 4621 return 0; 4622 4623 /* Sometimes an empty will end up here due to storage allocation issues, 4624 so we have to skip until we find something legit. */ 4625 while (next_fragp->fr_fix == 0) 4626 next_fragp = next_fragp->fr_next; 4627 4628 if (next_fragp->fr_type != rs_machine_dependent) 4629 return 0; 4630 4631 /* There is some implicit knowledge encoded in here. 4632 The LOOP instructions that are NOT RELAX_IMMED have 4633 been relaxed. Note that we can assume that the LOOP 4634 instruction is in slot 0 because loops aren't bundleable. */ 4635 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) 4636 return get_expanded_loop_offset (next_opcode); 4637 4638 return 0; 4639 } 4640 4641 4642 /* Mark a location where we can later insert literal frags. Update 4643 the section's literal_pool_loc, so subsequent literals can be 4644 placed nearest to their use. */ 4645 4646 static void 4647 xtensa_mark_literal_pool_location (void) 4648 { 4649 /* Any labels pointing to the current location need 4650 to be adjusted to after the literal pool. */ 4651 emit_state s; 4652 fragS *pool_location; 4653 4654 if (use_literal_section) 4655 return; 4656 4657 /* We stash info in these frags so we can later move the literal's 4658 fixes into this frchain's fix list. */ 4659 pool_location = frag_now; 4660 frag_now->tc_frag_data.lit_frchain = frchain_now; 4661 frag_now->tc_frag_data.literal_frag = frag_now; 4662 frag_variant (rs_machine_dependent, 0, 0, 4663 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); 4664 xtensa_set_frag_assembly_state (frag_now); 4665 frag_now->tc_frag_data.lit_seg = now_seg; 4666 frag_variant (rs_machine_dependent, 0, 0, 4667 RELAX_LITERAL_POOL_END, NULL, 0, NULL); 4668 xtensa_set_frag_assembly_state (frag_now); 4669 4670 /* Now put a frag into the literal pool that points to this location. */ 4671 set_literal_pool_location (now_seg, pool_location); 4672 xtensa_switch_to_non_abs_literal_fragment (&s); 4673 frag_align (2, 0, 0); 4674 record_alignment (now_seg, 2); 4675 4676 /* Close whatever frag is there. */ 4677 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4678 xtensa_set_frag_assembly_state (frag_now); 4679 frag_now->tc_frag_data.literal_frag = pool_location; 4680 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4681 xtensa_restore_emit_state (&s); 4682 xtensa_set_frag_assembly_state (frag_now); 4683 } 4684 4685 4686 /* Build a nop of the correct size into tinsn. */ 4687 4688 static void 4689 build_nop (TInsn *tinsn, int size) 4690 { 4691 tinsn_init (tinsn); 4692 switch (size) 4693 { 4694 case 2: 4695 tinsn->opcode = xtensa_nop_n_opcode; 4696 tinsn->ntok = 0; 4697 if (tinsn->opcode == XTENSA_UNDEFINED) 4698 as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); 4699 break; 4700 4701 case 3: 4702 if (xtensa_nop_opcode == XTENSA_UNDEFINED) 4703 { 4704 tinsn->opcode = xtensa_or_opcode; 4705 set_expr_const (&tinsn->tok[0], 1); 4706 set_expr_const (&tinsn->tok[1], 1); 4707 set_expr_const (&tinsn->tok[2], 1); 4708 tinsn->ntok = 3; 4709 } 4710 else 4711 tinsn->opcode = xtensa_nop_opcode; 4712 4713 assert (tinsn->opcode != XTENSA_UNDEFINED); 4714 } 4715 } 4716 4717 4718 /* Assemble a NOP of the requested size in the buffer. User must have 4719 allocated "buf" with at least "size" bytes. */ 4720 4721 static void 4722 assemble_nop (int size, char *buf) 4723 { 4724 static xtensa_insnbuf insnbuf = NULL; 4725 TInsn tinsn; 4726 4727 build_nop (&tinsn, size); 4728 4729 if (!insnbuf) 4730 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4731 4732 tinsn_to_insnbuf (&tinsn, insnbuf); 4733 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4734 (unsigned char *) buf, 0); 4735 } 4736 4737 4738 /* Return the number of bytes for the offset of the expanded loop 4739 instruction. This should be incorporated into the relaxation 4740 specification but is hard-coded here. This is used to auto-align 4741 the loop instruction. It is invalid to call this function if the 4742 configuration does not have loops or if the opcode is not a loop 4743 opcode. */ 4744 4745 static addressT 4746 get_expanded_loop_offset (xtensa_opcode opcode) 4747 { 4748 /* This is the OFFSET of the loop instruction in the expanded loop. 4749 This MUST correspond directly to the specification of the loop 4750 expansion. It will be validated on fragment conversion. */ 4751 assert (opcode != XTENSA_UNDEFINED); 4752 if (opcode == xtensa_loop_opcode) 4753 return 0; 4754 if (opcode == xtensa_loopnez_opcode) 4755 return 3; 4756 if (opcode == xtensa_loopgtz_opcode) 4757 return 6; 4758 as_fatal (_("get_expanded_loop_offset: invalid opcode")); 4759 return 0; 4760 } 4761 4762 4763 static fragS * 4764 get_literal_pool_location (segT seg) 4765 { 4766 return seg_info (seg)->tc_segment_info_data.literal_pool_loc; 4767 } 4768 4769 4770 static void 4771 set_literal_pool_location (segT seg, fragS *literal_pool_loc) 4772 { 4773 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; 4774 } 4775 4776 4777 /* Set frag assembly state should be called when a new frag is 4778 opened and after a frag has been closed. */ 4779 4780 static void 4781 xtensa_set_frag_assembly_state (fragS *fragP) 4782 { 4783 if (!density_supported) 4784 fragP->tc_frag_data.is_no_density = TRUE; 4785 4786 /* This function is called from subsegs_finish, which is called 4787 after xtensa_end, so we can't use "use_transform" or 4788 "use_schedule" here. */ 4789 if (!directive_state[directive_transform]) 4790 fragP->tc_frag_data.is_no_transform = TRUE; 4791 if (directive_state[directive_longcalls]) 4792 fragP->tc_frag_data.use_longcalls = TRUE; 4793 fragP->tc_frag_data.use_absolute_literals = 4794 directive_state[directive_absolute_literals]; 4795 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4796 } 4797 4798 4799 static bfd_boolean 4800 relaxable_section (asection *sec) 4801 { 4802 return ((sec->flags & SEC_DEBUGGING) == 0 4803 && strcmp (sec->name, ".eh_frame") != 0); 4804 } 4805 4806 4807 static void 4808 xtensa_mark_frags_for_org (void) 4809 { 4810 segT *seclist; 4811 4812 /* Walk over each fragment of all of the current segments. If we find 4813 a .org frag in any of the segments, mark all frags prior to it as 4814 "no transform", which will prevent linker optimizations from messing 4815 up the .org distance. This should be done after 4816 xtensa_find_unmarked_state_frags, because we don't want to worry here 4817 about that function trashing the data we save here. */ 4818 4819 for (seclist = &stdoutput->sections; 4820 seclist && *seclist; 4821 seclist = &(*seclist)->next) 4822 { 4823 segT sec = *seclist; 4824 segment_info_type *seginfo; 4825 fragS *fragP; 4826 flagword flags; 4827 flags = bfd_get_section_flags (stdoutput, sec); 4828 if (flags & SEC_DEBUGGING) 4829 continue; 4830 if (!(flags & SEC_ALLOC)) 4831 continue; 4832 4833 seginfo = seg_info (sec); 4834 if (seginfo && seginfo->frchainP) 4835 { 4836 fragS *last_fragP = seginfo->frchainP->frch_root; 4837 for (fragP = seginfo->frchainP->frch_root; fragP; 4838 fragP = fragP->fr_next) 4839 { 4840 /* cvt_frag_to_fill has changed the fr_type of org frags to 4841 rs_fill, so use the value as cached in rs_subtype here. */ 4842 if (fragP->fr_subtype == RELAX_ORG) 4843 { 4844 while (last_fragP != fragP->fr_next) 4845 { 4846 last_fragP->tc_frag_data.is_no_transform = TRUE; 4847 last_fragP = last_fragP->fr_next; 4848 } 4849 } 4850 } 4851 } 4852 } 4853 } 4854 4855 4856 static void 4857 xtensa_find_unmarked_state_frags (void) 4858 { 4859 segT *seclist; 4860 4861 /* Walk over each fragment of all of the current segments. For each 4862 unmarked fragment, mark it with the same info as the previous 4863 fragment. */ 4864 for (seclist = &stdoutput->sections; 4865 seclist && *seclist; 4866 seclist = &(*seclist)->next) 4867 { 4868 segT sec = *seclist; 4869 segment_info_type *seginfo; 4870 fragS *fragP; 4871 flagword flags; 4872 flags = bfd_get_section_flags (stdoutput, sec); 4873 if (flags & SEC_DEBUGGING) 4874 continue; 4875 if (!(flags & SEC_ALLOC)) 4876 continue; 4877 4878 seginfo = seg_info (sec); 4879 if (seginfo && seginfo->frchainP) 4880 { 4881 fragS *last_fragP = 0; 4882 for (fragP = seginfo->frchainP->frch_root; fragP; 4883 fragP = fragP->fr_next) 4884 { 4885 if (fragP->fr_fix != 0 4886 && !fragP->tc_frag_data.is_assembly_state_set) 4887 { 4888 if (last_fragP == 0) 4889 { 4890 as_warn_where (fragP->fr_file, fragP->fr_line, 4891 _("assembly state not set for first frag in section %s"), 4892 sec->name); 4893 } 4894 else 4895 { 4896 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4897 fragP->tc_frag_data.is_no_density = 4898 last_fragP->tc_frag_data.is_no_density; 4899 fragP->tc_frag_data.is_no_transform = 4900 last_fragP->tc_frag_data.is_no_transform; 4901 fragP->tc_frag_data.use_longcalls = 4902 last_fragP->tc_frag_data.use_longcalls; 4903 fragP->tc_frag_data.use_absolute_literals = 4904 last_fragP->tc_frag_data.use_absolute_literals; 4905 } 4906 } 4907 if (fragP->tc_frag_data.is_assembly_state_set) 4908 last_fragP = fragP; 4909 } 4910 } 4911 } 4912 } 4913 4914 4915 static void 4916 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, 4917 asection *sec, 4918 void *unused ATTRIBUTE_UNUSED) 4919 { 4920 flagword flags = bfd_get_section_flags (abfd, sec); 4921 segment_info_type *seginfo = seg_info (sec); 4922 fragS *frag = seginfo->frchainP->frch_root; 4923 4924 if (flags & SEC_CODE) 4925 { 4926 xtensa_isa isa = xtensa_default_isa; 4927 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 4928 while (frag != NULL) 4929 { 4930 if (frag->tc_frag_data.is_branch_target) 4931 { 4932 int op_size; 4933 addressT branch_align, frag_addr; 4934 xtensa_format fmt; 4935 4936 xtensa_insnbuf_from_chars 4937 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 4938 fmt = xtensa_format_decode (isa, insnbuf); 4939 op_size = xtensa_format_length (isa, fmt); 4940 branch_align = 1 << branch_align_power (sec); 4941 frag_addr = frag->fr_address % branch_align; 4942 if (frag_addr + op_size > branch_align) 4943 as_warn_where (frag->fr_file, frag->fr_line, 4944 _("unaligned branch target: %d bytes at 0x%lx"), 4945 op_size, (long) frag->fr_address); 4946 } 4947 frag = frag->fr_next; 4948 } 4949 xtensa_insnbuf_free (isa, insnbuf); 4950 } 4951 } 4952 4953 4954 static void 4955 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, 4956 asection *sec, 4957 void *unused ATTRIBUTE_UNUSED) 4958 { 4959 flagword flags = bfd_get_section_flags (abfd, sec); 4960 segment_info_type *seginfo = seg_info (sec); 4961 fragS *frag = seginfo->frchainP->frch_root; 4962 xtensa_isa isa = xtensa_default_isa; 4963 4964 if (flags & SEC_CODE) 4965 { 4966 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 4967 while (frag != NULL) 4968 { 4969 if (frag->tc_frag_data.is_first_loop_insn) 4970 { 4971 int op_size; 4972 addressT frag_addr; 4973 xtensa_format fmt; 4974 4975 xtensa_insnbuf_from_chars 4976 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 4977 fmt = xtensa_format_decode (isa, insnbuf); 4978 op_size = xtensa_format_length (isa, fmt); 4979 frag_addr = frag->fr_address % xtensa_fetch_width; 4980 4981 if (frag_addr + op_size > xtensa_fetch_width) 4982 as_warn_where (frag->fr_file, frag->fr_line, 4983 _("unaligned loop: %d bytes at 0x%lx"), 4984 op_size, (long) frag->fr_address); 4985 } 4986 frag = frag->fr_next; 4987 } 4988 xtensa_insnbuf_free (isa, insnbuf); 4989 } 4990 } 4991 4992 4993 static int 4994 xg_apply_fix_value (fixS *fixP, valueT val) 4995 { 4996 xtensa_isa isa = xtensa_default_isa; 4997 static xtensa_insnbuf insnbuf = NULL; 4998 static xtensa_insnbuf slotbuf = NULL; 4999 xtensa_format fmt; 5000 int slot; 5001 bfd_boolean alt_reloc; 5002 xtensa_opcode opcode; 5003 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5004 5005 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) 5006 || alt_reloc) 5007 as_fatal (_("unexpected fix")); 5008 5009 if (!insnbuf) 5010 { 5011 insnbuf = xtensa_insnbuf_alloc (isa); 5012 slotbuf = xtensa_insnbuf_alloc (isa); 5013 } 5014 5015 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5016 fmt = xtensa_format_decode (isa, insnbuf); 5017 if (fmt == XTENSA_UNDEFINED) 5018 as_fatal (_("undecodable fix")); 5019 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5020 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5021 if (opcode == XTENSA_UNDEFINED) 5022 as_fatal (_("undecodable fix")); 5023 5024 /* CONST16 immediates are not PC-relative, despite the fact that we 5025 reuse the normal PC-relative operand relocations for the low part 5026 of a CONST16 operand. */ 5027 if (opcode == xtensa_const16_opcode) 5028 return 0; 5029 5030 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, 5031 get_relaxable_immed (opcode), val, 5032 fixP->fx_file, fixP->fx_line); 5033 5034 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); 5035 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5036 5037 return 1; 5038 } 5039 5040 5041 /* External Functions and Other GAS Hooks. */ 5042 5043 const char * 5044 xtensa_target_format (void) 5045 { 5046 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); 5047 } 5048 5049 5050 void 5051 xtensa_file_arch_init (bfd *abfd) 5052 { 5053 bfd_set_private_flags (abfd, 0x100 | 0x200); 5054 } 5055 5056 5057 void 5058 md_number_to_chars (char *buf, valueT val, int n) 5059 { 5060 if (target_big_endian) 5061 number_to_chars_bigendian (buf, val, n); 5062 else 5063 number_to_chars_littleendian (buf, val, n); 5064 } 5065 5066 5067 /* This function is called once, at assembler startup time. It should 5068 set up all the tables, etc. that the MD part of the assembler will 5069 need. */ 5070 5071 void 5072 md_begin (void) 5073 { 5074 segT current_section = now_seg; 5075 int current_subsec = now_subseg; 5076 xtensa_isa isa; 5077 5078 xtensa_default_isa = xtensa_isa_init (0, 0); 5079 isa = xtensa_default_isa; 5080 5081 linkrelax = 1; 5082 5083 /* Set up the literal sections. */ 5084 memset (&default_lit_sections, 0, sizeof (default_lit_sections)); 5085 5086 subseg_set (current_section, current_subsec); 5087 5088 xg_init_vinsn (&cur_vinsn); 5089 5090 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); 5091 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); 5092 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); 5093 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); 5094 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); 5095 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); 5096 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); 5097 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); 5098 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); 5099 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); 5100 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); 5101 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); 5102 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); 5103 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); 5104 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); 5105 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); 5106 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); 5107 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); 5108 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); 5109 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); 5110 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); 5111 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); 5112 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); 5113 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); 5114 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); 5115 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); 5116 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); 5117 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); 5118 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); 5119 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); 5120 5121 xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); 5122 5123 init_op_placement_info_table (); 5124 5125 /* Set up the assembly state. */ 5126 if (!frag_now->tc_frag_data.is_assembly_state_set) 5127 xtensa_set_frag_assembly_state (frag_now); 5128 } 5129 5130 5131 /* TC_INIT_FIX_DATA hook */ 5132 5133 void 5134 xtensa_init_fix_data (fixS *x) 5135 { 5136 x->tc_fix_data.slot = 0; 5137 x->tc_fix_data.X_add_symbol = NULL; 5138 x->tc_fix_data.X_add_number = 0; 5139 } 5140 5141 5142 /* tc_frob_label hook */ 5143 5144 void 5145 xtensa_frob_label (symbolS *sym) 5146 { 5147 float freq; 5148 5149 if (cur_vinsn.inside_bundle) 5150 { 5151 as_bad (_("labels are not valid inside bundles")); 5152 return; 5153 } 5154 5155 freq = get_subseg_target_freq (now_seg, now_subseg); 5156 5157 /* Since the label was already attached to a frag associated with the 5158 previous basic block, it now needs to be reset to the current frag. */ 5159 symbol_set_frag (sym, frag_now); 5160 S_SET_VALUE (sym, (valueT) frag_now_fix ()); 5161 5162 if (generating_literals) 5163 xtensa_add_literal_sym (sym); 5164 else 5165 xtensa_add_insn_label (sym); 5166 5167 if (symbol_get_tc (sym)->is_loop_target) 5168 { 5169 if ((get_last_insn_flags (now_seg, now_subseg) 5170 & FLAG_IS_BAD_LOOPEND) != 0) 5171 as_bad (_("invalid last instruction for a zero-overhead loop")); 5172 5173 xtensa_set_frag_assembly_state (frag_now); 5174 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, 5175 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5176 5177 xtensa_set_frag_assembly_state (frag_now); 5178 xtensa_move_labels (frag_now, 0); 5179 } 5180 5181 /* No target aligning in the absolute section. */ 5182 if (now_seg != absolute_section 5183 && do_align_targets () 5184 && !is_unaligned_label (sym) 5185 && !generating_literals) 5186 { 5187 xtensa_set_frag_assembly_state (frag_now); 5188 5189 frag_var (rs_machine_dependent, 5190 0, (int) freq, 5191 RELAX_DESIRE_ALIGN_IF_TARGET, 5192 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5193 xtensa_set_frag_assembly_state (frag_now); 5194 xtensa_move_labels (frag_now, 0); 5195 } 5196 5197 /* We need to mark the following properties even if we aren't aligning. */ 5198 5199 /* If the label is already known to be a branch target, i.e., a 5200 forward branch, mark the frag accordingly. Backward branches 5201 are handled by xg_add_branch_and_loop_targets. */ 5202 if (symbol_get_tc (sym)->is_branch_target) 5203 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 5204 5205 /* Loops only go forward, so they can be identified here. */ 5206 if (symbol_get_tc (sym)->is_loop_target) 5207 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; 5208 5209 dwarf2_emit_label (sym); 5210 } 5211 5212 5213 /* tc_unrecognized_line hook */ 5214 5215 int 5216 xtensa_unrecognized_line (int ch) 5217 { 5218 switch (ch) 5219 { 5220 case '{' : 5221 if (cur_vinsn.inside_bundle == 0) 5222 { 5223 /* PR8110: Cannot emit line number info inside a FLIX bundle 5224 when using --gstabs. Temporarily disable debug info. */ 5225 generate_lineno_debug (); 5226 if (debug_type == DEBUG_STABS) 5227 { 5228 xt_saved_debug_type = debug_type; 5229 debug_type = DEBUG_NONE; 5230 } 5231 5232 cur_vinsn.inside_bundle = 1; 5233 } 5234 else 5235 { 5236 as_bad (_("extra opening brace")); 5237 return 0; 5238 } 5239 break; 5240 5241 case '}' : 5242 if (cur_vinsn.inside_bundle) 5243 finish_vinsn (&cur_vinsn); 5244 else 5245 { 5246 as_bad (_("extra closing brace")); 5247 return 0; 5248 } 5249 break; 5250 default: 5251 as_bad (_("syntax error")); 5252 return 0; 5253 } 5254 return 1; 5255 } 5256 5257 5258 /* md_flush_pending_output hook */ 5259 5260 void 5261 xtensa_flush_pending_output (void) 5262 { 5263 /* This line fixes a bug where automatically generated gstabs info 5264 separates a function label from its entry instruction, ending up 5265 with the literal position between the function label and the entry 5266 instruction and crashing code. It only happens with --gstabs and 5267 --text-section-literals, and when several other obscure relaxation 5268 conditions are met. */ 5269 if (outputting_stabs_line_debug) 5270 return; 5271 5272 if (cur_vinsn.inside_bundle) 5273 as_bad (_("missing closing brace")); 5274 5275 /* If there is a non-zero instruction fragment, close it. */ 5276 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) 5277 { 5278 frag_wane (frag_now); 5279 frag_new (0); 5280 xtensa_set_frag_assembly_state (frag_now); 5281 } 5282 frag_now->tc_frag_data.is_insn = FALSE; 5283 5284 xtensa_clear_insn_labels (); 5285 } 5286 5287 5288 /* We had an error while parsing an instruction. The string might look 5289 like this: "insn arg1, arg2 }". If so, we need to see the closing 5290 brace and reset some fields. Otherwise, the vinsn never gets closed 5291 and the num_slots field will grow past the end of the array of slots, 5292 and bad things happen. */ 5293 5294 static void 5295 error_reset_cur_vinsn (void) 5296 { 5297 if (cur_vinsn.inside_bundle) 5298 { 5299 if (*input_line_pointer == '}' 5300 || *(input_line_pointer - 1) == '}' 5301 || *(input_line_pointer - 2) == '}') 5302 xg_clear_vinsn (&cur_vinsn); 5303 } 5304 } 5305 5306 5307 void 5308 md_assemble (char *str) 5309 { 5310 xtensa_isa isa = xtensa_default_isa; 5311 char *opname; 5312 unsigned opnamelen; 5313 bfd_boolean has_underbar = FALSE; 5314 char *arg_strings[MAX_INSN_ARGS]; 5315 int num_args; 5316 TInsn orig_insn; /* Original instruction from the input. */ 5317 5318 tinsn_init (&orig_insn); 5319 5320 /* Split off the opcode. */ 5321 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); 5322 opname = xmalloc (opnamelen + 1); 5323 memcpy (opname, str, opnamelen); 5324 opname[opnamelen] = '\0'; 5325 5326 num_args = tokenize_arguments (arg_strings, str + opnamelen); 5327 if (num_args == -1) 5328 { 5329 as_bad (_("syntax error")); 5330 return; 5331 } 5332 5333 if (xg_translate_idioms (&opname, &num_args, arg_strings)) 5334 return; 5335 5336 /* Check for an underbar prefix. */ 5337 if (*opname == '_') 5338 { 5339 has_underbar = TRUE; 5340 opname += 1; 5341 } 5342 5343 orig_insn.insn_type = ITYPE_INSN; 5344 orig_insn.ntok = 0; 5345 orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); 5346 orig_insn.opcode = xtensa_opcode_lookup (isa, opname); 5347 5348 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its 5349 extra argument and set the opcode to "CALLXn". */ 5350 if (orig_insn.opcode == XTENSA_UNDEFINED 5351 && strncasecmp (opname, "callx", 5) == 0) 5352 { 5353 unsigned long window_size; 5354 char *suffix; 5355 5356 window_size = strtoul (opname + 5, &suffix, 10); 5357 if (suffix != opname + 5 5358 && (window_size == 0 5359 || window_size == 4 5360 || window_size == 8 5361 || window_size == 12) 5362 && strcasecmp (suffix, ".tls") == 0) 5363 { 5364 switch (window_size) 5365 { 5366 case 0: orig_insn.opcode = xtensa_callx0_opcode; break; 5367 case 4: orig_insn.opcode = xtensa_callx4_opcode; break; 5368 case 8: orig_insn.opcode = xtensa_callx8_opcode; break; 5369 case 12: orig_insn.opcode = xtensa_callx12_opcode; break; 5370 } 5371 5372 if (num_args != 2) 5373 as_bad (_("wrong number of operands for '%s'"), opname); 5374 else 5375 { 5376 bfd_reloc_code_real_type reloc; 5377 char *old_input_line_pointer; 5378 expressionS *tok = &orig_insn.tls_reloc; 5379 segT t; 5380 5381 old_input_line_pointer = input_line_pointer; 5382 input_line_pointer = arg_strings[num_args - 1]; 5383 5384 t = expression (tok); 5385 if (tok->X_op == O_symbol 5386 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 5387 == BFD_RELOC_XTENSA_TLS_CALL)) 5388 tok->X_op = map_suffix_reloc_to_operator (reloc); 5389 else 5390 as_bad (_("bad relocation expression for '%s'"), opname); 5391 5392 input_line_pointer = old_input_line_pointer; 5393 num_args -= 1; 5394 } 5395 } 5396 } 5397 5398 if (orig_insn.opcode == XTENSA_UNDEFINED) 5399 { 5400 xtensa_format fmt = xtensa_format_lookup (isa, opname); 5401 if (fmt == XTENSA_UNDEFINED) 5402 { 5403 as_bad (_("unknown opcode or format name '%s'"), opname); 5404 error_reset_cur_vinsn (); 5405 return; 5406 } 5407 if (!cur_vinsn.inside_bundle) 5408 { 5409 as_bad (_("format names only valid inside bundles")); 5410 error_reset_cur_vinsn (); 5411 return; 5412 } 5413 if (cur_vinsn.format != XTENSA_UNDEFINED) 5414 as_warn (_("multiple formats specified for one bundle; using '%s'"), 5415 opname); 5416 cur_vinsn.format = fmt; 5417 free (has_underbar ? opname - 1 : opname); 5418 error_reset_cur_vinsn (); 5419 return; 5420 } 5421 5422 /* Parse the arguments. */ 5423 if (parse_arguments (&orig_insn, num_args, arg_strings)) 5424 { 5425 as_bad (_("syntax error")); 5426 error_reset_cur_vinsn (); 5427 return; 5428 } 5429 5430 /* Free the opcode and argument strings, now that they've been parsed. */ 5431 free (has_underbar ? opname - 1 : opname); 5432 opname = 0; 5433 while (num_args-- > 0) 5434 free (arg_strings[num_args]); 5435 5436 /* Get expressions for invisible operands. */ 5437 if (get_invisible_operands (&orig_insn)) 5438 { 5439 error_reset_cur_vinsn (); 5440 return; 5441 } 5442 5443 /* Check for the right number and type of arguments. */ 5444 if (tinsn_check_arguments (&orig_insn)) 5445 { 5446 error_reset_cur_vinsn (); 5447 return; 5448 } 5449 5450 /* Record the line number for each TInsn, because a FLIX bundle may be 5451 spread across multiple input lines and individual instructions may be 5452 moved around in some cases. */ 5453 orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; 5454 dwarf2_where (&orig_insn.debug_line); 5455 dwarf2_consume_line_info (); 5456 5457 xg_add_branch_and_loop_targets (&orig_insn); 5458 5459 /* Check that immediate value for ENTRY is >= 16. */ 5460 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) 5461 { 5462 expressionS *exp = &orig_insn.tok[2]; 5463 if (exp->X_op == O_constant && exp->X_add_number < 16) 5464 as_warn (_("entry instruction with stack decrement < 16")); 5465 } 5466 5467 /* Finish it off: 5468 assemble_tokens (opcode, tok, ntok); 5469 expand the tokens from the orig_insn into the 5470 stack of instructions that will not expand 5471 unless required at relaxation time. */ 5472 5473 if (!cur_vinsn.inside_bundle) 5474 emit_single_op (&orig_insn); 5475 else /* We are inside a bundle. */ 5476 { 5477 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; 5478 cur_vinsn.num_slots++; 5479 if (*input_line_pointer == '}' 5480 || *(input_line_pointer - 1) == '}' 5481 || *(input_line_pointer - 2) == '}') 5482 finish_vinsn (&cur_vinsn); 5483 } 5484 5485 /* We've just emitted a new instruction so clear the list of labels. */ 5486 xtensa_clear_insn_labels (); 5487 } 5488 5489 5490 /* HANDLE_ALIGN hook */ 5491 5492 /* For a .align directive, we mark the previous block with the alignment 5493 information. This will be placed in the object file in the 5494 property section corresponding to this section. */ 5495 5496 void 5497 xtensa_handle_align (fragS *fragP) 5498 { 5499 if (linkrelax 5500 && ! fragP->tc_frag_data.is_literal 5501 && (fragP->fr_type == rs_align 5502 || fragP->fr_type == rs_align_code) 5503 && fragP->fr_address + fragP->fr_fix > 0 5504 && fragP->fr_offset > 0 5505 && now_seg != bss_section) 5506 { 5507 fragP->tc_frag_data.is_align = TRUE; 5508 fragP->tc_frag_data.alignment = fragP->fr_offset; 5509 } 5510 5511 if (fragP->fr_type == rs_align_test) 5512 { 5513 int count; 5514 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 5515 if (count != 0) 5516 as_bad_where (fragP->fr_file, fragP->fr_line, 5517 _("unaligned entry instruction")); 5518 } 5519 5520 if (linkrelax && fragP->fr_type == rs_org) 5521 fragP->fr_subtype = RELAX_ORG; 5522 } 5523 5524 5525 /* TC_FRAG_INIT hook */ 5526 5527 void 5528 xtensa_frag_init (fragS *frag) 5529 { 5530 xtensa_set_frag_assembly_state (frag); 5531 } 5532 5533 5534 symbolS * 5535 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 5536 { 5537 return NULL; 5538 } 5539 5540 5541 /* Round up a section size to the appropriate boundary. */ 5542 5543 valueT 5544 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 5545 { 5546 return size; /* Byte alignment is fine. */ 5547 } 5548 5549 5550 long 5551 md_pcrel_from (fixS *fixP) 5552 { 5553 char *insn_p; 5554 static xtensa_insnbuf insnbuf = NULL; 5555 static xtensa_insnbuf slotbuf = NULL; 5556 int opnum; 5557 uint32 opnd_value; 5558 xtensa_opcode opcode; 5559 xtensa_format fmt; 5560 int slot; 5561 xtensa_isa isa = xtensa_default_isa; 5562 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 5563 bfd_boolean alt_reloc; 5564 5565 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) 5566 return 0; 5567 5568 if (fixP->fx_r_type == BFD_RELOC_32_PCREL) 5569 return addr; 5570 5571 if (!insnbuf) 5572 { 5573 insnbuf = xtensa_insnbuf_alloc (isa); 5574 slotbuf = xtensa_insnbuf_alloc (isa); 5575 } 5576 5577 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; 5578 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); 5579 fmt = xtensa_format_decode (isa, insnbuf); 5580 5581 if (fmt == XTENSA_UNDEFINED) 5582 as_fatal (_("bad instruction format")); 5583 5584 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) 5585 as_fatal (_("invalid relocation")); 5586 5587 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5588 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5589 5590 /* Check for "alternate" relocations (operand not specified). None 5591 of the current uses for these are really PC-relative. */ 5592 if (alt_reloc || opcode == xtensa_const16_opcode) 5593 { 5594 if (opcode != xtensa_l32r_opcode 5595 && opcode != xtensa_const16_opcode) 5596 as_fatal (_("invalid relocation for '%s' instruction"), 5597 xtensa_opcode_name (isa, opcode)); 5598 return 0; 5599 } 5600 5601 opnum = get_relaxable_immed (opcode); 5602 opnd_value = 0; 5603 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 5604 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) 5605 { 5606 as_bad_where (fixP->fx_file, 5607 fixP->fx_line, 5608 _("invalid relocation for operand %d of '%s'"), 5609 opnum, xtensa_opcode_name (isa, opcode)); 5610 return 0; 5611 } 5612 return 0 - opnd_value; 5613 } 5614 5615 5616 /* TC_FORCE_RELOCATION hook */ 5617 5618 int 5619 xtensa_force_relocation (fixS *fix) 5620 { 5621 switch (fix->fx_r_type) 5622 { 5623 case BFD_RELOC_XTENSA_ASM_EXPAND: 5624 case BFD_RELOC_XTENSA_SLOT0_ALT: 5625 case BFD_RELOC_XTENSA_SLOT1_ALT: 5626 case BFD_RELOC_XTENSA_SLOT2_ALT: 5627 case BFD_RELOC_XTENSA_SLOT3_ALT: 5628 case BFD_RELOC_XTENSA_SLOT4_ALT: 5629 case BFD_RELOC_XTENSA_SLOT5_ALT: 5630 case BFD_RELOC_XTENSA_SLOT6_ALT: 5631 case BFD_RELOC_XTENSA_SLOT7_ALT: 5632 case BFD_RELOC_XTENSA_SLOT8_ALT: 5633 case BFD_RELOC_XTENSA_SLOT9_ALT: 5634 case BFD_RELOC_XTENSA_SLOT10_ALT: 5635 case BFD_RELOC_XTENSA_SLOT11_ALT: 5636 case BFD_RELOC_XTENSA_SLOT12_ALT: 5637 case BFD_RELOC_XTENSA_SLOT13_ALT: 5638 case BFD_RELOC_XTENSA_SLOT14_ALT: 5639 return 1; 5640 default: 5641 break; 5642 } 5643 5644 if (linkrelax && fix->fx_addsy 5645 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) 5646 return 1; 5647 5648 return generic_force_reloc (fix); 5649 } 5650 5651 5652 /* TC_VALIDATE_FIX_SUB hook */ 5653 5654 int 5655 xtensa_validate_fix_sub (fixS *fix) 5656 { 5657 segT add_symbol_segment, sub_symbol_segment; 5658 5659 /* The difference of two symbols should be resolved by the assembler when 5660 linkrelax is not set. If the linker may relax the section containing 5661 the symbols, then an Xtensa DIFF relocation must be generated so that 5662 the linker knows to adjust the difference value. */ 5663 if (!linkrelax || fix->fx_addsy == NULL) 5664 return 0; 5665 5666 /* Make sure both symbols are in the same segment, and that segment is 5667 "normal" and relaxable. If the segment is not "normal", then the 5668 fix is not valid. If the segment is not "relaxable", then the fix 5669 should have been handled earlier. */ 5670 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); 5671 if (! SEG_NORMAL (add_symbol_segment) || 5672 ! relaxable_section (add_symbol_segment)) 5673 return 0; 5674 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); 5675 return (sub_symbol_segment == add_symbol_segment); 5676 } 5677 5678 5679 /* NO_PSEUDO_DOT hook */ 5680 5681 /* This function has nothing to do with pseudo dots, but this is the 5682 nearest macro to where the check needs to take place. FIXME: This 5683 seems wrong. */ 5684 5685 bfd_boolean 5686 xtensa_check_inside_bundle (void) 5687 { 5688 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') 5689 as_bad (_("directives are not valid inside bundles")); 5690 5691 /* This function must always return FALSE because it is called via a 5692 macro that has nothing to do with bundling. */ 5693 return FALSE; 5694 } 5695 5696 5697 /* md_elf_section_change_hook */ 5698 5699 void 5700 xtensa_elf_section_change_hook (void) 5701 { 5702 /* Set up the assembly state. */ 5703 if (!frag_now->tc_frag_data.is_assembly_state_set) 5704 xtensa_set_frag_assembly_state (frag_now); 5705 } 5706 5707 5708 /* tc_fix_adjustable hook */ 5709 5710 bfd_boolean 5711 xtensa_fix_adjustable (fixS *fixP) 5712 { 5713 /* An offset is not allowed in combination with the difference of two 5714 symbols, but that cannot be easily detected after a local symbol 5715 has been adjusted to a (section+offset) form. Return 0 so that such 5716 an fix will not be adjusted. */ 5717 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset 5718 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) 5719 return 0; 5720 5721 /* We need the symbol name for the VTABLE entries. */ 5722 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 5723 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5724 return 0; 5725 5726 return 1; 5727 } 5728 5729 5730 /* tc_symbol_new_hook */ 5731 5732 symbolS *expr_symbols = NULL; 5733 5734 void 5735 xtensa_symbol_new_hook (symbolS *sym) 5736 { 5737 if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) 5738 { 5739 symbol_get_tc (sym)->next_expr_symbol = expr_symbols; 5740 expr_symbols = sym; 5741 } 5742 } 5743 5744 5745 void 5746 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 5747 { 5748 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5749 valueT val = 0; 5750 5751 /* Subtracted symbols are only allowed for a few relocation types, and 5752 unless linkrelax is enabled, they should not make it to this point. */ 5753 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 5754 || fixP->fx_r_type == BFD_RELOC_16 5755 || fixP->fx_r_type == BFD_RELOC_8))) 5756 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); 5757 5758 switch (fixP->fx_r_type) 5759 { 5760 case BFD_RELOC_32_PCREL: 5761 case BFD_RELOC_32: 5762 case BFD_RELOC_16: 5763 case BFD_RELOC_8: 5764 if (fixP->fx_subsy) 5765 { 5766 switch (fixP->fx_r_type) 5767 { 5768 case BFD_RELOC_8: 5769 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; 5770 break; 5771 case BFD_RELOC_16: 5772 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; 5773 break; 5774 case BFD_RELOC_32: 5775 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; 5776 break; 5777 default: 5778 break; 5779 } 5780 5781 /* An offset is only allowed when it results from adjusting a 5782 local symbol into a section-relative offset. If the offset 5783 came from the original expression, tc_fix_adjustable will have 5784 prevented the fix from being converted to a section-relative 5785 form so that we can flag the error here. */ 5786 if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) 5787 as_bad_where (fixP->fx_file, fixP->fx_line, 5788 _("cannot represent subtraction with an offset")); 5789 5790 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5791 - S_GET_VALUE (fixP->fx_subsy)); 5792 5793 /* The difference value gets written out, and the DIFF reloc 5794 identifies the address of the subtracted symbol (i.e., the one 5795 with the lowest address). */ 5796 *valP = val; 5797 fixP->fx_offset -= val; 5798 fixP->fx_subsy = NULL; 5799 } 5800 else if (! fixP->fx_addsy) 5801 { 5802 val = *valP; 5803 fixP->fx_done = 1; 5804 } 5805 /* fall through */ 5806 5807 case BFD_RELOC_XTENSA_PLT: 5808 md_number_to_chars (fixpos, val, fixP->fx_size); 5809 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 5810 break; 5811 5812 case BFD_RELOC_XTENSA_TLSDESC_FN: 5813 case BFD_RELOC_XTENSA_TLSDESC_ARG: 5814 case BFD_RELOC_XTENSA_TLS_TPOFF: 5815 case BFD_RELOC_XTENSA_TLS_DTPOFF: 5816 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5817 md_number_to_chars (fixpos, 0, fixP->fx_size); 5818 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 5819 break; 5820 5821 case BFD_RELOC_XTENSA_SLOT0_OP: 5822 case BFD_RELOC_XTENSA_SLOT1_OP: 5823 case BFD_RELOC_XTENSA_SLOT2_OP: 5824 case BFD_RELOC_XTENSA_SLOT3_OP: 5825 case BFD_RELOC_XTENSA_SLOT4_OP: 5826 case BFD_RELOC_XTENSA_SLOT5_OP: 5827 case BFD_RELOC_XTENSA_SLOT6_OP: 5828 case BFD_RELOC_XTENSA_SLOT7_OP: 5829 case BFD_RELOC_XTENSA_SLOT8_OP: 5830 case BFD_RELOC_XTENSA_SLOT9_OP: 5831 case BFD_RELOC_XTENSA_SLOT10_OP: 5832 case BFD_RELOC_XTENSA_SLOT11_OP: 5833 case BFD_RELOC_XTENSA_SLOT12_OP: 5834 case BFD_RELOC_XTENSA_SLOT13_OP: 5835 case BFD_RELOC_XTENSA_SLOT14_OP: 5836 if (linkrelax) 5837 { 5838 /* Write the tentative value of a PC-relative relocation to a 5839 local symbol into the instruction. The value will be ignored 5840 by the linker, and it makes the object file disassembly 5841 readable when all branch targets are encoded in relocations. */ 5842 5843 assert (fixP->fx_addsy); 5844 if (S_GET_SEGMENT (fixP->fx_addsy) == seg 5845 && !S_FORCE_RELOC (fixP->fx_addsy, 1)) 5846 { 5847 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5848 - md_pcrel_from (fixP)); 5849 (void) xg_apply_fix_value (fixP, val); 5850 } 5851 } 5852 else if (! fixP->fx_addsy) 5853 { 5854 val = *valP; 5855 if (xg_apply_fix_value (fixP, val)) 5856 fixP->fx_done = 1; 5857 } 5858 break; 5859 5860 case BFD_RELOC_XTENSA_ASM_EXPAND: 5861 case BFD_RELOC_XTENSA_TLS_FUNC: 5862 case BFD_RELOC_XTENSA_TLS_ARG: 5863 case BFD_RELOC_XTENSA_TLS_CALL: 5864 case BFD_RELOC_XTENSA_SLOT0_ALT: 5865 case BFD_RELOC_XTENSA_SLOT1_ALT: 5866 case BFD_RELOC_XTENSA_SLOT2_ALT: 5867 case BFD_RELOC_XTENSA_SLOT3_ALT: 5868 case BFD_RELOC_XTENSA_SLOT4_ALT: 5869 case BFD_RELOC_XTENSA_SLOT5_ALT: 5870 case BFD_RELOC_XTENSA_SLOT6_ALT: 5871 case BFD_RELOC_XTENSA_SLOT7_ALT: 5872 case BFD_RELOC_XTENSA_SLOT8_ALT: 5873 case BFD_RELOC_XTENSA_SLOT9_ALT: 5874 case BFD_RELOC_XTENSA_SLOT10_ALT: 5875 case BFD_RELOC_XTENSA_SLOT11_ALT: 5876 case BFD_RELOC_XTENSA_SLOT12_ALT: 5877 case BFD_RELOC_XTENSA_SLOT13_ALT: 5878 case BFD_RELOC_XTENSA_SLOT14_ALT: 5879 /* These all need to be resolved at link-time. Do nothing now. */ 5880 break; 5881 5882 case BFD_RELOC_VTABLE_INHERIT: 5883 case BFD_RELOC_VTABLE_ENTRY: 5884 fixP->fx_done = 0; 5885 break; 5886 5887 default: 5888 as_bad (_("unhandled local relocation fix %s"), 5889 bfd_get_reloc_code_name (fixP->fx_r_type)); 5890 } 5891 } 5892 5893 5894 char * 5895 md_atof (int type, char *litP, int *sizeP) 5896 { 5897 return ieee_md_atof (type, litP, sizeP, target_big_endian); 5898 } 5899 5900 5901 int 5902 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) 5903 { 5904 return total_frag_text_expansion (fragP); 5905 } 5906 5907 5908 /* Translate internal representation of relocation info to BFD target 5909 format. */ 5910 5911 arelent * 5912 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 5913 { 5914 arelent *reloc; 5915 5916 reloc = (arelent *) xmalloc (sizeof (arelent)); 5917 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5918 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5919 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 5920 5921 /* Make sure none of our internal relocations make it this far. 5922 They'd better have been fully resolved by this point. */ 5923 assert ((int) fixp->fx_r_type > 0); 5924 5925 reloc->addend = fixp->fx_offset; 5926 5927 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 5928 if (reloc->howto == NULL) 5929 { 5930 as_bad_where (fixp->fx_file, fixp->fx_line, 5931 _("cannot represent `%s' relocation in object file"), 5932 bfd_get_reloc_code_name (fixp->fx_r_type)); 5933 free (reloc->sym_ptr_ptr); 5934 free (reloc); 5935 return NULL; 5936 } 5937 5938 if (!fixp->fx_pcrel != !reloc->howto->pc_relative) 5939 as_fatal (_("internal error; cannot generate `%s' relocation"), 5940 bfd_get_reloc_code_name (fixp->fx_r_type)); 5941 5942 return reloc; 5943 } 5944 5945 5946 /* Checks for resource conflicts between instructions. */ 5947 5948 /* The func unit stuff could be implemented as bit-vectors rather 5949 than the iterative approach here. If it ends up being too 5950 slow, we will switch it. */ 5951 5952 resource_table * 5953 new_resource_table (void *data, 5954 int cycles, 5955 int nu, 5956 unit_num_copies_func uncf, 5957 opcode_num_units_func onuf, 5958 opcode_funcUnit_use_unit_func ouuf, 5959 opcode_funcUnit_use_stage_func ousf) 5960 { 5961 int i; 5962 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); 5963 rt->data = data; 5964 rt->cycles = cycles; 5965 rt->allocated_cycles = cycles; 5966 rt->num_units = nu; 5967 rt->unit_num_copies = uncf; 5968 rt->opcode_num_units = onuf; 5969 rt->opcode_unit_use = ouuf; 5970 rt->opcode_unit_stage = ousf; 5971 5972 rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); 5973 for (i = 0; i < cycles; i++) 5974 rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); 5975 5976 return rt; 5977 } 5978 5979 5980 void 5981 clear_resource_table (resource_table *rt) 5982 { 5983 int i, j; 5984 for (i = 0; i < rt->allocated_cycles; i++) 5985 for (j = 0; j < rt->num_units; j++) 5986 rt->units[i][j] = 0; 5987 } 5988 5989 5990 /* We never shrink it, just fake it into thinking so. */ 5991 5992 void 5993 resize_resource_table (resource_table *rt, int cycles) 5994 { 5995 int i, old_cycles; 5996 5997 rt->cycles = cycles; 5998 if (cycles <= rt->allocated_cycles) 5999 return; 6000 6001 old_cycles = rt->allocated_cycles; 6002 rt->allocated_cycles = cycles; 6003 6004 rt->units = xrealloc (rt->units, 6005 rt->allocated_cycles * sizeof (unsigned char *)); 6006 for (i = 0; i < old_cycles; i++) 6007 rt->units[i] = xrealloc (rt->units[i], 6008 rt->num_units * sizeof (unsigned char)); 6009 for (i = old_cycles; i < cycles; i++) 6010 rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); 6011 } 6012 6013 6014 bfd_boolean 6015 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) 6016 { 6017 int i; 6018 int uses = (rt->opcode_num_units) (rt->data, opcode); 6019 6020 for (i = 0; i < uses; i++) 6021 { 6022 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6023 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6024 int copies_in_use = rt->units[stage + cycle][unit]; 6025 int copies = (rt->unit_num_copies) (rt->data, unit); 6026 if (copies_in_use >= copies) 6027 return FALSE; 6028 } 6029 return TRUE; 6030 } 6031 6032 6033 void 6034 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6035 { 6036 int i; 6037 int uses = (rt->opcode_num_units) (rt->data, opcode); 6038 6039 for (i = 0; i < uses; i++) 6040 { 6041 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6042 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6043 /* Note that this allows resources to be oversubscribed. That's 6044 essential to the way the optional scheduler works. 6045 resources_available reports when a resource is over-subscribed, 6046 so it's easy to tell. */ 6047 rt->units[stage + cycle][unit]++; 6048 } 6049 } 6050 6051 6052 void 6053 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6054 { 6055 int i; 6056 int uses = (rt->opcode_num_units) (rt->data, opcode); 6057 6058 for (i = 0; i < uses; i++) 6059 { 6060 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6061 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6062 assert (rt->units[stage + cycle][unit] > 0); 6063 rt->units[stage + cycle][unit]--; 6064 } 6065 } 6066 6067 6068 /* Wrapper functions make parameterized resource reservation 6069 more convenient. */ 6070 6071 int 6072 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) 6073 { 6074 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6075 return use->unit; 6076 } 6077 6078 6079 int 6080 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) 6081 { 6082 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6083 return use->stage; 6084 } 6085 6086 6087 /* Note that this function does not check issue constraints, but 6088 solely whether the hardware is available to execute the given 6089 instructions together. It also doesn't check if the tinsns 6090 write the same state, or access the same tieports. That is 6091 checked by check_t1_t2_reads_and_writes. */ 6092 6093 static bfd_boolean 6094 resources_conflict (vliw_insn *vinsn) 6095 { 6096 int i; 6097 static resource_table *rt = NULL; 6098 6099 /* This is the most common case by far. Optimize it. */ 6100 if (vinsn->num_slots == 1) 6101 return FALSE; 6102 6103 if (rt == NULL) 6104 { 6105 xtensa_isa isa = xtensa_default_isa; 6106 rt = new_resource_table 6107 (isa, xtensa_num_pipe_stages, 6108 xtensa_isa_num_funcUnits (isa), 6109 (unit_num_copies_func) xtensa_funcUnit_num_copies, 6110 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, 6111 opcode_funcUnit_use_unit, 6112 opcode_funcUnit_use_stage); 6113 } 6114 6115 clear_resource_table (rt); 6116 6117 for (i = 0; i < vinsn->num_slots; i++) 6118 { 6119 if (!resources_available (rt, vinsn->slots[i].opcode, 0)) 6120 return TRUE; 6121 reserve_resources (rt, vinsn->slots[i].opcode, 0); 6122 } 6123 6124 return FALSE; 6125 } 6126 6127 6128 /* finish_vinsn, emit_single_op and helper functions. */ 6129 6130 static bfd_boolean find_vinsn_conflicts (vliw_insn *); 6131 static xtensa_format xg_find_narrowest_format (vliw_insn *); 6132 static void xg_assemble_vliw_tokens (vliw_insn *); 6133 6134 6135 /* We have reached the end of a bundle; emit into the frag. */ 6136 6137 static void 6138 finish_vinsn (vliw_insn *vinsn) 6139 { 6140 IStack slotstack; 6141 int i; 6142 char *file_name; 6143 unsigned line; 6144 6145 if (find_vinsn_conflicts (vinsn)) 6146 { 6147 xg_clear_vinsn (vinsn); 6148 return; 6149 } 6150 6151 /* First, find a format that works. */ 6152 if (vinsn->format == XTENSA_UNDEFINED) 6153 vinsn->format = xg_find_narrowest_format (vinsn); 6154 6155 if (vinsn->format == XTENSA_UNDEFINED) 6156 { 6157 as_where (&file_name, &line); 6158 as_bad_where (file_name, line, 6159 _("couldn't find a valid instruction format")); 6160 fprintf (stderr, _(" ops were: ")); 6161 for (i = 0; i < vinsn->num_slots; i++) 6162 fprintf (stderr, _(" %s;"), 6163 xtensa_opcode_name (xtensa_default_isa, 6164 vinsn->slots[i].opcode)); 6165 fprintf (stderr, _("\n")); 6166 xg_clear_vinsn (vinsn); 6167 return; 6168 } 6169 6170 if (vinsn->num_slots 6171 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) 6172 { 6173 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), 6174 xtensa_format_name (xtensa_default_isa, vinsn->format), 6175 xtensa_format_num_slots (xtensa_default_isa, vinsn->format), 6176 vinsn->num_slots); 6177 xg_clear_vinsn (vinsn); 6178 return; 6179 } 6180 6181 if (resources_conflict (vinsn)) 6182 { 6183 as_where (&file_name, &line); 6184 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 6185 fprintf (stderr, " ops were: "); 6186 for (i = 0; i < vinsn->num_slots; i++) 6187 fprintf (stderr, " %s;", 6188 xtensa_opcode_name (xtensa_default_isa, 6189 vinsn->slots[i].opcode)); 6190 fprintf (stderr, "\n"); 6191 xg_clear_vinsn (vinsn); 6192 return; 6193 } 6194 6195 for (i = 0; i < vinsn->num_slots; i++) 6196 { 6197 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) 6198 { 6199 symbolS *lit_sym = NULL; 6200 int j; 6201 bfd_boolean e = FALSE; 6202 bfd_boolean saved_density = density_supported; 6203 6204 /* We don't want to narrow ops inside multi-slot bundles. */ 6205 if (vinsn->num_slots > 1) 6206 density_supported = FALSE; 6207 6208 istack_init (&slotstack); 6209 if (vinsn->slots[i].opcode == xtensa_nop_opcode) 6210 { 6211 vinsn->slots[i].opcode = 6212 xtensa_format_slot_nop_opcode (xtensa_default_isa, 6213 vinsn->format, i); 6214 vinsn->slots[i].ntok = 0; 6215 } 6216 6217 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) 6218 { 6219 e = TRUE; 6220 continue; 6221 } 6222 6223 density_supported = saved_density; 6224 6225 if (e) 6226 { 6227 xg_clear_vinsn (vinsn); 6228 return; 6229 } 6230 6231 for (j = 0; j < slotstack.ninsn; j++) 6232 { 6233 TInsn *insn = &slotstack.insn[j]; 6234 if (insn->insn_type == ITYPE_LITERAL) 6235 { 6236 assert (lit_sym == NULL); 6237 lit_sym = xg_assemble_literal (insn); 6238 } 6239 else 6240 { 6241 assert (insn->insn_type == ITYPE_INSN); 6242 if (lit_sym) 6243 xg_resolve_literals (insn, lit_sym); 6244 if (j != slotstack.ninsn - 1) 6245 emit_single_op (insn); 6246 } 6247 } 6248 6249 if (vinsn->num_slots > 1) 6250 { 6251 if (opcode_fits_format_slot 6252 (slotstack.insn[slotstack.ninsn - 1].opcode, 6253 vinsn->format, i)) 6254 { 6255 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; 6256 } 6257 else 6258 { 6259 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); 6260 if (vinsn->format == XTENSA_UNDEFINED) 6261 vinsn->slots[i].opcode = xtensa_nop_opcode; 6262 else 6263 vinsn->slots[i].opcode 6264 = xtensa_format_slot_nop_opcode (xtensa_default_isa, 6265 vinsn->format, i); 6266 6267 vinsn->slots[i].ntok = 0; 6268 } 6269 } 6270 else 6271 { 6272 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; 6273 vinsn->format = XTENSA_UNDEFINED; 6274 } 6275 } 6276 } 6277 6278 /* Now check resource conflicts on the modified bundle. */ 6279 if (resources_conflict (vinsn)) 6280 { 6281 as_where (&file_name, &line); 6282 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 6283 fprintf (stderr, " ops were: "); 6284 for (i = 0; i < vinsn->num_slots; i++) 6285 fprintf (stderr, " %s;", 6286 xtensa_opcode_name (xtensa_default_isa, 6287 vinsn->slots[i].opcode)); 6288 fprintf (stderr, "\n"); 6289 xg_clear_vinsn (vinsn); 6290 return; 6291 } 6292 6293 /* First, find a format that works. */ 6294 if (vinsn->format == XTENSA_UNDEFINED) 6295 vinsn->format = xg_find_narrowest_format (vinsn); 6296 6297 xg_assemble_vliw_tokens (vinsn); 6298 6299 xg_clear_vinsn (vinsn); 6300 } 6301 6302 6303 /* Given an vliw instruction, what conflicts are there in register 6304 usage and in writes to states and queues? 6305 6306 This function does two things: 6307 1. Reports an error when a vinsn contains illegal combinations 6308 of writes to registers states or queues. 6309 2. Marks individual tinsns as not relaxable if the combination 6310 contains antidependencies. 6311 6312 Job 2 handles things like swap semantics in instructions that need 6313 to be relaxed. For example, 6314 6315 addi a0, a1, 100000 6316 6317 normally would be relaxed to 6318 6319 l32r a0, some_label 6320 add a0, a1, a0 6321 6322 _but_, if the above instruction is bundled with an a0 reader, e.g., 6323 6324 { addi a0, a1, 10000 ; add a2, a0, a4 ; } 6325 6326 then we can't relax it into 6327 6328 l32r a0, some_label 6329 { add a0, a1, a0 ; add a2, a0, a4 ; } 6330 6331 because the value of a0 is trashed before the second add can read it. */ 6332 6333 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); 6334 6335 static bfd_boolean 6336 find_vinsn_conflicts (vliw_insn *vinsn) 6337 { 6338 int i, j; 6339 int branches = 0; 6340 xtensa_isa isa = xtensa_default_isa; 6341 6342 assert (!past_xtensa_end); 6343 6344 for (i = 0 ; i < vinsn->num_slots; i++) 6345 { 6346 TInsn *op1 = &vinsn->slots[i]; 6347 if (op1->is_specific_opcode) 6348 op1->keep_wide = TRUE; 6349 else 6350 op1->keep_wide = FALSE; 6351 } 6352 6353 for (i = 0 ; i < vinsn->num_slots; i++) 6354 { 6355 TInsn *op1 = &vinsn->slots[i]; 6356 6357 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) 6358 branches++; 6359 6360 for (j = 0; j < vinsn->num_slots; j++) 6361 { 6362 if (i != j) 6363 { 6364 TInsn *op2 = &vinsn->slots[j]; 6365 char conflict_type = check_t1_t2_reads_and_writes (op1, op2); 6366 switch (conflict_type) 6367 { 6368 case 'c': 6369 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), 6370 xtensa_opcode_name (isa, op1->opcode), i, 6371 xtensa_opcode_name (isa, op2->opcode), j); 6372 return TRUE; 6373 case 'd': 6374 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), 6375 xtensa_opcode_name (isa, op1->opcode), i, 6376 xtensa_opcode_name (isa, op2->opcode), j); 6377 return TRUE; 6378 case 'e': 6379 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), 6380 xtensa_opcode_name (isa, op1->opcode), i, 6381 xtensa_opcode_name (isa, op2->opcode), j); 6382 return TRUE; 6383 case 'f': 6384 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), 6385 xtensa_opcode_name (isa, op1->opcode), i, 6386 xtensa_opcode_name (isa, op2->opcode), j); 6387 return TRUE; 6388 default: 6389 /* Everything is OK. */ 6390 break; 6391 } 6392 op2->is_specific_opcode = (op2->is_specific_opcode 6393 || conflict_type == 'a'); 6394 } 6395 } 6396 } 6397 6398 if (branches > 1) 6399 { 6400 as_bad (_("multiple branches or jumps in the same bundle")); 6401 return TRUE; 6402 } 6403 6404 return FALSE; 6405 } 6406 6407 6408 /* Check how the state used by t1 and t2 relate. 6409 Cases found are: 6410 6411 case A: t1 reads a register t2 writes (an antidependency within a bundle) 6412 case B: no relationship between what is read and written (both could 6413 read the same reg though) 6414 case C: t1 writes a register t2 writes (a register conflict within a 6415 bundle) 6416 case D: t1 writes a state that t2 also writes 6417 case E: t1 writes a tie queue that t2 also writes 6418 case F: two volatile queue accesses 6419 */ 6420 6421 static char 6422 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) 6423 { 6424 xtensa_isa isa = xtensa_default_isa; 6425 xtensa_regfile t1_regfile, t2_regfile; 6426 int t1_reg, t2_reg; 6427 int t1_base_reg, t1_last_reg; 6428 int t2_base_reg, t2_last_reg; 6429 char t1_inout, t2_inout; 6430 int i, j; 6431 char conflict = 'b'; 6432 int t1_states; 6433 int t2_states; 6434 int t1_interfaces; 6435 int t2_interfaces; 6436 bfd_boolean t1_volatile = FALSE; 6437 bfd_boolean t2_volatile = FALSE; 6438 6439 /* Check registers. */ 6440 for (j = 0; j < t2->ntok; j++) 6441 { 6442 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) 6443 continue; 6444 6445 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); 6446 t2_base_reg = t2->tok[j].X_add_number; 6447 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); 6448 6449 for (i = 0; i < t1->ntok; i++) 6450 { 6451 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) 6452 continue; 6453 6454 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); 6455 6456 if (t1_regfile != t2_regfile) 6457 continue; 6458 6459 t1_inout = xtensa_operand_inout (isa, t1->opcode, i); 6460 t2_inout = xtensa_operand_inout (isa, t2->opcode, j); 6461 6462 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 6463 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) 6464 { 6465 if (t1_inout == 'm' || t1_inout == 'o' 6466 || t2_inout == 'm' || t2_inout == 'o') 6467 { 6468 conflict = 'a'; 6469 continue; 6470 } 6471 } 6472 6473 t1_base_reg = t1->tok[i].X_add_number; 6474 t1_last_reg = (t1_base_reg 6475 + xtensa_operand_num_regs (isa, t1->opcode, i)); 6476 6477 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 6478 { 6479 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 6480 { 6481 if (t1_reg != t2_reg) 6482 continue; 6483 6484 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6485 { 6486 conflict = 'a'; 6487 continue; 6488 } 6489 6490 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6491 { 6492 conflict = 'a'; 6493 continue; 6494 } 6495 6496 if (t1_inout != 'i' && t2_inout != 'i') 6497 return 'c'; 6498 } 6499 } 6500 } 6501 } 6502 6503 /* Check states. */ 6504 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); 6505 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); 6506 for (j = 0; j < t2_states; j++) 6507 { 6508 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); 6509 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); 6510 for (i = 0; i < t1_states; i++) 6511 { 6512 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); 6513 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); 6514 if (t1_so != t2_so) 6515 continue; 6516 6517 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6518 { 6519 conflict = 'a'; 6520 continue; 6521 } 6522 6523 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6524 { 6525 conflict = 'a'; 6526 continue; 6527 } 6528 6529 if (t1_inout != 'i' && t2_inout != 'i') 6530 return 'd'; 6531 } 6532 } 6533 6534 /* Check tieports. */ 6535 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); 6536 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); 6537 for (j = 0; j < t2_interfaces; j++) 6538 { 6539 xtensa_interface t2_int 6540 = xtensa_interfaceOperand_interface (isa, t2->opcode, j); 6541 int t2_class = xtensa_interface_class_id (isa, t2_int); 6542 6543 t2_inout = xtensa_interface_inout (isa, t2_int); 6544 if (xtensa_interface_has_side_effect (isa, t2_int) == 1) 6545 t2_volatile = TRUE; 6546 6547 for (i = 0; i < t1_interfaces; i++) 6548 { 6549 xtensa_interface t1_int 6550 = xtensa_interfaceOperand_interface (isa, t1->opcode, j); 6551 int t1_class = xtensa_interface_class_id (isa, t1_int); 6552 6553 t1_inout = xtensa_interface_inout (isa, t1_int); 6554 if (xtensa_interface_has_side_effect (isa, t1_int) == 1) 6555 t1_volatile = TRUE; 6556 6557 if (t1_volatile && t2_volatile && (t1_class == t2_class)) 6558 return 'f'; 6559 6560 if (t1_int != t2_int) 6561 continue; 6562 6563 if (t2_inout == 'i' && t1_inout == 'o') 6564 { 6565 conflict = 'a'; 6566 continue; 6567 } 6568 6569 if (t1_inout == 'i' && t2_inout == 'o') 6570 { 6571 conflict = 'a'; 6572 continue; 6573 } 6574 6575 if (t1_inout != 'i' && t2_inout != 'i') 6576 return 'e'; 6577 } 6578 } 6579 6580 return conflict; 6581 } 6582 6583 6584 static xtensa_format 6585 xg_find_narrowest_format (vliw_insn *vinsn) 6586 { 6587 /* Right now we assume that the ops within the vinsn are properly 6588 ordered for the slots that the programmer wanted them in. In 6589 other words, we don't rearrange the ops in hopes of finding a 6590 better format. The scheduler handles that. */ 6591 6592 xtensa_isa isa = xtensa_default_isa; 6593 xtensa_format format; 6594 vliw_insn v_copy = *vinsn; 6595 xtensa_opcode nop_opcode = xtensa_nop_opcode; 6596 6597 if (vinsn->num_slots == 1) 6598 return xg_get_single_format (vinsn->slots[0].opcode); 6599 6600 for (format = 0; format < xtensa_isa_num_formats (isa); format++) 6601 { 6602 v_copy = *vinsn; 6603 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) 6604 { 6605 int slot; 6606 int fit = 0; 6607 for (slot = 0; slot < v_copy.num_slots; slot++) 6608 { 6609 if (v_copy.slots[slot].opcode == nop_opcode) 6610 { 6611 v_copy.slots[slot].opcode = 6612 xtensa_format_slot_nop_opcode (isa, format, slot); 6613 v_copy.slots[slot].ntok = 0; 6614 } 6615 6616 if (opcode_fits_format_slot (v_copy.slots[slot].opcode, 6617 format, slot)) 6618 fit++; 6619 else if (v_copy.num_slots > 1) 6620 { 6621 TInsn widened; 6622 /* Try the widened version. */ 6623 if (!v_copy.slots[slot].keep_wide 6624 && !v_copy.slots[slot].is_specific_opcode 6625 && xg_is_single_relaxable_insn (&v_copy.slots[slot], 6626 &widened, TRUE) 6627 && opcode_fits_format_slot (widened.opcode, 6628 format, slot)) 6629 { 6630 v_copy.slots[slot] = widened; 6631 fit++; 6632 } 6633 } 6634 } 6635 if (fit == v_copy.num_slots) 6636 { 6637 *vinsn = v_copy; 6638 xtensa_format_encode (isa, format, vinsn->insnbuf); 6639 vinsn->format = format; 6640 break; 6641 } 6642 } 6643 } 6644 6645 if (format == xtensa_isa_num_formats (isa)) 6646 return XTENSA_UNDEFINED; 6647 6648 return format; 6649 } 6650 6651 6652 /* Return the additional space needed in a frag 6653 for possible relaxations of any ops in a VLIW insn. 6654 Also fill out the relaxations that might be required of 6655 each tinsn in the vinsn. */ 6656 6657 static int 6658 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) 6659 { 6660 bfd_boolean finish_frag = FALSE; 6661 int extra_space = 0; 6662 int slot; 6663 6664 for (slot = 0; slot < vinsn->num_slots; slot++) 6665 { 6666 TInsn *tinsn = &vinsn->slots[slot]; 6667 if (!tinsn_has_symbolic_operands (tinsn)) 6668 { 6669 /* A narrow instruction could be widened later to help 6670 alignment issues. */ 6671 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) 6672 && !tinsn->is_specific_opcode 6673 && vinsn->num_slots == 1) 6674 { 6675 /* Difference in bytes between narrow and wide insns... */ 6676 extra_space += 1; 6677 tinsn->subtype = RELAX_NARROW; 6678 } 6679 } 6680 else 6681 { 6682 if (workaround_b_j_loop_end 6683 && tinsn->opcode == xtensa_jx_opcode 6684 && use_transform ()) 6685 { 6686 /* Add 2 of these. */ 6687 extra_space += 3; /* for the nop size */ 6688 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; 6689 } 6690 6691 /* Need to assemble it with space for the relocation. */ 6692 if (xg_is_relaxable_insn (tinsn, 0) 6693 && !tinsn->is_specific_opcode) 6694 { 6695 int max_size = xg_get_max_insn_widen_size (tinsn->opcode); 6696 int max_literal_size = 6697 xg_get_max_insn_widen_literal_size (tinsn->opcode); 6698 6699 tinsn->literal_space = max_literal_size; 6700 6701 tinsn->subtype = RELAX_IMMED; 6702 extra_space += max_size; 6703 } 6704 else 6705 { 6706 /* A fix record will be added for this instruction prior 6707 to relaxation, so make it end the frag. */ 6708 finish_frag = TRUE; 6709 } 6710 } 6711 } 6712 *pfinish_frag = finish_frag; 6713 return extra_space; 6714 } 6715 6716 6717 static void 6718 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) 6719 { 6720 xtensa_isa isa = xtensa_default_isa; 6721 int slot, chosen_slot; 6722 6723 vinsn->format = xg_get_single_format (tinsn->opcode); 6724 assert (vinsn->format != XTENSA_UNDEFINED); 6725 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); 6726 6727 chosen_slot = xg_get_single_slot (tinsn->opcode); 6728 for (slot = 0; slot < vinsn->num_slots; slot++) 6729 { 6730 if (slot == chosen_slot) 6731 vinsn->slots[slot] = *tinsn; 6732 else 6733 { 6734 vinsn->slots[slot].opcode = 6735 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); 6736 vinsn->slots[slot].ntok = 0; 6737 vinsn->slots[slot].insn_type = ITYPE_INSN; 6738 } 6739 } 6740 } 6741 6742 6743 static bfd_boolean 6744 emit_single_op (TInsn *orig_insn) 6745 { 6746 int i; 6747 IStack istack; /* put instructions into here */ 6748 symbolS *lit_sym = NULL; 6749 symbolS *label_sym = NULL; 6750 6751 istack_init (&istack); 6752 6753 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. 6754 Because the scheduling and bundling characteristics of movi and 6755 l32r or const16 are so different, we can do much better if we relax 6756 it prior to scheduling and bundling, rather than after. */ 6757 if ((orig_insn->opcode == xtensa_movi_opcode 6758 || orig_insn->opcode == xtensa_movi_n_opcode) 6759 && !cur_vinsn.inside_bundle 6760 && (orig_insn->tok[1].X_op == O_symbol 6761 || orig_insn->tok[1].X_op == O_pltrel 6762 || orig_insn->tok[1].X_op == O_tlsfunc 6763 || orig_insn->tok[1].X_op == O_tlsarg 6764 || orig_insn->tok[1].X_op == O_tpoff 6765 || orig_insn->tok[1].X_op == O_dtpoff) 6766 && !orig_insn->is_specific_opcode && use_transform ()) 6767 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); 6768 else 6769 if (xg_expand_assembly_insn (&istack, orig_insn)) 6770 return TRUE; 6771 6772 for (i = 0; i < istack.ninsn; i++) 6773 { 6774 TInsn *insn = &istack.insn[i]; 6775 switch (insn->insn_type) 6776 { 6777 case ITYPE_LITERAL: 6778 assert (lit_sym == NULL); 6779 lit_sym = xg_assemble_literal (insn); 6780 break; 6781 case ITYPE_LABEL: 6782 { 6783 static int relaxed_sym_idx = 0; 6784 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); 6785 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); 6786 colon (label); 6787 assert (label_sym == NULL); 6788 label_sym = symbol_find_or_make (label); 6789 assert (label_sym); 6790 free (label); 6791 } 6792 break; 6793 case ITYPE_INSN: 6794 { 6795 vliw_insn v; 6796 if (lit_sym) 6797 xg_resolve_literals (insn, lit_sym); 6798 if (label_sym) 6799 xg_resolve_labels (insn, label_sym); 6800 xg_init_vinsn (&v); 6801 bundle_tinsn (insn, &v); 6802 finish_vinsn (&v); 6803 xg_free_vinsn (&v); 6804 } 6805 break; 6806 default: 6807 assert (0); 6808 break; 6809 } 6810 } 6811 return FALSE; 6812 } 6813 6814 6815 static int 6816 total_frag_text_expansion (fragS *fragP) 6817 { 6818 int slot; 6819 int total_expansion = 0; 6820 6821 for (slot = 0; slot < MAX_SLOTS; slot++) 6822 total_expansion += fragP->tc_frag_data.text_expansion[slot]; 6823 6824 return total_expansion; 6825 } 6826 6827 6828 /* Emit a vliw instruction to the current fragment. */ 6829 6830 static void 6831 xg_assemble_vliw_tokens (vliw_insn *vinsn) 6832 { 6833 bfd_boolean finish_frag; 6834 bfd_boolean is_jump = FALSE; 6835 bfd_boolean is_branch = FALSE; 6836 xtensa_isa isa = xtensa_default_isa; 6837 int insn_size; 6838 int extra_space; 6839 char *f = NULL; 6840 int slot; 6841 struct dwarf2_line_info debug_line; 6842 bfd_boolean loc_directive_seen = FALSE; 6843 TInsn *tinsn; 6844 6845 memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); 6846 6847 if (generating_literals) 6848 { 6849 static int reported = 0; 6850 if (reported < 4) 6851 as_bad_where (frag_now->fr_file, frag_now->fr_line, 6852 _("cannot assemble into a literal fragment")); 6853 if (reported == 3) 6854 as_bad (_("...")); 6855 reported++; 6856 return; 6857 } 6858 6859 if (frag_now_fix () != 0 6860 && (! frag_now->tc_frag_data.is_insn 6861 || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 6862 || !use_transform () != frag_now->tc_frag_data.is_no_transform 6863 || (directive_state[directive_longcalls] 6864 != frag_now->tc_frag_data.use_longcalls) 6865 || (directive_state[directive_absolute_literals] 6866 != frag_now->tc_frag_data.use_absolute_literals))) 6867 { 6868 frag_wane (frag_now); 6869 frag_new (0); 6870 xtensa_set_frag_assembly_state (frag_now); 6871 } 6872 6873 if (workaround_a0_b_retw 6874 && vinsn->num_slots == 1 6875 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 6876 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 6877 && use_transform ()) 6878 { 6879 has_a0_b_retw = TRUE; 6880 6881 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. 6882 After the first assembly pass we will check all of them and 6883 add a nop if needed. */ 6884 frag_now->tc_frag_data.is_insn = TRUE; 6885 frag_var (rs_machine_dependent, 4, 4, 6886 RELAX_ADD_NOP_IF_A0_B_RETW, 6887 frag_now->fr_symbol, 6888 frag_now->fr_offset, 6889 NULL); 6890 xtensa_set_frag_assembly_state (frag_now); 6891 frag_now->tc_frag_data.is_insn = TRUE; 6892 frag_var (rs_machine_dependent, 4, 4, 6893 RELAX_ADD_NOP_IF_A0_B_RETW, 6894 frag_now->fr_symbol, 6895 frag_now->fr_offset, 6896 NULL); 6897 xtensa_set_frag_assembly_state (frag_now); 6898 } 6899 6900 for (slot = 0; slot < vinsn->num_slots; slot++) 6901 { 6902 tinsn = &vinsn->slots[slot]; 6903 6904 /* See if the instruction implies an aligned section. */ 6905 if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) 6906 record_alignment (now_seg, 2); 6907 6908 /* Determine the best line number for debug info. */ 6909 if ((tinsn->loc_directive_seen || !loc_directive_seen) 6910 && (tinsn->debug_line.filenum != debug_line.filenum 6911 || tinsn->debug_line.line < debug_line.line 6912 || tinsn->debug_line.column < debug_line.column)) 6913 debug_line = tinsn->debug_line; 6914 if (tinsn->loc_directive_seen) 6915 loc_directive_seen = TRUE; 6916 } 6917 6918 /* Special cases for instructions that force an alignment... */ 6919 /* None of these opcodes are bundle-able. */ 6920 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) 6921 { 6922 int max_fill; 6923 6924 /* Remember the symbol that marks the end of the loop in the frag 6925 that marks the start of the loop. This way we can easily find 6926 the end of the loop at the beginning, without adding special code 6927 to mark the loop instructions themselves. */ 6928 symbolS *target_sym = NULL; 6929 if (vinsn->slots[0].tok[1].X_op == O_symbol) 6930 target_sym = vinsn->slots[0].tok[1].X_add_symbol; 6931 6932 xtensa_set_frag_assembly_state (frag_now); 6933 frag_now->tc_frag_data.is_insn = TRUE; 6934 6935 max_fill = get_text_align_max_fill_size 6936 (get_text_align_power (xtensa_fetch_width), 6937 TRUE, frag_now->tc_frag_data.is_no_density); 6938 6939 if (use_transform ()) 6940 frag_var (rs_machine_dependent, max_fill, max_fill, 6941 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 6942 else 6943 frag_var (rs_machine_dependent, 0, 0, 6944 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 6945 xtensa_set_frag_assembly_state (frag_now); 6946 } 6947 6948 if (vinsn->slots[0].opcode == xtensa_entry_opcode 6949 && !vinsn->slots[0].is_specific_opcode) 6950 { 6951 xtensa_mark_literal_pool_location (); 6952 xtensa_move_labels (frag_now, 0); 6953 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); 6954 } 6955 6956 if (vinsn->num_slots == 1) 6957 { 6958 if (workaround_a0_b_retw && use_transform ()) 6959 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, 6960 is_register_writer (&vinsn->slots[0], "a", 0)); 6961 6962 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, 6963 is_bad_loopend_opcode (&vinsn->slots[0])); 6964 } 6965 else 6966 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); 6967 6968 insn_size = xtensa_format_length (isa, vinsn->format); 6969 6970 extra_space = relaxation_requirements (vinsn, &finish_frag); 6971 6972 /* vinsn_to_insnbuf will produce the error. */ 6973 if (vinsn->format != XTENSA_UNDEFINED) 6974 { 6975 f = frag_more (insn_size + extra_space); 6976 xtensa_set_frag_assembly_state (frag_now); 6977 frag_now->tc_frag_data.is_insn = TRUE; 6978 } 6979 6980 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); 6981 if (vinsn->format == XTENSA_UNDEFINED) 6982 return; 6983 6984 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); 6985 6986 if (debug_type == DEBUG_DWARF2 || loc_directive_seen) 6987 dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), 6988 &debug_line); 6989 6990 for (slot = 0; slot < vinsn->num_slots; slot++) 6991 { 6992 tinsn = &vinsn->slots[slot]; 6993 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; 6994 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; 6995 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; 6996 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; 6997 if (tinsn->literal_space != 0) 6998 xg_assemble_literal_space (tinsn->literal_space, slot); 6999 7000 if (tinsn->subtype == RELAX_NARROW) 7001 assert (vinsn->num_slots == 1); 7002 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) 7003 is_jump = TRUE; 7004 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) 7005 is_branch = TRUE; 7006 7007 if (tinsn->subtype || tinsn->symbol || tinsn->offset 7008 || tinsn->literal_frag || is_jump || is_branch) 7009 finish_frag = TRUE; 7010 } 7011 7012 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7013 frag_now->tc_frag_data.is_specific_opcode = TRUE; 7014 7015 if (finish_frag) 7016 { 7017 frag_variant (rs_machine_dependent, 7018 extra_space, extra_space, RELAX_SLOTS, 7019 frag_now->fr_symbol, frag_now->fr_offset, f); 7020 xtensa_set_frag_assembly_state (frag_now); 7021 } 7022 7023 /* Special cases for loops: 7024 close_loop_end should be inserted AFTER short_loop. 7025 Make sure that CLOSE loops are processed BEFORE short_loops 7026 when converting them. */ 7027 7028 /* "short_loop": Add a NOP if the loop is < 4 bytes. */ 7029 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 7030 && !vinsn->slots[0].is_specific_opcode) 7031 { 7032 if (workaround_short_loop && use_transform ()) 7033 { 7034 maybe_has_short_loop = TRUE; 7035 frag_now->tc_frag_data.is_insn = TRUE; 7036 frag_var (rs_machine_dependent, 4, 4, 7037 RELAX_ADD_NOP_IF_SHORT_LOOP, 7038 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7039 frag_now->tc_frag_data.is_insn = TRUE; 7040 frag_var (rs_machine_dependent, 4, 4, 7041 RELAX_ADD_NOP_IF_SHORT_LOOP, 7042 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7043 } 7044 7045 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a 7046 loop at least 12 bytes away from another loop's end. */ 7047 if (workaround_close_loop_end && use_transform ()) 7048 { 7049 maybe_has_close_loop_end = TRUE; 7050 frag_now->tc_frag_data.is_insn = TRUE; 7051 frag_var (rs_machine_dependent, 12, 12, 7052 RELAX_ADD_NOP_IF_CLOSE_LOOP_END, 7053 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7054 } 7055 } 7056 7057 if (use_transform ()) 7058 { 7059 if (is_jump) 7060 { 7061 assert (finish_frag); 7062 frag_var (rs_machine_dependent, 7063 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, 7064 RELAX_UNREACHABLE, 7065 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7066 xtensa_set_frag_assembly_state (frag_now); 7067 } 7068 else if (is_branch && do_align_targets ()) 7069 { 7070 assert (finish_frag); 7071 frag_var (rs_machine_dependent, 7072 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, 7073 RELAX_MAYBE_UNREACHABLE, 7074 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7075 xtensa_set_frag_assembly_state (frag_now); 7076 frag_var (rs_machine_dependent, 7077 0, 0, 7078 RELAX_MAYBE_DESIRE_ALIGN, 7079 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7080 xtensa_set_frag_assembly_state (frag_now); 7081 } 7082 } 7083 7084 /* Now, if the original opcode was a call... */ 7085 if (do_align_targets () 7086 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) 7087 { 7088 float freq = get_subseg_total_freq (now_seg, now_subseg); 7089 frag_now->tc_frag_data.is_insn = TRUE; 7090 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, 7091 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7092 xtensa_set_frag_assembly_state (frag_now); 7093 } 7094 7095 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7096 { 7097 frag_wane (frag_now); 7098 frag_new (0); 7099 xtensa_set_frag_assembly_state (frag_now); 7100 } 7101 } 7102 7103 7104 /* xtensa_end and helper functions. */ 7105 7106 static void xtensa_cleanup_align_frags (void); 7107 static void xtensa_fix_target_frags (void); 7108 static void xtensa_mark_narrow_branches (void); 7109 static void xtensa_mark_zcl_first_insns (void); 7110 static void xtensa_mark_difference_of_two_symbols (void); 7111 static void xtensa_fix_a0_b_retw_frags (void); 7112 static void xtensa_fix_b_j_loop_end_frags (void); 7113 static void xtensa_fix_close_loop_end_frags (void); 7114 static void xtensa_fix_short_loop_frags (void); 7115 static void xtensa_sanity_check (void); 7116 static void xtensa_add_config_info (void); 7117 7118 void 7119 xtensa_end (void) 7120 { 7121 directive_balance (); 7122 xtensa_flush_pending_output (); 7123 7124 past_xtensa_end = TRUE; 7125 7126 xtensa_move_literals (); 7127 7128 xtensa_reorder_segments (); 7129 xtensa_cleanup_align_frags (); 7130 xtensa_fix_target_frags (); 7131 if (workaround_a0_b_retw && has_a0_b_retw) 7132 xtensa_fix_a0_b_retw_frags (); 7133 if (workaround_b_j_loop_end) 7134 xtensa_fix_b_j_loop_end_frags (); 7135 7136 /* "close_loop_end" should be processed BEFORE "short_loop". */ 7137 if (workaround_close_loop_end && maybe_has_close_loop_end) 7138 xtensa_fix_close_loop_end_frags (); 7139 7140 if (workaround_short_loop && maybe_has_short_loop) 7141 xtensa_fix_short_loop_frags (); 7142 if (align_targets) 7143 xtensa_mark_narrow_branches (); 7144 xtensa_mark_zcl_first_insns (); 7145 7146 xtensa_sanity_check (); 7147 7148 xtensa_add_config_info (); 7149 } 7150 7151 7152 static void 7153 xtensa_cleanup_align_frags (void) 7154 { 7155 frchainS *frchP; 7156 asection *s; 7157 7158 for (s = stdoutput->sections; s; s = s->next) 7159 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7160 { 7161 fragS *fragP; 7162 /* Walk over all of the fragments in a subsection. */ 7163 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7164 { 7165 if ((fragP->fr_type == rs_align 7166 || fragP->fr_type == rs_align_code 7167 || (fragP->fr_type == rs_machine_dependent 7168 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN 7169 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) 7170 && fragP->fr_fix == 0) 7171 { 7172 fragS *next = fragP->fr_next; 7173 7174 while (next 7175 && next->fr_fix == 0 7176 && next->fr_type == rs_machine_dependent 7177 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 7178 { 7179 frag_wane (next); 7180 next = next->fr_next; 7181 } 7182 } 7183 /* If we don't widen branch targets, then they 7184 will be easier to align. */ 7185 if (fragP->tc_frag_data.is_branch_target 7186 && fragP->fr_opcode == fragP->fr_literal 7187 && fragP->fr_type == rs_machine_dependent 7188 && fragP->fr_subtype == RELAX_SLOTS 7189 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 7190 frag_wane (fragP); 7191 if (fragP->fr_type == rs_machine_dependent 7192 && fragP->fr_subtype == RELAX_UNREACHABLE) 7193 fragP->tc_frag_data.is_unreachable = TRUE; 7194 } 7195 } 7196 } 7197 7198 7199 /* Re-process all of the fragments looking to convert all of the 7200 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch 7201 target in the next fragment, convert this to RELAX_DESIRE_ALIGN. 7202 Otherwise, convert to a .fill 0. */ 7203 7204 static void 7205 xtensa_fix_target_frags (void) 7206 { 7207 frchainS *frchP; 7208 asection *s; 7209 7210 /* When this routine is called, all of the subsections are still intact 7211 so we walk over subsections instead of sections. */ 7212 for (s = stdoutput->sections; s; s = s->next) 7213 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7214 { 7215 fragS *fragP; 7216 7217 /* Walk over all of the fragments in a subsection. */ 7218 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7219 { 7220 if (fragP->fr_type == rs_machine_dependent 7221 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 7222 { 7223 if (next_frag_is_branch_target (fragP)) 7224 fragP->fr_subtype = RELAX_DESIRE_ALIGN; 7225 else 7226 frag_wane (fragP); 7227 } 7228 } 7229 } 7230 } 7231 7232 7233 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); 7234 7235 static void 7236 xtensa_mark_narrow_branches (void) 7237 { 7238 frchainS *frchP; 7239 asection *s; 7240 7241 for (s = stdoutput->sections; s; s = s->next) 7242 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7243 { 7244 fragS *fragP; 7245 /* Walk over all of the fragments in a subsection. */ 7246 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7247 { 7248 if (fragP->fr_type == rs_machine_dependent 7249 && fragP->fr_subtype == RELAX_SLOTS 7250 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 7251 { 7252 vliw_insn vinsn; 7253 7254 vinsn_from_chars (&vinsn, fragP->fr_opcode); 7255 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); 7256 7257 if (vinsn.num_slots == 1 7258 && xtensa_opcode_is_branch (xtensa_default_isa, 7259 vinsn.slots[0].opcode) == 1 7260 && xg_get_single_size (vinsn.slots[0].opcode) == 2 7261 && is_narrow_branch_guaranteed_in_range (fragP, 7262 &vinsn.slots[0])) 7263 { 7264 fragP->fr_subtype = RELAX_SLOTS; 7265 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; 7266 fragP->tc_frag_data.is_aligning_branch = 1; 7267 } 7268 } 7269 } 7270 } 7271 } 7272 7273 7274 /* A branch is typically widened only when its target is out of 7275 range. However, we would like to widen them to align a subsequent 7276 branch target when possible. 7277 7278 Because the branch relaxation code is so convoluted, the optimal solution 7279 (combining the two cases) is difficult to get right in all circumstances. 7280 We therefore go with an "almost as good" solution, where we only 7281 use for alignment narrow branches that definitely will not expand to a 7282 jump and a branch. These functions find and mark these cases. */ 7283 7284 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded 7285 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. 7286 We start counting beginning with the frag after the 2-byte branch, so the 7287 maximum offset is (4 - 2) + 63 = 65. */ 7288 #define MAX_IMMED6 65 7289 7290 static offsetT unrelaxed_frag_max_size (fragS *); 7291 7292 static bfd_boolean 7293 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) 7294 { 7295 const expressionS *expr = &tinsn->tok[1]; 7296 symbolS *symbolP = expr->X_add_symbol; 7297 offsetT max_distance = expr->X_add_number; 7298 fragS *target_frag; 7299 7300 if (expr->X_op != O_symbol) 7301 return FALSE; 7302 7303 target_frag = symbol_get_frag (symbolP); 7304 7305 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); 7306 if (is_branch_jmp_to_next (tinsn, fragP)) 7307 return FALSE; 7308 7309 /* The branch doesn't branch over it's own frag, 7310 but over the subsequent ones. */ 7311 fragP = fragP->fr_next; 7312 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) 7313 { 7314 max_distance += unrelaxed_frag_max_size (fragP); 7315 fragP = fragP->fr_next; 7316 } 7317 if (max_distance <= MAX_IMMED6 && fragP == target_frag) 7318 return TRUE; 7319 return FALSE; 7320 } 7321 7322 7323 static void 7324 xtensa_mark_zcl_first_insns (void) 7325 { 7326 frchainS *frchP; 7327 asection *s; 7328 7329 for (s = stdoutput->sections; s; s = s->next) 7330 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7331 { 7332 fragS *fragP; 7333 /* Walk over all of the fragments in a subsection. */ 7334 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7335 { 7336 if (fragP->fr_type == rs_machine_dependent 7337 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 7338 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 7339 { 7340 /* Find the loop frag. */ 7341 fragS *targ_frag = next_non_empty_frag (fragP); 7342 /* Find the first insn frag. */ 7343 targ_frag = next_non_empty_frag (targ_frag); 7344 7345 /* Of course, sometimes (mostly for toy test cases) a 7346 zero-cost loop instruction is the last in a section. */ 7347 if (targ_frag) 7348 { 7349 targ_frag->tc_frag_data.is_first_loop_insn = TRUE; 7350 /* Do not widen a frag that is the first instruction of a 7351 zero-cost loop. It makes that loop harder to align. */ 7352 if (targ_frag->fr_type == rs_machine_dependent 7353 && targ_frag->fr_subtype == RELAX_SLOTS 7354 && (targ_frag->tc_frag_data.slot_subtypes[0] 7355 == RELAX_NARROW)) 7356 { 7357 if (targ_frag->tc_frag_data.is_aligning_branch) 7358 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 7359 else 7360 { 7361 frag_wane (targ_frag); 7362 targ_frag->tc_frag_data.slot_subtypes[0] = 0; 7363 } 7364 } 7365 } 7366 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) 7367 frag_wane (fragP); 7368 } 7369 } 7370 } 7371 } 7372 7373 7374 /* When a difference-of-symbols expression is encoded as a uleb128 or 7375 sleb128 value, the linker is unable to adjust that value to account for 7376 link-time relaxation. Mark all the code between such symbols so that 7377 its size cannot be changed by linker relaxation. */ 7378 7379 static void 7380 xtensa_mark_difference_of_two_symbols (void) 7381 { 7382 symbolS *expr_sym; 7383 7384 for (expr_sym = expr_symbols; expr_sym; 7385 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) 7386 { 7387 expressionS *expr = symbol_get_value_expression (expr_sym); 7388 7389 if (expr->X_op == O_subtract) 7390 { 7391 symbolS *left = expr->X_add_symbol; 7392 symbolS *right = expr->X_op_symbol; 7393 7394 /* Difference of two symbols not in the same section 7395 are handled with relocations in the linker. */ 7396 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) 7397 { 7398 fragS *start; 7399 fragS *end; 7400 7401 if (symbol_get_frag (left)->fr_address 7402 <= symbol_get_frag (right)->fr_address) 7403 { 7404 start = symbol_get_frag (left); 7405 end = symbol_get_frag (right); 7406 } 7407 else 7408 { 7409 start = symbol_get_frag (right); 7410 end = symbol_get_frag (left); 7411 } 7412 do 7413 { 7414 start->tc_frag_data.is_no_transform = 1; 7415 start = start->fr_next; 7416 } 7417 while (start && start->fr_address < end->fr_address); 7418 } 7419 } 7420 } 7421 } 7422 7423 7424 /* Re-process all of the fragments looking to convert all of the 7425 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a 7426 conditional branch or a retw/retw.n, convert this frag to one that 7427 will generate a NOP. In any case close it off with a .fill 0. */ 7428 7429 static bfd_boolean next_instrs_are_b_retw (fragS *); 7430 7431 static void 7432 xtensa_fix_a0_b_retw_frags (void) 7433 { 7434 frchainS *frchP; 7435 asection *s; 7436 7437 /* When this routine is called, all of the subsections are still intact 7438 so we walk over subsections instead of sections. */ 7439 for (s = stdoutput->sections; s; s = s->next) 7440 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7441 { 7442 fragS *fragP; 7443 7444 /* Walk over all of the fragments in a subsection. */ 7445 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7446 { 7447 if (fragP->fr_type == rs_machine_dependent 7448 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) 7449 { 7450 if (next_instrs_are_b_retw (fragP)) 7451 { 7452 if (fragP->tc_frag_data.is_no_transform) 7453 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); 7454 else 7455 relax_frag_add_nop (fragP); 7456 } 7457 frag_wane (fragP); 7458 } 7459 } 7460 } 7461 } 7462 7463 7464 static bfd_boolean 7465 next_instrs_are_b_retw (fragS *fragP) 7466 { 7467 xtensa_opcode opcode; 7468 xtensa_format fmt; 7469 const fragS *next_fragP = next_non_empty_frag (fragP); 7470 static xtensa_insnbuf insnbuf = NULL; 7471 static xtensa_insnbuf slotbuf = NULL; 7472 xtensa_isa isa = xtensa_default_isa; 7473 int offset = 0; 7474 int slot; 7475 bfd_boolean branch_seen = FALSE; 7476 7477 if (!insnbuf) 7478 { 7479 insnbuf = xtensa_insnbuf_alloc (isa); 7480 slotbuf = xtensa_insnbuf_alloc (isa); 7481 } 7482 7483 if (next_fragP == NULL) 7484 return FALSE; 7485 7486 /* Check for the conditional branch. */ 7487 xtensa_insnbuf_from_chars 7488 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7489 fmt = xtensa_format_decode (isa, insnbuf); 7490 if (fmt == XTENSA_UNDEFINED) 7491 return FALSE; 7492 7493 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 7494 { 7495 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 7496 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 7497 7498 branch_seen = (branch_seen 7499 || xtensa_opcode_is_branch (isa, opcode) == 1); 7500 } 7501 7502 if (!branch_seen) 7503 return FALSE; 7504 7505 offset += xtensa_format_length (isa, fmt); 7506 if (offset == next_fragP->fr_fix) 7507 { 7508 next_fragP = next_non_empty_frag (next_fragP); 7509 offset = 0; 7510 } 7511 7512 if (next_fragP == NULL) 7513 return FALSE; 7514 7515 /* Check for the retw/retw.n. */ 7516 xtensa_insnbuf_from_chars 7517 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7518 fmt = xtensa_format_decode (isa, insnbuf); 7519 7520 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we 7521 have no problems. */ 7522 if (fmt == XTENSA_UNDEFINED 7523 || xtensa_format_num_slots (isa, fmt) != 1) 7524 return FALSE; 7525 7526 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); 7527 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); 7528 7529 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) 7530 return TRUE; 7531 7532 return FALSE; 7533 } 7534 7535 7536 /* Re-process all of the fragments looking to convert all of the 7537 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a 7538 loop end label, convert this frag to one that will generate a NOP. 7539 In any case close it off with a .fill 0. */ 7540 7541 static bfd_boolean next_instr_is_loop_end (fragS *); 7542 7543 static void 7544 xtensa_fix_b_j_loop_end_frags (void) 7545 { 7546 frchainS *frchP; 7547 asection *s; 7548 7549 /* When this routine is called, all of the subsections are still intact 7550 so we walk over subsections instead of sections. */ 7551 for (s = stdoutput->sections; s; s = s->next) 7552 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7553 { 7554 fragS *fragP; 7555 7556 /* Walk over all of the fragments in a subsection. */ 7557 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7558 { 7559 if (fragP->fr_type == rs_machine_dependent 7560 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) 7561 { 7562 if (next_instr_is_loop_end (fragP)) 7563 { 7564 if (fragP->tc_frag_data.is_no_transform) 7565 as_bad (_("branching or jumping to a loop end may trigger hardware errata")); 7566 else 7567 relax_frag_add_nop (fragP); 7568 } 7569 frag_wane (fragP); 7570 } 7571 } 7572 } 7573 } 7574 7575 7576 static bfd_boolean 7577 next_instr_is_loop_end (fragS *fragP) 7578 { 7579 const fragS *next_fragP; 7580 7581 if (next_frag_is_loop_target (fragP)) 7582 return FALSE; 7583 7584 next_fragP = next_non_empty_frag (fragP); 7585 if (next_fragP == NULL) 7586 return FALSE; 7587 7588 if (!next_frag_is_loop_target (next_fragP)) 7589 return FALSE; 7590 7591 /* If the size is >= 3 then there is more than one instruction here. 7592 The hardware bug will not fire. */ 7593 if (next_fragP->fr_fix > 3) 7594 return FALSE; 7595 7596 return TRUE; 7597 } 7598 7599 7600 /* Re-process all of the fragments looking to convert all of the 7601 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is 7602 not MY loop's loop end within 12 bytes, add enough nops here to 7603 make it at least 12 bytes away. In any case close it off with a 7604 .fill 0. */ 7605 7606 static offsetT min_bytes_to_other_loop_end 7607 (fragS *, fragS *, offsetT); 7608 7609 static void 7610 xtensa_fix_close_loop_end_frags (void) 7611 { 7612 frchainS *frchP; 7613 asection *s; 7614 7615 /* When this routine is called, all of the subsections are still intact 7616 so we walk over subsections instead of sections. */ 7617 for (s = stdoutput->sections; s; s = s->next) 7618 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7619 { 7620 fragS *fragP; 7621 7622 fragS *current_target = NULL; 7623 7624 /* Walk over all of the fragments in a subsection. */ 7625 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7626 { 7627 if (fragP->fr_type == rs_machine_dependent 7628 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7629 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7630 current_target = symbol_get_frag (fragP->fr_symbol); 7631 7632 if (current_target 7633 && fragP->fr_type == rs_machine_dependent 7634 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) 7635 { 7636 offsetT min_bytes; 7637 int bytes_added = 0; 7638 7639 #define REQUIRED_LOOP_DIVIDING_BYTES 12 7640 /* Max out at 12. */ 7641 min_bytes = min_bytes_to_other_loop_end 7642 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); 7643 7644 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) 7645 { 7646 if (fragP->tc_frag_data.is_no_transform) 7647 as_bad (_("loop end too close to another loop end may trigger hardware errata")); 7648 else 7649 { 7650 while (min_bytes + bytes_added 7651 < REQUIRED_LOOP_DIVIDING_BYTES) 7652 { 7653 int length = 3; 7654 7655 if (fragP->fr_var < length) 7656 as_fatal (_("fr_var %lu < length %d"), 7657 (long) fragP->fr_var, length); 7658 else 7659 { 7660 assemble_nop (length, 7661 fragP->fr_literal + fragP->fr_fix); 7662 fragP->fr_fix += length; 7663 fragP->fr_var -= length; 7664 } 7665 bytes_added += length; 7666 } 7667 } 7668 } 7669 frag_wane (fragP); 7670 } 7671 assert (fragP->fr_type != rs_machine_dependent 7672 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); 7673 } 7674 } 7675 } 7676 7677 7678 static offsetT unrelaxed_frag_min_size (fragS *); 7679 7680 static offsetT 7681 min_bytes_to_other_loop_end (fragS *fragP, 7682 fragS *current_target, 7683 offsetT max_size) 7684 { 7685 offsetT offset = 0; 7686 fragS *current_fragP; 7687 7688 for (current_fragP = fragP; 7689 current_fragP; 7690 current_fragP = current_fragP->fr_next) 7691 { 7692 if (current_fragP->tc_frag_data.is_loop_target 7693 && current_fragP != current_target) 7694 return offset; 7695 7696 offset += unrelaxed_frag_min_size (current_fragP); 7697 7698 if (offset >= max_size) 7699 return max_size; 7700 } 7701 return max_size; 7702 } 7703 7704 7705 static offsetT 7706 unrelaxed_frag_min_size (fragS *fragP) 7707 { 7708 offsetT size = fragP->fr_fix; 7709 7710 /* Add fill size. */ 7711 if (fragP->fr_type == rs_fill) 7712 size += fragP->fr_offset; 7713 7714 return size; 7715 } 7716 7717 7718 static offsetT 7719 unrelaxed_frag_max_size (fragS *fragP) 7720 { 7721 offsetT size = fragP->fr_fix; 7722 switch (fragP->fr_type) 7723 { 7724 case 0: 7725 /* Empty frags created by the obstack allocation scheme 7726 end up with type 0. */ 7727 break; 7728 case rs_fill: 7729 case rs_org: 7730 case rs_space: 7731 size += fragP->fr_offset; 7732 break; 7733 case rs_align: 7734 case rs_align_code: 7735 case rs_align_test: 7736 case rs_leb128: 7737 case rs_cfa: 7738 case rs_dwarf2dbg: 7739 /* No further adjustments needed. */ 7740 break; 7741 case rs_machine_dependent: 7742 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) 7743 size += fragP->fr_var; 7744 break; 7745 default: 7746 /* We had darn well better know how big it is. */ 7747 assert (0); 7748 break; 7749 } 7750 7751 return size; 7752 } 7753 7754 7755 /* Re-process all of the fragments looking to convert all 7756 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: 7757 7758 A) 7759 1) the instruction size count to the loop end label 7760 is too short (<= 2 instructions), 7761 2) loop has a jump or branch in it 7762 7763 or B) 7764 1) workaround_all_short_loops is TRUE 7765 2) The generating loop was a 'loopgtz' or 'loopnez' 7766 3) the instruction size count to the loop end label is too short 7767 (<= 2 instructions) 7768 then convert this frag (and maybe the next one) to generate a NOP. 7769 In any case close it off with a .fill 0. */ 7770 7771 static int count_insns_to_loop_end (fragS *, bfd_boolean, int); 7772 static bfd_boolean branch_before_loop_end (fragS *); 7773 7774 static void 7775 xtensa_fix_short_loop_frags (void) 7776 { 7777 frchainS *frchP; 7778 asection *s; 7779 7780 /* When this routine is called, all of the subsections are still intact 7781 so we walk over subsections instead of sections. */ 7782 for (s = stdoutput->sections; s; s = s->next) 7783 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7784 { 7785 fragS *fragP; 7786 fragS *current_target = NULL; 7787 xtensa_opcode current_opcode = XTENSA_UNDEFINED; 7788 7789 /* Walk over all of the fragments in a subsection. */ 7790 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7791 { 7792 if (fragP->fr_type == rs_machine_dependent 7793 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7794 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7795 { 7796 TInsn t_insn; 7797 fragS *loop_frag = next_non_empty_frag (fragP); 7798 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); 7799 current_target = symbol_get_frag (fragP->fr_symbol); 7800 current_opcode = t_insn.opcode; 7801 assert (xtensa_opcode_is_loop (xtensa_default_isa, 7802 current_opcode) == 1); 7803 } 7804 7805 if (fragP->fr_type == rs_machine_dependent 7806 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7807 { 7808 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 7809 && (branch_before_loop_end (fragP->fr_next) 7810 || (workaround_all_short_loops 7811 && current_opcode != XTENSA_UNDEFINED 7812 && current_opcode != xtensa_loop_opcode))) 7813 { 7814 if (fragP->tc_frag_data.is_no_transform) 7815 as_bad (_("loop containing less than three instructions may trigger hardware errata")); 7816 else 7817 relax_frag_add_nop (fragP); 7818 } 7819 frag_wane (fragP); 7820 } 7821 } 7822 } 7823 } 7824 7825 7826 static int unrelaxed_frag_min_insn_count (fragS *); 7827 7828 static int 7829 count_insns_to_loop_end (fragS *base_fragP, 7830 bfd_boolean count_relax_add, 7831 int max_count) 7832 { 7833 fragS *fragP = NULL; 7834 int insn_count = 0; 7835 7836 fragP = base_fragP; 7837 7838 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) 7839 { 7840 insn_count += unrelaxed_frag_min_insn_count (fragP); 7841 if (insn_count >= max_count) 7842 return max_count; 7843 7844 if (count_relax_add) 7845 { 7846 if (fragP->fr_type == rs_machine_dependent 7847 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7848 { 7849 /* In order to add the appropriate number of 7850 NOPs, we count an instruction for downstream 7851 occurrences. */ 7852 insn_count++; 7853 if (insn_count >= max_count) 7854 return max_count; 7855 } 7856 } 7857 } 7858 return insn_count; 7859 } 7860 7861 7862 static int 7863 unrelaxed_frag_min_insn_count (fragS *fragP) 7864 { 7865 xtensa_isa isa = xtensa_default_isa; 7866 static xtensa_insnbuf insnbuf = NULL; 7867 int insn_count = 0; 7868 int offset = 0; 7869 7870 if (!fragP->tc_frag_data.is_insn) 7871 return insn_count; 7872 7873 if (!insnbuf) 7874 insnbuf = xtensa_insnbuf_alloc (isa); 7875 7876 /* Decode the fixed instructions. */ 7877 while (offset < fragP->fr_fix) 7878 { 7879 xtensa_format fmt; 7880 7881 xtensa_insnbuf_from_chars 7882 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 7883 fmt = xtensa_format_decode (isa, insnbuf); 7884 7885 if (fmt == XTENSA_UNDEFINED) 7886 { 7887 as_fatal (_("undecodable instruction in instruction frag")); 7888 return insn_count; 7889 } 7890 offset += xtensa_format_length (isa, fmt); 7891 insn_count++; 7892 } 7893 7894 return insn_count; 7895 } 7896 7897 7898 static bfd_boolean unrelaxed_frag_has_b_j (fragS *); 7899 7900 static bfd_boolean 7901 branch_before_loop_end (fragS *base_fragP) 7902 { 7903 fragS *fragP; 7904 7905 for (fragP = base_fragP; 7906 fragP && !fragP->tc_frag_data.is_loop_target; 7907 fragP = fragP->fr_next) 7908 { 7909 if (unrelaxed_frag_has_b_j (fragP)) 7910 return TRUE; 7911 } 7912 return FALSE; 7913 } 7914 7915 7916 static bfd_boolean 7917 unrelaxed_frag_has_b_j (fragS *fragP) 7918 { 7919 static xtensa_insnbuf insnbuf = NULL; 7920 xtensa_isa isa = xtensa_default_isa; 7921 int offset = 0; 7922 7923 if (!fragP->tc_frag_data.is_insn) 7924 return FALSE; 7925 7926 if (!insnbuf) 7927 insnbuf = xtensa_insnbuf_alloc (isa); 7928 7929 /* Decode the fixed instructions. */ 7930 while (offset < fragP->fr_fix) 7931 { 7932 xtensa_format fmt; 7933 int slot; 7934 7935 xtensa_insnbuf_from_chars 7936 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 7937 fmt = xtensa_format_decode (isa, insnbuf); 7938 if (fmt == XTENSA_UNDEFINED) 7939 return FALSE; 7940 7941 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 7942 { 7943 xtensa_opcode opcode = 7944 get_opcode_from_buf (fragP->fr_literal + offset, slot); 7945 if (xtensa_opcode_is_branch (isa, opcode) == 1 7946 || xtensa_opcode_is_jump (isa, opcode) == 1) 7947 return TRUE; 7948 } 7949 offset += xtensa_format_length (isa, fmt); 7950 } 7951 return FALSE; 7952 } 7953 7954 7955 /* Checks to be made after initial assembly but before relaxation. */ 7956 7957 static bfd_boolean is_empty_loop (const TInsn *, fragS *); 7958 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); 7959 7960 static void 7961 xtensa_sanity_check (void) 7962 { 7963 char *file_name; 7964 unsigned line; 7965 frchainS *frchP; 7966 asection *s; 7967 7968 as_where (&file_name, &line); 7969 for (s = stdoutput->sections; s; s = s->next) 7970 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7971 { 7972 fragS *fragP; 7973 7974 /* Walk over all of the fragments in a subsection. */ 7975 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7976 { 7977 if (fragP->fr_type == rs_machine_dependent 7978 && fragP->fr_subtype == RELAX_SLOTS 7979 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 7980 { 7981 static xtensa_insnbuf insnbuf = NULL; 7982 TInsn t_insn; 7983 7984 if (fragP->fr_opcode != NULL) 7985 { 7986 if (!insnbuf) 7987 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 7988 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); 7989 tinsn_immed_from_frag (&t_insn, fragP, 0); 7990 7991 if (xtensa_opcode_is_loop (xtensa_default_isa, 7992 t_insn.opcode) == 1) 7993 { 7994 if (is_empty_loop (&t_insn, fragP)) 7995 { 7996 new_logical_line (fragP->fr_file, fragP->fr_line); 7997 as_bad (_("invalid empty loop")); 7998 } 7999 if (!is_local_forward_loop (&t_insn, fragP)) 8000 { 8001 new_logical_line (fragP->fr_file, fragP->fr_line); 8002 as_bad (_("loop target does not follow " 8003 "loop instruction in section")); 8004 } 8005 } 8006 } 8007 } 8008 } 8009 } 8010 new_logical_line (file_name, line); 8011 } 8012 8013 8014 #define LOOP_IMMED_OPN 1 8015 8016 /* Return TRUE if the loop target is the next non-zero fragment. */ 8017 8018 static bfd_boolean 8019 is_empty_loop (const TInsn *insn, fragS *fragP) 8020 { 8021 const expressionS *expr; 8022 symbolS *symbolP; 8023 fragS *next_fragP; 8024 8025 if (insn->insn_type != ITYPE_INSN) 8026 return FALSE; 8027 8028 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8029 return FALSE; 8030 8031 if (insn->ntok <= LOOP_IMMED_OPN) 8032 return FALSE; 8033 8034 expr = &insn->tok[LOOP_IMMED_OPN]; 8035 8036 if (expr->X_op != O_symbol) 8037 return FALSE; 8038 8039 symbolP = expr->X_add_symbol; 8040 if (!symbolP) 8041 return FALSE; 8042 8043 if (symbol_get_frag (symbolP) == NULL) 8044 return FALSE; 8045 8046 if (S_GET_VALUE (symbolP) != 0) 8047 return FALSE; 8048 8049 /* Walk through the zero-size fragments from this one. If we find 8050 the target fragment, then this is a zero-size loop. */ 8051 8052 for (next_fragP = fragP->fr_next; 8053 next_fragP != NULL; 8054 next_fragP = next_fragP->fr_next) 8055 { 8056 if (next_fragP == symbol_get_frag (symbolP)) 8057 return TRUE; 8058 if (next_fragP->fr_fix != 0) 8059 return FALSE; 8060 } 8061 return FALSE; 8062 } 8063 8064 8065 static bfd_boolean 8066 is_local_forward_loop (const TInsn *insn, fragS *fragP) 8067 { 8068 const expressionS *expr; 8069 symbolS *symbolP; 8070 fragS *next_fragP; 8071 8072 if (insn->insn_type != ITYPE_INSN) 8073 return FALSE; 8074 8075 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8076 return FALSE; 8077 8078 if (insn->ntok <= LOOP_IMMED_OPN) 8079 return FALSE; 8080 8081 expr = &insn->tok[LOOP_IMMED_OPN]; 8082 8083 if (expr->X_op != O_symbol) 8084 return FALSE; 8085 8086 symbolP = expr->X_add_symbol; 8087 if (!symbolP) 8088 return FALSE; 8089 8090 if (symbol_get_frag (symbolP) == NULL) 8091 return FALSE; 8092 8093 /* Walk through fragments until we find the target. 8094 If we do not find the target, then this is an invalid loop. */ 8095 8096 for (next_fragP = fragP->fr_next; 8097 next_fragP != NULL; 8098 next_fragP = next_fragP->fr_next) 8099 { 8100 if (next_fragP == symbol_get_frag (symbolP)) 8101 return TRUE; 8102 } 8103 8104 return FALSE; 8105 } 8106 8107 8108 #define XTINFO_NAME "Xtensa_Info" 8109 #define XTINFO_NAMESZ 12 8110 #define XTINFO_TYPE 1 8111 8112 static void 8113 xtensa_add_config_info (void) 8114 { 8115 asection *info_sec; 8116 char *data, *p; 8117 int sz; 8118 8119 info_sec = subseg_new (".xtensa.info", 0); 8120 bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); 8121 8122 data = xmalloc (100); 8123 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", 8124 XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); 8125 sz = strlen (data) + 1; 8126 8127 /* Add enough null terminators to pad to a word boundary. */ 8128 do 8129 data[sz++] = 0; 8130 while ((sz & 3) != 0); 8131 8132 /* Follow the standard note section layout: 8133 First write the length of the name string. */ 8134 p = frag_more (4); 8135 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); 8136 8137 /* Next comes the length of the "descriptor", i.e., the actual data. */ 8138 p = frag_more (4); 8139 md_number_to_chars (p, (valueT) sz, 4); 8140 8141 /* Write the note type. */ 8142 p = frag_more (4); 8143 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); 8144 8145 /* Write the name field. */ 8146 p = frag_more (XTINFO_NAMESZ); 8147 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); 8148 8149 /* Finally, write the descriptor. */ 8150 p = frag_more (sz); 8151 memcpy (p, data, sz); 8152 8153 free (data); 8154 } 8155 8156 8157 /* Alignment Functions. */ 8158 8159 static int 8160 get_text_align_power (unsigned target_size) 8161 { 8162 if (target_size <= 4) 8163 return 2; 8164 assert (target_size == 8); 8165 return 3; 8166 } 8167 8168 8169 static int 8170 get_text_align_max_fill_size (int align_pow, 8171 bfd_boolean use_nops, 8172 bfd_boolean use_no_density) 8173 { 8174 if (!use_nops) 8175 return (1 << align_pow); 8176 if (use_no_density) 8177 return 3 * (1 << align_pow); 8178 8179 return 1 + (1 << align_pow); 8180 } 8181 8182 8183 /* Calculate the minimum bytes of fill needed at "address" to align a 8184 target instruction of size "target_size" so that it does not cross a 8185 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, 8186 the fill can be an arbitrary number of bytes. Otherwise, the space must 8187 be filled by NOP instructions. */ 8188 8189 static int 8190 get_text_align_fill_size (addressT address, 8191 int align_pow, 8192 int target_size, 8193 bfd_boolean use_nops, 8194 bfd_boolean use_no_density) 8195 { 8196 addressT alignment, fill, fill_limit, fill_step; 8197 bfd_boolean skip_one = FALSE; 8198 8199 alignment = (1 << align_pow); 8200 assert (target_size > 0 && alignment >= (addressT) target_size); 8201 8202 if (!use_nops) 8203 { 8204 fill_limit = alignment; 8205 fill_step = 1; 8206 } 8207 else if (!use_no_density) 8208 { 8209 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ 8210 fill_limit = alignment * 2; 8211 fill_step = 1; 8212 skip_one = TRUE; 8213 } 8214 else 8215 { 8216 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ 8217 fill_limit = alignment * 3; 8218 fill_step = 3; 8219 } 8220 8221 /* Try all fill sizes until finding one that works. */ 8222 for (fill = 0; fill < fill_limit; fill += fill_step) 8223 { 8224 if (skip_one && fill == 1) 8225 continue; 8226 if ((address + fill) >> align_pow 8227 == (address + fill + target_size - 1) >> align_pow) 8228 return fill; 8229 } 8230 assert (0); 8231 return 0; 8232 } 8233 8234 8235 static int 8236 branch_align_power (segT sec) 8237 { 8238 /* If the Xtensa processor has a fetch width of 8 bytes, and the section 8239 is aligned to at least an 8-byte boundary, then a branch target need 8240 only fit within an 8-byte aligned block of memory to avoid a stall. 8241 Otherwise, try to fit branch targets within 4-byte aligned blocks 8242 (which may be insufficient, e.g., if the section has no alignment, but 8243 it's good enough). */ 8244 if (xtensa_fetch_width == 8) 8245 { 8246 if (get_recorded_alignment (sec) >= 3) 8247 return 3; 8248 } 8249 else 8250 assert (xtensa_fetch_width == 4); 8251 8252 return 2; 8253 } 8254 8255 8256 /* This will assert if it is not possible. */ 8257 8258 static int 8259 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) 8260 { 8261 int count = 0; 8262 8263 if (use_no_density) 8264 { 8265 assert (fill_size % 3 == 0); 8266 return (fill_size / 3); 8267 } 8268 8269 assert (fill_size != 1); /* Bad argument. */ 8270 8271 while (fill_size > 1) 8272 { 8273 int insn_size = 3; 8274 if (fill_size == 2 || fill_size == 4) 8275 insn_size = 2; 8276 fill_size -= insn_size; 8277 count++; 8278 } 8279 assert (fill_size != 1); /* Bad algorithm. */ 8280 return count; 8281 } 8282 8283 8284 static int 8285 get_text_align_nth_nop_size (offsetT fill_size, 8286 int n, 8287 bfd_boolean use_no_density) 8288 { 8289 int count = 0; 8290 8291 if (use_no_density) 8292 return 3; 8293 8294 assert (fill_size != 1); /* Bad argument. */ 8295 8296 while (fill_size > 1) 8297 { 8298 int insn_size = 3; 8299 if (fill_size == 2 || fill_size == 4) 8300 insn_size = 2; 8301 fill_size -= insn_size; 8302 count++; 8303 if (n + 1 == count) 8304 return insn_size; 8305 } 8306 assert (0); 8307 return 0; 8308 } 8309 8310 8311 /* For the given fragment, find the appropriate address 8312 for it to begin at if we are using NOPs to align it. */ 8313 8314 static addressT 8315 get_noop_aligned_address (fragS *fragP, addressT address) 8316 { 8317 /* The rule is: get next fragment's FIRST instruction. Find 8318 the smallest number of bytes that need to be added to 8319 ensure that the next fragment's FIRST instruction will fit 8320 in a single word. 8321 8322 E.G., 2 bytes : 0, 1, 2 mod 4 8323 3 bytes: 0, 1 mod 4 8324 8325 If the FIRST instruction MIGHT be relaxed, 8326 assume that it will become a 3-byte instruction. 8327 8328 Note again here that LOOP instructions are not bundleable, 8329 and this relaxation only applies to LOOP opcodes. */ 8330 8331 int fill_size = 0; 8332 int first_insn_size; 8333 int loop_insn_size; 8334 addressT pre_opcode_bytes; 8335 int align_power; 8336 fragS *first_insn; 8337 xtensa_opcode opcode; 8338 bfd_boolean is_loop; 8339 8340 assert (fragP->fr_type == rs_machine_dependent); 8341 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); 8342 8343 /* Find the loop frag. */ 8344 first_insn = next_non_empty_frag (fragP); 8345 /* Now find the first insn frag. */ 8346 first_insn = next_non_empty_frag (first_insn); 8347 8348 is_loop = next_frag_opcode_is_loop (fragP, &opcode); 8349 assert (is_loop); 8350 loop_insn_size = xg_get_single_size (opcode); 8351 8352 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); 8353 pre_opcode_bytes += loop_insn_size; 8354 8355 /* For loops, the alignment depends on the size of the 8356 instruction following the loop, not the LOOP instruction. */ 8357 8358 if (first_insn == NULL) 8359 first_insn_size = xtensa_fetch_width; 8360 else 8361 first_insn_size = get_loop_align_size (frag_format_size (first_insn)); 8362 8363 /* If it was 8, then we'll need a larger alignment for the section. */ 8364 align_power = get_text_align_power (first_insn_size); 8365 record_alignment (now_seg, align_power); 8366 8367 fill_size = get_text_align_fill_size 8368 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, 8369 fragP->tc_frag_data.is_no_density); 8370 8371 return address + fill_size; 8372 } 8373 8374 8375 /* 3 mechanisms for relaxing an alignment: 8376 8377 Align to a power of 2. 8378 Align so the next fragment's instruction does not cross a word boundary. 8379 Align the current instruction so that if the next instruction 8380 were 3 bytes, it would not cross a word boundary. 8381 8382 We can align with: 8383 8384 zeros - This is easy; always insert zeros. 8385 nops - 3-byte and 2-byte instructions 8386 2 - 2-byte nop 8387 3 - 3-byte nop 8388 4 - 2 2-byte nops 8389 >=5 : 3-byte instruction + fn (n-3) 8390 widening - widen previous instructions. */ 8391 8392 static offsetT 8393 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) 8394 { 8395 addressT target_address, loop_insn_offset; 8396 int target_size; 8397 xtensa_opcode loop_opcode; 8398 bfd_boolean is_loop; 8399 int align_power; 8400 offsetT opt_diff; 8401 offsetT branch_align; 8402 fragS *loop_frag; 8403 8404 assert (fragP->fr_type == rs_machine_dependent); 8405 switch (fragP->fr_subtype) 8406 { 8407 case RELAX_DESIRE_ALIGN: 8408 target_size = next_frag_format_size (fragP); 8409 if (target_size == XTENSA_UNDEFINED) 8410 target_size = 3; 8411 align_power = branch_align_power (now_seg); 8412 branch_align = 1 << align_power; 8413 /* Don't count on the section alignment being as large as the target. */ 8414 if (target_size > branch_align) 8415 target_size = branch_align; 8416 opt_diff = get_text_align_fill_size (address, align_power, 8417 target_size, FALSE, FALSE); 8418 8419 *max_diff = (opt_diff + branch_align 8420 - (target_size + ((address + opt_diff) % branch_align))); 8421 assert (*max_diff >= opt_diff); 8422 return opt_diff; 8423 8424 case RELAX_ALIGN_NEXT_OPCODE: 8425 /* The next non-empty frag after this one holds the LOOP instruction 8426 that needs to be aligned. The required alignment depends on the 8427 size of the next non-empty frag after the loop frag, i.e., the 8428 first instruction in the loop. */ 8429 loop_frag = next_non_empty_frag (fragP); 8430 target_size = get_loop_align_size (next_frag_format_size (loop_frag)); 8431 loop_insn_offset = 0; 8432 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); 8433 assert (is_loop); 8434 8435 /* If the loop has been expanded then the LOOP instruction 8436 could be at an offset from this fragment. */ 8437 if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) 8438 loop_insn_offset = get_expanded_loop_offset (loop_opcode); 8439 8440 /* In an ideal world, which is what we are shooting for here, 8441 we wouldn't need to use any NOPs immediately prior to the 8442 LOOP instruction. If this approach fails, relax_frag_loop_align 8443 will call get_noop_aligned_address. */ 8444 target_address = 8445 address + loop_insn_offset + xg_get_single_size (loop_opcode); 8446 align_power = get_text_align_power (target_size); 8447 opt_diff = get_text_align_fill_size (target_address, align_power, 8448 target_size, FALSE, FALSE); 8449 8450 *max_diff = xtensa_fetch_width 8451 - ((target_address + opt_diff) % xtensa_fetch_width) 8452 - target_size + opt_diff; 8453 assert (*max_diff >= opt_diff); 8454 return opt_diff; 8455 8456 default: 8457 break; 8458 } 8459 assert (0); 8460 return 0; 8461 } 8462 8463 8464 /* md_relax_frag Hook and Helper Functions. */ 8465 8466 static long relax_frag_loop_align (fragS *, long); 8467 static long relax_frag_for_align (fragS *, long); 8468 static long relax_frag_immed 8469 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); 8470 8471 8472 /* Return the number of bytes added to this fragment, given that the 8473 input has been stretched already by "stretch". */ 8474 8475 long 8476 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) 8477 { 8478 xtensa_isa isa = xtensa_default_isa; 8479 int unreported = fragP->tc_frag_data.unreported_expansion; 8480 long new_stretch = 0; 8481 char *file_name; 8482 unsigned line; 8483 int lit_size; 8484 static xtensa_insnbuf vbuf = NULL; 8485 int slot, num_slots; 8486 xtensa_format fmt; 8487 8488 as_where (&file_name, &line); 8489 new_logical_line (fragP->fr_file, fragP->fr_line); 8490 8491 fragP->tc_frag_data.unreported_expansion = 0; 8492 8493 switch (fragP->fr_subtype) 8494 { 8495 case RELAX_ALIGN_NEXT_OPCODE: 8496 /* Always convert. */ 8497 if (fragP->tc_frag_data.relax_seen) 8498 new_stretch = relax_frag_loop_align (fragP, stretch); 8499 break; 8500 8501 case RELAX_LOOP_END: 8502 /* Do nothing. */ 8503 break; 8504 8505 case RELAX_LOOP_END_ADD_NOP: 8506 /* Add a NOP and switch to .fill 0. */ 8507 new_stretch = relax_frag_add_nop (fragP); 8508 frag_wane (fragP); 8509 break; 8510 8511 case RELAX_DESIRE_ALIGN: 8512 /* Do nothing. The narrowing before this frag will either align 8513 it or not. */ 8514 break; 8515 8516 case RELAX_LITERAL: 8517 case RELAX_LITERAL_FINAL: 8518 return 0; 8519 8520 case RELAX_LITERAL_NR: 8521 lit_size = 4; 8522 fragP->fr_subtype = RELAX_LITERAL_FINAL; 8523 assert (unreported == lit_size); 8524 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); 8525 fragP->fr_var -= lit_size; 8526 fragP->fr_fix += lit_size; 8527 new_stretch = 4; 8528 break; 8529 8530 case RELAX_SLOTS: 8531 if (vbuf == NULL) 8532 vbuf = xtensa_insnbuf_alloc (isa); 8533 8534 xtensa_insnbuf_from_chars 8535 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); 8536 fmt = xtensa_format_decode (isa, vbuf); 8537 num_slots = xtensa_format_num_slots (isa, fmt); 8538 8539 for (slot = 0; slot < num_slots; slot++) 8540 { 8541 switch (fragP->tc_frag_data.slot_subtypes[slot]) 8542 { 8543 case RELAX_NARROW: 8544 if (fragP->tc_frag_data.relax_seen) 8545 new_stretch += relax_frag_for_align (fragP, stretch); 8546 break; 8547 8548 case RELAX_IMMED: 8549 case RELAX_IMMED_STEP1: 8550 case RELAX_IMMED_STEP2: 8551 case RELAX_IMMED_STEP3: 8552 /* Place the immediate. */ 8553 new_stretch += relax_frag_immed 8554 (now_seg, fragP, stretch, 8555 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 8556 fmt, slot, stretched_p, FALSE); 8557 break; 8558 8559 default: 8560 /* This is OK; see the note in xg_assemble_vliw_tokens. */ 8561 break; 8562 } 8563 } 8564 break; 8565 8566 case RELAX_LITERAL_POOL_BEGIN: 8567 case RELAX_LITERAL_POOL_END: 8568 case RELAX_MAYBE_UNREACHABLE: 8569 case RELAX_MAYBE_DESIRE_ALIGN: 8570 /* No relaxation required. */ 8571 break; 8572 8573 case RELAX_FILL_NOP: 8574 case RELAX_UNREACHABLE: 8575 if (fragP->tc_frag_data.relax_seen) 8576 new_stretch += relax_frag_for_align (fragP, stretch); 8577 break; 8578 8579 default: 8580 as_bad (_("bad relaxation state")); 8581 } 8582 8583 /* Tell gas we need another relaxation pass. */ 8584 if (! fragP->tc_frag_data.relax_seen) 8585 { 8586 fragP->tc_frag_data.relax_seen = TRUE; 8587 *stretched_p = 1; 8588 } 8589 8590 new_logical_line (file_name, line); 8591 return new_stretch; 8592 } 8593 8594 8595 static long 8596 relax_frag_loop_align (fragS *fragP, long stretch) 8597 { 8598 addressT old_address, old_next_address, old_size; 8599 addressT new_address, new_next_address, new_size; 8600 addressT growth; 8601 8602 /* All the frags with relax_frag_for_alignment prior to this one in the 8603 section have been done, hopefully eliminating the need for a NOP here. 8604 But, this will put it in if necessary. */ 8605 8606 /* Calculate the old address of this fragment and the next fragment. */ 8607 old_address = fragP->fr_address - stretch; 8608 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + 8609 fragP->tc_frag_data.text_expansion[0]); 8610 old_size = old_next_address - old_address; 8611 8612 /* Calculate the new address of this fragment and the next fragment. */ 8613 new_address = fragP->fr_address; 8614 new_next_address = 8615 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); 8616 new_size = new_next_address - new_address; 8617 8618 growth = new_size - old_size; 8619 8620 /* Fix up the text_expansion field and return the new growth. */ 8621 fragP->tc_frag_data.text_expansion[0] += growth; 8622 return growth; 8623 } 8624 8625 8626 /* Add a NOP instruction. */ 8627 8628 static long 8629 relax_frag_add_nop (fragS *fragP) 8630 { 8631 char *nop_buf = fragP->fr_literal + fragP->fr_fix; 8632 int length = fragP->tc_frag_data.is_no_density ? 3 : 2; 8633 assemble_nop (length, nop_buf); 8634 fragP->tc_frag_data.is_insn = TRUE; 8635 8636 if (fragP->fr_var < length) 8637 { 8638 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); 8639 return 0; 8640 } 8641 8642 fragP->fr_fix += length; 8643 fragP->fr_var -= length; 8644 return length; 8645 } 8646 8647 8648 static long future_alignment_required (fragS *, long); 8649 8650 static long 8651 relax_frag_for_align (fragS *fragP, long stretch) 8652 { 8653 /* Overview of the relaxation procedure for alignment: 8654 We can widen with NOPs or by widening instructions or by filling 8655 bytes after jump instructions. Find the opportune places and widen 8656 them if necessary. */ 8657 8658 long stretch_me; 8659 long diff; 8660 8661 assert (fragP->fr_subtype == RELAX_FILL_NOP 8662 || fragP->fr_subtype == RELAX_UNREACHABLE 8663 || (fragP->fr_subtype == RELAX_SLOTS 8664 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); 8665 8666 stretch_me = future_alignment_required (fragP, stretch); 8667 diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; 8668 if (diff == 0) 8669 return 0; 8670 8671 if (diff < 0) 8672 { 8673 /* We expanded on a previous pass. Can we shrink now? */ 8674 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; 8675 if (shrink <= stretch && stretch > 0) 8676 { 8677 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8678 return -shrink; 8679 } 8680 return 0; 8681 } 8682 8683 /* Below here, diff > 0. */ 8684 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8685 8686 return diff; 8687 } 8688 8689 8690 /* Return the address of the next frag that should be aligned. 8691 8692 By "address" we mean the address it _would_ be at if there 8693 is no action taken to align it between here and the target frag. 8694 In other words, if no narrows and no fill nops are used between 8695 here and the frag to align, _even_if_ some of the frags we use 8696 to align targets have already expanded on a previous relaxation 8697 pass. 8698 8699 Also, count each frag that may be used to help align the target. 8700 8701 Return 0 if there are no frags left in the chain that need to be 8702 aligned. */ 8703 8704 static addressT 8705 find_address_of_next_align_frag (fragS **fragPP, 8706 int *wide_nops, 8707 int *narrow_nops, 8708 int *widens, 8709 bfd_boolean *paddable) 8710 { 8711 fragS *fragP = *fragPP; 8712 addressT address = fragP->fr_address; 8713 8714 /* Do not reset the counts to 0. */ 8715 8716 while (fragP) 8717 { 8718 /* Limit this to a small search. */ 8719 if (*widens >= (int) xtensa_fetch_width) 8720 { 8721 *fragPP = fragP; 8722 return 0; 8723 } 8724 address += fragP->fr_fix; 8725 8726 if (fragP->fr_type == rs_fill) 8727 address += fragP->fr_offset * fragP->fr_var; 8728 else if (fragP->fr_type == rs_machine_dependent) 8729 { 8730 switch (fragP->fr_subtype) 8731 { 8732 case RELAX_UNREACHABLE: 8733 *paddable = TRUE; 8734 break; 8735 8736 case RELAX_FILL_NOP: 8737 (*wide_nops)++; 8738 if (!fragP->tc_frag_data.is_no_density) 8739 (*narrow_nops)++; 8740 break; 8741 8742 case RELAX_SLOTS: 8743 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8744 { 8745 (*widens)++; 8746 break; 8747 } 8748 address += total_frag_text_expansion (fragP);; 8749 break; 8750 8751 case RELAX_IMMED: 8752 address += fragP->tc_frag_data.text_expansion[0]; 8753 break; 8754 8755 case RELAX_ALIGN_NEXT_OPCODE: 8756 case RELAX_DESIRE_ALIGN: 8757 *fragPP = fragP; 8758 return address; 8759 8760 case RELAX_MAYBE_UNREACHABLE: 8761 case RELAX_MAYBE_DESIRE_ALIGN: 8762 /* Do nothing. */ 8763 break; 8764 8765 default: 8766 /* Just punt if we don't know the type. */ 8767 *fragPP = fragP; 8768 return 0; 8769 } 8770 } 8771 else 8772 { 8773 /* Just punt if we don't know the type. */ 8774 *fragPP = fragP; 8775 return 0; 8776 } 8777 fragP = fragP->fr_next; 8778 } 8779 8780 *fragPP = fragP; 8781 return 0; 8782 } 8783 8784 8785 static long bytes_to_stretch (fragS *, int, int, int, int); 8786 8787 static long 8788 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) 8789 { 8790 fragS *this_frag = fragP; 8791 long address; 8792 int num_widens = 0; 8793 int wide_nops = 0; 8794 int narrow_nops = 0; 8795 bfd_boolean paddable = FALSE; 8796 offsetT local_opt_diff; 8797 offsetT opt_diff; 8798 offsetT max_diff; 8799 int stretch_amount = 0; 8800 int local_stretch_amount; 8801 int global_stretch_amount; 8802 8803 address = find_address_of_next_align_frag 8804 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); 8805 8806 if (!address) 8807 { 8808 if (this_frag->tc_frag_data.is_aligning_branch) 8809 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 8810 else 8811 frag_wane (this_frag); 8812 } 8813 else 8814 { 8815 local_opt_diff = get_aligned_diff (fragP, address, &max_diff); 8816 opt_diff = local_opt_diff; 8817 assert (opt_diff >= 0); 8818 assert (max_diff >= opt_diff); 8819 if (max_diff == 0) 8820 return 0; 8821 8822 if (fragP) 8823 fragP = fragP->fr_next; 8824 8825 while (fragP && opt_diff < max_diff && address) 8826 { 8827 /* We only use these to determine if we can exit early 8828 because there will be plenty of ways to align future 8829 align frags. */ 8830 int glob_widens = 0; 8831 int dnn = 0; 8832 int dw = 0; 8833 bfd_boolean glob_pad = 0; 8834 address = find_address_of_next_align_frag 8835 (&fragP, &glob_widens, &dnn, &dw, &glob_pad); 8836 /* If there is a padable portion, then skip. */ 8837 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) 8838 address = 0; 8839 8840 if (address) 8841 { 8842 offsetT next_m_diff; 8843 offsetT next_o_diff; 8844 8845 /* Downrange frags haven't had stretch added to them yet. */ 8846 address += stretch; 8847 8848 /* The address also includes any text expansion from this 8849 frag in a previous pass, but we don't want that. */ 8850 address -= this_frag->tc_frag_data.text_expansion[0]; 8851 8852 /* Assume we are going to move at least opt_diff. In 8853 reality, we might not be able to, but assuming that 8854 we will helps catch cases where moving opt_diff pushes 8855 the next target from aligned to unaligned. */ 8856 address += opt_diff; 8857 8858 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); 8859 8860 /* Now cleanup for the adjustments to address. */ 8861 next_o_diff += opt_diff; 8862 next_m_diff += opt_diff; 8863 if (next_o_diff <= max_diff && next_o_diff > opt_diff) 8864 opt_diff = next_o_diff; 8865 if (next_m_diff < max_diff) 8866 max_diff = next_m_diff; 8867 fragP = fragP->fr_next; 8868 } 8869 } 8870 8871 /* If there are enough wideners in between, do it. */ 8872 if (paddable) 8873 { 8874 if (this_frag->fr_subtype == RELAX_UNREACHABLE) 8875 { 8876 assert (opt_diff <= UNREACHABLE_MAX_WIDTH); 8877 return opt_diff; 8878 } 8879 return 0; 8880 } 8881 local_stretch_amount 8882 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 8883 num_widens, local_opt_diff); 8884 global_stretch_amount 8885 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 8886 num_widens, opt_diff); 8887 /* If the condition below is true, then the frag couldn't 8888 stretch the correct amount for the global case, so we just 8889 optimize locally. We'll rely on the subsequent frags to get 8890 the correct alignment in the global case. */ 8891 if (global_stretch_amount < local_stretch_amount) 8892 stretch_amount = local_stretch_amount; 8893 else 8894 stretch_amount = global_stretch_amount; 8895 8896 if (this_frag->fr_subtype == RELAX_SLOTS 8897 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8898 assert (stretch_amount <= 1); 8899 else if (this_frag->fr_subtype == RELAX_FILL_NOP) 8900 { 8901 if (this_frag->tc_frag_data.is_no_density) 8902 assert (stretch_amount == 3 || stretch_amount == 0); 8903 else 8904 assert (stretch_amount <= 3); 8905 } 8906 } 8907 return stretch_amount; 8908 } 8909 8910 8911 /* The idea: widen everything you can to get a target or loop aligned, 8912 then start using NOPs. 8913 8914 When we must have a NOP, here is a table of how we decide 8915 (so you don't have to fight through the control flow below): 8916 8917 wide_nops = the number of wide NOPs available for aligning 8918 narrow_nops = the number of narrow NOPs available for aligning 8919 (a subset of wide_nops) 8920 widens = the number of narrow instructions that should be widened 8921 8922 Desired wide narrow 8923 Diff nop nop widens 8924 1 0 0 1 8925 2 0 1 0 8926 3a 1 0 0 8927 b 0 1 1 (case 3a makes this case unnecessary) 8928 4a 1 0 1 8929 b 0 2 0 8930 c 0 1 2 (case 4a makes this case unnecessary) 8931 5a 1 0 2 8932 b 1 1 0 8933 c 0 2 1 (case 5b makes this case unnecessary) 8934 6a 2 0 0 8935 b 1 0 3 8936 c 0 1 4 (case 6b makes this case unnecessary) 8937 d 1 1 1 (case 6a makes this case unnecessary) 8938 e 0 2 2 (case 6a makes this case unnecessary) 8939 f 0 3 0 (case 6a makes this case unnecessary) 8940 7a 1 0 4 8941 b 2 0 1 8942 c 1 1 2 (case 7b makes this case unnecessary) 8943 d 0 1 5 (case 7a makes this case unnecessary) 8944 e 0 2 3 (case 7b makes this case unnecessary) 8945 f 0 3 1 (case 7b makes this case unnecessary) 8946 g 1 2 1 (case 7b makes this case unnecessary) 8947 */ 8948 8949 static long 8950 bytes_to_stretch (fragS *this_frag, 8951 int wide_nops, 8952 int narrow_nops, 8953 int num_widens, 8954 int desired_diff) 8955 { 8956 int bytes_short = desired_diff - num_widens; 8957 8958 assert (desired_diff >= 0 && desired_diff < 8); 8959 if (desired_diff == 0) 8960 return 0; 8961 8962 assert (wide_nops > 0 || num_widens > 0); 8963 8964 /* Always prefer widening to NOP-filling. */ 8965 if (bytes_short < 0) 8966 { 8967 /* There are enough RELAX_NARROW frags after this one 8968 to align the target without widening this frag in any way. */ 8969 return 0; 8970 } 8971 8972 if (bytes_short == 0) 8973 { 8974 /* Widen every narrow between here and the align target 8975 and the align target will be properly aligned. */ 8976 if (this_frag->fr_subtype == RELAX_FILL_NOP) 8977 return 0; 8978 else 8979 return 1; 8980 } 8981 8982 /* From here we will need at least one NOP to get an alignment. 8983 However, we may not be able to align at all, in which case, 8984 don't widen. */ 8985 if (this_frag->fr_subtype == RELAX_FILL_NOP) 8986 { 8987 switch (desired_diff) 8988 { 8989 case 1: 8990 return 0; 8991 case 2: 8992 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) 8993 return 2; /* case 2 */ 8994 return 0; 8995 case 3: 8996 if (wide_nops > 1) 8997 return 0; 8998 else 8999 return 3; /* case 3a */ 9000 case 4: 9001 if (num_widens >= 1 && wide_nops == 1) 9002 return 3; /* case 4a */ 9003 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) 9004 return 2; /* case 4b */ 9005 return 0; 9006 case 5: 9007 if (num_widens >= 2 && wide_nops == 1) 9008 return 3; /* case 5a */ 9009 /* We will need two nops. Are there enough nops 9010 between here and the align target? */ 9011 if (wide_nops < 2 || narrow_nops == 0) 9012 return 0; 9013 /* Are there other nops closer that can serve instead? */ 9014 if (wide_nops > 2 && narrow_nops > 1) 9015 return 0; 9016 /* Take the density one first, because there might not be 9017 another density one available. */ 9018 if (!this_frag->tc_frag_data.is_no_density) 9019 return 2; /* case 5b narrow */ 9020 else 9021 return 3; /* case 5b wide */ 9022 return 0; 9023 case 6: 9024 if (wide_nops == 2) 9025 return 3; /* case 6a */ 9026 else if (num_widens >= 3 && wide_nops == 1) 9027 return 3; /* case 6b */ 9028 return 0; 9029 case 7: 9030 if (wide_nops == 1 && num_widens >= 4) 9031 return 3; /* case 7a */ 9032 else if (wide_nops == 2 && num_widens >= 1) 9033 return 3; /* case 7b */ 9034 return 0; 9035 default: 9036 assert (0); 9037 } 9038 } 9039 else 9040 { 9041 /* We will need a NOP no matter what, but should we widen 9042 this instruction to help? 9043 9044 This is a RELAX_NARROW frag. */ 9045 switch (desired_diff) 9046 { 9047 case 1: 9048 assert (0); 9049 return 0; 9050 case 2: 9051 case 3: 9052 return 0; 9053 case 4: 9054 if (wide_nops >= 1 && num_widens == 1) 9055 return 1; /* case 4a */ 9056 return 0; 9057 case 5: 9058 if (wide_nops >= 1 && num_widens == 2) 9059 return 1; /* case 5a */ 9060 return 0; 9061 case 6: 9062 if (wide_nops >= 2) 9063 return 0; /* case 6a */ 9064 else if (wide_nops >= 1 && num_widens == 3) 9065 return 1; /* case 6b */ 9066 return 0; 9067 case 7: 9068 if (wide_nops >= 1 && num_widens == 4) 9069 return 1; /* case 7a */ 9070 else if (wide_nops >= 2 && num_widens == 1) 9071 return 1; /* case 7b */ 9072 return 0; 9073 default: 9074 assert (0); 9075 return 0; 9076 } 9077 } 9078 assert (0); 9079 return 0; 9080 } 9081 9082 9083 static long 9084 relax_frag_immed (segT segP, 9085 fragS *fragP, 9086 long stretch, 9087 int min_steps, 9088 xtensa_format fmt, 9089 int slot, 9090 int *stretched_p, 9091 bfd_boolean estimate_only) 9092 { 9093 TInsn tinsn; 9094 int old_size; 9095 bfd_boolean negatable_branch = FALSE; 9096 bfd_boolean branch_jmp_to_next = FALSE; 9097 bfd_boolean from_wide_insn = FALSE; 9098 xtensa_isa isa = xtensa_default_isa; 9099 IStack istack; 9100 offsetT frag_offset; 9101 int num_steps; 9102 int num_text_bytes, num_literal_bytes; 9103 int literal_diff, total_text_diff, this_text_diff; 9104 9105 assert (fragP->fr_opcode != NULL); 9106 9107 xg_clear_vinsn (&cur_vinsn); 9108 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); 9109 if (cur_vinsn.num_slots > 1) 9110 from_wide_insn = TRUE; 9111 9112 tinsn = cur_vinsn.slots[slot]; 9113 tinsn_immed_from_frag (&tinsn, fragP, slot); 9114 9115 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) 9116 return 0; 9117 9118 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 9119 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); 9120 9121 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); 9122 9123 old_size = xtensa_format_length (isa, fmt); 9124 9125 /* Special case: replace a branch to the next instruction with a NOP. 9126 This is required to work around a hardware bug in T1040.0 and also 9127 serves as an optimization. */ 9128 9129 if (branch_jmp_to_next 9130 && ((old_size == 2) || (old_size == 3)) 9131 && !next_frag_is_loop_target (fragP)) 9132 return 0; 9133 9134 /* Here is the fun stuff: Get the immediate field from this 9135 instruction. If it fits, we are done. If not, find the next 9136 instruction sequence that fits. */ 9137 9138 frag_offset = fragP->fr_opcode - fragP->fr_literal; 9139 istack_init (&istack); 9140 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, 9141 min_steps, stretch); 9142 assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 9143 9144 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; 9145 9146 /* Figure out the number of bytes needed. */ 9147 num_literal_bytes = get_num_stack_literal_bytes (&istack); 9148 literal_diff 9149 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 9150 num_text_bytes = get_num_stack_text_bytes (&istack); 9151 9152 if (from_wide_insn) 9153 { 9154 int first = 0; 9155 while (istack.insn[first].opcode == XTENSA_UNDEFINED) 9156 first++; 9157 9158 num_text_bytes += old_size; 9159 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) 9160 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); 9161 else 9162 { 9163 /* The first instruction in the relaxed sequence will go after 9164 the current wide instruction, and thus its symbolic immediates 9165 might not fit. */ 9166 9167 istack_init (&istack); 9168 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, 9169 frag_offset + old_size, 9170 min_steps, stretch + old_size); 9171 assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 9172 9173 fragP->tc_frag_data.slot_subtypes[slot] 9174 = (int) RELAX_IMMED + num_steps; 9175 9176 num_literal_bytes = get_num_stack_literal_bytes (&istack); 9177 literal_diff 9178 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 9179 9180 num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; 9181 } 9182 } 9183 9184 total_text_diff = num_text_bytes - old_size; 9185 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; 9186 9187 /* It MUST get larger. If not, we could get an infinite loop. */ 9188 assert (num_text_bytes >= 0); 9189 assert (literal_diff >= 0); 9190 assert (total_text_diff >= 0); 9191 9192 fragP->tc_frag_data.text_expansion[slot] = total_text_diff; 9193 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; 9194 assert (fragP->tc_frag_data.text_expansion[slot] >= 0); 9195 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); 9196 9197 /* Find the associated expandable literal for this. */ 9198 if (literal_diff != 0) 9199 { 9200 fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; 9201 if (lit_fragP) 9202 { 9203 assert (literal_diff == 4); 9204 lit_fragP->tc_frag_data.unreported_expansion += literal_diff; 9205 9206 /* We expect that the literal section state has NOT been 9207 modified yet. */ 9208 assert (lit_fragP->fr_type == rs_machine_dependent 9209 && lit_fragP->fr_subtype == RELAX_LITERAL); 9210 lit_fragP->fr_subtype = RELAX_LITERAL_NR; 9211 9212 /* We need to mark this section for another iteration 9213 of relaxation. */ 9214 (*stretched_p)++; 9215 } 9216 } 9217 9218 if (negatable_branch && istack.ninsn > 1) 9219 update_next_frag_state (fragP); 9220 9221 return this_text_diff; 9222 } 9223 9224 9225 /* md_convert_frag Hook and Helper Functions. */ 9226 9227 static void convert_frag_align_next_opcode (fragS *); 9228 static void convert_frag_narrow (segT, fragS *, xtensa_format, int); 9229 static void convert_frag_fill_nop (fragS *); 9230 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); 9231 9232 void 9233 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) 9234 { 9235 static xtensa_insnbuf vbuf = NULL; 9236 xtensa_isa isa = xtensa_default_isa; 9237 int slot; 9238 int num_slots; 9239 xtensa_format fmt; 9240 char *file_name; 9241 unsigned line; 9242 9243 as_where (&file_name, &line); 9244 new_logical_line (fragp->fr_file, fragp->fr_line); 9245 9246 switch (fragp->fr_subtype) 9247 { 9248 case RELAX_ALIGN_NEXT_OPCODE: 9249 /* Always convert. */ 9250 convert_frag_align_next_opcode (fragp); 9251 break; 9252 9253 case RELAX_DESIRE_ALIGN: 9254 /* Do nothing. If not aligned already, too bad. */ 9255 break; 9256 9257 case RELAX_LITERAL: 9258 case RELAX_LITERAL_FINAL: 9259 break; 9260 9261 case RELAX_SLOTS: 9262 if (vbuf == NULL) 9263 vbuf = xtensa_insnbuf_alloc (isa); 9264 9265 xtensa_insnbuf_from_chars 9266 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); 9267 fmt = xtensa_format_decode (isa, vbuf); 9268 num_slots = xtensa_format_num_slots (isa, fmt); 9269 9270 for (slot = 0; slot < num_slots; slot++) 9271 { 9272 switch (fragp->tc_frag_data.slot_subtypes[slot]) 9273 { 9274 case RELAX_NARROW: 9275 convert_frag_narrow (sec, fragp, fmt, slot); 9276 break; 9277 9278 case RELAX_IMMED: 9279 case RELAX_IMMED_STEP1: 9280 case RELAX_IMMED_STEP2: 9281 case RELAX_IMMED_STEP3: 9282 /* Place the immediate. */ 9283 convert_frag_immed 9284 (sec, fragp, 9285 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 9286 fmt, slot); 9287 break; 9288 9289 default: 9290 /* This is OK because some slots could have 9291 relaxations and others have none. */ 9292 break; 9293 } 9294 } 9295 break; 9296 9297 case RELAX_UNREACHABLE: 9298 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); 9299 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; 9300 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; 9301 frag_wane (fragp); 9302 break; 9303 9304 case RELAX_MAYBE_UNREACHABLE: 9305 case RELAX_MAYBE_DESIRE_ALIGN: 9306 frag_wane (fragp); 9307 break; 9308 9309 case RELAX_FILL_NOP: 9310 convert_frag_fill_nop (fragp); 9311 break; 9312 9313 case RELAX_LITERAL_NR: 9314 if (use_literal_section) 9315 { 9316 /* This should have been handled during relaxation. When 9317 relaxing a code segment, literals sometimes need to be 9318 added to the corresponding literal segment. If that 9319 literal segment has already been relaxed, then we end up 9320 in this situation. Marking the literal segments as data 9321 would make this happen less often (since GAS always relaxes 9322 code before data), but we could still get into trouble if 9323 there are instructions in a segment that is not marked as 9324 containing code. Until we can implement a better solution, 9325 cheat and adjust the addresses of all the following frags. 9326 This could break subsequent alignments, but the linker's 9327 literal coalescing will do that anyway. */ 9328 9329 fragS *f; 9330 fragp->fr_subtype = RELAX_LITERAL_FINAL; 9331 assert (fragp->tc_frag_data.unreported_expansion == 4); 9332 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); 9333 fragp->fr_var -= 4; 9334 fragp->fr_fix += 4; 9335 for (f = fragp->fr_next; f; f = f->fr_next) 9336 f->fr_address += 4; 9337 } 9338 else 9339 as_bad (_("invalid relaxation fragment result")); 9340 break; 9341 } 9342 9343 fragp->fr_var = 0; 9344 new_logical_line (file_name, line); 9345 } 9346 9347 9348 static void 9349 convert_frag_align_next_opcode (fragS *fragp) 9350 { 9351 char *nop_buf; /* Location for Writing. */ 9352 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; 9353 addressT aligned_address; 9354 offsetT fill_size; 9355 int nop, nop_count; 9356 9357 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + 9358 fragp->fr_fix); 9359 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); 9360 nop_count = get_text_align_nop_count (fill_size, use_no_density); 9361 nop_buf = fragp->fr_literal + fragp->fr_fix; 9362 9363 for (nop = 0; nop < nop_count; nop++) 9364 { 9365 int nop_size; 9366 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); 9367 9368 assemble_nop (nop_size, nop_buf); 9369 nop_buf += nop_size; 9370 } 9371 9372 fragp->fr_fix += fill_size; 9373 fragp->fr_var -= fill_size; 9374 } 9375 9376 9377 static void 9378 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) 9379 { 9380 TInsn tinsn, single_target; 9381 int size, old_size, diff; 9382 offsetT frag_offset; 9383 9384 assert (slot == 0); 9385 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); 9386 9387 if (fragP->tc_frag_data.is_aligning_branch == 1) 9388 { 9389 assert (fragP->tc_frag_data.text_expansion[0] == 1 9390 || fragP->tc_frag_data.text_expansion[0] == 0); 9391 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], 9392 fmt, slot); 9393 return; 9394 } 9395 9396 if (fragP->tc_frag_data.text_expansion[0] == 0) 9397 { 9398 /* No conversion. */ 9399 fragP->fr_var = 0; 9400 return; 9401 } 9402 9403 assert (fragP->fr_opcode != NULL); 9404 9405 /* Frags in this relaxation state should only contain 9406 single instruction bundles. */ 9407 tinsn_immed_from_frag (&tinsn, fragP, 0); 9408 9409 /* Just convert it to a wide form.... */ 9410 size = 0; 9411 old_size = xg_get_single_size (tinsn.opcode); 9412 9413 tinsn_init (&single_target); 9414 frag_offset = fragP->fr_opcode - fragP->fr_literal; 9415 9416 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) 9417 { 9418 as_bad (_("unable to widen instruction")); 9419 return; 9420 } 9421 9422 size = xg_get_single_size (single_target.opcode); 9423 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, 9424 frag_offset, TRUE); 9425 9426 diff = size - old_size; 9427 assert (diff >= 0); 9428 assert (diff <= fragP->fr_var); 9429 fragP->fr_var -= diff; 9430 fragP->fr_fix += diff; 9431 9432 /* clean it up */ 9433 fragP->fr_var = 0; 9434 } 9435 9436 9437 static void 9438 convert_frag_fill_nop (fragS *fragP) 9439 { 9440 char *loc = &fragP->fr_literal[fragP->fr_fix]; 9441 int size = fragP->tc_frag_data.text_expansion[0]; 9442 assert ((unsigned) size == (fragP->fr_next->fr_address 9443 - fragP->fr_address - fragP->fr_fix)); 9444 if (size == 0) 9445 { 9446 /* No conversion. */ 9447 fragP->fr_var = 0; 9448 return; 9449 } 9450 assemble_nop (size, loc); 9451 fragP->tc_frag_data.is_insn = TRUE; 9452 fragP->fr_var -= size; 9453 fragP->fr_fix += size; 9454 frag_wane (fragP); 9455 } 9456 9457 9458 static fixS *fix_new_exp_in_seg 9459 (segT, subsegT, fragS *, int, int, expressionS *, int, 9460 bfd_reloc_code_real_type); 9461 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); 9462 9463 static void 9464 convert_frag_immed (segT segP, 9465 fragS *fragP, 9466 int min_steps, 9467 xtensa_format fmt, 9468 int slot) 9469 { 9470 char *immed_instr = fragP->fr_opcode; 9471 TInsn orig_tinsn; 9472 bfd_boolean expanded = FALSE; 9473 bfd_boolean branch_jmp_to_next = FALSE; 9474 char *fr_opcode = fragP->fr_opcode; 9475 xtensa_isa isa = xtensa_default_isa; 9476 bfd_boolean from_wide_insn = FALSE; 9477 int bytes; 9478 bfd_boolean is_loop; 9479 9480 assert (fr_opcode != NULL); 9481 9482 xg_clear_vinsn (&cur_vinsn); 9483 9484 vinsn_from_chars (&cur_vinsn, fr_opcode); 9485 if (cur_vinsn.num_slots > 1) 9486 from_wide_insn = TRUE; 9487 9488 orig_tinsn = cur_vinsn.slots[slot]; 9489 tinsn_immed_from_frag (&orig_tinsn, fragP, slot); 9490 9491 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; 9492 9493 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 9494 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); 9495 9496 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) 9497 { 9498 /* Conversion just inserts a NOP and marks the fix as completed. */ 9499 bytes = xtensa_format_length (isa, fmt); 9500 if (bytes >= 4) 9501 { 9502 cur_vinsn.slots[slot].opcode = 9503 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); 9504 cur_vinsn.slots[slot].ntok = 0; 9505 } 9506 else 9507 { 9508 bytes += fragP->tc_frag_data.text_expansion[0]; 9509 assert (bytes == 2 || bytes == 3); 9510 build_nop (&cur_vinsn.slots[0], bytes); 9511 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; 9512 } 9513 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); 9514 xtensa_insnbuf_to_chars 9515 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); 9516 fragP->fr_var = 0; 9517 } 9518 else 9519 { 9520 /* Here is the fun stuff: Get the immediate field from this 9521 instruction. If it fits, we're done. If not, find the next 9522 instruction sequence that fits. */ 9523 9524 IStack istack; 9525 int i; 9526 symbolS *lit_sym = NULL; 9527 int total_size = 0; 9528 int target_offset = 0; 9529 int old_size; 9530 int diff; 9531 symbolS *gen_label = NULL; 9532 offsetT frag_offset; 9533 bfd_boolean first = TRUE; 9534 bfd_boolean last_is_jump; 9535 9536 /* It does not fit. Find something that does and 9537 convert immediately. */ 9538 frag_offset = fr_opcode - fragP->fr_literal; 9539 istack_init (&istack); 9540 xg_assembly_relax (&istack, &orig_tinsn, 9541 segP, fragP, frag_offset, min_steps, 0); 9542 9543 old_size = xtensa_format_length (isa, fmt); 9544 9545 /* Assemble this right inline. */ 9546 9547 /* First, create the mapping from a label name to the REAL label. */ 9548 target_offset = 0; 9549 for (i = 0; i < istack.ninsn; i++) 9550 { 9551 TInsn *tinsn = &istack.insn[i]; 9552 fragS *lit_frag; 9553 9554 switch (tinsn->insn_type) 9555 { 9556 case ITYPE_LITERAL: 9557 if (lit_sym != NULL) 9558 as_bad (_("multiple literals in expansion")); 9559 /* First find the appropriate space in the literal pool. */ 9560 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9561 if (lit_frag == NULL) 9562 as_bad (_("no registered fragment for literal")); 9563 if (tinsn->ntok != 1) 9564 as_bad (_("number of literal tokens != 1")); 9565 9566 /* Set the literal symbol and add a fixup. */ 9567 lit_sym = lit_frag->fr_symbol; 9568 break; 9569 9570 case ITYPE_LABEL: 9571 if (align_targets && !is_loop) 9572 { 9573 fragS *unreach = fragP->fr_next; 9574 while (!(unreach->fr_type == rs_machine_dependent 9575 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9576 || unreach->fr_subtype == RELAX_UNREACHABLE))) 9577 { 9578 unreach = unreach->fr_next; 9579 } 9580 9581 assert (unreach->fr_type == rs_machine_dependent 9582 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9583 || unreach->fr_subtype == RELAX_UNREACHABLE)); 9584 9585 target_offset += unreach->tc_frag_data.text_expansion[0]; 9586 } 9587 assert (gen_label == NULL); 9588 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, 9589 fr_opcode - fragP->fr_literal 9590 + target_offset, fragP); 9591 break; 9592 9593 case ITYPE_INSN: 9594 if (first && from_wide_insn) 9595 { 9596 target_offset += xtensa_format_length (isa, fmt); 9597 first = FALSE; 9598 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9599 target_offset += xg_get_single_size (tinsn->opcode); 9600 } 9601 else 9602 target_offset += xg_get_single_size (tinsn->opcode); 9603 break; 9604 } 9605 } 9606 9607 total_size = 0; 9608 first = TRUE; 9609 last_is_jump = FALSE; 9610 for (i = 0; i < istack.ninsn; i++) 9611 { 9612 TInsn *tinsn = &istack.insn[i]; 9613 fragS *lit_frag; 9614 int size; 9615 segT target_seg; 9616 bfd_reloc_code_real_type reloc_type; 9617 9618 switch (tinsn->insn_type) 9619 { 9620 case ITYPE_LITERAL: 9621 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9622 /* Already checked. */ 9623 assert (lit_frag != NULL); 9624 assert (lit_sym != NULL); 9625 assert (tinsn->ntok == 1); 9626 /* Add a fixup. */ 9627 target_seg = S_GET_SEGMENT (lit_sym); 9628 assert (target_seg); 9629 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); 9630 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, 9631 &tinsn->tok[0], FALSE, reloc_type); 9632 break; 9633 9634 case ITYPE_LABEL: 9635 break; 9636 9637 case ITYPE_INSN: 9638 xg_resolve_labels (tinsn, gen_label); 9639 xg_resolve_literals (tinsn, lit_sym); 9640 if (from_wide_insn && first) 9641 { 9642 first = FALSE; 9643 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9644 { 9645 cur_vinsn.slots[slot] = *tinsn; 9646 } 9647 else 9648 { 9649 cur_vinsn.slots[slot].opcode = 9650 xtensa_format_slot_nop_opcode (isa, fmt, slot); 9651 cur_vinsn.slots[slot].ntok = 0; 9652 } 9653 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); 9654 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, 9655 (unsigned char *) immed_instr, 0); 9656 fragP->tc_frag_data.is_insn = TRUE; 9657 size = xtensa_format_length (isa, fmt); 9658 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9659 { 9660 xg_emit_insn_to_buf 9661 (tinsn, immed_instr + size, fragP, 9662 immed_instr - fragP->fr_literal + size, TRUE); 9663 size += xg_get_single_size (tinsn->opcode); 9664 } 9665 } 9666 else 9667 { 9668 size = xg_get_single_size (tinsn->opcode); 9669 xg_emit_insn_to_buf (tinsn, immed_instr, fragP, 9670 immed_instr - fragP->fr_literal, TRUE); 9671 } 9672 immed_instr += size; 9673 total_size += size; 9674 break; 9675 } 9676 } 9677 9678 diff = total_size - old_size; 9679 assert (diff >= 0); 9680 if (diff != 0) 9681 expanded = TRUE; 9682 assert (diff <= fragP->fr_var); 9683 fragP->fr_var -= diff; 9684 fragP->fr_fix += diff; 9685 } 9686 9687 /* Check for undefined immediates in LOOP instructions. */ 9688 if (is_loop) 9689 { 9690 symbolS *sym; 9691 sym = orig_tinsn.tok[1].X_add_symbol; 9692 if (sym != NULL && !S_IS_DEFINED (sym)) 9693 { 9694 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9695 return; 9696 } 9697 sym = orig_tinsn.tok[1].X_op_symbol; 9698 if (sym != NULL && !S_IS_DEFINED (sym)) 9699 { 9700 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9701 return; 9702 } 9703 } 9704 9705 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) 9706 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); 9707 9708 if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) 9709 { 9710 /* Add an expansion note on the expanded instruction. */ 9711 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, 9712 &orig_tinsn.tok[0], TRUE, 9713 BFD_RELOC_XTENSA_ASM_EXPAND); 9714 } 9715 } 9716 9717 9718 /* Add a new fix expression into the desired segment. We have to 9719 switch to that segment to do this. */ 9720 9721 static fixS * 9722 fix_new_exp_in_seg (segT new_seg, 9723 subsegT new_subseg, 9724 fragS *frag, 9725 int where, 9726 int size, 9727 expressionS *exp, 9728 int pcrel, 9729 bfd_reloc_code_real_type r_type) 9730 { 9731 fixS *new_fix; 9732 segT seg = now_seg; 9733 subsegT subseg = now_subseg; 9734 9735 assert (new_seg != 0); 9736 subseg_set (new_seg, new_subseg); 9737 9738 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); 9739 subseg_set (seg, subseg); 9740 return new_fix; 9741 } 9742 9743 9744 /* Relax a loop instruction so that it can span loop >256 bytes. 9745 9746 loop as, .L1 9747 .L0: 9748 rsr as, LEND 9749 wsr as, LBEG 9750 addi as, as, lo8 (label-.L1) 9751 addmi as, as, mid8 (label-.L1) 9752 wsr as, LEND 9753 isync 9754 rsr as, LCOUNT 9755 addi as, as, 1 9756 .L1: 9757 <<body>> 9758 label: 9759 */ 9760 9761 static void 9762 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) 9763 { 9764 TInsn loop_insn; 9765 TInsn addi_insn; 9766 TInsn addmi_insn; 9767 unsigned long target; 9768 static xtensa_insnbuf insnbuf = NULL; 9769 unsigned int loop_length, loop_length_hi, loop_length_lo; 9770 xtensa_isa isa = xtensa_default_isa; 9771 addressT loop_offset; 9772 addressT addi_offset = 9; 9773 addressT addmi_offset = 12; 9774 fragS *next_fragP; 9775 int target_count; 9776 9777 if (!insnbuf) 9778 insnbuf = xtensa_insnbuf_alloc (isa); 9779 9780 /* Get the loop offset. */ 9781 loop_offset = get_expanded_loop_offset (tinsn->opcode); 9782 9783 /* Validate that there really is a LOOP at the loop_offset. Because 9784 loops are not bundleable, we can assume that the instruction will be 9785 in slot 0. */ 9786 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); 9787 tinsn_immed_from_frag (&loop_insn, fragP, 0); 9788 9789 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); 9790 addi_offset += loop_offset; 9791 addmi_offset += loop_offset; 9792 9793 assert (tinsn->ntok == 2); 9794 if (tinsn->tok[1].X_op == O_constant) 9795 target = tinsn->tok[1].X_add_number; 9796 else if (tinsn->tok[1].X_op == O_symbol) 9797 { 9798 /* Find the fragment. */ 9799 symbolS *sym = tinsn->tok[1].X_add_symbol; 9800 assert (S_GET_SEGMENT (sym) == segP 9801 || S_GET_SEGMENT (sym) == absolute_section); 9802 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); 9803 } 9804 else 9805 { 9806 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); 9807 target = 0; 9808 } 9809 9810 loop_length = target - (fragP->fr_address + fragP->fr_fix); 9811 loop_length_hi = loop_length & ~0x0ff; 9812 loop_length_lo = loop_length & 0x0ff; 9813 if (loop_length_lo >= 128) 9814 { 9815 loop_length_lo -= 256; 9816 loop_length_hi += 256; 9817 } 9818 9819 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most 9820 32512. If the loop is larger than that, then we just fail. */ 9821 if (loop_length_hi > 32512) 9822 as_bad_where (fragP->fr_file, fragP->fr_line, 9823 _("loop too long for LOOP instruction")); 9824 9825 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); 9826 assert (addi_insn.opcode == xtensa_addi_opcode); 9827 9828 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); 9829 assert (addmi_insn.opcode == xtensa_addmi_opcode); 9830 9831 set_expr_const (&addi_insn.tok[2], loop_length_lo); 9832 tinsn_to_insnbuf (&addi_insn, insnbuf); 9833 9834 fragP->tc_frag_data.is_insn = TRUE; 9835 xtensa_insnbuf_to_chars 9836 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); 9837 9838 set_expr_const (&addmi_insn.tok[2], loop_length_hi); 9839 tinsn_to_insnbuf (&addmi_insn, insnbuf); 9840 xtensa_insnbuf_to_chars 9841 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); 9842 9843 /* Walk through all of the frags from here to the loop end 9844 and mark them as no_transform to keep them from being modified 9845 by the linker. If we ever have a relocation for the 9846 addi/addmi of the difference of two symbols we can remove this. */ 9847 9848 target_count = 0; 9849 for (next_fragP = fragP; next_fragP != NULL; 9850 next_fragP = next_fragP->fr_next) 9851 { 9852 next_fragP->tc_frag_data.is_no_transform = TRUE; 9853 if (next_fragP->tc_frag_data.is_loop_target) 9854 target_count++; 9855 if (target_count == 2) 9856 break; 9857 } 9858 } 9859 9860 9861 /* A map that keeps information on a per-subsegment basis. This is 9862 maintained during initial assembly, but is invalid once the 9863 subsegments are smashed together. I.E., it cannot be used during 9864 the relaxation. */ 9865 9866 typedef struct subseg_map_struct 9867 { 9868 /* the key */ 9869 segT seg; 9870 subsegT subseg; 9871 9872 /* the data */ 9873 unsigned flags; 9874 float total_freq; /* fall-through + branch target frequency */ 9875 float target_freq; /* branch target frequency alone */ 9876 9877 struct subseg_map_struct *next; 9878 } subseg_map; 9879 9880 9881 static subseg_map *sseg_map = NULL; 9882 9883 static subseg_map * 9884 get_subseg_info (segT seg, subsegT subseg) 9885 { 9886 subseg_map *subseg_e; 9887 9888 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) 9889 { 9890 if (seg == subseg_e->seg && subseg == subseg_e->subseg) 9891 break; 9892 } 9893 return subseg_e; 9894 } 9895 9896 9897 static subseg_map * 9898 add_subseg_info (segT seg, subsegT subseg) 9899 { 9900 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); 9901 memset (subseg_e, 0, sizeof (subseg_map)); 9902 subseg_e->seg = seg; 9903 subseg_e->subseg = subseg; 9904 subseg_e->flags = 0; 9905 /* Start off considering every branch target very important. */ 9906 subseg_e->target_freq = 1.0; 9907 subseg_e->total_freq = 1.0; 9908 subseg_e->next = sseg_map; 9909 sseg_map = subseg_e; 9910 return subseg_e; 9911 } 9912 9913 9914 static unsigned 9915 get_last_insn_flags (segT seg, subsegT subseg) 9916 { 9917 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9918 if (subseg_e) 9919 return subseg_e->flags; 9920 return 0; 9921 } 9922 9923 9924 static void 9925 set_last_insn_flags (segT seg, 9926 subsegT subseg, 9927 unsigned fl, 9928 bfd_boolean val) 9929 { 9930 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9931 if (! subseg_e) 9932 subseg_e = add_subseg_info (seg, subseg); 9933 if (val) 9934 subseg_e->flags |= fl; 9935 else 9936 subseg_e->flags &= ~fl; 9937 } 9938 9939 9940 static float 9941 get_subseg_total_freq (segT seg, subsegT subseg) 9942 { 9943 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9944 if (subseg_e) 9945 return subseg_e->total_freq; 9946 return 1.0; 9947 } 9948 9949 9950 static float 9951 get_subseg_target_freq (segT seg, subsegT subseg) 9952 { 9953 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9954 if (subseg_e) 9955 return subseg_e->target_freq; 9956 return 1.0; 9957 } 9958 9959 9960 static void 9961 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) 9962 { 9963 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9964 if (! subseg_e) 9965 subseg_e = add_subseg_info (seg, subseg); 9966 subseg_e->total_freq = total_f; 9967 subseg_e->target_freq = target_f; 9968 } 9969 9970 9971 /* Segment Lists and emit_state Stuff. */ 9972 9973 static void 9974 xtensa_move_seg_list_to_beginning (seg_list *head) 9975 { 9976 head = head->next; 9977 while (head) 9978 { 9979 segT literal_section = head->seg; 9980 9981 /* Move the literal section to the front of the section list. */ 9982 assert (literal_section); 9983 if (literal_section != stdoutput->sections) 9984 { 9985 bfd_section_list_remove (stdoutput, literal_section); 9986 bfd_section_list_prepend (stdoutput, literal_section); 9987 } 9988 head = head->next; 9989 } 9990 } 9991 9992 9993 static void mark_literal_frags (seg_list *); 9994 9995 static void 9996 xtensa_move_literals (void) 9997 { 9998 seg_list *segment; 9999 frchainS *frchain_from, *frchain_to; 10000 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; 10001 fragS **frag_splice; 10002 emit_state state; 10003 segT dest_seg; 10004 fixS *fix, *next_fix, **fix_splice; 10005 sym_list *lit; 10006 10007 mark_literal_frags (literal_head->next); 10008 10009 if (use_literal_section) 10010 return; 10011 10012 for (segment = literal_head->next; segment; segment = segment->next) 10013 { 10014 /* Keep the literals for .init and .fini in separate sections. */ 10015 if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) 10016 || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) 10017 continue; 10018 10019 frchain_from = seg_info (segment->seg)->frchainP; 10020 search_frag = frchain_from->frch_root; 10021 literal_pool = NULL; 10022 frchain_to = NULL; 10023 frag_splice = &(frchain_from->frch_root); 10024 10025 while (!search_frag->tc_frag_data.literal_frag) 10026 { 10027 assert (search_frag->fr_fix == 0 10028 || search_frag->fr_type == rs_align); 10029 search_frag = search_frag->fr_next; 10030 } 10031 10032 assert (search_frag->tc_frag_data.literal_frag->fr_subtype 10033 == RELAX_LITERAL_POOL_BEGIN); 10034 xtensa_switch_section_emit_state (&state, segment->seg, 0); 10035 10036 /* Make sure that all the frags in this series are closed, and 10037 that there is at least one left over of zero-size. This 10038 prevents us from making a segment with an frchain without any 10039 frags in it. */ 10040 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10041 xtensa_set_frag_assembly_state (frag_now); 10042 last_frag = frag_now; 10043 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10044 xtensa_set_frag_assembly_state (frag_now); 10045 10046 while (search_frag != frag_now) 10047 { 10048 next_frag = search_frag->fr_next; 10049 10050 /* First, move the frag out of the literal section and 10051 to the appropriate place. */ 10052 if (search_frag->tc_frag_data.literal_frag) 10053 { 10054 literal_pool = search_frag->tc_frag_data.literal_frag; 10055 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); 10056 frchain_to = literal_pool->tc_frag_data.lit_frchain; 10057 assert (frchain_to); 10058 } 10059 insert_after = literal_pool->tc_frag_data.literal_frag; 10060 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; 10061 10062 *frag_splice = next_frag; 10063 search_frag->fr_next = insert_after->fr_next; 10064 insert_after->fr_next = search_frag; 10065 search_frag->tc_frag_data.lit_seg = dest_seg; 10066 literal_pool->tc_frag_data.literal_frag = search_frag; 10067 10068 /* Now move any fixups associated with this frag to the 10069 right section. */ 10070 fix = frchain_from->fix_root; 10071 fix_splice = &(frchain_from->fix_root); 10072 while (fix) 10073 { 10074 next_fix = fix->fx_next; 10075 if (fix->fx_frag == search_frag) 10076 { 10077 *fix_splice = next_fix; 10078 fix->fx_next = frchain_to->fix_root; 10079 frchain_to->fix_root = fix; 10080 if (frchain_to->fix_tail == NULL) 10081 frchain_to->fix_tail = fix; 10082 } 10083 else 10084 fix_splice = &(fix->fx_next); 10085 fix = next_fix; 10086 } 10087 search_frag = next_frag; 10088 } 10089 10090 if (frchain_from->fix_root != NULL) 10091 { 10092 frchain_from = seg_info (segment->seg)->frchainP; 10093 as_warn (_("fixes not all moved from %s"), segment->seg->name); 10094 10095 assert (frchain_from->fix_root == NULL); 10096 } 10097 frchain_from->fix_tail = NULL; 10098 xtensa_restore_emit_state (&state); 10099 } 10100 10101 /* Now fix up the SEGMENT value for all the literal symbols. */ 10102 for (lit = literal_syms; lit; lit = lit->next) 10103 { 10104 symbolS *lit_sym = lit->sym; 10105 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; 10106 if (dest_seg) 10107 S_SET_SEGMENT (lit_sym, dest_seg); 10108 } 10109 } 10110 10111 10112 /* Walk over all the frags for segments in a list and mark them as 10113 containing literals. As clunky as this is, we can't rely on frag_var 10114 and frag_variant to get called in all situations. */ 10115 10116 static void 10117 mark_literal_frags (seg_list *segment) 10118 { 10119 frchainS *frchain_from; 10120 fragS *search_frag; 10121 10122 while (segment) 10123 { 10124 frchain_from = seg_info (segment->seg)->frchainP; 10125 search_frag = frchain_from->frch_root; 10126 while (search_frag) 10127 { 10128 search_frag->tc_frag_data.is_literal = TRUE; 10129 search_frag = search_frag->fr_next; 10130 } 10131 segment = segment->next; 10132 } 10133 } 10134 10135 10136 static void 10137 xtensa_reorder_seg_list (seg_list *head, segT after) 10138 { 10139 /* Move all of the sections in the section list to come 10140 after "after" in the gnu segment list. */ 10141 10142 head = head->next; 10143 while (head) 10144 { 10145 segT literal_section = head->seg; 10146 10147 /* Move the literal section after "after". */ 10148 assert (literal_section); 10149 if (literal_section != after) 10150 { 10151 bfd_section_list_remove (stdoutput, literal_section); 10152 bfd_section_list_insert_after (stdoutput, after, literal_section); 10153 } 10154 10155 head = head->next; 10156 } 10157 } 10158 10159 10160 /* Push all the literal segments to the end of the gnu list. */ 10161 10162 static void 10163 xtensa_reorder_segments (void) 10164 { 10165 segT sec; 10166 segT last_sec = 0; 10167 int old_count = 0; 10168 int new_count = 0; 10169 10170 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 10171 { 10172 last_sec = sec; 10173 old_count++; 10174 } 10175 10176 /* Now that we have the last section, push all the literal 10177 sections to the end. */ 10178 xtensa_reorder_seg_list (literal_head, last_sec); 10179 10180 /* Now perform the final error check. */ 10181 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 10182 new_count++; 10183 assert (new_count == old_count); 10184 } 10185 10186 10187 /* Change the emit state (seg, subseg, and frag related stuff) to the 10188 correct location. Return a emit_state which can be passed to 10189 xtensa_restore_emit_state to return to current fragment. */ 10190 10191 static void 10192 xtensa_switch_to_literal_fragment (emit_state *result) 10193 { 10194 if (directive_state[directive_absolute_literals]) 10195 { 10196 segT lit4_seg = cache_literal_section (TRUE); 10197 xtensa_switch_section_emit_state (result, lit4_seg, 0); 10198 } 10199 else 10200 xtensa_switch_to_non_abs_literal_fragment (result); 10201 10202 /* Do a 4-byte align here. */ 10203 frag_align (2, 0, 0); 10204 record_alignment (now_seg, 2); 10205 } 10206 10207 10208 static void 10209 xtensa_switch_to_non_abs_literal_fragment (emit_state *result) 10210 { 10211 static bfd_boolean recursive = FALSE; 10212 fragS *pool_location = get_literal_pool_location (now_seg); 10213 segT lit_seg; 10214 bfd_boolean is_init = 10215 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); 10216 bfd_boolean is_fini = 10217 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); 10218 10219 if (pool_location == NULL 10220 && !use_literal_section 10221 && !recursive 10222 && !is_init && ! is_fini) 10223 { 10224 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); 10225 10226 /* When we mark a literal pool location, we want to put a frag in 10227 the literal pool that points to it. But to do that, we want to 10228 switch_to_literal_fragment. But literal sections don't have 10229 literal pools, so their location is always null, so we would 10230 recurse forever. This is kind of hacky, but it works. */ 10231 10232 recursive = TRUE; 10233 xtensa_mark_literal_pool_location (); 10234 recursive = FALSE; 10235 } 10236 10237 lit_seg = cache_literal_section (FALSE); 10238 xtensa_switch_section_emit_state (result, lit_seg, 0); 10239 10240 if (!use_literal_section 10241 && !is_init && !is_fini 10242 && get_literal_pool_location (now_seg) != pool_location) 10243 { 10244 /* Close whatever frag is there. */ 10245 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10246 xtensa_set_frag_assembly_state (frag_now); 10247 frag_now->tc_frag_data.literal_frag = pool_location; 10248 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10249 xtensa_set_frag_assembly_state (frag_now); 10250 } 10251 } 10252 10253 10254 /* Call this function before emitting data into the literal section. 10255 This is a helper function for xtensa_switch_to_literal_fragment. 10256 This is similar to a .section new_now_seg subseg. */ 10257 10258 static void 10259 xtensa_switch_section_emit_state (emit_state *state, 10260 segT new_now_seg, 10261 subsegT new_now_subseg) 10262 { 10263 state->name = now_seg->name; 10264 state->now_seg = now_seg; 10265 state->now_subseg = now_subseg; 10266 state->generating_literals = generating_literals; 10267 generating_literals++; 10268 subseg_set (new_now_seg, new_now_subseg); 10269 } 10270 10271 10272 /* Use to restore the emitting into the normal place. */ 10273 10274 static void 10275 xtensa_restore_emit_state (emit_state *state) 10276 { 10277 generating_literals = state->generating_literals; 10278 subseg_set (state->now_seg, state->now_subseg); 10279 } 10280 10281 10282 /* Predicate function used to look up a section in a particular group. */ 10283 10284 static bfd_boolean 10285 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) 10286 { 10287 const char *gname = inf; 10288 const char *group_name = elf_group_name (sec); 10289 10290 return (group_name == gname 10291 || (group_name != NULL 10292 && gname != NULL 10293 && strcmp (group_name, gname) == 0)); 10294 } 10295 10296 10297 /* Get the literal section to be used for the current text section. 10298 The result may be cached in the default_lit_sections structure. */ 10299 10300 static segT 10301 cache_literal_section (bfd_boolean use_abs_literals) 10302 { 10303 const char *text_name, *group_name = 0; 10304 char *base_name, *name, *suffix; 10305 segT *pcached; 10306 segT seg, current_section; 10307 int current_subsec; 10308 bfd_boolean linkonce = FALSE; 10309 10310 /* Save the current section/subsection. */ 10311 current_section = now_seg; 10312 current_subsec = now_subseg; 10313 10314 /* Clear the cached values if they are no longer valid. */ 10315 if (now_seg != default_lit_sections.current_text_seg) 10316 { 10317 default_lit_sections.current_text_seg = now_seg; 10318 default_lit_sections.lit_seg = NULL; 10319 default_lit_sections.lit4_seg = NULL; 10320 } 10321 10322 /* Check if the literal section is already cached. */ 10323 if (use_abs_literals) 10324 pcached = &default_lit_sections.lit4_seg; 10325 else 10326 pcached = &default_lit_sections.lit_seg; 10327 10328 if (*pcached) 10329 return *pcached; 10330 10331 text_name = default_lit_sections.lit_prefix; 10332 if (! text_name || ! *text_name) 10333 { 10334 text_name = segment_name (current_section); 10335 group_name = elf_group_name (current_section); 10336 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; 10337 } 10338 10339 base_name = use_abs_literals ? ".lit4" : ".literal"; 10340 if (group_name) 10341 { 10342 name = xmalloc (strlen (base_name) + strlen (group_name) + 2); 10343 sprintf (name, "%s.%s", base_name, group_name); 10344 } 10345 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) 10346 { 10347 suffix = strchr (text_name + linkonce_len, '.'); 10348 10349 name = xmalloc (linkonce_len + strlen (base_name) + 1 10350 + (suffix ? strlen (suffix) : 0)); 10351 strcpy (name, ".gnu.linkonce"); 10352 strcat (name, base_name); 10353 if (suffix) 10354 strcat (name, suffix); 10355 linkonce = TRUE; 10356 } 10357 else 10358 { 10359 /* If the section name ends with ".text", then replace that suffix 10360 instead of appending an additional suffix. */ 10361 size_t len = strlen (text_name); 10362 if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) 10363 len -= 5; 10364 10365 name = xmalloc (len + strlen (base_name) + 1); 10366 strcpy (name, text_name); 10367 strcpy (name + len, base_name); 10368 } 10369 10370 /* Canonicalize section names to allow renaming literal sections. 10371 The group name, if any, came from the current text section and 10372 has already been canonicalized. */ 10373 name = tc_canonicalize_symbol_name (name); 10374 10375 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, 10376 (void *) group_name); 10377 if (! seg) 10378 { 10379 flagword flags; 10380 10381 seg = subseg_force_new (name, 0); 10382 10383 if (! use_abs_literals) 10384 { 10385 /* Add the newly created literal segment to the list. */ 10386 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); 10387 n->seg = seg; 10388 n->next = literal_head->next; 10389 literal_head->next = n; 10390 } 10391 10392 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD 10393 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) 10394 | (use_abs_literals ? SEC_DATA : SEC_CODE)); 10395 10396 elf_group_name (seg) = group_name; 10397 10398 bfd_set_section_flags (stdoutput, seg, flags); 10399 bfd_set_section_alignment (stdoutput, seg, 2); 10400 } 10401 10402 *pcached = seg; 10403 subseg_set (current_section, current_subsec); 10404 return seg; 10405 } 10406 10407 10408 /* Property Tables Stuff. */ 10409 10410 #define XTENSA_INSN_SEC_NAME ".xt.insn" 10411 #define XTENSA_LIT_SEC_NAME ".xt.lit" 10412 #define XTENSA_PROP_SEC_NAME ".xt.prop" 10413 10414 typedef bfd_boolean (*frag_predicate) (const fragS *); 10415 typedef void (*frag_flags_fn) (const fragS *, frag_flags *); 10416 10417 static bfd_boolean get_frag_is_literal (const fragS *); 10418 static void xtensa_create_property_segments 10419 (frag_predicate, frag_predicate, const char *, xt_section_type); 10420 static void xtensa_create_xproperty_segments 10421 (frag_flags_fn, const char *, xt_section_type); 10422 static bfd_boolean exclude_section_from_property_tables (segT); 10423 static bfd_boolean section_has_property (segT, frag_predicate); 10424 static bfd_boolean section_has_xproperty (segT, frag_flags_fn); 10425 static void add_xt_block_frags 10426 (segT, xtensa_block_info **, frag_predicate, frag_predicate); 10427 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); 10428 static void xtensa_frag_flags_init (frag_flags *); 10429 static void get_frag_property_flags (const fragS *, frag_flags *); 10430 static bfd_vma frag_flags_to_number (const frag_flags *); 10431 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); 10432 10433 /* Set up property tables after relaxation. */ 10434 10435 void 10436 xtensa_post_relax_hook (void) 10437 { 10438 xtensa_move_seg_list_to_beginning (literal_head); 10439 10440 xtensa_find_unmarked_state_frags (); 10441 xtensa_mark_frags_for_org (); 10442 xtensa_mark_difference_of_two_symbols (); 10443 10444 xtensa_create_property_segments (get_frag_is_literal, 10445 NULL, 10446 XTENSA_LIT_SEC_NAME, 10447 xt_literal_sec); 10448 xtensa_create_xproperty_segments (get_frag_property_flags, 10449 XTENSA_PROP_SEC_NAME, 10450 xt_prop_sec); 10451 10452 if (warn_unaligned_branch_targets) 10453 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); 10454 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); 10455 } 10456 10457 10458 /* This function is only meaningful after xtensa_move_literals. */ 10459 10460 static bfd_boolean 10461 get_frag_is_literal (const fragS *fragP) 10462 { 10463 assert (fragP != NULL); 10464 return fragP->tc_frag_data.is_literal; 10465 } 10466 10467 10468 static void 10469 xtensa_create_property_segments (frag_predicate property_function, 10470 frag_predicate end_property_function, 10471 const char *section_name_base, 10472 xt_section_type sec_type) 10473 { 10474 segT *seclist; 10475 10476 /* Walk over all of the current segments. 10477 Walk over each fragment 10478 For each non-empty fragment, 10479 Build a property record (append where possible). */ 10480 10481 for (seclist = &stdoutput->sections; 10482 seclist && *seclist; 10483 seclist = &(*seclist)->next) 10484 { 10485 segT sec = *seclist; 10486 10487 if (exclude_section_from_property_tables (sec)) 10488 continue; 10489 10490 if (section_has_property (sec, property_function)) 10491 { 10492 segment_info_type *xt_seg_info; 10493 xtensa_block_info **xt_blocks; 10494 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 10495 10496 prop_sec->output_section = prop_sec; 10497 subseg_set (prop_sec, 0); 10498 xt_seg_info = seg_info (prop_sec); 10499 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10500 10501 /* Walk over all of the frchains here and add new sections. */ 10502 add_xt_block_frags (sec, xt_blocks, property_function, 10503 end_property_function); 10504 } 10505 } 10506 10507 /* Now we fill them out.... */ 10508 10509 for (seclist = &stdoutput->sections; 10510 seclist && *seclist; 10511 seclist = &(*seclist)->next) 10512 { 10513 segment_info_type *seginfo; 10514 xtensa_block_info *block; 10515 segT sec = *seclist; 10516 10517 seginfo = seg_info (sec); 10518 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10519 10520 if (block) 10521 { 10522 xtensa_block_info *cur_block; 10523 int num_recs = 0; 10524 bfd_size_type rec_size; 10525 10526 for (cur_block = block; cur_block; cur_block = cur_block->next) 10527 num_recs++; 10528 10529 rec_size = num_recs * 8; 10530 bfd_set_section_size (stdoutput, sec, rec_size); 10531 10532 if (num_recs) 10533 { 10534 char *frag_data; 10535 int i; 10536 10537 subseg_set (sec, 0); 10538 frag_data = frag_more (rec_size); 10539 cur_block = block; 10540 for (i = 0; i < num_recs; i++) 10541 { 10542 fixS *fix; 10543 10544 /* Write the fixup. */ 10545 assert (cur_block); 10546 fix = fix_new (frag_now, i * 8, 4, 10547 section_symbol (cur_block->sec), 10548 cur_block->offset, 10549 FALSE, BFD_RELOC_32); 10550 fix->fx_file = "<internal>"; 10551 fix->fx_line = 0; 10552 10553 /* Write the length. */ 10554 md_number_to_chars (&frag_data[4 + i * 8], 10555 cur_block->size, 4); 10556 cur_block = cur_block->next; 10557 } 10558 frag_wane (frag_now); 10559 frag_new (0); 10560 frag_wane (frag_now); 10561 } 10562 } 10563 } 10564 } 10565 10566 10567 static void 10568 xtensa_create_xproperty_segments (frag_flags_fn flag_fn, 10569 const char *section_name_base, 10570 xt_section_type sec_type) 10571 { 10572 segT *seclist; 10573 10574 /* Walk over all of the current segments. 10575 Walk over each fragment. 10576 For each fragment that has instructions, 10577 build an instruction record (append where possible). */ 10578 10579 for (seclist = &stdoutput->sections; 10580 seclist && *seclist; 10581 seclist = &(*seclist)->next) 10582 { 10583 segT sec = *seclist; 10584 10585 if (exclude_section_from_property_tables (sec)) 10586 continue; 10587 10588 if (section_has_xproperty (sec, flag_fn)) 10589 { 10590 segment_info_type *xt_seg_info; 10591 xtensa_block_info **xt_blocks; 10592 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 10593 10594 prop_sec->output_section = prop_sec; 10595 subseg_set (prop_sec, 0); 10596 xt_seg_info = seg_info (prop_sec); 10597 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10598 10599 /* Walk over all of the frchains here and add new sections. */ 10600 add_xt_prop_frags (sec, xt_blocks, flag_fn); 10601 } 10602 } 10603 10604 /* Now we fill them out.... */ 10605 10606 for (seclist = &stdoutput->sections; 10607 seclist && *seclist; 10608 seclist = &(*seclist)->next) 10609 { 10610 segment_info_type *seginfo; 10611 xtensa_block_info *block; 10612 segT sec = *seclist; 10613 10614 seginfo = seg_info (sec); 10615 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10616 10617 if (block) 10618 { 10619 xtensa_block_info *cur_block; 10620 int num_recs = 0; 10621 bfd_size_type rec_size; 10622 10623 for (cur_block = block; cur_block; cur_block = cur_block->next) 10624 num_recs++; 10625 10626 rec_size = num_recs * (8 + 4); 10627 bfd_set_section_size (stdoutput, sec, rec_size); 10628 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ 10629 10630 if (num_recs) 10631 { 10632 char *frag_data; 10633 int i; 10634 10635 subseg_set (sec, 0); 10636 frag_data = frag_more (rec_size); 10637 cur_block = block; 10638 for (i = 0; i < num_recs; i++) 10639 { 10640 fixS *fix; 10641 10642 /* Write the fixup. */ 10643 assert (cur_block); 10644 fix = fix_new (frag_now, i * 12, 4, 10645 section_symbol (cur_block->sec), 10646 cur_block->offset, 10647 FALSE, BFD_RELOC_32); 10648 fix->fx_file = "<internal>"; 10649 fix->fx_line = 0; 10650 10651 /* Write the length. */ 10652 md_number_to_chars (&frag_data[4 + i * 12], 10653 cur_block->size, 4); 10654 md_number_to_chars (&frag_data[8 + i * 12], 10655 frag_flags_to_number (&cur_block->flags), 10656 4); 10657 cur_block = cur_block->next; 10658 } 10659 frag_wane (frag_now); 10660 frag_new (0); 10661 frag_wane (frag_now); 10662 } 10663 } 10664 } 10665 } 10666 10667 10668 static bfd_boolean 10669 exclude_section_from_property_tables (segT sec) 10670 { 10671 flagword flags = bfd_get_section_flags (stdoutput, sec); 10672 10673 /* Sections that don't contribute to the memory footprint are excluded. */ 10674 if ((flags & SEC_DEBUGGING) 10675 || !(flags & SEC_ALLOC) 10676 || (flags & SEC_MERGE)) 10677 return TRUE; 10678 10679 /* Linker cie and fde optimizations mess up property entries for 10680 eh_frame sections, but there is nothing inside them relevant to 10681 property tables anyway. */ 10682 if (strcmp (sec->name, ".eh_frame") == 0) 10683 return TRUE; 10684 10685 return FALSE; 10686 } 10687 10688 10689 static bfd_boolean 10690 section_has_property (segT sec, frag_predicate property_function) 10691 { 10692 segment_info_type *seginfo = seg_info (sec); 10693 fragS *fragP; 10694 10695 if (seginfo && seginfo->frchainP) 10696 { 10697 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10698 { 10699 if (property_function (fragP) 10700 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10701 return TRUE; 10702 } 10703 } 10704 return FALSE; 10705 } 10706 10707 10708 static bfd_boolean 10709 section_has_xproperty (segT sec, frag_flags_fn property_function) 10710 { 10711 segment_info_type *seginfo = seg_info (sec); 10712 fragS *fragP; 10713 10714 if (seginfo && seginfo->frchainP) 10715 { 10716 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10717 { 10718 frag_flags prop_flags; 10719 property_function (fragP, &prop_flags); 10720 if (!xtensa_frag_flags_is_empty (&prop_flags)) 10721 return TRUE; 10722 } 10723 } 10724 return FALSE; 10725 } 10726 10727 10728 /* Two types of block sections exist right now: literal and insns. */ 10729 10730 static void 10731 add_xt_block_frags (segT sec, 10732 xtensa_block_info **xt_block, 10733 frag_predicate property_function, 10734 frag_predicate end_property_function) 10735 { 10736 bfd_vma seg_offset; 10737 fragS *fragP; 10738 10739 /* Build it if needed. */ 10740 while (*xt_block != NULL) 10741 xt_block = &(*xt_block)->next; 10742 /* We are either at NULL at the beginning or at the end. */ 10743 10744 /* Walk through the frags. */ 10745 seg_offset = 0; 10746 10747 if (seg_info (sec)->frchainP) 10748 { 10749 for (fragP = seg_info (sec)->frchainP->frch_root; 10750 fragP; 10751 fragP = fragP->fr_next) 10752 { 10753 if (property_function (fragP) 10754 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10755 { 10756 if (*xt_block != NULL) 10757 { 10758 if ((*xt_block)->offset + (*xt_block)->size 10759 == fragP->fr_address) 10760 (*xt_block)->size += fragP->fr_fix; 10761 else 10762 xt_block = &((*xt_block)->next); 10763 } 10764 if (*xt_block == NULL) 10765 { 10766 xtensa_block_info *new_block = (xtensa_block_info *) 10767 xmalloc (sizeof (xtensa_block_info)); 10768 new_block->sec = sec; 10769 new_block->offset = fragP->fr_address; 10770 new_block->size = fragP->fr_fix; 10771 new_block->next = NULL; 10772 xtensa_frag_flags_init (&new_block->flags); 10773 *xt_block = new_block; 10774 } 10775 if (end_property_function 10776 && end_property_function (fragP)) 10777 { 10778 xt_block = &((*xt_block)->next); 10779 } 10780 } 10781 } 10782 } 10783 } 10784 10785 10786 /* Break the encapsulation of add_xt_prop_frags here. */ 10787 10788 static bfd_boolean 10789 xtensa_frag_flags_is_empty (const frag_flags *prop_flags) 10790 { 10791 if (prop_flags->is_literal 10792 || prop_flags->is_insn 10793 || prop_flags->is_data 10794 || prop_flags->is_unreachable) 10795 return FALSE; 10796 return TRUE; 10797 } 10798 10799 10800 static void 10801 xtensa_frag_flags_init (frag_flags *prop_flags) 10802 { 10803 memset (prop_flags, 0, sizeof (frag_flags)); 10804 } 10805 10806 10807 static void 10808 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) 10809 { 10810 xtensa_frag_flags_init (prop_flags); 10811 if (fragP->tc_frag_data.is_literal) 10812 prop_flags->is_literal = TRUE; 10813 if (fragP->tc_frag_data.is_specific_opcode 10814 || fragP->tc_frag_data.is_no_transform) 10815 { 10816 prop_flags->is_no_transform = TRUE; 10817 if (xtensa_frag_flags_is_empty (prop_flags)) 10818 prop_flags->is_data = TRUE; 10819 } 10820 if (fragP->tc_frag_data.is_unreachable) 10821 prop_flags->is_unreachable = TRUE; 10822 else if (fragP->tc_frag_data.is_insn) 10823 { 10824 prop_flags->is_insn = TRUE; 10825 if (fragP->tc_frag_data.is_loop_target) 10826 prop_flags->insn.is_loop_target = TRUE; 10827 if (fragP->tc_frag_data.is_branch_target) 10828 prop_flags->insn.is_branch_target = TRUE; 10829 if (fragP->tc_frag_data.is_no_density) 10830 prop_flags->insn.is_no_density = TRUE; 10831 if (fragP->tc_frag_data.use_absolute_literals) 10832 prop_flags->insn.is_abslit = TRUE; 10833 } 10834 if (fragP->tc_frag_data.is_align) 10835 { 10836 prop_flags->is_align = TRUE; 10837 prop_flags->alignment = fragP->tc_frag_data.alignment; 10838 if (xtensa_frag_flags_is_empty (prop_flags)) 10839 prop_flags->is_data = TRUE; 10840 } 10841 } 10842 10843 10844 static bfd_vma 10845 frag_flags_to_number (const frag_flags *prop_flags) 10846 { 10847 bfd_vma num = 0; 10848 if (prop_flags->is_literal) 10849 num |= XTENSA_PROP_LITERAL; 10850 if (prop_flags->is_insn) 10851 num |= XTENSA_PROP_INSN; 10852 if (prop_flags->is_data) 10853 num |= XTENSA_PROP_DATA; 10854 if (prop_flags->is_unreachable) 10855 num |= XTENSA_PROP_UNREACHABLE; 10856 if (prop_flags->insn.is_loop_target) 10857 num |= XTENSA_PROP_INSN_LOOP_TARGET; 10858 if (prop_flags->insn.is_branch_target) 10859 { 10860 num |= XTENSA_PROP_INSN_BRANCH_TARGET; 10861 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); 10862 } 10863 10864 if (prop_flags->insn.is_no_density) 10865 num |= XTENSA_PROP_INSN_NO_DENSITY; 10866 if (prop_flags->is_no_transform) 10867 num |= XTENSA_PROP_NO_TRANSFORM; 10868 if (prop_flags->insn.is_no_reorder) 10869 num |= XTENSA_PROP_INSN_NO_REORDER; 10870 if (prop_flags->insn.is_abslit) 10871 num |= XTENSA_PROP_INSN_ABSLIT; 10872 10873 if (prop_flags->is_align) 10874 { 10875 num |= XTENSA_PROP_ALIGN; 10876 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); 10877 } 10878 10879 return num; 10880 } 10881 10882 10883 static bfd_boolean 10884 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, 10885 const frag_flags *prop_flags_2) 10886 { 10887 /* Cannot combine with an end marker. */ 10888 10889 if (prop_flags_1->is_literal != prop_flags_2->is_literal) 10890 return FALSE; 10891 if (prop_flags_1->is_insn != prop_flags_2->is_insn) 10892 return FALSE; 10893 if (prop_flags_1->is_data != prop_flags_2->is_data) 10894 return FALSE; 10895 10896 if (prop_flags_1->is_insn) 10897 { 10898 /* Properties of the beginning of the frag. */ 10899 if (prop_flags_2->insn.is_loop_target) 10900 return FALSE; 10901 if (prop_flags_2->insn.is_branch_target) 10902 return FALSE; 10903 if (prop_flags_1->insn.is_no_density != 10904 prop_flags_2->insn.is_no_density) 10905 return FALSE; 10906 if (prop_flags_1->is_no_transform != 10907 prop_flags_2->is_no_transform) 10908 return FALSE; 10909 if (prop_flags_1->insn.is_no_reorder != 10910 prop_flags_2->insn.is_no_reorder) 10911 return FALSE; 10912 if (prop_flags_1->insn.is_abslit != 10913 prop_flags_2->insn.is_abslit) 10914 return FALSE; 10915 } 10916 10917 if (prop_flags_1->is_align) 10918 return FALSE; 10919 10920 return TRUE; 10921 } 10922 10923 10924 static bfd_vma 10925 xt_block_aligned_size (const xtensa_block_info *xt_block) 10926 { 10927 bfd_vma end_addr; 10928 unsigned align_bits; 10929 10930 if (!xt_block->flags.is_align) 10931 return xt_block->size; 10932 10933 end_addr = xt_block->offset + xt_block->size; 10934 align_bits = xt_block->flags.alignment; 10935 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; 10936 return end_addr - xt_block->offset; 10937 } 10938 10939 10940 static bfd_boolean 10941 xtensa_xt_block_combine (xtensa_block_info *xt_block, 10942 const xtensa_block_info *xt_block_2) 10943 { 10944 if (xt_block->sec != xt_block_2->sec) 10945 return FALSE; 10946 if (xt_block->offset + xt_block_aligned_size (xt_block) 10947 != xt_block_2->offset) 10948 return FALSE; 10949 10950 if (xt_block_2->size == 0 10951 && (!xt_block_2->flags.is_unreachable 10952 || xt_block->flags.is_unreachable)) 10953 { 10954 if (xt_block_2->flags.is_align 10955 && xt_block->flags.is_align) 10956 { 10957 /* Nothing needed. */ 10958 if (xt_block->flags.alignment >= xt_block_2->flags.alignment) 10959 return TRUE; 10960 } 10961 else 10962 { 10963 if (xt_block_2->flags.is_align) 10964 { 10965 /* Push alignment to previous entry. */ 10966 xt_block->flags.is_align = xt_block_2->flags.is_align; 10967 xt_block->flags.alignment = xt_block_2->flags.alignment; 10968 } 10969 return TRUE; 10970 } 10971 } 10972 if (!xtensa_frag_flags_combinable (&xt_block->flags, 10973 &xt_block_2->flags)) 10974 return FALSE; 10975 10976 xt_block->size += xt_block_2->size; 10977 10978 if (xt_block_2->flags.is_align) 10979 { 10980 xt_block->flags.is_align = TRUE; 10981 xt_block->flags.alignment = xt_block_2->flags.alignment; 10982 } 10983 10984 return TRUE; 10985 } 10986 10987 10988 static void 10989 add_xt_prop_frags (segT sec, 10990 xtensa_block_info **xt_block, 10991 frag_flags_fn property_function) 10992 { 10993 bfd_vma seg_offset; 10994 fragS *fragP; 10995 10996 /* Build it if needed. */ 10997 while (*xt_block != NULL) 10998 { 10999 xt_block = &(*xt_block)->next; 11000 } 11001 /* We are either at NULL at the beginning or at the end. */ 11002 11003 /* Walk through the frags. */ 11004 seg_offset = 0; 11005 11006 if (seg_info (sec)->frchainP) 11007 { 11008 for (fragP = seg_info (sec)->frchainP->frch_root; fragP; 11009 fragP = fragP->fr_next) 11010 { 11011 xtensa_block_info tmp_block; 11012 tmp_block.sec = sec; 11013 tmp_block.offset = fragP->fr_address; 11014 tmp_block.size = fragP->fr_fix; 11015 tmp_block.next = NULL; 11016 property_function (fragP, &tmp_block.flags); 11017 11018 if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) 11019 /* && fragP->fr_fix != 0) */ 11020 { 11021 if ((*xt_block) == NULL 11022 || !xtensa_xt_block_combine (*xt_block, &tmp_block)) 11023 { 11024 xtensa_block_info *new_block; 11025 if ((*xt_block) != NULL) 11026 xt_block = &(*xt_block)->next; 11027 new_block = (xtensa_block_info *) 11028 xmalloc (sizeof (xtensa_block_info)); 11029 *new_block = tmp_block; 11030 *xt_block = new_block; 11031 } 11032 } 11033 } 11034 } 11035 } 11036 11037 11038 /* op_placement_info_table */ 11039 11040 /* op_placement_info makes it easier to determine which 11041 ops can go in which slots. */ 11042 11043 static void 11044 init_op_placement_info_table (void) 11045 { 11046 xtensa_isa isa = xtensa_default_isa; 11047 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); 11048 xtensa_opcode opcode; 11049 xtensa_format fmt; 11050 int slot; 11051 int num_opcodes = xtensa_isa_num_opcodes (isa); 11052 11053 op_placement_table = (op_placement_info_table) 11054 xmalloc (sizeof (op_placement_info) * num_opcodes); 11055 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); 11056 11057 for (opcode = 0; opcode < num_opcodes; opcode++) 11058 { 11059 op_placement_info *opi = &op_placement_table[opcode]; 11060 /* FIXME: Make tinsn allocation dynamic. */ 11061 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) 11062 as_fatal (_("too many operands in instruction")); 11063 opi->narrowest = XTENSA_UNDEFINED; 11064 opi->narrowest_size = 0x7F; 11065 opi->narrowest_slot = 0; 11066 opi->formats = 0; 11067 opi->num_formats = 0; 11068 opi->issuef = 0; 11069 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 11070 { 11071 opi->slots[fmt] = 0; 11072 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 11073 { 11074 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) 11075 { 11076 int fmt_length = xtensa_format_length (isa, fmt); 11077 opi->issuef++; 11078 set_bit (fmt, opi->formats); 11079 set_bit (slot, opi->slots[fmt]); 11080 if (fmt_length < opi->narrowest_size 11081 || (fmt_length == opi->narrowest_size 11082 && (xtensa_format_num_slots (isa, fmt) 11083 < xtensa_format_num_slots (isa, 11084 opi->narrowest)))) 11085 { 11086 opi->narrowest = fmt; 11087 opi->narrowest_size = fmt_length; 11088 opi->narrowest_slot = slot; 11089 } 11090 } 11091 } 11092 if (opi->formats) 11093 opi->num_formats++; 11094 } 11095 } 11096 xtensa_insnbuf_free (isa, ibuf); 11097 } 11098 11099 11100 bfd_boolean 11101 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) 11102 { 11103 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); 11104 } 11105 11106 11107 /* If the opcode is available in a single slot format, return its size. */ 11108 11109 static int 11110 xg_get_single_size (xtensa_opcode opcode) 11111 { 11112 return op_placement_table[opcode].narrowest_size; 11113 } 11114 11115 11116 static xtensa_format 11117 xg_get_single_format (xtensa_opcode opcode) 11118 { 11119 return op_placement_table[opcode].narrowest; 11120 } 11121 11122 11123 static int 11124 xg_get_single_slot (xtensa_opcode opcode) 11125 { 11126 return op_placement_table[opcode].narrowest_slot; 11127 } 11128 11129 11130 /* Instruction Stack Functions (from "xtensa-istack.h"). */ 11131 11132 void 11133 istack_init (IStack *stack) 11134 { 11135 memset (stack, 0, sizeof (IStack)); 11136 stack->ninsn = 0; 11137 } 11138 11139 11140 bfd_boolean 11141 istack_empty (IStack *stack) 11142 { 11143 return (stack->ninsn == 0); 11144 } 11145 11146 11147 bfd_boolean 11148 istack_full (IStack *stack) 11149 { 11150 return (stack->ninsn == MAX_ISTACK); 11151 } 11152 11153 11154 /* Return a pointer to the top IStack entry. 11155 It is an error to call this if istack_empty () is TRUE. */ 11156 11157 TInsn * 11158 istack_top (IStack *stack) 11159 { 11160 int rec = stack->ninsn - 1; 11161 assert (!istack_empty (stack)); 11162 return &stack->insn[rec]; 11163 } 11164 11165 11166 /* Add a new TInsn to an IStack. 11167 It is an error to call this if istack_full () is TRUE. */ 11168 11169 void 11170 istack_push (IStack *stack, TInsn *insn) 11171 { 11172 int rec = stack->ninsn; 11173 assert (!istack_full (stack)); 11174 stack->insn[rec] = *insn; 11175 stack->ninsn++; 11176 } 11177 11178 11179 /* Clear space for the next TInsn on the IStack and return a pointer 11180 to it. It is an error to call this if istack_full () is TRUE. */ 11181 11182 TInsn * 11183 istack_push_space (IStack *stack) 11184 { 11185 int rec = stack->ninsn; 11186 TInsn *insn; 11187 assert (!istack_full (stack)); 11188 insn = &stack->insn[rec]; 11189 tinsn_init (insn); 11190 stack->ninsn++; 11191 return insn; 11192 } 11193 11194 11195 /* Remove the last pushed instruction. It is an error to call this if 11196 istack_empty () returns TRUE. */ 11197 11198 void 11199 istack_pop (IStack *stack) 11200 { 11201 int rec = stack->ninsn - 1; 11202 assert (!istack_empty (stack)); 11203 stack->ninsn--; 11204 tinsn_init (&stack->insn[rec]); 11205 } 11206 11207 11208 /* TInsn functions. */ 11209 11210 void 11211 tinsn_init (TInsn *dst) 11212 { 11213 memset (dst, 0, sizeof (TInsn)); 11214 } 11215 11216 11217 /* Return TRUE if ANY of the operands in the insn are symbolic. */ 11218 11219 static bfd_boolean 11220 tinsn_has_symbolic_operands (const TInsn *insn) 11221 { 11222 int i; 11223 int n = insn->ntok; 11224 11225 assert (insn->insn_type == ITYPE_INSN); 11226 11227 for (i = 0; i < n; ++i) 11228 { 11229 switch (insn->tok[i].X_op) 11230 { 11231 case O_register: 11232 case O_constant: 11233 break; 11234 default: 11235 return TRUE; 11236 } 11237 } 11238 return FALSE; 11239 } 11240 11241 11242 bfd_boolean 11243 tinsn_has_invalid_symbolic_operands (const TInsn *insn) 11244 { 11245 xtensa_isa isa = xtensa_default_isa; 11246 int i; 11247 int n = insn->ntok; 11248 11249 assert (insn->insn_type == ITYPE_INSN); 11250 11251 for (i = 0; i < n; ++i) 11252 { 11253 switch (insn->tok[i].X_op) 11254 { 11255 case O_register: 11256 case O_constant: 11257 break; 11258 case O_big: 11259 case O_illegal: 11260 case O_absent: 11261 /* Errors for these types are caught later. */ 11262 break; 11263 case O_hi16: 11264 case O_lo16: 11265 default: 11266 /* Symbolic immediates are only allowed on the last immediate 11267 operand. At this time, CONST16 is the only opcode where we 11268 support non-PC-relative relocations. */ 11269 if (i != get_relaxable_immed (insn->opcode) 11270 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 11271 && insn->opcode != xtensa_const16_opcode)) 11272 { 11273 as_bad (_("invalid symbolic operand")); 11274 return TRUE; 11275 } 11276 } 11277 } 11278 return FALSE; 11279 } 11280 11281 11282 /* For assembly code with complex expressions (e.g. subtraction), 11283 we have to build them in the literal pool so that 11284 their results are calculated correctly after relaxation. 11285 The relaxation only handles expressions that 11286 boil down to SYMBOL + OFFSET. */ 11287 11288 static bfd_boolean 11289 tinsn_has_complex_operands (const TInsn *insn) 11290 { 11291 int i; 11292 int n = insn->ntok; 11293 assert (insn->insn_type == ITYPE_INSN); 11294 for (i = 0; i < n; ++i) 11295 { 11296 switch (insn->tok[i].X_op) 11297 { 11298 case O_register: 11299 case O_constant: 11300 case O_symbol: 11301 case O_lo16: 11302 case O_hi16: 11303 break; 11304 default: 11305 return TRUE; 11306 } 11307 } 11308 return FALSE; 11309 } 11310 11311 11312 /* Encode a TInsn opcode and its constant operands into slotbuf. 11313 Return TRUE if there is a symbol in the immediate field. This 11314 function assumes that: 11315 1) The number of operands are correct. 11316 2) The insn_type is ITYPE_INSN. 11317 3) The opcode can be encoded in the specified format and slot. 11318 4) Operands are either O_constant or O_symbol, and all constants fit. */ 11319 11320 static bfd_boolean 11321 tinsn_to_slotbuf (xtensa_format fmt, 11322 int slot, 11323 TInsn *tinsn, 11324 xtensa_insnbuf slotbuf) 11325 { 11326 xtensa_isa isa = xtensa_default_isa; 11327 xtensa_opcode opcode = tinsn->opcode; 11328 bfd_boolean has_fixup = FALSE; 11329 int noperands = xtensa_opcode_num_operands (isa, opcode); 11330 int i; 11331 11332 assert (tinsn->insn_type == ITYPE_INSN); 11333 if (noperands != tinsn->ntok) 11334 as_fatal (_("operand number mismatch")); 11335 11336 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) 11337 { 11338 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), 11339 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); 11340 return FALSE; 11341 } 11342 11343 for (i = 0; i < noperands; i++) 11344 { 11345 expressionS *expr = &tinsn->tok[i]; 11346 int rc; 11347 unsigned line; 11348 char *file_name; 11349 uint32 opnd_value; 11350 11351 switch (expr->X_op) 11352 { 11353 case O_register: 11354 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11355 break; 11356 /* The register number has already been checked in 11357 expression_maybe_register, so we don't need to check here. */ 11358 opnd_value = expr->X_add_number; 11359 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); 11360 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, 11361 opnd_value); 11362 if (rc != 0) 11363 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); 11364 break; 11365 11366 case O_constant: 11367 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11368 break; 11369 as_where (&file_name, &line); 11370 /* It is a constant and we called this function 11371 then we have to try to fit it. */ 11372 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, 11373 expr->X_add_number, file_name, line); 11374 break; 11375 11376 default: 11377 has_fixup = TRUE; 11378 break; 11379 } 11380 } 11381 11382 return has_fixup; 11383 } 11384 11385 11386 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded 11387 into a multi-slot instruction, fill the other slots with NOPs. 11388 Return TRUE if there is a symbol in the immediate field. See also the 11389 assumptions listed for tinsn_to_slotbuf. */ 11390 11391 static bfd_boolean 11392 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) 11393 { 11394 static xtensa_insnbuf slotbuf = 0; 11395 static vliw_insn vinsn; 11396 xtensa_isa isa = xtensa_default_isa; 11397 bfd_boolean has_fixup = FALSE; 11398 int i; 11399 11400 if (!slotbuf) 11401 { 11402 slotbuf = xtensa_insnbuf_alloc (isa); 11403 xg_init_vinsn (&vinsn); 11404 } 11405 11406 xg_clear_vinsn (&vinsn); 11407 11408 bundle_tinsn (tinsn, &vinsn); 11409 11410 xtensa_format_encode (isa, vinsn.format, insnbuf); 11411 11412 for (i = 0; i < vinsn.num_slots; i++) 11413 { 11414 /* Only one slot may have a fix-up because the rest contains NOPs. */ 11415 has_fixup |= 11416 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); 11417 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); 11418 } 11419 11420 return has_fixup; 11421 } 11422 11423 11424 /* Check the instruction arguments. Return TRUE on failure. */ 11425 11426 static bfd_boolean 11427 tinsn_check_arguments (const TInsn *insn) 11428 { 11429 xtensa_isa isa = xtensa_default_isa; 11430 xtensa_opcode opcode = insn->opcode; 11431 11432 if (opcode == XTENSA_UNDEFINED) 11433 { 11434 as_bad (_("invalid opcode")); 11435 return TRUE; 11436 } 11437 11438 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) 11439 { 11440 as_bad (_("too few operands")); 11441 return TRUE; 11442 } 11443 11444 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) 11445 { 11446 as_bad (_("too many operands")); 11447 return TRUE; 11448 } 11449 return FALSE; 11450 } 11451 11452 11453 /* Load an instruction from its encoded form. */ 11454 11455 static void 11456 tinsn_from_chars (TInsn *tinsn, char *f, int slot) 11457 { 11458 vliw_insn vinsn; 11459 11460 xg_init_vinsn (&vinsn); 11461 vinsn_from_chars (&vinsn, f); 11462 11463 *tinsn = vinsn.slots[slot]; 11464 xg_free_vinsn (&vinsn); 11465 } 11466 11467 11468 static void 11469 tinsn_from_insnbuf (TInsn *tinsn, 11470 xtensa_insnbuf slotbuf, 11471 xtensa_format fmt, 11472 int slot) 11473 { 11474 int i; 11475 xtensa_isa isa = xtensa_default_isa; 11476 11477 /* Find the immed. */ 11478 tinsn_init (tinsn); 11479 tinsn->insn_type = ITYPE_INSN; 11480 tinsn->is_specific_opcode = FALSE; /* must not be specific */ 11481 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 11482 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); 11483 for (i = 0; i < tinsn->ntok; i++) 11484 { 11485 set_expr_const (&tinsn->tok[i], 11486 xtensa_insnbuf_get_operand (slotbuf, fmt, slot, 11487 tinsn->opcode, i)); 11488 } 11489 } 11490 11491 11492 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ 11493 11494 static void 11495 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) 11496 { 11497 xtensa_opcode opcode = tinsn->opcode; 11498 int opnum; 11499 11500 if (fragP->tc_frag_data.slot_symbols[slot]) 11501 { 11502 opnum = get_relaxable_immed (opcode); 11503 assert (opnum >= 0); 11504 set_expr_symbol_offset (&tinsn->tok[opnum], 11505 fragP->tc_frag_data.slot_symbols[slot], 11506 fragP->tc_frag_data.slot_offsets[slot]); 11507 } 11508 } 11509 11510 11511 static int 11512 get_num_stack_text_bytes (IStack *istack) 11513 { 11514 int i; 11515 int text_bytes = 0; 11516 11517 for (i = 0; i < istack->ninsn; i++) 11518 { 11519 TInsn *tinsn = &istack->insn[i]; 11520 if (tinsn->insn_type == ITYPE_INSN) 11521 text_bytes += xg_get_single_size (tinsn->opcode); 11522 } 11523 return text_bytes; 11524 } 11525 11526 11527 static int 11528 get_num_stack_literal_bytes (IStack *istack) 11529 { 11530 int i; 11531 int lit_bytes = 0; 11532 11533 for (i = 0; i < istack->ninsn; i++) 11534 { 11535 TInsn *tinsn = &istack->insn[i]; 11536 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) 11537 lit_bytes += 4; 11538 } 11539 return lit_bytes; 11540 } 11541 11542 11543 /* vliw_insn functions. */ 11544 11545 static void 11546 xg_init_vinsn (vliw_insn *v) 11547 { 11548 int i; 11549 xtensa_isa isa = xtensa_default_isa; 11550 11551 xg_clear_vinsn (v); 11552 11553 v->insnbuf = xtensa_insnbuf_alloc (isa); 11554 if (v->insnbuf == NULL) 11555 as_fatal (_("out of memory")); 11556 11557 for (i = 0; i < MAX_SLOTS; i++) 11558 { 11559 v->slotbuf[i] = xtensa_insnbuf_alloc (isa); 11560 if (v->slotbuf[i] == NULL) 11561 as_fatal (_("out of memory")); 11562 } 11563 } 11564 11565 11566 static void 11567 xg_clear_vinsn (vliw_insn *v) 11568 { 11569 int i; 11570 11571 memset (v, 0, offsetof (vliw_insn, insnbuf)); 11572 11573 v->format = XTENSA_UNDEFINED; 11574 v->num_slots = 0; 11575 v->inside_bundle = FALSE; 11576 11577 if (xt_saved_debug_type != DEBUG_NONE) 11578 debug_type = xt_saved_debug_type; 11579 11580 for (i = 0; i < MAX_SLOTS; i++) 11581 v->slots[i].opcode = XTENSA_UNDEFINED; 11582 } 11583 11584 11585 static bfd_boolean 11586 vinsn_has_specific_opcodes (vliw_insn *v) 11587 { 11588 int i; 11589 11590 for (i = 0; i < v->num_slots; i++) 11591 { 11592 if (v->slots[i].is_specific_opcode) 11593 return TRUE; 11594 } 11595 return FALSE; 11596 } 11597 11598 11599 static void 11600 xg_free_vinsn (vliw_insn *v) 11601 { 11602 int i; 11603 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); 11604 for (i = 0; i < MAX_SLOTS; i++) 11605 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); 11606 } 11607 11608 11609 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic 11610 operands. See also the assumptions listed for tinsn_to_slotbuf. */ 11611 11612 static bfd_boolean 11613 vinsn_to_insnbuf (vliw_insn *vinsn, 11614 char *frag_offset, 11615 fragS *fragP, 11616 bfd_boolean record_fixup) 11617 { 11618 xtensa_isa isa = xtensa_default_isa; 11619 xtensa_format fmt = vinsn->format; 11620 xtensa_insnbuf insnbuf = vinsn->insnbuf; 11621 int slot; 11622 bfd_boolean has_fixup = FALSE; 11623 11624 xtensa_format_encode (isa, fmt, insnbuf); 11625 11626 for (slot = 0; slot < vinsn->num_slots; slot++) 11627 { 11628 TInsn *tinsn = &vinsn->slots[slot]; 11629 expressionS *tls_reloc = &tinsn->tls_reloc; 11630 bfd_boolean tinsn_has_fixup = 11631 tinsn_to_slotbuf (vinsn->format, slot, tinsn, 11632 vinsn->slotbuf[slot]); 11633 11634 xtensa_format_set_slot (isa, fmt, slot, 11635 insnbuf, vinsn->slotbuf[slot]); 11636 if (tls_reloc->X_op != O_illegal) 11637 { 11638 if (vinsn->num_slots != 1) 11639 as_bad (_("TLS relocation not allowed in FLIX bundle")); 11640 else if (record_fixup) 11641 /* Instructions that generate TLS relocations should always be 11642 relaxed in the front-end. If "record_fixup" is set, then this 11643 function is being called during back-end relaxation, so flag 11644 the unexpected behavior as an error. */ 11645 as_bad (_("unexpected TLS relocation")); 11646 else 11647 fix_new (fragP, frag_offset - fragP->fr_literal, 11648 xtensa_format_length (isa, fmt), 11649 tls_reloc->X_add_symbol, tls_reloc->X_add_number, 11650 FALSE, map_operator_to_reloc (tls_reloc->X_op, FALSE)); 11651 } 11652 if (tinsn_has_fixup) 11653 { 11654 int i; 11655 xtensa_opcode opcode = tinsn->opcode; 11656 int noperands = xtensa_opcode_num_operands (isa, opcode); 11657 has_fixup = TRUE; 11658 11659 for (i = 0; i < noperands; i++) 11660 { 11661 expressionS* expr = &tinsn->tok[i]; 11662 switch (expr->X_op) 11663 { 11664 case O_symbol: 11665 case O_lo16: 11666 case O_hi16: 11667 if (get_relaxable_immed (opcode) == i) 11668 { 11669 /* Add a fix record for the instruction, except if this 11670 function is being called prior to relaxation, i.e., 11671 if record_fixup is false, and the instruction might 11672 be relaxed later. */ 11673 if (record_fixup 11674 || tinsn->is_specific_opcode 11675 || !xg_is_relaxable_insn (tinsn, 0)) 11676 { 11677 xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, 11678 frag_offset - fragP->fr_literal); 11679 } 11680 else 11681 { 11682 if (expr->X_op != O_symbol) 11683 as_bad (_("invalid operand")); 11684 tinsn->symbol = expr->X_add_symbol; 11685 tinsn->offset = expr->X_add_number; 11686 } 11687 } 11688 else 11689 as_bad (_("symbolic operand not allowed")); 11690 break; 11691 11692 case O_constant: 11693 case O_register: 11694 break; 11695 11696 default: 11697 as_bad (_("expression too complex")); 11698 break; 11699 } 11700 } 11701 } 11702 } 11703 11704 return has_fixup; 11705 } 11706 11707 11708 static void 11709 vinsn_from_chars (vliw_insn *vinsn, char *f) 11710 { 11711 static xtensa_insnbuf insnbuf = NULL; 11712 static xtensa_insnbuf slotbuf = NULL; 11713 int i; 11714 xtensa_format fmt; 11715 xtensa_isa isa = xtensa_default_isa; 11716 11717 if (!insnbuf) 11718 { 11719 insnbuf = xtensa_insnbuf_alloc (isa); 11720 slotbuf = xtensa_insnbuf_alloc (isa); 11721 } 11722 11723 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); 11724 fmt = xtensa_format_decode (isa, insnbuf); 11725 if (fmt == XTENSA_UNDEFINED) 11726 as_fatal (_("cannot decode instruction format")); 11727 vinsn->format = fmt; 11728 vinsn->num_slots = xtensa_format_num_slots (isa, fmt); 11729 11730 for (i = 0; i < vinsn->num_slots; i++) 11731 { 11732 TInsn *tinsn = &vinsn->slots[i]; 11733 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); 11734 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); 11735 } 11736 } 11737 11738 11739 /* Expression utilities. */ 11740 11741 /* Return TRUE if the expression is an integer constant. */ 11742 11743 bfd_boolean 11744 expr_is_const (const expressionS *s) 11745 { 11746 return (s->X_op == O_constant); 11747 } 11748 11749 11750 /* Get the expression constant. 11751 Calling this is illegal if expr_is_const () returns TRUE. */ 11752 11753 offsetT 11754 get_expr_const (const expressionS *s) 11755 { 11756 assert (expr_is_const (s)); 11757 return s->X_add_number; 11758 } 11759 11760 11761 /* Set the expression to a constant value. */ 11762 11763 void 11764 set_expr_const (expressionS *s, offsetT val) 11765 { 11766 s->X_op = O_constant; 11767 s->X_add_number = val; 11768 s->X_add_symbol = NULL; 11769 s->X_op_symbol = NULL; 11770 } 11771 11772 11773 bfd_boolean 11774 expr_is_register (const expressionS *s) 11775 { 11776 return (s->X_op == O_register); 11777 } 11778 11779 11780 /* Get the expression constant. 11781 Calling this is illegal if expr_is_const () returns TRUE. */ 11782 11783 offsetT 11784 get_expr_register (const expressionS *s) 11785 { 11786 assert (expr_is_register (s)); 11787 return s->X_add_number; 11788 } 11789 11790 11791 /* Set the expression to a symbol + constant offset. */ 11792 11793 void 11794 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) 11795 { 11796 s->X_op = O_symbol; 11797 s->X_add_symbol = sym; 11798 s->X_op_symbol = NULL; /* unused */ 11799 s->X_add_number = offset; 11800 } 11801 11802 11803 /* Return TRUE if the two expressions are equal. */ 11804 11805 bfd_boolean 11806 expr_is_equal (expressionS *s1, expressionS *s2) 11807 { 11808 if (s1->X_op != s2->X_op) 11809 return FALSE; 11810 if (s1->X_add_symbol != s2->X_add_symbol) 11811 return FALSE; 11812 if (s1->X_op_symbol != s2->X_op_symbol) 11813 return FALSE; 11814 if (s1->X_add_number != s2->X_add_number) 11815 return FALSE; 11816 return TRUE; 11817 } 11818 11819 11820 static void 11821 copy_expr (expressionS *dst, const expressionS *src) 11822 { 11823 memcpy (dst, src, sizeof (expressionS)); 11824 } 11825 11826 11827 /* Support for the "--rename-section" option. */ 11828 11829 struct rename_section_struct 11830 { 11831 char *old_name; 11832 char *new_name; 11833 struct rename_section_struct *next; 11834 }; 11835 11836 static struct rename_section_struct *section_rename; 11837 11838 11839 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add 11840 entries to the section_rename list. Note: Specifying multiple 11841 renamings separated by colons is not documented and is retained only 11842 for backward compatibility. */ 11843 11844 static void 11845 build_section_rename (const char *arg) 11846 { 11847 struct rename_section_struct *r; 11848 char *this_arg = NULL; 11849 char *next_arg = NULL; 11850 11851 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) 11852 { 11853 char *old_name, *new_name; 11854 11855 if (this_arg) 11856 { 11857 next_arg = strchr (this_arg, ':'); 11858 if (next_arg) 11859 { 11860 *next_arg = '\0'; 11861 next_arg++; 11862 } 11863 } 11864 11865 old_name = this_arg; 11866 new_name = strchr (this_arg, '='); 11867 11868 if (*old_name == '\0') 11869 { 11870 as_warn (_("ignoring extra '-rename-section' delimiter ':'")); 11871 continue; 11872 } 11873 if (!new_name || new_name[1] == '\0') 11874 { 11875 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), 11876 old_name); 11877 continue; 11878 } 11879 *new_name = '\0'; 11880 new_name++; 11881 11882 /* Check for invalid section renaming. */ 11883 for (r = section_rename; r != NULL; r = r->next) 11884 { 11885 if (strcmp (r->old_name, old_name) == 0) 11886 as_bad (_("section %s renamed multiple times"), old_name); 11887 if (strcmp (r->new_name, new_name) == 0) 11888 as_bad (_("multiple sections remapped to output section %s"), 11889 new_name); 11890 } 11891 11892 /* Now add it. */ 11893 r = (struct rename_section_struct *) 11894 xmalloc (sizeof (struct rename_section_struct)); 11895 r->old_name = xstrdup (old_name); 11896 r->new_name = xstrdup (new_name); 11897 r->next = section_rename; 11898 section_rename = r; 11899 } 11900 } 11901 11902 11903 char * 11904 xtensa_section_rename (char *name) 11905 { 11906 struct rename_section_struct *r = section_rename; 11907 11908 for (r = section_rename; r != NULL; r = r->next) 11909 { 11910 if (strcmp (r->old_name, name) == 0) 11911 return r->new_name; 11912 } 11913 11914 return name; 11915 } 11916