1@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, 2@c 2004 Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@ifset GENERIC 6@page 7@node M68K-Dependent 8@chapter M680x0 Dependent Features 9@end ifset 10@ifclear GENERIC 11@node Machine Dependencies 12@chapter M680x0 Dependent Features 13@end ifclear 14 15@cindex M680x0 support 16@menu 17* M68K-Opts:: M680x0 Options 18* M68K-Syntax:: Syntax 19* M68K-Moto-Syntax:: Motorola Syntax 20* M68K-Float:: Floating Point 21* M68K-Directives:: 680x0 Machine Directives 22* M68K-opcodes:: Opcodes 23@end menu 24 25@node M68K-Opts 26@section M680x0 Options 27 28@cindex options, M680x0 29@cindex M680x0 options 30The Motorola 680x0 version of @code{@value{AS}} has a few machine 31dependent options: 32 33@table @samp 34 35@cindex @samp{-march=} command line option, M680x0 36@item -march=@var{architecture} 37This option specifies a target architecture. The following 38architectures are recognized: 39@code{68000}, 40@code{68010}, 41@code{68020}, 42@code{68030}, 43@code{68040}, 44@code{68060}, 45@code{cpu32}, 46@code{isaa}, 47@code{isaaplus}, 48@code{isab}, 49@code{isac} and 50@code{cfv4e}. 51 52 53@cindex @samp{-mcpu=} command line option, M680x0 54@item -mcpu=@var{cpu} 55This option specifies a target cpu. When used in conjunction with the 56@option{-march} option, the cpu must be within the specified 57architecture. Also, the generic features of the architecture are used 58for instruction generation, rather than those of the specific chip. 59 60@cindex @samp{-m[no-]68851} command line option, M680x0 61@cindex @samp{-m[no-]68881} command line option, M680x0 62@cindex @samp{-m[no-]div} command line option, M680x0 63@cindex @samp{-m[no-]usp} command line option, M680x0 64@cindex @samp{-m[no-]float} command line option, M680x0 65@cindex @samp{-m[no-]mac} command line option, M680x0 66@cindex @samp{-m[no-]emac} command line option, M680x0 67@item -m[no-]68851 68@item -m[no-]68881 69@item -m[no-]div 70@item -m[no-]usp 71@item -m[no-]float 72@item -m[no-]mac 73@item -m[no-]emac 74 75Enable or disable various architecture specific features. If a chip 76or architecture by default supports an option (for instance 77@option{-march=isaaplus} includes the @option{-mdiv} option), 78explicitly disabling the option will override the default. 79 80@cindex @samp{-l} option, M680x0 81@item -l 82You can use the @samp{-l} option to shorten the size of references to undefined 83symbols. If you do not use the @samp{-l} option, references to undefined 84symbols are wide enough for a full @code{long} (32 bits). (Since 85@code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can 86only allocate space for the linker to fill in later. Since @code{@value{AS}} 87does not know how far away these symbols are, it allocates as much space as it 88can.) If you use this option, the references are only one word wide (16 bits). 89This may be useful if you want the object file to be as small as possible, and 90you know that the relevant symbols are always less than 17 bits away. 91 92@cindex @samp{--register-prefix-optional} option, M680x0 93@item --register-prefix-optional 94For some configurations, especially those where the compiler normally 95does not prepend an underscore to the names of user variables, the 96assembler requires a @samp{%} before any use of a register name. This 97is intended to let the assembler distinguish between C variables and 98functions named @samp{a0} through @samp{a7}, and so on. The @samp{%} is 99always accepted, but is not required for certain configurations, notably 100@samp{sun3}. The @samp{--register-prefix-optional} option may be used 101to permit omitting the @samp{%} even for configurations for which it is 102normally required. If this is done, it will generally be impossible to 103refer to C variables and functions with the same names as register 104names. 105 106@cindex @samp{--bitwise-or} option, M680x0 107@item --bitwise-or 108Normally the character @samp{|} is treated as a comment character, which 109means that it can not be used in expressions. The @samp{--bitwise-or} 110option turns @samp{|} into a normal character. In this mode, you must 111either use C style comments, or start comments with a @samp{#} character 112at the beginning of a line. 113 114@cindex @samp{--base-size-default-16} 115@cindex @samp{--base-size-default-32} 116@item --base-size-default-16 --base-size-default-32 117If you use an addressing mode with a base register without specifying 118the size, @code{@value{AS}} will normally use the full 32 bit value. 119For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to 120@samp{%a0@@(%d0:l)}. You may use the @samp{--base-size-default-16} 121option to tell @code{@value{AS}} to default to using the 16 bit value. 122In this case, @samp{%a0@@(%d0)} is equivalent to @samp{%a0@@(%d0:w)}. 123You may use the @samp{--base-size-default-32} option to restore the 124default behaviour. 125 126@cindex @samp{--disp-size-default-16} 127@cindex @samp{--disp-size-default-32} 128@item --disp-size-default-16 --disp-size-default-32 129If you use an addressing mode with a displacement, and the value of the 130displacement is not known, @code{@value{AS}} will normally assume that 131the value is 32 bits. For example, if the symbol @samp{disp} has not 132been defined, @code{@value{AS}} will assemble the addressing mode 133@samp{%a0@@(disp,%d0)} as though @samp{disp} is a 32 bit value. You may 134use the @samp{--disp-size-default-16} option to tell @code{@value{AS}} 135to instead assume that the displacement is 16 bits. In this case, 136@code{@value{AS}} will assemble @samp{%a0@@(disp,%d0)} as though 137@samp{disp} is a 16 bit value. You may use the 138@samp{--disp-size-default-32} option to restore the default behaviour. 139 140@cindex @samp{--pcrel} 141@item --pcrel 142Always keep branches PC-relative. In the M680x0 architecture all branches 143are defined as PC-relative. However, on some processors they are limited 144to word displacements maximum. When @code{@value{AS}} needs a long branch 145that is not available, it normally emits an absolute jump instead. This 146option disables this substitution. When this option is given and no long 147branches are available, only word branches will be emitted. An error 148message will be generated if a word branch cannot reach its target. This 149option has no effect on 68020 and other processors that have long branches. 150@pxref{M68K-Branch,,Branch Improvement}. 151 152@cindex @samp{-m68000} and related options 153@cindex architecture options, M680x0 154@cindex M680x0 architecture options 155@item -m68000 156@code{@value{AS}} can assemble code for several different members of the 157Motorola 680x0 family. The default depends upon how @code{@value{AS}} 158was configured when it was built; normally, the default is to assemble 159code for the 68020 microprocessor. The following options may be used to 160change the default. These options control which instructions and 161addressing modes are permitted. The members of the 680x0 family are 162very similar. For detailed information about the differences, see the 163Motorola manuals. 164 165@table @samp 166@item -m68000 167@itemx -m68ec000 168@itemx -m68hc000 169@itemx -m68hc001 170@itemx -m68008 171@itemx -m68302 172@itemx -m68306 173@itemx -m68307 174@itemx -m68322 175@itemx -m68356 176Assemble for the 68000. @samp{-m68008}, @samp{-m68302}, and so on are synonyms 177for @samp{-m68000}, since the chips are the same from the point of view 178of the assembler. 179 180@item -m68010 181Assemble for the 68010. 182 183@item -m68020 184@itemx -m68ec020 185Assemble for the 68020. This is normally the default. 186 187@item -m68030 188@itemx -m68ec030 189Assemble for the 68030. 190 191@item -m68040 192@itemx -m68ec040 193Assemble for the 68040. 194 195@item -m68060 196@itemx -m68ec060 197Assemble for the 68060. 198 199@item -mcpu32 200@itemx -m68330 201@itemx -m68331 202@itemx -m68332 203@itemx -m68333 204@itemx -m68334 205@itemx -m68336 206@itemx -m68340 207@itemx -m68341 208@itemx -m68349 209@itemx -m68360 210Assemble for the CPU32 family of chips. 211 212@item -m5200 213@item -m5202 214@item -m5204 215@item -m5206 216@item -m5206e 217@item -m521x 218@item -m5249 219@item -m528x 220@item -m5307 221@item -m5407 222@item -m547x 223@item -m548x 224@item -mcfv4 225@item -mcfv4e 226Assemble for the ColdFire family of chips. 227 228@item -m68881 229@itemx -m68882 230Assemble 68881 floating point instructions. This is the default for the 23168020, 68030, and the CPU32. The 68040 and 68060 always support 232floating point instructions. 233 234@item -mno-68881 235Do not assemble 68881 floating point instructions. This is the default 236for 68000 and the 68010. The 68040 and 68060 always support floating 237point instructions, even if this option is used. 238 239@item -m68851 240Assemble 68851 MMU instructions. This is the default for the 68020, 24168030, and 68060. The 68040 accepts a somewhat different set of MMU 242instructions; @samp{-m68851} and @samp{-m68040} should not be used 243together. 244 245@item -mno-68851 246Do not assemble 68851 MMU instructions. This is the default for the 24768000, 68010, and the CPU32. The 68040 accepts a somewhat different set 248of MMU instructions. 249@end table 250@end table 251 252@node M68K-Syntax 253@section Syntax 254 255@cindex @sc{mit} 256This syntax for the Motorola 680x0 was developed at @sc{mit}. 257 258@cindex M680x0 syntax 259@cindex syntax, M680x0 260@cindex M680x0 size modifiers 261@cindex size modifiers, M680x0 262The 680x0 version of @code{@value{AS}} uses instructions names and 263syntax compatible with the Sun assembler. Intervening periods are 264ignored; for example, @samp{movl} is equivalent to @samp{mov.l}. 265 266In the following table @var{apc} stands for any of the address registers 267(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the 268zero-address relative to the program counter (@samp{%zpc}), a suppressed 269address register (@samp{%za0} through @samp{%za7}), or it may be omitted 270entirely. The use of @var{size} means one of @samp{w} or @samp{l}, and 271it may be omitted, along with the leading colon, unless a scale is also 272specified. The use of @var{scale} means one of @samp{1}, @samp{2}, 273@samp{4}, or @samp{8}, and it may always be omitted along with the 274leading colon. 275 276@cindex M680x0 addressing modes 277@cindex addressing modes, M680x0 278The following addressing modes are understood: 279@table @dfn 280@item Immediate 281@samp{#@var{number}} 282 283@item Data Register 284@samp{%d0} through @samp{%d7} 285 286@item Address Register 287@samp{%a0} through @samp{%a7}@* 288@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer. @code{%a6} 289is also known as @samp{%fp}, the Frame Pointer. 290 291@item Address Register Indirect 292@samp{%a0@@} through @samp{%a7@@} 293 294@item Address Register Postincrement 295@samp{%a0@@+} through @samp{%a7@@+} 296 297@item Address Register Predecrement 298@samp{%a0@@-} through @samp{%a7@@-} 299 300@item Indirect Plus Offset 301@samp{@var{apc}@@(@var{number})} 302 303@item Index 304@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})} 305 306The @var{number} may be omitted. 307 308@item Postindex 309@samp{@var{apc}@@(@var{number})@@(@var{onumber},@var{register}:@var{size}:@var{scale})} 310 311The @var{onumber} or the @var{register}, but not both, may be omitted. 312 313@item Preindex 314@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})@@(@var{onumber})} 315 316The @var{number} may be omitted. Omitting the @var{register} produces 317the Postindex addressing mode. 318 319@item Absolute 320@samp{@var{symbol}}, or @samp{@var{digits}}, optionally followed by 321@samp{:b}, @samp{:w}, or @samp{:l}. 322@end table 323 324@node M68K-Moto-Syntax 325@section Motorola Syntax 326 327@cindex Motorola syntax for the 680x0 328@cindex alternate syntax for the 680x0 329 330The standard Motorola syntax for this chip differs from the syntax 331already discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can 332accept Motorola syntax for operands, even if @sc{mit} syntax is used for 333other operands in the same instruction. The two kinds of syntax are 334fully compatible. 335 336In the following table @var{apc} stands for any of the address registers 337(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the 338zero-address relative to the program counter (@samp{%zpc}), or a 339suppressed address register (@samp{%za0} through @samp{%za7}). The use 340of @var{size} means one of @samp{w} or @samp{l}, and it may always be 341omitted along with the leading dot. The use of @var{scale} means one of 342@samp{1}, @samp{2}, @samp{4}, or @samp{8}, and it may always be omitted 343along with the leading asterisk. 344 345The following additional addressing modes are understood: 346 347@table @dfn 348@item Address Register Indirect 349@samp{(%a0)} through @samp{(%a7)}@* 350@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer. @code{%a6} 351is also known as @samp{%fp}, the Frame Pointer. 352 353@item Address Register Postincrement 354@samp{(%a0)+} through @samp{(%a7)+} 355 356@item Address Register Predecrement 357@samp{-(%a0)} through @samp{-(%a7)} 358 359@item Indirect Plus Offset 360@samp{@var{number}(@var{%a0})} through @samp{@var{number}(@var{%a7})}, 361or @samp{@var{number}(@var{%pc})}. 362 363The @var{number} may also appear within the parentheses, as in 364@samp{(@var{number},@var{%a0})}. When used with the @var{pc}, the 365@var{number} may be omitted (with an address register, omitting the 366@var{number} produces Address Register Indirect mode). 367 368@item Index 369@samp{@var{number}(@var{apc},@var{register}.@var{size}*@var{scale})} 370 371The @var{number} may be omitted, or it may appear within the 372parentheses. The @var{apc} may be omitted. The @var{register} and the 373@var{apc} may appear in either order. If both @var{apc} and 374@var{register} are address registers, and the @var{size} and @var{scale} 375are omitted, then the first register is taken as the base register, and 376the second as the index register. 377 378@item Postindex 379@samp{([@var{number},@var{apc}],@var{register}.@var{size}*@var{scale},@var{onumber})} 380 381The @var{onumber}, or the @var{register}, or both, may be omitted. 382Either the @var{number} or the @var{apc} may be omitted, but not both. 383 384@item Preindex 385@samp{([@var{number},@var{apc},@var{register}.@var{size}*@var{scale}],@var{onumber})} 386 387The @var{number}, or the @var{apc}, or the @var{register}, or any two of 388them, may be omitted. The @var{onumber} may be omitted. The 389@var{register} and the @var{apc} may appear in either order. If both 390@var{apc} and @var{register} are address registers, and the @var{size} 391and @var{scale} are omitted, then the first register is taken as the 392base register, and the second as the index register. 393@end table 394 395@node M68K-Float 396@section Floating Point 397 398@cindex floating point, M680x0 399@cindex M680x0 floating point 400Packed decimal (P) format floating literals are not supported. 401Feel free to add the code! 402 403The floating point formats generated by directives are these. 404 405@table @code 406@cindex @code{float} directive, M680x0 407@item .float 408@code{Single} precision floating point constants. 409 410@cindex @code{double} directive, M680x0 411@item .double 412@code{Double} precision floating point constants. 413 414@cindex @code{extend} directive M680x0 415@cindex @code{ldouble} directive M680x0 416@item .extend 417@itemx .ldouble 418@code{Extended} precision (@code{long double}) floating point constants. 419@end table 420 421@node M68K-Directives 422@section 680x0 Machine Directives 423 424@cindex M680x0 directives 425@cindex directives, M680x0 426In order to be compatible with the Sun assembler the 680x0 assembler 427understands the following directives. 428 429@table @code 430@cindex @code{data1} directive, M680x0 431@item .data1 432This directive is identical to a @code{.data 1} directive. 433 434@cindex @code{data2} directive, M680x0 435@item .data2 436This directive is identical to a @code{.data 2} directive. 437 438@cindex @code{even} directive, M680x0 439@item .even 440This directive is a special case of the @code{.align} directive; it 441aligns the output to an even byte boundary. 442 443@cindex @code{skip} directive, M680x0 444@item .skip 445This directive is identical to a @code{.space} directive. 446 447@cindex @code{arch} directive, M680x0 448@item .arch @var{name} 449Select the target architecture and extension features. Valid values 450for @var{name} are the same as for the @option{-march} command line 451option. This directive cannot be specified after 452any instructions have been assembled. If it is given multiple times, 453or in conjunction with the @option{-march} option, all uses must be for 454the same architecture and extension set. 455 456@cindex @code{cpu} directive, M680x0 457@item .cpu @var{name} 458Select the target cpu. Valid valuse 459for @var{name} are the same as for the @option{-mcpu} command line 460option. This directive cannot be specified after 461any instructions have been assembled. If it is given multiple times, 462or in conjunction with the @option{-mopt} option, all uses must be for 463the same cpu. 464 465@end table 466 467@need 2000 468@node M68K-opcodes 469@section Opcodes 470 471@cindex M680x0 opcodes 472@cindex opcodes, M680x0 473@cindex instruction set, M680x0 474@c doc@cygnus.com: I don't see any point in the following 475@c paragraph. Bugs are bugs; how does saying this 476@c help anyone? 477@ignore 478Danger: Several bugs have been found in the opcode table (and 479fixed). More bugs may exist. Be careful when using obscure 480instructions. 481@end ignore 482 483@menu 484* M68K-Branch:: Branch Improvement 485* M68K-Chars:: Special Characters 486@end menu 487 488@node M68K-Branch 489@subsection Branch Improvement 490 491@cindex pseudo-opcodes, M680x0 492@cindex M680x0 pseudo-opcodes 493@cindex branch improvement, M680x0 494@cindex M680x0 branch improvement 495Certain pseudo opcodes are permitted for branch instructions. 496They expand to the shortest branch instruction that reach the 497target. Generally these mnemonics are made by substituting @samp{j} for 498@samp{b} at the start of a Motorola mnemonic. 499 500The following table summarizes the pseudo-operations. A @code{*} flags 501cases that are more fully described after the table: 502 503@smallexample 504 Displacement 505 +------------------------------------------------------------ 506 | 68020 68000/10, not PC-relative OK 507Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 508 +------------------------------------------------------------ 509 jbsr |bsrs bsrw bsrl jsr 510 jra |bras braw bral jmp 511* jXX |bXXs bXXw bXXl bNXs;jmp 512* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 513 fjXX | N/A fbXXw fbXXl N/A 514 515XX: condition 516NX: negative of condition XX 517 518@end smallexample 519@center @code{*}---see full description below 520@center @code{**}---this expansion mode is disallowed by @samp{--pcrel} 521 522@table @code 523@item jbsr 524@itemx jra 525These are the simplest jump pseudo-operations; they always map to one 526particular machine instruction, depending on the displacement to the 527branch target. This instruction will be a byte or word branch is that 528is sufficient. Otherwise, a long branch will be emitted if available. 529If no long branches are available and the @samp{--pcrel} option is not 530given, an absolute long jump will be emitted instead. If no long 531branches are available, the @samp{--pcrel} option is given, and a word 532branch cannot reach the target, an error message is generated. 533 534In addition to standard branch operands, @code{@value{AS}} allows these 535pseudo-operations to have all operands that are allowed for jsr and jmp, 536substituting these instructions if the operand given is not valid for a 537branch instruction. 538 539@item j@var{XX} 540Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations, 541where @var{XX} is a conditional branch or condition-code test. The full 542list of pseudo-ops in this family is: 543@smallexample 544 jhi jls jcc jcs jne jeq jvc 545 jvs jpl jmi jge jlt jgt jle 546@end smallexample 547 548Usually, each of these pseudo-operations expands to a single branch 549instruction. However, if a word branch is not sufficient, no long branches 550are available, and the @samp{--pcrel} option is not given, @code{@value{AS}} 551issues a longer code fragment in terms of @var{NX}, the opposite condition 552to @var{XX}. For example, under these conditions: 553@smallexample 554 j@var{XX} foo 555@end smallexample 556gives 557@smallexample 558 b@var{NX}s oof 559 jmp foo 560 oof: 561@end smallexample 562 563@item db@var{XX} 564The full family of pseudo-operations covered here is 565@smallexample 566 dbhi dbls dbcc dbcs dbne dbeq dbvc 567 dbvs dbpl dbmi dbge dblt dbgt dble 568 dbf dbra dbt 569@end smallexample 570 571Motorola @samp{db@var{XX}} instructions allow word displacements only. When 572a word displacement is sufficient, each of these pseudo-operations expands 573to the corresponding Motorola instruction. When a word displacement is not 574sufficient and long branches are available, when the source reads 575@samp{db@var{XX} foo}, @code{@value{AS}} emits 576@smallexample 577 db@var{XX} oo1 578 bras oo2 579 oo1:bral foo 580 oo2: 581@end smallexample 582 583If, however, long branches are not available and the @samp{--pcrel} option is 584not given, @code{@value{AS}} emits 585@smallexample 586 db@var{XX} oo1 587 bras oo2 588 oo1:jmp foo 589 oo2: 590@end smallexample 591 592@item fj@var{XX} 593This family includes 594@smallexample 595 fjne fjeq fjge fjlt fjgt fjle fjf 596 fjt fjgl fjgle fjnge fjngl fjngle fjngt 597 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 598 fjor fjseq fjsf fjsne fjst fjueq fjuge 599 fjugt fjule fjult fjun 600@end smallexample 601 602Each of these pseudo-operations always expands to a single Motorola 603coprocessor branch instruction, word or long. All Motorola coprocessor 604branch instructions allow both word and long displacements. 605 606@end table 607 608@node M68K-Chars 609@subsection Special Characters 610 611@cindex special characters, M680x0 612@cindex M680x0 immediate character 613@cindex immediate character, M680x0 614@cindex M680x0 line comment character 615@cindex line comment character, M680x0 616@cindex comments, M680x0 617The immediate character is @samp{#} for Sun compatibility. The 618line-comment character is @samp{|} (unless the @samp{--bitwise-or} 619option is used). If a @samp{#} appears at the beginning of a line, it 620is treated as a comment unless it looks like @samp{# line file}, in 621which case it is treated normally. 622 623