1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS symbol sizes:: Directives to override the size of symbols 30* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 31* MIPS insn:: Directive to mark data as an instruction 32* MIPS option stack:: Directives to save and restore options 33* MIPS ASE instruction generation overrides:: Directives to control 34 generation of MIPS ASE instructions 35* MIPS floating-point:: Directives to override floating-point options 36@end menu 37 38@node MIPS Opts 39@section Assembler options 40 41The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 42special options: 43 44@table @code 45@cindex @code{-G} option (MIPS) 46@item -G @var{num} 47This option sets the largest size of an object that can be referenced 48implicitly with the @code{gp} register. It is only accepted for targets 49that use @sc{ecoff} format. The default value is 8. 50 51@cindex @code{-EB} option (MIPS) 52@cindex @code{-EL} option (MIPS) 53@cindex MIPS big-endian output 54@cindex MIPS little-endian output 55@cindex big-endian output, MIPS 56@cindex little-endian output, MIPS 57@item -EB 58@itemx -EL 59Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 60little-endian output at run time (unlike the other @sc{gnu} development 61tools, which must be configured for one or the other). Use @samp{-EB} 62to select big-endian output, and @samp{-EL} for little-endian. 63 64@item -KPIC 65@cindex PIC selection, MIPS 66@cindex @option{-KPIC} option, MIPS 67Generate SVR4-style PIC. This option tells the assembler to generate 68SVR4-style position-independent macro expansions. It also tells the 69assembler to mark the output file as PIC. 70 71@item -mvxworks-pic 72@cindex @option{-mvxworks-pic} option, MIPS 73Generate VxWorks PIC. This option tells the assembler to generate 74VxWorks-style position-independent macro expansions. 75 76@cindex MIPS architecture options 77@item -mips1 78@itemx -mips2 79@itemx -mips3 80@itemx -mips4 81@itemx -mips5 82@itemx -mips32 83@itemx -mips32r2 84@itemx -mips64 85@itemx -mips64r2 86Generate code for a particular MIPS Instruction Set Architecture level. 87@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 88@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 89@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 90@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 91@samp{-mips64}, and @samp{-mips64r2} 92correspond to generic 93@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 94and @sc{MIPS64 Release 2} 95ISA processors, respectively. You can also switch 96instruction sets during the assembly; see @ref{MIPS ISA, Directives to 97override the ISA level}. 98 99@item -mgp32 100@itemx -mfp32 101Some macros have different expansions for 32-bit and 64-bit registers. 102The register sizes are normally inferred from the ISA and ABI, but these 103flags force a certain group of registers to be treated as 32 bits wide at 104all times. @samp{-mgp32} controls the size of general-purpose registers 105and @samp{-mfp32} controls the size of floating-point registers. 106 107The @code{.set gp=32} and @code{.set fp=32} directives allow the size 108of registers to be changed for parts of an object. The default value is 109restored by @code{.set gp=default} and @code{.set fp=default}. 110 111On some MIPS variants there is a 32-bit mode flag; when this flag is 112set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 113save the 32-bit registers on a context switch, so it is essential never 114to use the 64-bit registers. 115 116@item -mgp64 117@itemx -mfp64 118Assume that 64-bit registers are available. This is provided in the 119interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 120 121The @code{.set gp=64} and @code{.set fp=64} directives allow the size 122of registers to be changed for parts of an object. The default value is 123restored by @code{.set gp=default} and @code{.set fp=default}. 124 125@item -mips16 126@itemx -no-mips16 127Generate code for the MIPS 16 processor. This is equivalent to putting 128@code{.set mips16} at the start of the assembly file. @samp{-no-mips16} 129turns off this option. 130 131@item -msmartmips 132@itemx -mno-smartmips 133Enables the SmartMIPS extensions to the MIPS32 instruction set, which 134provides a number of new instructions which target smartcard and 135cryptographic applications. This is equivalent to putting 136@code{.set smartmips} at the start of the assembly file. 137@samp{-mno-smartmips} turns off this option. 138 139@item -mips3d 140@itemx -no-mips3d 141Generate code for the MIPS-3D Application Specific Extension. 142This tells the assembler to accept MIPS-3D instructions. 143@samp{-no-mips3d} turns off this option. 144 145@item -mdmx 146@itemx -no-mdmx 147Generate code for the MDMX Application Specific Extension. 148This tells the assembler to accept MDMX instructions. 149@samp{-no-mdmx} turns off this option. 150 151@item -mdsp 152@itemx -mno-dsp 153Generate code for the DSP Release 1 Application Specific Extension. 154This tells the assembler to accept DSP Release 1 instructions. 155@samp{-mno-dsp} turns off this option. 156 157@item -mdspr2 158@itemx -mno-dspr2 159Generate code for the DSP Release 2 Application Specific Extension. 160This option implies -mdsp. 161This tells the assembler to accept DSP Release 2 instructions. 162@samp{-mno-dspr2} turns off this option. 163 164@item -mmt 165@itemx -mno-mt 166Generate code for the MT Application Specific Extension. 167This tells the assembler to accept MT instructions. 168@samp{-mno-mt} turns off this option. 169 170@item -mfix7000 171@itemx -mno-fix7000 172Cause nops to be inserted if the read of the destination register 173of an mfhi or mflo instruction occurs in the following two instructions. 174 175@item -mfix-vr4120 176@itemx -no-mfix-vr4120 177Insert nops to work around certain VR4120 errata. This option is 178intended to be used on GCC-generated code: it is not designed to catch 179all problems in hand-written assembler code. 180 181@item -mfix-vr4130 182@itemx -no-mfix-vr4130 183Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 184 185@item -m4010 186@itemx -no-m4010 187Generate code for the LSI @sc{r4010} chip. This tells the assembler to 188accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 189etc.), and to not schedule @samp{nop} instructions around accesses to 190the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 191option. 192 193@item -m4650 194@itemx -no-m4650 195Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 196the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 197instructions around accesses to the @samp{HI} and @samp{LO} registers. 198@samp{-no-m4650} turns off this option. 199 200@itemx -m3900 201@itemx -no-m3900 202@itemx -m4100 203@itemx -no-m4100 204For each option @samp{-m@var{nnnn}}, generate code for the MIPS 205@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 206specific to that chip, and to schedule for that chip's hazards. 207 208@item -march=@var{cpu} 209Generate code for a particular MIPS cpu. It is exactly equivalent to 210@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 211understood. Valid @var{cpu} value are: 212 213@quotation 2142000, 2153000, 2163900, 2174000, 2184010, 2194100, 2204111, 221vr4120, 222vr4130, 223vr4181, 2244300, 2254400, 2264600, 2274650, 2285000, 229rm5200, 230rm5230, 231rm5231, 232rm5261, 233rm5721, 234vr5400, 235vr5500, 2366000, 237rm7000, 2388000, 239rm9000, 24010000, 24112000, 2424kc, 2434km, 2444kp, 2454ksc, 2464kec, 2474kem, 2484kep, 2494ksd, 250m4k, 251m4kp, 25224kc, 25324kf2_1, 25424kf, 25524kf1_1, 25624kec, 25724kef2_1, 25824kef, 25924kef1_1, 26034kc, 26134kf2_1, 26234kf, 26334kf1_1, 26474kc, 26574kf2_1, 26674kf, 26774kf1_1, 26874kf3_2, 2695kc, 2705kf, 27120kc, 27225kf, 273sb1, 274sb1a, 275loongson2e, 276loongson2f, 277octeon 278@end quotation 279 280For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are 281accepted as synonyms for @samp{@var{n}f1_1}. These values are 282deprecated. 283 284@item -mtune=@var{cpu} 285Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 286identical to @samp{-march=@var{cpu}}. 287 288@item -mabi=@var{abi} 289Record which ABI the source code uses. The recognized arguments 290are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 291 292@item -msym32 293@itemx -mno-sym32 294@cindex -msym32 295@cindex -mno-sym32 296Equivalent to adding @code{.set sym32} or @code{.set nosym32} to 297the beginning of the assembler input. @xref{MIPS symbol sizes}. 298 299@cindex @code{-nocpp} ignored (MIPS) 300@item -nocpp 301This option is ignored. It is accepted for command-line compatibility with 302other assemblers, which use it to turn off C style preprocessing. With 303@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 304@sc{gnu} assembler itself never runs the C preprocessor. 305 306@item -msoft-float 307@itemx -mhard-float 308Disable or enable floating-point instructions. Note that by default 309floating-point instructions are always allowed even with CPU targets 310that don't have support for these instructions. 311 312@item -msingle-float 313@itemx -mdouble-float 314Disable or enable double-precision floating-point operations. Note 315that by default double-precision floating-point operations are always 316allowed even with CPU targets that don't have support for these 317operations. 318 319@item --construct-floats 320@itemx --no-construct-floats 321The @code{--no-construct-floats} option disables the construction of 322double width floating point constants by loading the two halves of the 323value into the two single width floating point registers that make up 324the double width register. This feature is useful if the processor 325support the FR bit in its status register, and this bit is known (by 326the programmer) to be set. This bit prevents the aliasing of the double 327width register by the single width registers. 328 329By default @code{--construct-floats} is selected, allowing construction 330of these floating point constants. 331 332@item --trap 333@itemx --no-break 334@c FIXME! (1) reflect these options (next item too) in option summaries; 335@c (2) stop teasing, say _which_ instructions expanded _how_. 336@code{@value{AS}} automatically macro expands certain division and 337multiplication instructions to check for overflow and division by zero. This 338option causes @code{@value{AS}} to generate code to take a trap exception 339rather than a break exception when an error is detected. The trap instructions 340are only supported at Instruction Set Architecture level 2 and higher. 341 342@item --break 343@itemx --no-trap 344Generate code to take a break exception rather than a trap exception when an 345error is detected. This is the default. 346 347@item -mpdr 348@itemx -mno-pdr 349Control generation of @code{.pdr} sections. Off by default on IRIX, on 350elsewhere. 351 352@item -mshared 353@itemx -mno-shared 354When generating code using the Unix calling conventions (selected by 355@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 356which can go into a shared library. The @samp{-mno-shared} option 357tells gas to generate code which uses the calling convention, but can 358not go into a shared library. The resulting code is slightly more 359efficient. This option only affects the handling of the 360@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 361@end table 362 363@node MIPS Object 364@section MIPS ECOFF object code 365 366@cindex ECOFF sections 367@cindex MIPS ECOFF sections 368Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 369besides the usual @code{.text}, @code{.data} and @code{.bss}. The 370additional sections are @code{.rdata}, used for read-only data, 371@code{.sdata}, used for small data, and @code{.sbss}, used for small 372common objects. 373 374@cindex small objects, MIPS ECOFF 375@cindex @code{gp} register, MIPS 376When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 377register to form the address of a ``small object''. Any object in the 378@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 379For external objects, or for objects in the @code{.bss} section, you can use 380the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 381@code{$gp}; the default value is 8, meaning that a reference to any object 382eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 383@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 384of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 385or @code{sbss} in any case). The size of an object in the @code{.bss} section 386is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 387size of an external object may be set with the @code{.extern} directive. For 388example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 389in length, whie leaving @code{sym} otherwise undefined. 390 391Using small @sc{ecoff} objects requires linker support, and assumes that the 392@code{$gp} register is correctly initialized (normally done automatically by 393the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 394@code{$gp} register. 395 396@node MIPS Stabs 397@section Directives for debugging information 398 399@cindex MIPS debugging directives 400@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 401generating debugging information which are not support by traditional @sc{mips} 402assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 403@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 404@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 405generated by the three @code{.stab} directives can only be read by @sc{gdb}, 406not by traditional @sc{mips} debuggers (this enhancement is required to fully 407support C++ debugging). These directives are primarily used by compilers, not 408assembly language programmers! 409 410@node MIPS symbol sizes 411@section Directives to override the size of symbols 412 413@cindex @code{.set sym32} 414@cindex @code{.set nosym32} 415The n64 ABI allows symbols to have any 64-bit value. Although this 416provides a great deal of flexibility, it means that some macros have 417much longer expansions than their 32-bit counterparts. For example, 418the non-PIC expansion of @samp{dla $4,sym} is usually: 419 420@smallexample 421lui $4,%highest(sym) 422lui $1,%hi(sym) 423daddiu $4,$4,%higher(sym) 424daddiu $1,$1,%lo(sym) 425dsll32 $4,$4,0 426daddu $4,$4,$1 427@end smallexample 428 429whereas the 32-bit expansion is simply: 430 431@smallexample 432lui $4,%hi(sym) 433daddiu $4,$4,%lo(sym) 434@end smallexample 435 436n64 code is sometimes constructed in such a way that all symbolic 437constants are known to have 32-bit values, and in such cases, it's 438preferable to use the 32-bit expansion instead of the 64-bit 439expansion. 440 441You can use the @code{.set sym32} directive to tell the assembler 442that, from this point on, all expressions of the form 443@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 444have 32-bit values. For example: 445 446@smallexample 447.set sym32 448dla $4,sym 449lw $4,sym+16 450sw $4,sym+0x8000($4) 451@end smallexample 452 453will cause the assembler to treat @samp{sym}, @code{sym+16} and 454@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 455addresses is not affected. 456 457The directive @code{.set nosym32} ends a @code{.set sym32} block and 458reverts to the normal behavior. It is also possible to change the 459symbol size using the command-line options @option{-msym32} and 460@option{-mno-sym32}. 461 462These options and directives are always accepted, but at present, 463they have no effect for anything other than n64. 464 465@node MIPS ISA 466@section Directives to override the ISA level 467 468@cindex MIPS ISA override 469@kindex @code{.set mips@var{n}} 470@sc{gnu} @code{@value{AS}} supports an additional directive to change 471the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 472mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 473or 64r2. 474The values other than 0 make the assembler accept instructions 475for the corresponding @sc{isa} level, from that point on in the 476assembly. @code{.set mips@var{n}} affects not only which instructions 477are permitted, but also how certain macros are expanded. @code{.set 478mips0} restores the @sc{isa} level to its original level: either the 479level you selected with command line options, or the default for your 480configuration. You can use this feature to permit specific @sc{mips3} 481instructions while assembling in 32 bit mode. Use this directive with 482care! 483 484@cindex MIPS CPU override 485@kindex @code{.set arch=@var{cpu}} 486The @code{.set arch=@var{cpu}} directive provides even finer control. 487It changes the effective CPU target and allows the assembler to use 488instructions specific to a particular CPU. All CPUs supported by the 489@samp{-march} command line option are also selectable by this directive. 490The original value is restored by @code{.set arch=default}. 491 492The directive @code{.set mips16} puts the assembler into MIPS 16 mode, 493in which it will assemble instructions for the MIPS 16 processor. Use 494@code{.set nomips16} to return to normal 32 bit mode. 495 496Traditional @sc{mips} assemblers do not support this directive. 497 498@node MIPS autoextend 499@section Directives for extending MIPS 16 bit instructions 500 501@kindex @code{.set autoextend} 502@kindex @code{.set noautoextend} 503By default, MIPS 16 instructions are automatically extended to 32 bits 504when necessary. The directive @code{.set noautoextend} will turn this 505off. When @code{.set noautoextend} is in effect, any 32 bit instruction 506must be explicitly extended with the @code{.e} modifier (e.g., 507@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 508to once again automatically extend instructions when necessary. 509 510This directive is only meaningful when in MIPS 16 mode. Traditional 511@sc{mips} assemblers do not support this directive. 512 513@node MIPS insn 514@section Directive to mark data as an instruction 515 516@kindex @code{.insn} 517The @code{.insn} directive tells @code{@value{AS}} that the following 518data is actually instructions. This makes a difference in MIPS 16 mode: 519when loading the address of a label which precedes instructions, 520@code{@value{AS}} automatically adds 1 to the value, so that jumping to 521the loaded address will do the right thing. 522 523@node MIPS option stack 524@section Directives to save and restore options 525 526@cindex MIPS option stack 527@kindex @code{.set push} 528@kindex @code{.set pop} 529The directives @code{.set push} and @code{.set pop} may be used to save 530and restore the current settings for all the options which are 531controlled by @code{.set}. The @code{.set push} directive saves the 532current settings on a stack. The @code{.set pop} directive pops the 533stack and restores the settings. 534 535These directives can be useful inside an macro which must change an 536option such as the ISA level or instruction reordering but does not want 537to change the state of the code which invoked the macro. 538 539Traditional @sc{mips} assemblers do not support these directives. 540 541@node MIPS ASE instruction generation overrides 542@section Directives to control generation of MIPS ASE instructions 543 544@cindex MIPS MIPS-3D instruction generation override 545@kindex @code{.set mips3d} 546@kindex @code{.set nomips3d} 547The directive @code{.set mips3d} makes the assembler accept instructions 548from the MIPS-3D Application Specific Extension from that point on 549in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 550instructions from being accepted. 551 552@cindex SmartMIPS instruction generation override 553@kindex @code{.set smartmips} 554@kindex @code{.set nosmartmips} 555The directive @code{.set smartmips} makes the assembler accept 556instructions from the SmartMIPS Application Specific Extension to the 557MIPS32 @sc{isa} from that point on in the assembly. The 558@code{.set nosmartmips} directive prevents SmartMIPS instructions from 559being accepted. 560 561@cindex MIPS MDMX instruction generation override 562@kindex @code{.set mdmx} 563@kindex @code{.set nomdmx} 564The directive @code{.set mdmx} makes the assembler accept instructions 565from the MDMX Application Specific Extension from that point on 566in the assembly. The @code{.set nomdmx} directive prevents MDMX 567instructions from being accepted. 568 569@cindex MIPS DSP Release 1 instruction generation override 570@kindex @code{.set dsp} 571@kindex @code{.set nodsp} 572The directive @code{.set dsp} makes the assembler accept instructions 573from the DSP Release 1 Application Specific Extension from that point 574on in the assembly. The @code{.set nodsp} directive prevents DSP 575Release 1 instructions from being accepted. 576 577@cindex MIPS DSP Release 2 instruction generation override 578@kindex @code{.set dspr2} 579@kindex @code{.set nodspr2} 580The directive @code{.set dspr2} makes the assembler accept instructions 581from the DSP Release 2 Application Specific Extension from that point 582on in the assembly. This dirctive implies @code{.set dsp}. The 583@code{.set nodspr2} directive prevents DSP Release 2 instructions from 584being accepted. 585 586@cindex MIPS MT instruction generation override 587@kindex @code{.set mt} 588@kindex @code{.set nomt} 589The directive @code{.set mt} makes the assembler accept instructions 590from the MT Application Specific Extension from that point on 591in the assembly. The @code{.set nomt} directive prevents MT 592instructions from being accepted. 593 594Traditional @sc{mips} assemblers do not support these directives. 595 596@node MIPS floating-point 597@section Directives to override floating-point options 598 599@cindex Disable floating-point instructions 600@kindex @code{.set softfloat} 601@kindex @code{.set hardfloat} 602The directives @code{.set softfloat} and @code{.set hardfloat} provide 603finer control of disabling and enabling float-point instructions. 604These directives always override the default (that hard-float 605instructions are accepted) or the command-line options 606(@samp{-msoft-float} and @samp{-mhard-float}). 607 608@cindex Disable single-precision floating-point operations 609@kindex @code{.set singlefloat} 610@kindex @code{.set doublefloat} 611The directives @code{.set singlefloat} and @code{.set doublefloat} 612provide finer control of disabling and enabling double-precision 613float-point operations. These directives always override the default 614(that double-precision operations are accepted) or the command-line 615options (@samp{-msingle-float} and @samp{-mdouble-float}). 616 617Traditional @sc{mips} assemblers do not support these directives. 618