12a6b7db3Sskrll /* crx.h -- Header file for CRX opcode and register tables. 2*f22f0ef4Schristos Copyright (C) 2004-2022 Free Software Foundation, Inc. 32a6b7db3Sskrll Contributed by Tomer Levi, NSC, Israel. 42a6b7db3Sskrll Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. 52a6b7db3Sskrll Updates, BFDizing, GNUifying and ELF support by Tomer Levi. 62a6b7db3Sskrll 72a6b7db3Sskrll This file is part of GAS, GDB and the GNU binutils. 82a6b7db3Sskrll 92a6b7db3Sskrll GAS, GDB, and GNU binutils is free software; you can redistribute it 102a6b7db3Sskrll and/or modify it under the terms of the GNU General Public License as 11b075ecf2Schristos published by the Free Software Foundation; either version 3, or (at your 122a6b7db3Sskrll option) any later version. 132a6b7db3Sskrll 142a6b7db3Sskrll GAS, GDB, and GNU binutils are distributed in the hope that they will be 152a6b7db3Sskrll useful, but WITHOUT ANY WARRANTY; without even the implied warranty of 162a6b7db3Sskrll MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 172a6b7db3Sskrll GNU General Public License for more details. 182a6b7db3Sskrll 192a6b7db3Sskrll You should have received a copy of the GNU General Public License 202a6b7db3Sskrll along with this program; if not, write to the Free Software 21b075ecf2Schristos Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22b075ecf2Schristos MA 02110-1301, USA. */ 232a6b7db3Sskrll 242a6b7db3Sskrll #ifndef _CRX_H_ 252a6b7db3Sskrll #define _CRX_H_ 262a6b7db3Sskrll 272a6b7db3Sskrll /* CRX core/debug Registers : 282a6b7db3Sskrll The enums are used as indices to CRX registers table (crx_regtab). 292a6b7db3Sskrll Therefore, order MUST be preserved. */ 302a6b7db3Sskrll 312a6b7db3Sskrll typedef enum 322a6b7db3Sskrll { 332a6b7db3Sskrll /* 32-bit general purpose registers. */ 342a6b7db3Sskrll r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, 352a6b7db3Sskrll r10, r11, r12, r13, r14, r15, ra, sp, 362a6b7db3Sskrll /* 32-bit user registers. */ 372a6b7db3Sskrll u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, 382a6b7db3Sskrll u10, u11, u12, u13, u14, u15, ura, usp, 392a6b7db3Sskrll /* hi and lo registers. */ 402a6b7db3Sskrll hi, lo, 412a6b7db3Sskrll /* hi and lo user registers. */ 422a6b7db3Sskrll uhi, ulo, 432a6b7db3Sskrll /* Processor Status Register. */ 442a6b7db3Sskrll psr, 452a6b7db3Sskrll /* Interrupt Base Register. */ 462a6b7db3Sskrll intbase, 472a6b7db3Sskrll /* Interrupt Stack Pointer Register. */ 482a6b7db3Sskrll isp, 492a6b7db3Sskrll /* Configuration Register. */ 502a6b7db3Sskrll cfg, 512a6b7db3Sskrll /* Coprocessor Configuration Register. */ 522a6b7db3Sskrll cpcfg, 532a6b7db3Sskrll /* Coprocessor Enable Register. */ 542a6b7db3Sskrll cen, 552a6b7db3Sskrll /* Not a register. */ 562a6b7db3Sskrll nullregister, 572a6b7db3Sskrll MAX_REG 582a6b7db3Sskrll } 592a6b7db3Sskrll reg; 602a6b7db3Sskrll 612a6b7db3Sskrll /* CRX Coprocessor registers and special registers : 622a6b7db3Sskrll The enums are used as indices to CRX coprocessor registers table 632a6b7db3Sskrll (crx_copregtab). Therefore, order MUST be preserved. */ 642a6b7db3Sskrll 652a6b7db3Sskrll typedef enum 662a6b7db3Sskrll { 672a6b7db3Sskrll /* Coprocessor registers. */ 682a6b7db3Sskrll c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, 692a6b7db3Sskrll c9, c10, c11, c12, c13, c14, c15, 702a6b7db3Sskrll /* Coprocessor special registers. */ 712a6b7db3Sskrll cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, 722a6b7db3Sskrll cs9, cs10, cs11, cs12, cs13, cs14, cs15, 732a6b7db3Sskrll /* Not a Coprocessor register. */ 742a6b7db3Sskrll nullcopregister, 752a6b7db3Sskrll MAX_COPREG 762a6b7db3Sskrll } 772a6b7db3Sskrll copreg; 782a6b7db3Sskrll 792a6b7db3Sskrll /* CRX Register types. */ 802a6b7db3Sskrll 812a6b7db3Sskrll typedef enum 822a6b7db3Sskrll { 832a6b7db3Sskrll CRX_R_REGTYPE, /* r<N> */ 842a6b7db3Sskrll CRX_U_REGTYPE, /* u<N> */ 852a6b7db3Sskrll CRX_C_REGTYPE, /* c<N> */ 862a6b7db3Sskrll CRX_CS_REGTYPE, /* cs<N> */ 872a6b7db3Sskrll CRX_CFG_REGTYPE /* configuration register */ 882a6b7db3Sskrll } 892a6b7db3Sskrll reg_type; 902a6b7db3Sskrll 912a6b7db3Sskrll /* CRX argument types : 922a6b7db3Sskrll The argument types correspond to instructions operands 932a6b7db3Sskrll 942a6b7db3Sskrll Argument types : 952a6b7db3Sskrll r - register 962a6b7db3Sskrll c - constant 972a6b7db3Sskrll i - immediate 982a6b7db3Sskrll idxr - index register 992a6b7db3Sskrll rbase - register base 1002a6b7db3Sskrll s - star ('*') 1012a6b7db3Sskrll copr - coprocessor register 1022a6b7db3Sskrll copsr - coprocessor special register. */ 1032a6b7db3Sskrll 1042a6b7db3Sskrll typedef enum 1052a6b7db3Sskrll { 1062a6b7db3Sskrll arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, 1072a6b7db3Sskrll arg_idxr, arg_rbase, arg_copr, arg_copsr, 1082a6b7db3Sskrll /* Not an argument. */ 1092a6b7db3Sskrll nullargs 1102a6b7db3Sskrll } 1112a6b7db3Sskrll argtype; 1122a6b7db3Sskrll 1132a6b7db3Sskrll /* CRX operand types : 1142a6b7db3Sskrll The operand types correspond to instructions operands. */ 1152a6b7db3Sskrll 1162a6b7db3Sskrll typedef enum 1172a6b7db3Sskrll { 1182a6b7db3Sskrll dummy, 1192a6b7db3Sskrll /* 4-bit encoded constant. */ 1202a6b7db3Sskrll cst4, 1212a6b7db3Sskrll /* N-bit immediate. */ 1222a6b7db3Sskrll i16, i32, 1232a6b7db3Sskrll /* N-bit unsigned immediate. */ 1242a6b7db3Sskrll ui3, ui4, ui5, ui16, 1252a6b7db3Sskrll /* N-bit signed displacement. */ 1262a6b7db3Sskrll disps9, disps17, disps25, disps32, 1272a6b7db3Sskrll /* N-bit unsigned displacement. */ 1282a6b7db3Sskrll dispu5, 1292a6b7db3Sskrll /* N-bit escaped displacement. */ 1302a6b7db3Sskrll dispe9, 1312a6b7db3Sskrll /* N-bit absolute address. */ 1322a6b7db3Sskrll abs16, abs32, 1332a6b7db3Sskrll /* Register relative. */ 1342a6b7db3Sskrll rbase, rbase_dispu4, 1352a6b7db3Sskrll rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, 1362a6b7db3Sskrll /* Register index. */ 1372a6b7db3Sskrll rindex_disps6, rindex_disps22, 1382a6b7db3Sskrll /* 4-bit genaral-purpose register specifier. */ 1392a6b7db3Sskrll regr, 1402a6b7db3Sskrll /* 8-bit register address space. */ 1412a6b7db3Sskrll regr8, 1422a6b7db3Sskrll /* coprocessor register. */ 1432a6b7db3Sskrll copregr, 1442a6b7db3Sskrll /* coprocessor special register. */ 1452a6b7db3Sskrll copsregr, 1462a6b7db3Sskrll /* Not an operand. */ 1472a6b7db3Sskrll nulloperand, 1482a6b7db3Sskrll /* Maximum supported operand. */ 1492a6b7db3Sskrll MAX_OPRD 1502a6b7db3Sskrll } 1512a6b7db3Sskrll operand_type; 1522a6b7db3Sskrll 1532a6b7db3Sskrll /* CRX instruction types. */ 1542a6b7db3Sskrll 1552a6b7db3Sskrll #define NO_TYPE_INS 0 1562a6b7db3Sskrll #define ARITH_INS 1 1572a6b7db3Sskrll #define LD_STOR_INS 2 1582a6b7db3Sskrll #define BRANCH_INS 3 1592a6b7db3Sskrll #define ARITH_BYTE_INS 4 1602a6b7db3Sskrll #define CMPBR_INS 5 1612a6b7db3Sskrll #define SHIFT_INS 6 1622a6b7db3Sskrll #define BRANCH_NEQ_INS 7 1632a6b7db3Sskrll #define LD_STOR_INS_INC 8 1642a6b7db3Sskrll #define STOR_IMM_INS 9 1652a6b7db3Sskrll #define CSTBIT_INS 10 1662a6b7db3Sskrll #define COP_BRANCH_INS 11 1672a6b7db3Sskrll #define COP_REG_INS 12 1682a6b7db3Sskrll #define COPS_REG_INS 13 1692a6b7db3Sskrll #define DCR_BRANCH_INS 14 1702a6b7db3Sskrll 1712a6b7db3Sskrll /* Maximum value supported for instruction types. */ 1722a6b7db3Sskrll #define CRX_INS_MAX (1 << 4) 1732a6b7db3Sskrll /* Mask to record an instruction type. */ 1742a6b7db3Sskrll #define CRX_INS_MASK (CRX_INS_MAX - 1) 1752a6b7db3Sskrll /* Return instruction type, given instruction's attributes. */ 1762a6b7db3Sskrll #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) 1772a6b7db3Sskrll 1782a6b7db3Sskrll /* Indicates whether this instruction has a register list as parameter. */ 1792a6b7db3Sskrll #define REG_LIST CRX_INS_MAX 1802a6b7db3Sskrll /* The operands in binary and assembly are placed in reverse order. 1812a6b7db3Sskrll load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ 1822a6b7db3Sskrll #define REVERSE_MATCH (1 << 5) 1832a6b7db3Sskrll 1842a6b7db3Sskrll /* Kind of displacement map used DISPU[BWD]4. */ 1852a6b7db3Sskrll #define DISPUB4 (1 << 6) 1862a6b7db3Sskrll #define DISPUW4 (1 << 7) 1872a6b7db3Sskrll #define DISPUD4 (1 << 8) 1882a6b7db3Sskrll #define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) 1892a6b7db3Sskrll 1902a6b7db3Sskrll /* Printing formats, where the instruction prefix isn't consecutive. */ 1912a6b7db3Sskrll #define FMT_1 (1 << 9) /* 0xF0F00000 */ 1922a6b7db3Sskrll #define FMT_2 (1 << 10) /* 0xFFF0FF00 */ 1932a6b7db3Sskrll #define FMT_3 (1 << 11) /* 0xFFF00F00 */ 1942a6b7db3Sskrll #define FMT_4 (1 << 12) /* 0xFFF0F000 */ 1952a6b7db3Sskrll #define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ 1962a6b7db3Sskrll #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) 1972a6b7db3Sskrll 1982a6b7db3Sskrll /* Indicates whether this instruction can be relaxed. */ 1992a6b7db3Sskrll #define RELAXABLE (1 << 14) 2002a6b7db3Sskrll 2012a6b7db3Sskrll /* Indicates that instruction uses user registers (and not 2022a6b7db3Sskrll general-purpose registers) as operands. */ 2032a6b7db3Sskrll #define USER_REG (1 << 15) 2042a6b7db3Sskrll 2052a6b7db3Sskrll /* Indicates that instruction can perfom a cst4 mapping. */ 2062a6b7db3Sskrll #define CST4MAP (1 << 16) 2072a6b7db3Sskrll 2082a6b7db3Sskrll /* Instruction shouldn't allow 'sp' usage. */ 2092a6b7db3Sskrll #define NO_SP (1 << 17) 2102a6b7db3Sskrll 2112a6b7db3Sskrll /* Instruction shouldn't allow to push a register which is used as a rptr. */ 2122a6b7db3Sskrll #define NO_RPTR (1 << 18) 2132a6b7db3Sskrll 2142a6b7db3Sskrll /* Maximum operands per instruction. */ 2152a6b7db3Sskrll #define MAX_OPERANDS 5 2162a6b7db3Sskrll /* Maximum register name length. */ 2172a6b7db3Sskrll #define MAX_REGNAME_LEN 10 2182a6b7db3Sskrll /* Maximum instruction length. */ 2192a6b7db3Sskrll #define MAX_INST_LEN 256 2202a6b7db3Sskrll 2212a6b7db3Sskrll 2222a6b7db3Sskrll /* Values defined for the flags field of a struct operand_entry. */ 2232a6b7db3Sskrll 2242a6b7db3Sskrll /* Operand must be an unsigned number. */ 2252a6b7db3Sskrll #define OP_UNSIGNED (1 << 0) 2262a6b7db3Sskrll /* Operand must be a signed number. */ 2272a6b7db3Sskrll #define OP_SIGNED (1 << 1) 2282a6b7db3Sskrll /* A special arithmetic 4-bit constant operand. */ 2292a6b7db3Sskrll #define OP_CST4 (1 << 2) 2302a6b7db3Sskrll /* A special load/stor 4-bit unsigned displacement operand. */ 2312a6b7db3Sskrll #define OP_DISPU4 (1 << 3) 2322a6b7db3Sskrll /* Operand must be an even number. */ 2332a6b7db3Sskrll #define OP_EVEN (1 << 4) 2342a6b7db3Sskrll /* Operand is shifted right. */ 2352a6b7db3Sskrll #define OP_SHIFT (1 << 5) 2362a6b7db3Sskrll /* Operand is shifted right and decremented. */ 2372a6b7db3Sskrll #define OP_SHIFT_DEC (1 << 6) 2382a6b7db3Sskrll /* Operand has reserved escape sequences. */ 2392a6b7db3Sskrll #define OP_ESC (1 << 7) 2402a6b7db3Sskrll /* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ 2412a6b7db3Sskrll #define OP_UPPER_64KB (1 << 8) 2422a6b7db3Sskrll 2432a6b7db3Sskrll /* Single operand description. */ 2442a6b7db3Sskrll 2452a6b7db3Sskrll typedef struct 2462a6b7db3Sskrll { 2472a6b7db3Sskrll /* Operand type. */ 2482a6b7db3Sskrll operand_type op_type; 2492a6b7db3Sskrll /* Operand location within the opcode. */ 2502a6b7db3Sskrll unsigned int shift; 2512a6b7db3Sskrll } 2522a6b7db3Sskrll operand_desc; 2532a6b7db3Sskrll 2542a6b7db3Sskrll /* Instruction data structure used in instruction table. */ 2552a6b7db3Sskrll 2562a6b7db3Sskrll typedef struct 2572a6b7db3Sskrll { 2582a6b7db3Sskrll /* Name. */ 2592a6b7db3Sskrll const char *mnemonic; 2602a6b7db3Sskrll /* Size (in words). */ 2612a6b7db3Sskrll unsigned int size; 2622a6b7db3Sskrll /* Constant prefix (matched by the disassembler). */ 263f7172901Schristos unsigned int match; 2642a6b7db3Sskrll /* Match size (in bits). */ 2652a6b7db3Sskrll int match_bits; 2662a6b7db3Sskrll /* Attributes. */ 2672a6b7db3Sskrll unsigned int flags; 2682a6b7db3Sskrll /* Operands (always last, so unreferenced operands are initialized). */ 2692a6b7db3Sskrll operand_desc operands[MAX_OPERANDS]; 2702a6b7db3Sskrll } 2712a6b7db3Sskrll inst; 2722a6b7db3Sskrll 2732a6b7db3Sskrll /* Data structure for a single instruction's arguments (Operands). */ 2742a6b7db3Sskrll 2752a6b7db3Sskrll typedef struct 2762a6b7db3Sskrll { 2772a6b7db3Sskrll /* Register or base register. */ 2782a6b7db3Sskrll reg r; 2792a6b7db3Sskrll /* Index register. */ 2802a6b7db3Sskrll reg i_r; 2812a6b7db3Sskrll /* Coprocessor register. */ 2822a6b7db3Sskrll copreg cr; 2832a6b7db3Sskrll /* Constant/immediate/absolute value. */ 2842a6b7db3Sskrll long constant; 2852a6b7db3Sskrll /* Scaled index mode. */ 2862a6b7db3Sskrll unsigned int scale; 2872a6b7db3Sskrll /* Argument type. */ 2882a6b7db3Sskrll argtype type; 2892a6b7db3Sskrll /* Size of the argument (in bits) required to represent. */ 2902a6b7db3Sskrll int size; 2912a6b7db3Sskrll /* The type of the expression. */ 2922a6b7db3Sskrll unsigned char X_op; 2932a6b7db3Sskrll } 2942a6b7db3Sskrll argument; 2952a6b7db3Sskrll 2962a6b7db3Sskrll /* Internal structure to hold the various entities 2972a6b7db3Sskrll corresponding to the current assembling instruction. */ 2982a6b7db3Sskrll 2992a6b7db3Sskrll typedef struct 3002a6b7db3Sskrll { 3012a6b7db3Sskrll /* Number of arguments. */ 3022a6b7db3Sskrll int nargs; 3032a6b7db3Sskrll /* The argument data structure for storing args (operands). */ 3042a6b7db3Sskrll argument arg[MAX_OPERANDS]; 3052a6b7db3Sskrll /* The following fields are required only by CRX-assembler. */ 3062a6b7db3Sskrll #ifdef TC_CRX 3072a6b7db3Sskrll /* Expression used for setting the fixups (if any). */ 3082a6b7db3Sskrll expressionS exp; 3092a6b7db3Sskrll bfd_reloc_code_real_type rtype; 3102a6b7db3Sskrll #endif /* TC_CRX */ 3112a6b7db3Sskrll /* Instruction size (in bytes). */ 3122a6b7db3Sskrll int size; 3132a6b7db3Sskrll } 3142a6b7db3Sskrll ins; 3152a6b7db3Sskrll 3162a6b7db3Sskrll /* Structure to hold information about predefined operands. */ 3172a6b7db3Sskrll 3182a6b7db3Sskrll typedef struct 3192a6b7db3Sskrll { 3202a6b7db3Sskrll /* Size (in bits). */ 3212a6b7db3Sskrll unsigned int bit_size; 3222a6b7db3Sskrll /* Argument type. */ 3232a6b7db3Sskrll argtype arg_type; 3242a6b7db3Sskrll /* One bit syntax flags. */ 3252a6b7db3Sskrll int flags; 3262a6b7db3Sskrll } 3272a6b7db3Sskrll operand_entry; 3282a6b7db3Sskrll 3292a6b7db3Sskrll /* Structure to hold trap handler information. */ 3302a6b7db3Sskrll 3312a6b7db3Sskrll typedef struct 3322a6b7db3Sskrll { 3332a6b7db3Sskrll /* Trap name. */ 3342a6b7db3Sskrll char *name; 3352a6b7db3Sskrll /* Index in dispatch table. */ 3362a6b7db3Sskrll unsigned int entry; 3372a6b7db3Sskrll } 3382a6b7db3Sskrll trap_entry; 3392a6b7db3Sskrll 3402a6b7db3Sskrll /* Structure to hold information about predefined registers. */ 3412a6b7db3Sskrll 3422a6b7db3Sskrll typedef struct 3432a6b7db3Sskrll { 3442a6b7db3Sskrll /* Name (string representation). */ 3452a6b7db3Sskrll char *name; 3462a6b7db3Sskrll /* Value (enum representation). */ 3472a6b7db3Sskrll union 3482a6b7db3Sskrll { 3492a6b7db3Sskrll /* Register. */ 3502a6b7db3Sskrll reg reg_val; 3512a6b7db3Sskrll /* Coprocessor register. */ 3522a6b7db3Sskrll copreg copreg_val; 3532a6b7db3Sskrll } value; 3542a6b7db3Sskrll /* Register image. */ 3552a6b7db3Sskrll int image; 3562a6b7db3Sskrll /* Register type. */ 3572a6b7db3Sskrll reg_type type; 3582a6b7db3Sskrll } 3592a6b7db3Sskrll reg_entry; 3602a6b7db3Sskrll 3612a6b7db3Sskrll /* Structure to hold a cst4 operand mapping. */ 3622a6b7db3Sskrll 3632a6b7db3Sskrll /* CRX opcode table. */ 3642a6b7db3Sskrll extern const inst crx_instruction[]; 3652a6b7db3Sskrll extern const int crx_num_opcodes; 3662a6b7db3Sskrll #define NUMOPCODES crx_num_opcodes 3672a6b7db3Sskrll 3682a6b7db3Sskrll /* CRX operands table. */ 3692a6b7db3Sskrll extern const operand_entry crx_optab[]; 3702a6b7db3Sskrll 3712a6b7db3Sskrll /* CRX registers table. */ 3722a6b7db3Sskrll extern const reg_entry crx_regtab[]; 3732a6b7db3Sskrll extern const int crx_num_regs; 3742a6b7db3Sskrll #define NUMREGS crx_num_regs 3752a6b7db3Sskrll 3762a6b7db3Sskrll /* CRX coprocessor registers table. */ 3772a6b7db3Sskrll extern const reg_entry crx_copregtab[]; 3782a6b7db3Sskrll extern const int crx_num_copregs; 3792a6b7db3Sskrll #define NUMCOPREGS crx_num_copregs 3802a6b7db3Sskrll 3812a6b7db3Sskrll /* CRX trap/interrupt table. */ 3822a6b7db3Sskrll extern const trap_entry crx_traps[]; 3832a6b7db3Sskrll extern const int crx_num_traps; 3842a6b7db3Sskrll #define NUMTRAPS crx_num_traps 3852a6b7db3Sskrll 3862a6b7db3Sskrll /* cst4 operand mapping. */ 38798f124a6Schristos extern const int crx_cst4_map[]; 38898f124a6Schristos extern const int crx_cst4_maps; 3892a6b7db3Sskrll 3902a6b7db3Sskrll /* Table of instructions with no operands. */ 39198f124a6Schristos extern const char* crx_no_op_insn[]; 3922a6b7db3Sskrll 3932a6b7db3Sskrll /* A macro for representing the instruction "constant" opcode, that is, 3942a6b7db3Sskrll the FIXED part of the instruction. The "constant" opcode is represented 3952a6b7db3Sskrll as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) 3962a6b7db3Sskrll over that range. */ 3972a6b7db3Sskrll #define BIN(OPC,SHIFT) (OPC << SHIFT) 3982a6b7db3Sskrll 3992a6b7db3Sskrll /* Is the current instruction type is TYPE ? */ 4002a6b7db3Sskrll #define IS_INSN_TYPE(TYPE) \ 4012a6b7db3Sskrll (CRX_INS_TYPE(instruction->flags) == TYPE) 4022a6b7db3Sskrll 4032a6b7db3Sskrll /* Is the current instruction mnemonic is MNEMONIC ? */ 4042a6b7db3Sskrll #define IS_INSN_MNEMONIC(MNEMONIC) \ 4052a6b7db3Sskrll (strcmp(instruction->mnemonic,MNEMONIC) == 0) 4062a6b7db3Sskrll 4072a6b7db3Sskrll /* Does the current instruction has register list ? */ 4082a6b7db3Sskrll #define INST_HAS_REG_LIST \ 4092a6b7db3Sskrll (instruction->flags & REG_LIST) 4102a6b7db3Sskrll 4112a6b7db3Sskrll /* Long long type handling. */ 4122a6b7db3Sskrll /* Replace all appearances of 'long long int' with LONGLONG. */ 4132a6b7db3Sskrll typedef long long int LONGLONG; 4142a6b7db3Sskrll typedef unsigned long long ULONGLONG; 4152a6b7db3Sskrll 4162a6b7db3Sskrll #endif /* _CRX_H_ */ 417