1 /* d10v.h -- Header file for D10V opcode table 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 3 Free Software Foundation, Inc. 4 Written by Martin Hunt (hunt@cygnus.com), Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #ifndef D10V_H 23 #define D10V_H 24 25 /* Format Specifier */ 26 #define FM00 0 27 #define FM01 0x40000000 28 #define FM10 0x80000000 29 #define FM11 0xC0000000 30 31 #define NOP 0x5e00 32 #define OPCODE_DIVS 0x14002800 33 34 /* The opcode table is an array of struct d10v_opcode. */ 35 36 struct d10v_opcode 37 { 38 /* The opcode name. */ 39 const char *name; 40 41 /* the opcode format */ 42 int format; 43 44 /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ 45 #define SHORT_OPCODE 1 46 #define LONG_OPCODE 8 47 #define SHORT_2 1 /* short with 2 operands */ 48 #define SHORT_B 3 /* short with 8-bit branch */ 49 #define LONG_B 8 /* long with 16-bit branch */ 50 #define LONG_L 10 /* long with 3 operands */ 51 #define LONG_R 12 /* reserved */ 52 53 /* just a placeholder for variable-length instructions */ 54 /* for example, "bra" will be a fake for "bra.s" and bra.l" */ 55 /* which will immediately follow in the opcode table. */ 56 #define OPCODE_FAKE 32 57 58 /* the number of cycles */ 59 int cycles; 60 61 /* the execution unit(s) used */ 62 int unit; 63 #define EITHER 0 64 #define IU 1 65 #define MU 2 66 #define BOTH 3 67 68 /* execution type; parallel or sequential */ 69 /* this field is used to decide if two instructions */ 70 /* can be executed in parallel */ 71 int exec_type; 72 #define PARONLY 1 /* parallel only */ 73 #define SEQ 2 /* must be sequential */ 74 #define PAR 4 /* may be parallel */ 75 #define BRANCH_LINK 8 /* subroutine call. must be aligned */ 76 #define RMEM 16 /* reads memory */ 77 #define WMEM 32 /* writes memory */ 78 #define RF0 64 /* reads f0 */ 79 #define WF0 128 /* modifies f0 */ 80 #define WCAR 256 /* write Carry */ 81 #define BRANCH 512 /* branch, no link */ 82 #define ALONE 1024 /* short but pack with a NOP if on asm line alone */ 83 84 /* the opcode */ 85 long opcode; 86 87 /* mask. if( (i & mask) == opcode ) then match */ 88 long mask; 89 90 /* An array of operand codes. Each code is an index into the 91 operand table. They appear in the order which the operands must 92 appear in assembly code, and are terminated by a zero. */ 93 unsigned char operands[6]; 94 }; 95 96 /* The table itself is sorted by major opcode number, and is otherwise 97 in the order in which the disassembler should consider 98 instructions. */ 99 extern const struct d10v_opcode d10v_opcodes[]; 100 extern const int d10v_num_opcodes; 101 102 /* The operands table is an array of struct d10v_operand. */ 103 struct d10v_operand 104 { 105 /* The number of bits in the operand. */ 106 int bits; 107 108 /* How far the operand is left shifted in the instruction. */ 109 int shift; 110 111 /* One bit syntax flags. */ 112 int flags; 113 }; 114 115 /* Elements in the table are retrieved by indexing with values from 116 the operands field of the d10v_opcodes table. */ 117 118 extern const struct d10v_operand d10v_operands[]; 119 120 /* Values defined for the flags field of a struct d10v_operand. */ 121 122 /* the operand must be an even number */ 123 #define OPERAND_EVEN (1) 124 125 /* the operand must be an odd number */ 126 #define OPERAND_ODD (2) 127 128 /* this is the destination register; it will be modified */ 129 /* this is used by the optimizer */ 130 #define OPERAND_DEST (4) 131 132 /* number or symbol */ 133 #define OPERAND_NUM (8) 134 135 /* address or label */ 136 #define OPERAND_ADDR (0x10) 137 138 /* register */ 139 #define OPERAND_REG (0x20) 140 141 /* postincrement + */ 142 #define OPERAND_PLUS (0x40) 143 144 /* postdecrement - */ 145 #define OPERAND_MINUS (0x80) 146 147 /* @ */ 148 #define OPERAND_ATSIGN (0x100) 149 150 /* @( */ 151 #define OPERAND_ATPAR (0x200) 152 153 /* accumulator 0 */ 154 #define OPERAND_ACC0 (0x400) 155 156 /* accumulator 1 */ 157 #define OPERAND_ACC1 (0x800) 158 159 /* f0 / f1 flag register */ 160 #define OPERAND_FFLAG (0x1000) 161 162 /* c flag register */ 163 #define OPERAND_CFLAG (0x2000) 164 165 /* control register */ 166 #define OPERAND_CONTROL (0x4000) 167 168 /* predecrement mode '@-sp' */ 169 #define OPERAND_ATMINUS (0x8000) 170 171 /* signed number */ 172 #define OPERAND_SIGNED (0x10000) 173 174 /* special accumulator shifts need a 4-bit number */ 175 /* 1 <= x <= 16 */ 176 #define OPERAND_SHIFT (0x20000) 177 178 /* general purpose register */ 179 #define OPERAND_GPR (0x40000) 180 181 /* special imm3 values with range restricted to -2 <= imm3 <= 3 */ 182 /* needed for rac/rachi */ 183 #define RESTRICTED_NUM3 (0x80000) 184 185 /* Pre-decrement is only supported for SP. */ 186 #define OPERAND_SP (0x100000) 187 188 /* Post-decrement is not supported for SP. Like OPERAND_EVEN, and 189 unlike OPERAND_SP, this flag doesn't prevent the instruction from 190 matching, it only fails validation later on. */ 191 #define OPERAND_NOSP (0x200000) 192 193 /* Structure to hold information about predefined registers. */ 194 struct pd_reg 195 { 196 char *name; /* name to recognize */ 197 char *pname; /* name to print for this register */ 198 int value; 199 }; 200 201 extern const struct pd_reg d10v_predefined_registers[]; 202 int d10v_reg_name_cnt (void); 203 204 /* an expressionS only has one register type, so we fake it */ 205 /* by setting high bits to indicate type */ 206 #define REGISTER_MASK 0xFF 207 208 #endif /* D10V_H */ 209