1 /* alpha-opc.c -- Alpha AXP opcode list 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 3 Free Software Foundation, Inc. 4 Contributed by Richard Henderson <rth@cygnus.com>, 5 patterned after the PPC opcode handling written by Ian Lance Taylor. 6 7 This file is part of libopcodes. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this file; see the file COPYING. If not, write to the 21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 22 02110-1301, USA. */ 23 24 #include <stdio.h> 25 #include "sysdep.h" 26 #include "opcode/alpha.h" 27 #include "bfd.h" 28 #include "opintl.h" 29 30 /* This file holds the Alpha AXP opcode table. The opcode table includes 31 almost all of the extended instruction mnemonics. This permits the 32 disassembler to use them, and simplifies the assembler logic, at the 33 cost of increasing the table size. The table is strictly constant 34 data, so the compiler should be able to put it in the text segment. 35 36 This file also holds the operand table. All knowledge about inserting 37 and extracting operands from instructions is kept in this file. 38 39 The information for the base instruction set was compiled from the 40 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 41 version 2. 42 43 The information for the post-ev5 architecture extensions BWX, CIX and 44 MAX came from version 3 of this same document, which is also available 45 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 46 /literature/alphahb2.pdf 47 48 The information for the EV4 PALcode instructions was compiled from 49 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 50 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 51 revision dated June 1994. 52 53 The information for the EV5 PALcode instructions was compiled from 54 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 55 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 56 57 /* The RB field when it is the same as the RA field in the same insn. 58 This operand is marked fake. The insertion function just copies 59 the RA field into the RB field, and the extraction function just 60 checks that the fields are the same. */ 61 62 static unsigned 63 insert_rba (unsigned insn, 64 int value ATTRIBUTE_UNUSED, 65 const char **errmsg ATTRIBUTE_UNUSED) 66 { 67 return insn | (((insn >> 21) & 0x1f) << 16); 68 } 69 70 static int 71 extract_rba (unsigned insn, int *invalid) 72 { 73 if (invalid != (int *) NULL 74 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 75 *invalid = 1; 76 return 0; 77 } 78 79 /* The same for the RC field. */ 80 81 static unsigned 82 insert_rca (unsigned insn, 83 int value ATTRIBUTE_UNUSED, 84 const char **errmsg ATTRIBUTE_UNUSED) 85 { 86 return insn | ((insn >> 21) & 0x1f); 87 } 88 89 static int 90 extract_rca (unsigned insn, int *invalid) 91 { 92 if (invalid != (int *) NULL 93 && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 94 *invalid = 1; 95 return 0; 96 } 97 98 /* Fake arguments in which the registers must be set to ZERO. */ 99 100 static unsigned 101 insert_za (unsigned insn, 102 int value ATTRIBUTE_UNUSED, 103 const char **errmsg ATTRIBUTE_UNUSED) 104 { 105 return insn | (31 << 21); 106 } 107 108 static int 109 extract_za (unsigned insn, int *invalid) 110 { 111 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 112 *invalid = 1; 113 return 0; 114 } 115 116 static unsigned 117 insert_zb (unsigned insn, 118 int value ATTRIBUTE_UNUSED, 119 const char **errmsg ATTRIBUTE_UNUSED) 120 { 121 return insn | (31 << 16); 122 } 123 124 static int 125 extract_zb (unsigned insn, int *invalid) 126 { 127 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 128 *invalid = 1; 129 return 0; 130 } 131 132 static unsigned 133 insert_zc (unsigned insn, 134 int value ATTRIBUTE_UNUSED, 135 const char **errmsg ATTRIBUTE_UNUSED) 136 { 137 return insn | 31; 138 } 139 140 static int 141 extract_zc (unsigned insn, int *invalid) 142 { 143 if (invalid != (int *) NULL && (insn & 0x1f) != 31) 144 *invalid = 1; 145 return 0; 146 } 147 148 149 /* The displacement field of a Branch format insn. */ 150 151 static unsigned 152 insert_bdisp (unsigned insn, int value, const char **errmsg) 153 { 154 if (errmsg != (const char **)NULL && (value & 3)) 155 *errmsg = _("branch operand unaligned"); 156 return insn | ((value / 4) & 0x1FFFFF); 157 } 158 159 static int 160 extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 161 { 162 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 163 } 164 165 /* The hint field of a JMP/JSR insn. */ 166 167 static unsigned 168 insert_jhint (unsigned insn, int value, const char **errmsg) 169 { 170 if (errmsg != (const char **)NULL && (value & 3)) 171 *errmsg = _("jump hint unaligned"); 172 return insn | ((value / 4) & 0x3FFF); 173 } 174 175 static int 176 extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 177 { 178 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 179 } 180 181 /* The hint field of an EV6 HW_JMP/JSR insn. */ 182 183 static unsigned 184 insert_ev6hwjhint (unsigned insn, int value, const char **errmsg) 185 { 186 if (errmsg != (const char **)NULL && (value & 3)) 187 *errmsg = _("jump hint unaligned"); 188 return insn | ((value / 4) & 0x1FFF); 189 } 190 191 static int 192 extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 193 { 194 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); 195 } 196 197 /* The operands table. */ 198 199 const struct alpha_operand alpha_operands[] = 200 { 201 /* The fields are bits, shift, insert, extract, flags */ 202 /* The zero index is used to indicate end-of-list */ 203 #define UNUSED 0 204 { 0, 0, 0, 0, 0, 0 }, 205 206 /* The plain integer register fields. */ 207 #define RA (UNUSED + 1) 208 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 209 #define RB (RA + 1) 210 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 211 #define RC (RB + 1) 212 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 213 214 /* The plain fp register fields. */ 215 #define FA (RC + 1) 216 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 217 #define FB (FA + 1) 218 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 219 #define FC (FB + 1) 220 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 221 222 /* The integer registers when they are ZERO. */ 223 #define ZA (FC + 1) 224 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 225 #define ZB (ZA + 1) 226 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 227 #define ZC (ZB + 1) 228 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 229 230 /* The RB field when it needs parentheses. */ 231 #define PRB (ZC + 1) 232 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 233 234 /* The RB field when it needs parentheses _and_ a preceding comma. */ 235 #define CPRB (PRB + 1) 236 { 5, 16, 0, 237 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 238 239 /* The RB field when it must be the same as the RA field. */ 240 #define RBA (CPRB + 1) 241 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 242 243 /* The RC field when it must be the same as the RB field. */ 244 #define RCA (RBA + 1) 245 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 246 247 /* The RC field when it can *default* to RA. */ 248 #define DRC1 (RCA + 1) 249 { 5, 0, 0, 250 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 251 252 /* The RC field when it can *default* to RB. */ 253 #define DRC2 (DRC1 + 1) 254 { 5, 0, 0, 255 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 256 257 /* The FC field when it can *default* to RA. */ 258 #define DFC1 (DRC2 + 1) 259 { 5, 0, 0, 260 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 261 262 /* The FC field when it can *default* to RB. */ 263 #define DFC2 (DFC1 + 1) 264 { 5, 0, 0, 265 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 266 267 /* The unsigned 8-bit literal of Operate format insns. */ 268 #define LIT (DFC2 + 1) 269 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 270 271 /* The signed 16-bit displacement of Memory format insns. From here 272 we can't tell what relocation should be used, so don't use a default. */ 273 #define MDISP (LIT + 1) 274 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 275 276 /* The signed "23-bit" aligned displacement of Branch format insns. */ 277 #define BDISP (MDISP + 1) 278 { 21, 0, BFD_RELOC_23_PCREL_S2, 279 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 280 281 /* The 26-bit PALcode function */ 282 #define PALFN (BDISP + 1) 283 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 284 285 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */ 286 #define JMPHINT (PALFN + 1) 287 { 14, 0, BFD_RELOC_ALPHA_HINT, 288 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 289 insert_jhint, extract_jhint }, 290 291 /* The optional hint to RET/JSR_COROUTINE. */ 292 #define RETHINT (JMPHINT + 1) 293 { 14, 0, -RETHINT, 294 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 295 296 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */ 297 #define EV4HWDISP (RETHINT + 1) 298 #define EV6HWDISP (EV4HWDISP) 299 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 300 301 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */ 302 #define EV4HWINDEX (EV4HWDISP + 1) 303 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 304 305 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 306 that occur in DEC PALcode. */ 307 #define EV4EXTHWINDEX (EV4HWINDEX + 1) 308 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 309 310 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */ 311 #define EV5HWDISP (EV4EXTHWINDEX + 1) 312 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 313 314 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */ 315 #define EV5HWINDEX (EV5HWDISP + 1) 316 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 317 318 /* The 16-bit combined index/scoreboard mask for the ev6 319 hw_m[ft]pr (pal19/pal1d) insns. */ 320 #define EV6HWINDEX (EV5HWINDEX + 1) 321 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 322 323 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */ 324 #define EV6HWJMPHINT (EV6HWINDEX+ 1) 325 { 8, 0, -EV6HWJMPHINT, 326 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 327 insert_ev6hwjhint, extract_ev6hwjhint } 328 }; 329 330 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 331 332 333 /* Macros used to form opcodes. */ 334 335 /* The main opcode. */ 336 #define OP(x) (((x) & 0x3F) << 26) 337 #define OP_MASK 0xFC000000 338 339 /* Branch format instructions. */ 340 #define BRA_(oo) OP(oo) 341 #define BRA_MASK OP_MASK 342 #define BRA(oo) BRA_(oo), BRA_MASK 343 344 /* Floating point format instructions. */ 345 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 346 #define FP_MASK (OP_MASK | 0xFFE0) 347 #define FP(oo,fff) FP_(oo,fff), FP_MASK 348 349 /* Memory format instructions. */ 350 #define MEM_(oo) OP(oo) 351 #define MEM_MASK OP_MASK 352 #define MEM(oo) MEM_(oo), MEM_MASK 353 354 /* Memory/Func Code format instructions. */ 355 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 356 #define MFC_MASK (OP_MASK | 0xFFFF) 357 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 358 359 /* Memory/Branch format instructions. */ 360 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 361 #define MBR_MASK (OP_MASK | 0xC000) 362 #define MBR(oo,h) MBR_(oo,h), MBR_MASK 363 364 /* Operate format instructions. The OPRL variant specifies a 365 literal second argument. */ 366 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 367 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 368 #define OPR_MASK (OP_MASK | 0x1FE0) 369 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 370 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 371 372 /* Generic PALcode format instructions. */ 373 #define PCD_(oo) OP(oo) 374 #define PCD_MASK OP_MASK 375 #define PCD(oo) PCD_(oo), PCD_MASK 376 377 /* Specific PALcode instructions. */ 378 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 379 #define SPCD_MASK 0xFFFFFFFF 380 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 381 382 /* Hardware memory (hw_{ld,st}) instructions. */ 383 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 384 #define EV4HWMEM_MASK (OP_MASK | 0xF000) 385 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 386 387 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 388 #define EV5HWMEM_MASK (OP_MASK | 0xF800) 389 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 390 391 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 392 #define EV6HWMEM_MASK (OP_MASK | 0xF000) 393 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK 394 395 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) 396 #define EV6HWMBR_MASK (OP_MASK | 0xE000) 397 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK 398 399 /* Abbreviations for instruction subsets. */ 400 #define BASE AXP_OPCODE_BASE 401 #define EV4 AXP_OPCODE_EV4 402 #define EV5 AXP_OPCODE_EV5 403 #define EV6 AXP_OPCODE_EV6 404 #define BWX AXP_OPCODE_BWX 405 #define CIX AXP_OPCODE_CIX 406 #define MAX AXP_OPCODE_MAX 407 408 /* Common combinations of arguments. */ 409 #define ARG_NONE { 0 } 410 #define ARG_BRA { RA, BDISP } 411 #define ARG_FBRA { FA, BDISP } 412 #define ARG_FP { FA, FB, DFC1 } 413 #define ARG_FPZ1 { ZA, FB, DFC1 } 414 #define ARG_MEM { RA, MDISP, PRB } 415 #define ARG_FMEM { FA, MDISP, PRB } 416 #define ARG_OPR { RA, RB, DRC1 } 417 #define ARG_OPRL { RA, LIT, DRC1 } 418 #define ARG_OPRZ1 { ZA, RB, DRC1 } 419 #define ARG_OPRLZ1 { ZA, LIT, RC } 420 #define ARG_PCD { PALFN } 421 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 422 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 423 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 424 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } 425 426 /* The opcode table. 427 428 The format of the opcode table is: 429 430 NAME OPCODE MASK { OPERANDS } 431 432 NAME is the name of the instruction. 433 434 OPCODE is the instruction opcode. 435 436 MASK is the opcode mask; this is used to tell the disassembler 437 which bits in the actual opcode must match OPCODE. 438 439 OPERANDS is the list of operands. 440 441 The preceding macros merge the text of the OPCODE and MASK fields. 442 443 The disassembler reads the table in order and prints the first 444 instruction which matches, so this table is sorted to put more 445 specific instructions before more general instructions. 446 447 Otherwise, it is sorted by major opcode and minor function code. 448 449 There are three classes of not-really-instructions in this table: 450 451 ALIAS is another name for another instruction. Some of 452 these come from the Architecture Handbook, some 453 come from the original gas opcode tables. In all 454 cases, the functionality of the opcode is unchanged. 455 456 PSEUDO a stylized code form endorsed by Chapter A.4 of the 457 Architecture Handbook. 458 459 EXTRA a stylized code form found in the original gas tables. 460 461 And two annotations: 462 463 EV56 BUT opcodes that are officially introduced as of the ev56, 464 but with defined results on previous implementations. 465 466 EV56 UNA opcodes that were introduced as of the ev56 with 467 presumably undefined results on previous implementations 468 that were not assigned to a particular extension. */ 469 470 const struct alpha_opcode alpha_opcodes[] = 471 { 472 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 473 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 474 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 475 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, 476 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 477 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 478 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 479 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, 480 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, 481 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, 482 { "call_pal", PCD(0x00), BASE, ARG_PCD }, 483 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 484 485 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ 486 { "lda", MEM(0x08), BASE, ARG_MEM }, 487 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ 488 { "ldah", MEM(0x09), BASE, ARG_MEM }, 489 { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 490 { "unop", MEM_(0x0B) | (30 << 16), 491 MEM_MASK, BASE, { ZA } }, /* pseudo */ 492 { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 493 { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 494 { "stw", MEM(0x0D), BWX, ARG_MEM }, 495 { "stb", MEM(0x0E), BWX, ARG_MEM }, 496 { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 497 498 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 499 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 500 { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 501 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 502 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 503 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 504 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 505 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 506 { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 507 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 508 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 509 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 510 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 511 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 512 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 513 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 514 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 515 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 516 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 517 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 518 { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 519 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 520 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 521 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 522 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 523 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 524 { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 525 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 526 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 527 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 528 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 529 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 530 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 531 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 532 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 533 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 534 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 535 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 536 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 537 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 538 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 539 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 540 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 541 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 542 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 543 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 544 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 545 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 546 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 547 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 548 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 549 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 550 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 551 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 552 553 { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 554 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 555 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 556 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 557 { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 558 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 559 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 560 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 561 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 562 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 563 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 564 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 565 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 566 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 567 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 568 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 569 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 570 { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 571 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 572 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 573 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 574 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 575 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 576 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 577 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 578 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 579 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 580 { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 581 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 582 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 583 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 584 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 585 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 586 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 587 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 588 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 589 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 590 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 591 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 592 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 593 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 594 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 595 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 596 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 597 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 598 599 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 600 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 601 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 602 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 603 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 604 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 605 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 606 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 607 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 608 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 609 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 610 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 611 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 612 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 613 { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 614 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 615 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 616 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 617 { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 618 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 619 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 620 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 621 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 622 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 623 { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 624 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 625 { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 626 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 627 { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 628 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 629 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 630 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 631 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 632 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 633 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 634 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 635 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 636 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 637 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 638 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 639 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 640 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 641 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 642 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 643 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 644 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 645 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 646 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 647 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 648 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 649 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 650 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 651 652 { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 653 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 654 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 655 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 656 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 657 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 658 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 659 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 660 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 661 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 662 663 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 664 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, 665 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, 666 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 667 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 668 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, 669 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, 670 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, 671 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, 672 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 673 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 674 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 675 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 676 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, 677 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, 678 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, 679 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, 680 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, 681 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, 682 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, 683 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, 684 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, 685 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, 686 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, 687 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, 688 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, 689 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, 690 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, 691 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, 692 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, 693 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, 694 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, 695 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, 696 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, 697 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, 698 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, 699 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, 700 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, 701 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, 702 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, 703 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, 704 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, 705 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, 706 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, 707 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, 708 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, 709 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, 710 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, 711 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, 712 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, 713 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, 714 715 { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 716 { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 717 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 718 { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 719 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 720 { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 721 { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 722 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 723 { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 724 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 725 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 726 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 727 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 728 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 729 { "addf", FP(0x15,0x080), BASE, ARG_FP }, 730 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 731 { "subf", FP(0x15,0x081), BASE, ARG_FP }, 732 { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 733 { "divf", FP(0x15,0x083), BASE, ARG_FP }, 734 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 735 { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 736 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 737 { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 738 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 739 { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 740 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 741 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 742 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 743 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 744 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 745 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 746 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 747 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 748 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 749 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 750 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 751 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 752 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 753 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 754 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 755 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 756 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 757 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 758 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 759 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 760 { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 761 { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 762 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 763 { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 764 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 765 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 766 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 767 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 768 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 769 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 770 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 771 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 772 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 773 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 774 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 775 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 776 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 777 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 778 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 779 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 780 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 781 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 782 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 783 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 784 { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 785 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 786 { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 787 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 788 { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 789 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 790 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 791 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 792 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 793 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 794 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 795 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 796 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 797 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 798 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 799 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 800 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 801 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 802 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 803 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 804 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 805 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 806 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 807 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 808 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 809 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 810 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 811 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 812 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 813 { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 814 { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 815 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 816 { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 817 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 818 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 819 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 820 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 821 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 822 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 823 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 824 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 825 826 { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 827 { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 828 { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 829 { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 830 { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 831 { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 832 { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 833 { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 834 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 835 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 836 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 837 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 838 { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 839 { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 840 { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 841 { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 842 { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 843 { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 844 { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 845 { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 846 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 847 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 848 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 849 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 850 { "adds", FP(0x16,0x080), BASE, ARG_FP }, 851 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 852 { "subs", FP(0x16,0x081), BASE, ARG_FP }, 853 { "muls", FP(0x16,0x082), BASE, ARG_FP }, 854 { "divs", FP(0x16,0x083), BASE, ARG_FP }, 855 { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 856 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 857 { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 858 { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 859 { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 860 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 861 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 862 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 863 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 864 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 865 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 866 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 867 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 868 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 869 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 870 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 871 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 872 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 873 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 874 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 875 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 876 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 877 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 878 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 879 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 880 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 881 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 882 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 883 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 884 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 885 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 886 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 887 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 888 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 889 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 890 { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 891 { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 892 { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 893 { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 894 { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 895 { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 896 { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 897 { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 898 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 899 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 900 { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 901 { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 902 { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 903 { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 904 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 905 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 906 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 907 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 908 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 909 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 910 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 911 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 912 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 913 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 914 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 915 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 916 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 917 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 918 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 919 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 920 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 921 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 922 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 923 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 924 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 925 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 926 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 927 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 928 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 929 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 930 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 931 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 932 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 933 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 934 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 935 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 936 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 937 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 938 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 939 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 940 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 941 { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 942 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 943 { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 944 { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 945 { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 946 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 947 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 948 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 949 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 950 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 951 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 952 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 953 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 954 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 955 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 956 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 957 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 958 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 959 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 960 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 961 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 962 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 963 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 964 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 965 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 966 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 967 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 968 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 969 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 970 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 971 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 972 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 973 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 974 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 975 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 976 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 977 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 978 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 979 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 980 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 981 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 982 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 983 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 984 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 985 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 986 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 987 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 988 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 989 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 990 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 991 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 992 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 993 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 994 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 995 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 996 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 997 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 998 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 999 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 1000 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 1001 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 1002 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 1003 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 1004 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 1005 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 1006 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 1007 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 1008 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 1009 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 1010 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 1011 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 1012 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 1013 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 1014 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 1015 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 1016 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 1017 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 1018 1019 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 1020 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 1021 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 1022 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 1023 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 1024 { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 1025 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 1026 { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 1027 { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 1028 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 1029 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 1030 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 1031 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 1032 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 1033 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 1034 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 1035 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 1036 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 1037 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 1038 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 1039 1040 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 1041 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 1042 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 1043 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 1044 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 1045 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, 1046 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, 1047 { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, 1048 { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ 1049 { "rc", MFC(0x18,0xE000), BASE, { RA } }, 1050 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ 1051 { "rs", MFC(0x18,0xF000), BASE, { RA } }, 1052 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ 1053 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ 1054 1055 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1056 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1057 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, 1058 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 1059 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 1060 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 1061 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 1062 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 1063 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 1064 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 1065 { "pal19", PCD(0x19), BASE, ARG_PCD }, 1066 1067 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ 1068 BASE, { ZA, CPRB } }, 1069 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 1070 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 1071 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ 1072 0xFFFFFFFF, BASE, { 0 } }, 1073 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 1074 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 1075 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 1076 1077 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1078 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1079 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, 1080 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1081 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1082 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, 1083 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1084 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1085 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1086 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1087 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1088 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1089 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1090 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1091 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1092 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1093 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1094 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, 1095 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1096 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1097 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1098 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1099 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1100 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1101 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1102 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1103 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1104 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1105 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1106 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1107 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1108 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1109 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1110 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1111 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1112 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1113 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1114 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1115 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, 1116 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1117 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1118 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, 1119 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, 1120 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1121 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1122 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1123 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1124 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1125 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1126 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1127 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1128 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1129 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, 1130 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1131 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1132 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1133 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1134 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1135 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1136 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1137 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1138 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1139 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1140 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1141 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1142 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, 1143 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1144 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1145 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, 1146 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1147 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1148 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1149 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1150 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1151 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1152 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1153 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1154 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1155 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1156 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1157 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, 1158 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1159 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1160 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1161 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1162 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1163 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1164 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1165 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1166 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1167 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1168 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1169 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1170 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1171 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1172 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1173 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1174 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1175 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1176 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1177 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1178 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, 1179 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1180 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1181 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, 1182 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, 1183 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1184 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1185 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1186 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1187 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1188 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1189 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1190 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1191 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1192 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, 1193 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1194 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1195 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1196 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1197 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1198 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1199 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1200 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1201 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1202 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1203 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1204 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1205 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1206 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1207 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1208 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1209 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1210 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1211 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1212 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1213 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1214 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1215 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1216 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1217 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1218 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1219 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1220 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1221 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1222 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1223 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1224 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1225 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1226 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1227 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1228 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1229 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1230 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1231 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1232 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1233 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1234 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1235 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1236 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1237 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1238 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1239 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1240 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1241 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1242 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1243 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1244 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1245 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1246 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1247 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1248 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1249 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1250 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1251 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1252 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1253 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1254 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1255 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1256 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1257 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1258 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1259 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1260 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1261 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1262 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1263 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1264 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1265 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1266 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1267 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1268 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1269 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1270 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1271 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1272 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1273 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1274 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1275 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1276 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1277 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1278 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1279 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1280 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1281 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1282 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1283 { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 1284 1285 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 1286 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 1287 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 1288 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 1289 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 1290 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 1291 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 1292 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 1293 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 1294 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 1295 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 1296 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 1297 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 1298 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 1299 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 1300 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 1301 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 1302 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 1303 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 1304 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 1305 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 1306 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 1307 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 1308 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 1309 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 1310 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 1311 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 1312 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 1313 1314 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1315 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1316 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, 1317 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 1318 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 1319 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 1320 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 1321 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 1322 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 1323 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 1324 { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 1325 1326 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 1327 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 1328 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1329 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1330 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, 1331 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, 1332 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ 1333 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1334 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1335 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, 1336 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, 1337 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ 1338 { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 1339 1340 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1341 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1342 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ 1343 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1344 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1345 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, 1346 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1347 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1348 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1349 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1350 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1351 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1352 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1353 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, 1354 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1355 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1356 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1357 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1358 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1359 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1360 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1361 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1362 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1363 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1364 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1365 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1366 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1367 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1368 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1369 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1370 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, 1371 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1372 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1373 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1374 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1375 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1376 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1377 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ 1378 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1379 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1380 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, 1381 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1382 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1383 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1384 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1385 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1386 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1387 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1388 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, 1389 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1390 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1391 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1392 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1393 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1394 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1395 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1396 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1397 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1398 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1399 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1400 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 1401 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1402 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1403 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1404 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1405 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1406 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1407 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, 1408 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1409 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1410 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1411 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1412 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1413 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1414 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1415 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1416 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1417 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1418 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1419 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1420 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1421 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1422 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1423 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1424 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1425 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1426 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1427 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1428 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1429 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1430 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1431 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1432 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1433 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1434 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1435 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1436 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1437 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1438 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1439 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1440 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1441 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1442 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1443 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1444 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1445 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1446 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1447 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1448 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1449 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1450 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1451 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1452 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1453 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1454 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1455 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1456 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1457 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1458 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1459 { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 1460 1461 { "ldf", MEM(0x20), BASE, ARG_FMEM }, 1462 { "ldg", MEM(0x21), BASE, ARG_FMEM }, 1463 { "lds", MEM(0x22), BASE, ARG_FMEM }, 1464 { "ldt", MEM(0x23), BASE, ARG_FMEM }, 1465 { "stf", MEM(0x24), BASE, ARG_FMEM }, 1466 { "stg", MEM(0x25), BASE, ARG_FMEM }, 1467 { "sts", MEM(0x26), BASE, ARG_FMEM }, 1468 { "stt", MEM(0x27), BASE, ARG_FMEM }, 1469 1470 { "ldl", MEM(0x28), BASE, ARG_MEM }, 1471 { "ldq", MEM(0x29), BASE, ARG_MEM }, 1472 { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 1473 { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 1474 { "stl", MEM(0x2C), BASE, ARG_MEM }, 1475 { "stq", MEM(0x2D), BASE, ARG_MEM }, 1476 { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 1477 { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 1478 1479 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 1480 { "br", BRA(0x30), BASE, ARG_BRA }, 1481 { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 1482 { "fblt", BRA(0x32), BASE, ARG_FBRA }, 1483 { "fble", BRA(0x33), BASE, ARG_FBRA }, 1484 { "bsr", BRA(0x34), BASE, ARG_BRA }, 1485 { "fbne", BRA(0x35), BASE, ARG_FBRA }, 1486 { "fbge", BRA(0x36), BASE, ARG_FBRA }, 1487 { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 1488 { "blbc", BRA(0x38), BASE, ARG_BRA }, 1489 { "beq", BRA(0x39), BASE, ARG_BRA }, 1490 { "blt", BRA(0x3A), BASE, ARG_BRA }, 1491 { "ble", BRA(0x3B), BASE, ARG_BRA }, 1492 { "blbs", BRA(0x3C), BASE, ARG_BRA }, 1493 { "bne", BRA(0x3D), BASE, ARG_BRA }, 1494 { "bge", BRA(0x3E), BASE, ARG_BRA }, 1495 { "bgt", BRA(0x3F), BASE, ARG_BRA }, 1496 }; 1497 1498 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1499