110d565efSmrg /* Definitions of target machine for GNU compiler. MIPS version. 2*ec02198aSmrg Copyright (C) 1989-2020 Free Software Foundation, Inc. 310d565efSmrg Contributed by A. Lichnewsky (lich@inria.inria.fr). 410d565efSmrg Changed by Michael Meissner (meissner@osf.org). 510d565efSmrg 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 610d565efSmrg Brendan Eich (brendan@microunity.com). 710d565efSmrg 810d565efSmrg This file is part of GCC. 910d565efSmrg 1010d565efSmrg GCC is free software; you can redistribute it and/or modify 1110d565efSmrg it under the terms of the GNU General Public License as published by 1210d565efSmrg the Free Software Foundation; either version 3, or (at your option) 1310d565efSmrg any later version. 1410d565efSmrg 1510d565efSmrg GCC is distributed in the hope that it will be useful, 1610d565efSmrg but WITHOUT ANY WARRANTY; without even the implied warranty of 1710d565efSmrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1810d565efSmrg GNU General Public License for more details. 1910d565efSmrg 2010d565efSmrg You should have received a copy of the GNU General Public License 2110d565efSmrg along with GCC; see the file COPYING3. If not see 2210d565efSmrg <http://www.gnu.org/licenses/>. */ 2310d565efSmrg 2410d565efSmrg 2510d565efSmrg #include "config/vxworks-dummy.h" 2610d565efSmrg 2710d565efSmrg #ifdef GENERATOR_FILE 2810d565efSmrg /* This is used in some insn conditions, so needs to be declared, but 2910d565efSmrg does not need to be defined. */ 3010d565efSmrg extern int target_flags_explicit; 3110d565efSmrg #endif 3210d565efSmrg 3310d565efSmrg /* MIPS external variables defined in mips.c. */ 3410d565efSmrg 3510d565efSmrg /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 3610d565efSmrg ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 3710d565efSmrg to work on a 64-bit machine. */ 3810d565efSmrg 3910d565efSmrg #define ABI_32 0 4010d565efSmrg #define ABI_N32 1 4110d565efSmrg #define ABI_64 2 4210d565efSmrg #define ABI_EABI 3 4310d565efSmrg #define ABI_O64 4 4410d565efSmrg 4510d565efSmrg /* Masks that affect tuning. 4610d565efSmrg 4710d565efSmrg PTF_AVOID_BRANCHLIKELY_SPEED 4810d565efSmrg Set if it is usually not profitable to use branch-likely instructions 4910d565efSmrg for this target when optimizing code for speed, typically because 5010d565efSmrg the branches are always predicted taken and so incur a large overhead 5110d565efSmrg when not taken. 5210d565efSmrg 5310d565efSmrg PTF_AVOID_BRANCHLIKELY_SIZE 5410d565efSmrg As above but when optimizing for size. 5510d565efSmrg 5610d565efSmrg PTF_AVOID_BRANCHLIKELY_ALWAYS 5710d565efSmrg As above but regardless of whether we optimize for speed or size. 5810d565efSmrg 5910d565efSmrg PTF_AVOID_IMADD 6010d565efSmrg Set if it is usually not profitable to use the integer MADD or MSUB 6110d565efSmrg instructions because of the overhead of getting the result out of 6210d565efSmrg the HI/LO registers. */ 6310d565efSmrg 6410d565efSmrg #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1 6510d565efSmrg #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2 6610d565efSmrg #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \ 6710d565efSmrg PTF_AVOID_BRANCHLIKELY_SIZE) 6810d565efSmrg #define PTF_AVOID_IMADD 0x4 6910d565efSmrg 7010d565efSmrg /* Information about one recognized processor. Defined here for the 7110d565efSmrg benefit of TARGET_CPU_CPP_BUILTINS. */ 7210d565efSmrg struct mips_cpu_info { 7310d565efSmrg /* The 'canonical' name of the processor as far as GCC is concerned. 7410d565efSmrg It's typically a manufacturer's prefix followed by a numerical 7510d565efSmrg designation. It should be lowercase. */ 7610d565efSmrg const char *name; 7710d565efSmrg 7810d565efSmrg /* The internal processor number that most closely matches this 7910d565efSmrg entry. Several processors can have the same value, if there's no 8010d565efSmrg difference between them from GCC's point of view. */ 8110d565efSmrg enum processor cpu; 8210d565efSmrg 8310d565efSmrg /* The ISA level that the processor implements. */ 8410d565efSmrg int isa; 8510d565efSmrg 8610d565efSmrg /* A mask of PTF_* values. */ 8710d565efSmrg unsigned int tune_flags; 8810d565efSmrg }; 8910d565efSmrg 9010d565efSmrg #include "config/mips/mips-opts.h" 9110d565efSmrg 9210d565efSmrg /* Macros to silence warnings about numbers being signed in traditional 9310d565efSmrg C and unsigned in ISO C when compiled on 32-bit hosts. */ 9410d565efSmrg 9510d565efSmrg #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 9610d565efSmrg #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 9710d565efSmrg #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 9810d565efSmrg 9910d565efSmrg 10010d565efSmrg /* Run-time compilation parameters selecting different hardware subsets. */ 10110d565efSmrg 10210d565efSmrg /* True if we are generating position-independent VxWorks RTP code. */ 10310d565efSmrg #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) 10410d565efSmrg 10510d565efSmrg /* Compact branches must not be used if the user either selects the 10610d565efSmrg 'never' policy or the 'optimal' policy on a core that lacks 10710d565efSmrg compact branch instructions. */ 10810d565efSmrg #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \ 10910d565efSmrg || (mips_cb == MIPS_CB_OPTIMAL \ 11010d565efSmrg && !ISA_HAS_COMPACT_BRANCHES)) 11110d565efSmrg 11210d565efSmrg /* Compact branches may be used if the user either selects the 11310d565efSmrg 'always' policy or the 'optimal' policy on a core that supports 11410d565efSmrg compact branch instructions. */ 11510d565efSmrg #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \ 11610d565efSmrg || (mips_cb == MIPS_CB_OPTIMAL \ 11710d565efSmrg && ISA_HAS_COMPACT_BRANCHES)) 11810d565efSmrg 11910d565efSmrg /* Compact branches must always be generated if the user selects 12010d565efSmrg the 'always' policy or the 'optimal' policy om a core that 12110d565efSmrg lacks delay slot branch instructions. */ 12210d565efSmrg #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \ 12310d565efSmrg || (mips_cb == MIPS_CB_OPTIMAL \ 12410d565efSmrg && !ISA_HAS_DELAY_SLOTS)) 12510d565efSmrg 12610d565efSmrg /* Special handling for JRC that exists in microMIPSR3 as well as R6 12710d565efSmrg ISAs with full compact branch support. */ 12810d565efSmrg #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \ 12910d565efSmrg || TARGET_MICROMIPS) \ 13010d565efSmrg && mips_cb != MIPS_CB_NEVER) 13110d565efSmrg 13210d565efSmrg /* True if the output file is marked as ".abicalls; .option pic0" 13310d565efSmrg (-call_nonpic). */ 13410d565efSmrg #define TARGET_ABICALLS_PIC0 \ 13510d565efSmrg (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) 13610d565efSmrg 13710d565efSmrg /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ 13810d565efSmrg #define TARGET_ABICALLS_PIC2 \ 13910d565efSmrg (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) 14010d565efSmrg 14110d565efSmrg /* True if the call patterns should be split into a jalr followed by 14210d565efSmrg an instruction to restore $gp. It is only safe to split the load 14310d565efSmrg from the call when every use of $gp is explicit. 14410d565efSmrg 14510d565efSmrg See mips_must_initialize_gp_p for details about how we manage the 14610d565efSmrg global pointer. */ 14710d565efSmrg 14810d565efSmrg #define TARGET_SPLIT_CALLS \ 14910d565efSmrg (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) 15010d565efSmrg 15110d565efSmrg /* True if we're generating a form of -mabicalls in which we can use 15210d565efSmrg operators like %hi and %lo to refer to locally-binding symbols. 15310d565efSmrg We can only do this for -mno-shared, and only then if we can use 15410d565efSmrg relocation operations instead of assembly macros. It isn't really 15510d565efSmrg worth using absolute sequences for 64-bit symbols because GOT 15610d565efSmrg accesses are so much shorter. */ 15710d565efSmrg 15810d565efSmrg #define TARGET_ABSOLUTE_ABICALLS \ 15910d565efSmrg (TARGET_ABICALLS \ 16010d565efSmrg && !TARGET_SHARED \ 16110d565efSmrg && TARGET_EXPLICIT_RELOCS \ 16210d565efSmrg && !ABI_HAS_64BIT_SYMBOLS) 16310d565efSmrg 16410d565efSmrg /* True if we can optimize sibling calls. For simplicity, we only 16510d565efSmrg handle cases in which call_insn_operand will reject invalid 16610d565efSmrg sibcall addresses. There are two cases in which this isn't true: 16710d565efSmrg 16810d565efSmrg - TARGET_MIPS16. call_insn_operand accepts constant addresses 16910d565efSmrg but there is no direct jump instruction. It isn't worth 17010d565efSmrg using sibling calls in this case anyway; they would usually 17110d565efSmrg be longer than normal calls. 17210d565efSmrg 17310d565efSmrg - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand 17410d565efSmrg accepts global constants, but all sibcalls must be indirect. */ 17510d565efSmrg #define TARGET_SIBCALLS \ 17610d565efSmrg (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) 17710d565efSmrg 17810d565efSmrg /* True if we need to use a global offset table to access some symbols. */ 17910d565efSmrg #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) 18010d565efSmrg 18110d565efSmrg /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ 18210d565efSmrg #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) 18310d565efSmrg 18410d565efSmrg /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ 18510d565efSmrg #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) 18610d565efSmrg 18710d565efSmrg /* True if we should use .cprestore to store to the cprestore slot. 18810d565efSmrg 18910d565efSmrg We continue to use .cprestore for explicit-reloc code so that JALs 19010d565efSmrg inside inline asms will work correctly. */ 19110d565efSmrg #define TARGET_CPRESTORE_DIRECTIVE \ 19210d565efSmrg (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) 19310d565efSmrg 19410d565efSmrg /* True if we can use the J and JAL instructions. */ 19510d565efSmrg #define TARGET_ABSOLUTE_JUMPS \ 19610d565efSmrg (!flag_pic || TARGET_ABSOLUTE_ABICALLS) 19710d565efSmrg 19810d565efSmrg /* True if indirect calls must use register class PIC_FN_ADDR_REG. 19910d565efSmrg This is true for both the PIC and non-PIC VxWorks RTP modes. */ 20010d565efSmrg #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) 20110d565efSmrg 20210d565efSmrg /* True if .gpword or .gpdword should be used for switch tables. */ 20310d565efSmrg #define TARGET_GPWORD \ 20410d565efSmrg (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 20510d565efSmrg 20610d565efSmrg /* True if the output must have a writable .eh_frame. 20710d565efSmrg See ASM_PREFERRED_EH_DATA_FORMAT for details. */ 20810d565efSmrg #ifdef HAVE_LD_PERSONALITY_RELAXATION 20910d565efSmrg #define TARGET_WRITABLE_EH_FRAME 0 21010d565efSmrg #else 21110d565efSmrg #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) 21210d565efSmrg #endif 21310d565efSmrg 21410d565efSmrg /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */ 21510d565efSmrg #ifdef HAVE_AS_DSPR1_MULT 21610d565efSmrg #define ISA_HAS_DSP_MULT ISA_HAS_DSP 21710d565efSmrg #else 21810d565efSmrg #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2 21910d565efSmrg #endif 22010d565efSmrg 22110d565efSmrg /* ISA has LSA available. */ 22210d565efSmrg #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA) 22310d565efSmrg 22410d565efSmrg /* ISA has DLSA available. */ 22510d565efSmrg #define ISA_HAS_DLSA (TARGET_64BIT \ 22610d565efSmrg && (mips_isa_rev >= 6 \ 22710d565efSmrg || ISA_HAS_MSA)) 22810d565efSmrg 22910d565efSmrg /* The ISA compression flags that are currently in effect. */ 23010d565efSmrg #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS)) 23110d565efSmrg 23210d565efSmrg /* Generate mips16 code */ 23310d565efSmrg #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 23410d565efSmrg /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ 23510d565efSmrg #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 23610d565efSmrg /* Generate mips16e register save/restore sequences. */ 23710d565efSmrg #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) 23810d565efSmrg 23910d565efSmrg /* True if we're generating a form of MIPS16 code in which general 24010d565efSmrg text loads are allowed. */ 24110d565efSmrg #define TARGET_MIPS16_TEXT_LOADS \ 24210d565efSmrg (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) 24310d565efSmrg 24410d565efSmrg /* True if we're generating a form of MIPS16 code in which PC-relative 24510d565efSmrg loads are allowed. */ 24610d565efSmrg #define TARGET_MIPS16_PCREL_LOADS \ 24710d565efSmrg (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) 24810d565efSmrg 24910d565efSmrg /* Generic ISA defines. */ 25010d565efSmrg #define ISA_MIPS1 (mips_isa == 1) 25110d565efSmrg #define ISA_MIPS2 (mips_isa == 2) 25210d565efSmrg #define ISA_MIPS3 (mips_isa == 3) 25310d565efSmrg #define ISA_MIPS4 (mips_isa == 4) 25410d565efSmrg #define ISA_MIPS32 (mips_isa == 32) 25510d565efSmrg #define ISA_MIPS32R2 (mips_isa == 33) 25610d565efSmrg #define ISA_MIPS32R3 (mips_isa == 34) 25710d565efSmrg #define ISA_MIPS32R5 (mips_isa == 36) 25810d565efSmrg #define ISA_MIPS32R6 (mips_isa == 37) 25910d565efSmrg #define ISA_MIPS64 (mips_isa == 64) 26010d565efSmrg #define ISA_MIPS64R2 (mips_isa == 65) 26110d565efSmrg #define ISA_MIPS64R3 (mips_isa == 66) 26210d565efSmrg #define ISA_MIPS64R5 (mips_isa == 68) 26310d565efSmrg #define ISA_MIPS64R6 (mips_isa == 69) 26410d565efSmrg 26510d565efSmrg /* Architecture target defines. */ 26610d565efSmrg #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) 26710d565efSmrg #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) 26810d565efSmrg #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) 2690fc04c29Smrg #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) 2700fc04c29Smrg #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) 2710fc04c29Smrg #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) 27210d565efSmrg #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 27310d565efSmrg #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 27410d565efSmrg #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 27510d565efSmrg #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 27610d565efSmrg #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 27710d565efSmrg #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 27810d565efSmrg #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900) 27910d565efSmrg #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 28010d565efSmrg #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000) 28110d565efSmrg #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 28210d565efSmrg #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ 28310d565efSmrg || mips_arch == PROCESSOR_OCTEON2 \ 28410d565efSmrg || mips_arch == PROCESSOR_OCTEON3) 28510d565efSmrg #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ 28610d565efSmrg || mips_arch == PROCESSOR_OCTEON3) 28710d565efSmrg #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 28810d565efSmrg || mips_arch == PROCESSOR_SB1A) 28910d565efSmrg #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 29010d565efSmrg #define TARGET_XLP (mips_arch == PROCESSOR_XLP) 29110d565efSmrg 29210d565efSmrg /* Scheduling target defines. */ 29310d565efSmrg #define TUNE_20KC (mips_tune == PROCESSOR_20KC) 29410d565efSmrg #define TUNE_24K (mips_tune == PROCESSOR_24KC \ 29510d565efSmrg || mips_tune == PROCESSOR_24KF2_1 \ 29610d565efSmrg || mips_tune == PROCESSOR_24KF1_1) 29710d565efSmrg #define TUNE_74K (mips_tune == PROCESSOR_74KC \ 29810d565efSmrg || mips_tune == PROCESSOR_74KF2_1 \ 29910d565efSmrg || mips_tune == PROCESSOR_74KF1_1 \ 30010d565efSmrg || mips_tune == PROCESSOR_74KF3_2) 30110d565efSmrg #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ 30210d565efSmrg || mips_tune == PROCESSOR_LOONGSON_2F) 3030fc04c29Smrg #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) 3040fc04c29Smrg #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) 3050fc04c29Smrg #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) 30610d565efSmrg #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 30710d565efSmrg #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 30810d565efSmrg #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 30910d565efSmrg #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 31010d565efSmrg #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 31110d565efSmrg #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 31210d565efSmrg #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 31310d565efSmrg #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 31410d565efSmrg #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 31510d565efSmrg #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 31610d565efSmrg #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 31710d565efSmrg #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ 31810d565efSmrg || mips_tune == PROCESSOR_OCTEON2 \ 31910d565efSmrg || mips_tune == PROCESSOR_OCTEON3) 32010d565efSmrg #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 32110d565efSmrg || mips_tune == PROCESSOR_SB1A) 32210d565efSmrg #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) 32310d565efSmrg #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) 3240fc04c29Smrg #define TUNE_P6600 (mips_tune == PROCESSOR_P6600) 32510d565efSmrg 32610d565efSmrg /* True if the pre-reload scheduler should try to create chains of 32710d565efSmrg multiply-add or multiply-subtract instructions. For example, 32810d565efSmrg suppose we have: 32910d565efSmrg 33010d565efSmrg t1 = a * b 33110d565efSmrg t2 = t1 + c * d 33210d565efSmrg t3 = e * f 33310d565efSmrg t4 = t3 - g * h 33410d565efSmrg 33510d565efSmrg t1 will have a higher priority than t2 and t3 will have a higher 33610d565efSmrg priority than t4. However, before reload, there is no dependence 33710d565efSmrg between t1 and t3, and they can often have similar priorities. 33810d565efSmrg The scheduler will then tend to prefer: 33910d565efSmrg 34010d565efSmrg t1 = a * b 34110d565efSmrg t3 = e * f 34210d565efSmrg t2 = t1 + c * d 34310d565efSmrg t4 = t3 - g * h 34410d565efSmrg 34510d565efSmrg which stops us from making full use of macc/madd-style instructions. 34610d565efSmrg This sort of situation occurs frequently in Fourier transforms and 34710d565efSmrg in unrolled loops. 34810d565efSmrg 34910d565efSmrg To counter this, the TUNE_MACC_CHAINS code will reorder the ready 35010d565efSmrg queue so that chained multiply-add and multiply-subtract instructions 35110d565efSmrg appear ahead of any other instruction that is likely to clobber lo. 35210d565efSmrg In the example above, if t2 and t3 become ready at the same time, 35310d565efSmrg the code ensures that t2 is scheduled first. 35410d565efSmrg 35510d565efSmrg Multiply-accumulate instructions are a bigger win for some targets 35610d565efSmrg than others, so this macro is defined on an opt-in basis. */ 35710d565efSmrg #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 35810d565efSmrg || TUNE_MIPS4120 \ 35910d565efSmrg || TUNE_MIPS4130 \ 36010d565efSmrg || TUNE_24K \ 36110d565efSmrg || TUNE_P5600) 36210d565efSmrg 36310d565efSmrg #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 36410d565efSmrg #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 36510d565efSmrg 36610d565efSmrg /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is 36710d565efSmrg directly accessible, while the command-line options select 36810d565efSmrg TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI 36910d565efSmrg in use. */ 37010d565efSmrg #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) 37110d565efSmrg #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) 37210d565efSmrg 37310d565efSmrg /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents 37410d565efSmrg -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */ 37510d565efSmrg #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX) 37610d565efSmrg 37710d565efSmrg /* TARGET_O32_FP64A_ABI represents all the conditions that form the 37810d565efSmrg o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */ 37910d565efSmrg #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \ 38010d565efSmrg && !TARGET_ODD_SPREG) 38110d565efSmrg 38210d565efSmrg /* False if SC acts as a memory barrier with respect to itself, 38310d565efSmrg otherwise a SYNC will be emitted after SC for atomic operations 38410d565efSmrg that require ordering between the SC and following loads and 38510d565efSmrg stores. It does not tell anything about ordering of loads and 38610d565efSmrg stores prior to and following the SC, only about the SC itself and 38710d565efSmrg those loads and stores follow it. */ 38810d565efSmrg #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP) 38910d565efSmrg 39010d565efSmrg /* Define preprocessor macros for the -march and -mtune options. 39110d565efSmrg PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 39210d565efSmrg processor. If INFO's canonical name is "foo", define PREFIX to 39310d565efSmrg be "foo", and define an additional macro PREFIX_FOO. */ 39410d565efSmrg #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 39510d565efSmrg do \ 39610d565efSmrg { \ 39710d565efSmrg char *macro, *p; \ 39810d565efSmrg \ 39910d565efSmrg macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 40010d565efSmrg for (p = macro; *p != 0; p++) \ 40110d565efSmrg if (*p == '+') \ 40210d565efSmrg *p = 'P'; \ 40310d565efSmrg else \ 40410d565efSmrg *p = TOUPPER (*p); \ 40510d565efSmrg \ 40610d565efSmrg builtin_define (macro); \ 40710d565efSmrg builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 40810d565efSmrg free (macro); \ 40910d565efSmrg } \ 41010d565efSmrg while (0) 41110d565efSmrg 41210d565efSmrg /* Target CPU builtins. */ 41310d565efSmrg #define TARGET_CPU_CPP_BUILTINS() \ 41410d565efSmrg do \ 41510d565efSmrg { \ 41610d565efSmrg builtin_assert ("machine=mips"); \ 41710d565efSmrg builtin_assert ("cpu=mips"); \ 41810d565efSmrg builtin_define ("__mips__"); \ 41910d565efSmrg builtin_define ("_mips"); \ 42010d565efSmrg \ 42110d565efSmrg /* We do this here because __mips is defined below and so we \ 42210d565efSmrg can't use builtin_define_std. We don't ever want to define \ 42310d565efSmrg "mips" for VxWorks because some of the VxWorks headers \ 42410d565efSmrg construct include filenames from a root directory macro, \ 42510d565efSmrg an architecture macro and a filename, where the architecture \ 42610d565efSmrg macro expands to 'mips'. If we define 'mips' to 1, the \ 42710d565efSmrg architecture macro expands to 1 as well. */ \ 42810d565efSmrg if (!flag_iso && !TARGET_VXWORKS) \ 42910d565efSmrg builtin_define ("mips"); \ 43010d565efSmrg \ 43110d565efSmrg if (TARGET_64BIT) \ 43210d565efSmrg builtin_define ("__mips64"); \ 43310d565efSmrg \ 43410d565efSmrg /* Treat _R3000 and _R4000 like register-size \ 43510d565efSmrg defines, which is how they've historically \ 43610d565efSmrg been used. */ \ 43710d565efSmrg if (TARGET_64BIT) \ 43810d565efSmrg { \ 43910d565efSmrg builtin_define_std ("R4000"); \ 44010d565efSmrg builtin_define ("_R4000"); \ 44110d565efSmrg } \ 44210d565efSmrg else \ 44310d565efSmrg { \ 44410d565efSmrg builtin_define_std ("R3000"); \ 44510d565efSmrg builtin_define ("_R3000"); \ 44610d565efSmrg } \ 44710d565efSmrg \ 44810d565efSmrg if (TARGET_FLOAT64) \ 44910d565efSmrg builtin_define ("__mips_fpr=64"); \ 45010d565efSmrg else if (TARGET_FLOATXX) \ 45110d565efSmrg builtin_define ("__mips_fpr=0"); \ 45210d565efSmrg else \ 45310d565efSmrg builtin_define ("__mips_fpr=32"); \ 45410d565efSmrg \ 45510d565efSmrg if (mips_base_compression_flags & MASK_MIPS16) \ 45610d565efSmrg builtin_define ("__mips16"); \ 45710d565efSmrg \ 45810d565efSmrg if (TARGET_MIPS3D) \ 45910d565efSmrg builtin_define ("__mips3d"); \ 46010d565efSmrg \ 46110d565efSmrg if (TARGET_SMARTMIPS) \ 46210d565efSmrg builtin_define ("__mips_smartmips"); \ 46310d565efSmrg \ 46410d565efSmrg if (mips_base_compression_flags & MASK_MICROMIPS) \ 46510d565efSmrg builtin_define ("__mips_micromips"); \ 46610d565efSmrg \ 46710d565efSmrg if (TARGET_MCU) \ 46810d565efSmrg builtin_define ("__mips_mcu"); \ 46910d565efSmrg \ 47010d565efSmrg if (TARGET_EVA) \ 47110d565efSmrg builtin_define ("__mips_eva"); \ 47210d565efSmrg \ 47310d565efSmrg if (TARGET_DSP) \ 47410d565efSmrg { \ 47510d565efSmrg builtin_define ("__mips_dsp"); \ 47610d565efSmrg if (TARGET_DSPR2) \ 47710d565efSmrg { \ 47810d565efSmrg builtin_define ("__mips_dspr2"); \ 47910d565efSmrg builtin_define ("__mips_dsp_rev=2"); \ 48010d565efSmrg } \ 48110d565efSmrg else \ 48210d565efSmrg builtin_define ("__mips_dsp_rev=1"); \ 48310d565efSmrg } \ 48410d565efSmrg \ 48510d565efSmrg if (ISA_HAS_MSA) \ 48610d565efSmrg { \ 48710d565efSmrg builtin_define ("__mips_msa"); \ 48810d565efSmrg builtin_define ("__mips_msa_width=128"); \ 48910d565efSmrg } \ 49010d565efSmrg \ 49110d565efSmrg MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 49210d565efSmrg MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 49310d565efSmrg \ 49410d565efSmrg if (ISA_MIPS1) \ 49510d565efSmrg { \ 49610d565efSmrg builtin_define ("__mips=1"); \ 49710d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 49810d565efSmrg } \ 49910d565efSmrg else if (ISA_MIPS2) \ 50010d565efSmrg { \ 50110d565efSmrg builtin_define ("__mips=2"); \ 50210d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 50310d565efSmrg } \ 50410d565efSmrg else if (ISA_MIPS3) \ 50510d565efSmrg { \ 50610d565efSmrg builtin_define ("__mips=3"); \ 50710d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 50810d565efSmrg } \ 50910d565efSmrg else if (ISA_MIPS4) \ 51010d565efSmrg { \ 51110d565efSmrg builtin_define ("__mips=4"); \ 51210d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 51310d565efSmrg } \ 51410d565efSmrg else if (mips_isa >= 32 && mips_isa < 64) \ 51510d565efSmrg { \ 51610d565efSmrg builtin_define ("__mips=32"); \ 51710d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 51810d565efSmrg } \ 51910d565efSmrg else if (mips_isa >= 64) \ 52010d565efSmrg { \ 52110d565efSmrg builtin_define ("__mips=64"); \ 52210d565efSmrg builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 52310d565efSmrg } \ 52410d565efSmrg if (mips_isa_rev > 0) \ 52510d565efSmrg builtin_define_with_int_value ("__mips_isa_rev", \ 52610d565efSmrg mips_isa_rev); \ 52710d565efSmrg \ 52810d565efSmrg switch (mips_abi) \ 52910d565efSmrg { \ 53010d565efSmrg case ABI_32: \ 53110d565efSmrg builtin_define ("_ABIO32=1"); \ 53210d565efSmrg builtin_define ("_MIPS_SIM=_ABIO32"); \ 53310d565efSmrg break; \ 53410d565efSmrg \ 53510d565efSmrg case ABI_N32: \ 53610d565efSmrg builtin_define ("_ABIN32=2"); \ 53710d565efSmrg builtin_define ("_MIPS_SIM=_ABIN32"); \ 53810d565efSmrg break; \ 53910d565efSmrg \ 54010d565efSmrg case ABI_64: \ 54110d565efSmrg builtin_define ("_ABI64=3"); \ 54210d565efSmrg builtin_define ("_MIPS_SIM=_ABI64"); \ 54310d565efSmrg break; \ 54410d565efSmrg \ 54510d565efSmrg case ABI_O64: \ 54610d565efSmrg builtin_define ("_ABIO64=4"); \ 54710d565efSmrg builtin_define ("_MIPS_SIM=_ABIO64"); \ 54810d565efSmrg break; \ 54910d565efSmrg } \ 55010d565efSmrg \ 55110d565efSmrg builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ 55210d565efSmrg builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ 55310d565efSmrg builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ 55410d565efSmrg builtin_define_with_int_value ("_MIPS_FPSET", \ 55510d565efSmrg 32 / MAX_FPRS_PER_FMT); \ 55610d565efSmrg builtin_define_with_int_value ("_MIPS_SPFPSET", \ 55710d565efSmrg TARGET_ODD_SPREG ? 32 : 16); \ 55810d565efSmrg \ 55910d565efSmrg /* These defines reflect the ABI in use, not whether the \ 56010d565efSmrg FPU is directly accessible. */ \ 56110d565efSmrg if (TARGET_NO_FLOAT) \ 56210d565efSmrg builtin_define ("__mips_no_float"); \ 56310d565efSmrg else if (TARGET_HARD_FLOAT_ABI) \ 56410d565efSmrg builtin_define ("__mips_hard_float"); \ 56510d565efSmrg else \ 56610d565efSmrg builtin_define ("__mips_soft_float"); \ 56710d565efSmrg \ 56810d565efSmrg if (TARGET_SINGLE_FLOAT) \ 56910d565efSmrg builtin_define ("__mips_single_float"); \ 57010d565efSmrg \ 57110d565efSmrg if (TARGET_PAIRED_SINGLE_FLOAT) \ 57210d565efSmrg builtin_define ("__mips_paired_single_float"); \ 57310d565efSmrg \ 57410d565efSmrg if (mips_abs == MIPS_IEEE_754_2008) \ 57510d565efSmrg builtin_define ("__mips_abs2008"); \ 57610d565efSmrg \ 57710d565efSmrg if (mips_nan == MIPS_IEEE_754_2008) \ 57810d565efSmrg builtin_define ("__mips_nan2008"); \ 57910d565efSmrg \ 58010d565efSmrg if (TARGET_BIG_ENDIAN) \ 58110d565efSmrg { \ 58210d565efSmrg builtin_define_std ("MIPSEB"); \ 58310d565efSmrg builtin_define ("_MIPSEB"); \ 58410d565efSmrg } \ 58510d565efSmrg else \ 58610d565efSmrg { \ 58710d565efSmrg builtin_define_std ("MIPSEL"); \ 58810d565efSmrg builtin_define ("_MIPSEL"); \ 58910d565efSmrg } \ 59010d565efSmrg \ 59110d565efSmrg /* Whether calls should go through $25. The separate __PIC__ \ 59210d565efSmrg macro indicates whether abicalls code might use a GOT. */ \ 59310d565efSmrg if (TARGET_ABICALLS) \ 59410d565efSmrg builtin_define ("__mips_abicalls"); \ 59510d565efSmrg \ 59610d565efSmrg /* Whether Loongson vector modes are enabled. */ \ 5970fc04c29Smrg if (TARGET_LOONGSON_MMI) \ 5980fc04c29Smrg { \ 59910d565efSmrg builtin_define ("__mips_loongson_vector_rev"); \ 6000fc04c29Smrg builtin_define ("__mips_loongson_mmi"); \ 6010fc04c29Smrg } \ 6020fc04c29Smrg \ 6030fc04c29Smrg /* Whether Loongson EXT modes are enabled. */ \ 6040fc04c29Smrg if (TARGET_LOONGSON_EXT) \ 6050fc04c29Smrg { \ 6060fc04c29Smrg builtin_define ("__mips_loongson_ext"); \ 6070fc04c29Smrg if (TARGET_LOONGSON_EXT2) \ 6080fc04c29Smrg { \ 6090fc04c29Smrg builtin_define ("__mips_loongson_ext2"); \ 6100fc04c29Smrg builtin_define ("__mips_loongson_ext_rev=2"); \ 6110fc04c29Smrg } \ 6120fc04c29Smrg else \ 6130fc04c29Smrg builtin_define ("__mips_loongson_ext_rev=1"); \ 6140fc04c29Smrg } \ 61510d565efSmrg \ 61610d565efSmrg /* Historical Octeon macro. */ \ 61710d565efSmrg if (TARGET_OCTEON) \ 61810d565efSmrg builtin_define ("__OCTEON__"); \ 61910d565efSmrg \ 62010d565efSmrg if (TARGET_SYNCI) \ 62110d565efSmrg builtin_define ("__mips_synci"); \ 62210d565efSmrg \ 62310d565efSmrg /* Macros dependent on the C dialect. */ \ 62410d565efSmrg if (preprocessing_asm_p ()) \ 62510d565efSmrg { \ 62610d565efSmrg builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 62710d565efSmrg builtin_define ("_LANGUAGE_ASSEMBLY"); \ 62810d565efSmrg } \ 62910d565efSmrg else if (c_dialect_cxx ()) \ 63010d565efSmrg { \ 63110d565efSmrg builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 63210d565efSmrg builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 63310d565efSmrg builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 63410d565efSmrg } \ 63510d565efSmrg else \ 63610d565efSmrg { \ 63710d565efSmrg builtin_define_std ("LANGUAGE_C"); \ 63810d565efSmrg builtin_define ("_LANGUAGE_C"); \ 63910d565efSmrg } \ 64010d565efSmrg if (c_dialect_objc ()) \ 64110d565efSmrg { \ 64210d565efSmrg builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 64310d565efSmrg builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 64410d565efSmrg /* Bizarre, but retained for backwards compatibility. */ \ 64510d565efSmrg builtin_define_std ("LANGUAGE_C"); \ 64610d565efSmrg builtin_define ("_LANGUAGE_C"); \ 64710d565efSmrg } \ 64810d565efSmrg \ 64910d565efSmrg if (mips_abi == ABI_EABI) \ 65010d565efSmrg builtin_define ("__mips_eabi"); \ 65110d565efSmrg \ 65210d565efSmrg if (TARGET_CACHE_BUILTIN) \ 65310d565efSmrg builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ 65410d565efSmrg if (!ISA_HAS_LXC1_SXC1) \ 65510d565efSmrg builtin_define ("__mips_no_lxc1_sxc1"); \ 65610d565efSmrg if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \ 65710d565efSmrg builtin_define ("__mips_no_madd4"); \ 65810d565efSmrg } \ 65910d565efSmrg while (0) 66010d565efSmrg 6610fc04c29Smrg /* Target CPU versions for D. */ 6620fc04c29Smrg #define TARGET_D_CPU_VERSIONS mips_d_target_versions 6630fc04c29Smrg 66410d565efSmrg /* Default target_flags if no switches are specified */ 66510d565efSmrg 66610d565efSmrg #ifndef TARGET_DEFAULT 66710d565efSmrg #define TARGET_DEFAULT 0 66810d565efSmrg #endif 66910d565efSmrg 67010d565efSmrg #ifndef TARGET_CPU_DEFAULT 67110d565efSmrg #define TARGET_CPU_DEFAULT 0 67210d565efSmrg #endif 67310d565efSmrg 67410d565efSmrg #ifndef TARGET_ENDIAN_DEFAULT 67510d565efSmrg #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 67610d565efSmrg #endif 67710d565efSmrg 67810d565efSmrg #ifdef IN_LIBGCC2 67910d565efSmrg #undef TARGET_64BIT 68010d565efSmrg /* Make this compile time constant for libgcc2 */ 68110d565efSmrg #ifdef __mips64 68210d565efSmrg #define TARGET_64BIT 1 68310d565efSmrg #else 68410d565efSmrg #define TARGET_64BIT 0 68510d565efSmrg #endif 68610d565efSmrg #endif /* IN_LIBGCC2 */ 68710d565efSmrg 68810d565efSmrg /* Force the call stack unwinders in unwind.inc not to be MIPS16 code 68910d565efSmrg when compiled with hardware floating point. This is because MIPS16 69010d565efSmrg code cannot save and restore the floating-point registers, which is 69110d565efSmrg important if in a mixed MIPS16/non-MIPS16 environment. */ 69210d565efSmrg 69310d565efSmrg #ifdef IN_LIBGCC2 69410d565efSmrg #if __mips_hard_float 69510d565efSmrg #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) 69610d565efSmrg #endif 69710d565efSmrg #endif /* IN_LIBGCC2 */ 69810d565efSmrg 69910d565efSmrg #define TARGET_LIBGCC_SDATA_SECTION ".sdata" 70010d565efSmrg 70110d565efSmrg #ifndef MULTILIB_ENDIAN_DEFAULT 70210d565efSmrg #if TARGET_ENDIAN_DEFAULT == 0 70310d565efSmrg #define MULTILIB_ENDIAN_DEFAULT "EL" 70410d565efSmrg #else 70510d565efSmrg #define MULTILIB_ENDIAN_DEFAULT "EB" 70610d565efSmrg #endif 70710d565efSmrg #endif 70810d565efSmrg 70910d565efSmrg #ifndef MULTILIB_ISA_DEFAULT 71010d565efSmrg #if MIPS_ISA_DEFAULT == 1 71110d565efSmrg #define MULTILIB_ISA_DEFAULT "mips1" 71210d565efSmrg #elif MIPS_ISA_DEFAULT == 2 71310d565efSmrg #define MULTILIB_ISA_DEFAULT "mips2" 71410d565efSmrg #elif MIPS_ISA_DEFAULT == 3 71510d565efSmrg #define MULTILIB_ISA_DEFAULT "mips3" 71610d565efSmrg #elif MIPS_ISA_DEFAULT == 4 71710d565efSmrg #define MULTILIB_ISA_DEFAULT "mips4" 71810d565efSmrg #elif MIPS_ISA_DEFAULT == 32 71910d565efSmrg #define MULTILIB_ISA_DEFAULT "mips32" 72010d565efSmrg #elif MIPS_ISA_DEFAULT == 33 72110d565efSmrg #define MULTILIB_ISA_DEFAULT "mips32r2" 72210d565efSmrg #elif MIPS_ISA_DEFAULT == 37 72310d565efSmrg #define MULTILIB_ISA_DEFAULT "mips32r6" 72410d565efSmrg #elif MIPS_ISA_DEFAULT == 64 72510d565efSmrg #define MULTILIB_ISA_DEFAULT "mips64" 72610d565efSmrg #elif MIPS_ISA_DEFAULT == 65 72710d565efSmrg #define MULTILIB_ISA_DEFAULT "mips64r2" 72810d565efSmrg #elif MIPS_ISA_DEFAULT == 69 72910d565efSmrg #define MULTILIB_ISA_DEFAULT "mips64r6" 73010d565efSmrg #else 73110d565efSmrg #define MULTILIB_ISA_DEFAULT "mips1" 73210d565efSmrg #endif 73310d565efSmrg #endif 73410d565efSmrg 73510d565efSmrg #ifndef MIPS_ABI_DEFAULT 73610d565efSmrg #define MIPS_ABI_DEFAULT ABI_32 73710d565efSmrg #endif 73810d565efSmrg 73910d565efSmrg /* Use the most portable ABI flag for the ASM specs. */ 74010d565efSmrg 74110d565efSmrg #if MIPS_ABI_DEFAULT == ABI_32 74210d565efSmrg #define MULTILIB_ABI_DEFAULT "mabi=32" 74310d565efSmrg #elif MIPS_ABI_DEFAULT == ABI_O64 74410d565efSmrg #define MULTILIB_ABI_DEFAULT "mabi=o64" 74510d565efSmrg #elif MIPS_ABI_DEFAULT == ABI_N32 74610d565efSmrg #define MULTILIB_ABI_DEFAULT "mabi=n32" 74710d565efSmrg #elif MIPS_ABI_DEFAULT == ABI_64 74810d565efSmrg #define MULTILIB_ABI_DEFAULT "mabi=64" 74910d565efSmrg #elif MIPS_ABI_DEFAULT == ABI_EABI 75010d565efSmrg #define MULTILIB_ABI_DEFAULT "mabi=eabi" 75110d565efSmrg #endif 75210d565efSmrg 75310d565efSmrg #ifndef MULTILIB_DEFAULTS 75410d565efSmrg #define MULTILIB_DEFAULTS \ 75510d565efSmrg { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 75610d565efSmrg #endif 75710d565efSmrg 75810d565efSmrg /* We must pass -EL to the linker by default for little endian embedded 75910d565efSmrg targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 76010d565efSmrg linker will default to using big-endian output files. The OUTPUT_FORMAT 76110d565efSmrg line must be in the linker script, otherwise -EB/-EL will not work. */ 76210d565efSmrg 76310d565efSmrg #ifndef ENDIAN_SPEC 76410d565efSmrg #if TARGET_ENDIAN_DEFAULT == 0 76510d565efSmrg #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 76610d565efSmrg #else 76710d565efSmrg #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 76810d565efSmrg #endif 76910d565efSmrg #endif 77010d565efSmrg 77110d565efSmrg /* A spec condition that matches all non-mips16 -mips arguments. */ 77210d565efSmrg 77310d565efSmrg #define MIPS_ISA_LEVEL_OPTION_SPEC \ 77410d565efSmrg "mips1|mips2|mips3|mips4|mips32*|mips64*" 77510d565efSmrg 77610d565efSmrg /* A spec condition that matches all non-mips16 architecture arguments. */ 77710d565efSmrg 77810d565efSmrg #define MIPS_ARCH_OPTION_SPEC \ 77910d565efSmrg MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" 78010d565efSmrg 78110d565efSmrg /* A spec that infers a -mips argument from an -march argument. */ 78210d565efSmrg 78310d565efSmrg #define MIPS_ISA_LEVEL_SPEC \ 78410d565efSmrg "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ 78510d565efSmrg %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ 78610d565efSmrg %{march=mips2|march=r6000:-mips2} \ 78710d565efSmrg %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ 78810d565efSmrg %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ 78910d565efSmrg |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ 79010d565efSmrg %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ 79110d565efSmrg %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ 79210d565efSmrg |march=34k*|march=74k*|march=m14k*|march=1004k* \ 79310d565efSmrg |march=interaptiv: -mips32r2} \ 79410d565efSmrg %{march=mips32r3: -mips32r3} \ 79510d565efSmrg %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ 79610d565efSmrg %{march=mips32r6: -mips32r6} \ 79710d565efSmrg %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ 79810d565efSmrg |march=xlr: -mips64} \ 7990fc04c29Smrg %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ 8000fc04c29Smrg |march=octeon|march=xlp: -mips64r2} \ 80110d565efSmrg %{march=mips64r3: -mips64r3} \ 80210d565efSmrg %{march=mips64r5: -mips64r5} \ 8030fc04c29Smrg %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" 80410d565efSmrg 80510d565efSmrg /* A spec that injects the default multilib ISA if no architecture is 80610d565efSmrg specified. */ 80710d565efSmrg 80810d565efSmrg #define MIPS_DEFAULT_ISA_LEVEL_SPEC \ 80910d565efSmrg "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ 81010d565efSmrg %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" 81110d565efSmrg 81210d565efSmrg /* A spec that infers a -mhard-float or -msoft-float setting from an 81310d565efSmrg -march argument. Note that soft-float and hard-float code are not 81410d565efSmrg link-compatible. */ 81510d565efSmrg 81610d565efSmrg #define MIPS_ARCH_FLOAT_SPEC \ 81710d565efSmrg "%{mhard-float|msoft-float|mno-float|march=mips*:; \ 81810d565efSmrg march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ 81910d565efSmrg |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ 82010d565efSmrg |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ 82110d565efSmrg march=*: -mhard-float}" 82210d565efSmrg 82310d565efSmrg /* A spec condition that matches 32-bit options. It only works if 82410d565efSmrg MIPS_ISA_LEVEL_SPEC has been applied. */ 82510d565efSmrg 82610d565efSmrg #define MIPS_32BIT_OPTION_SPEC \ 82710d565efSmrg "mips1|mips2|mips32*|mgp32" 82810d565efSmrg 82910d565efSmrg /* A spec condition that matches architectures should be targeted with 83010d565efSmrg o32 FPXX for compatibility reasons. */ 83110d565efSmrg #define MIPS_FPXX_OPTION_SPEC \ 83210d565efSmrg "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \ 83310d565efSmrg mips64|mips64r2|mips64r3|mips64r5" 83410d565efSmrg 83510d565efSmrg /* Infer a -msynci setting from a -mips argument, on the assumption that 83610d565efSmrg -msynci is desired where possible. */ 83710d565efSmrg #define MIPS_ISA_SYNCI_SPEC \ 83810d565efSmrg "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \ 83910d565efSmrg |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}" 84010d565efSmrg 84110d565efSmrg /* Infer a -mnan=2008 setting from a -mips argument. */ 84210d565efSmrg #define MIPS_ISA_NAN2008_SPEC \ 84310d565efSmrg "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ 84410d565efSmrg %{!msoft-float:-mnan=2008}}" 84510d565efSmrg 84610d565efSmrg #if (MIPS_ABI_DEFAULT == ABI_O64 \ 84710d565efSmrg || MIPS_ABI_DEFAULT == ABI_N32 \ 84810d565efSmrg || MIPS_ABI_DEFAULT == ABI_64) 84910d565efSmrg #define OPT_ARCH64 "mabi=32|mgp32:;" 85010d565efSmrg #define OPT_ARCH32 "mabi=32|mgp32" 85110d565efSmrg #else 85210d565efSmrg #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" 85310d565efSmrg #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" 85410d565efSmrg #endif 85510d565efSmrg 85610d565efSmrg /* Support for a compile-time default CPU, et cetera. The rules are: 85710d565efSmrg --with-arch is ignored if -march is specified or a -mips is specified 85810d565efSmrg (other than -mips16); likewise --with-arch-32 and --with-arch-64. 85910d565efSmrg --with-tune is ignored if -mtune is specified; likewise 86010d565efSmrg --with-tune-32 and --with-tune-64. 86110d565efSmrg --with-abi is ignored if -mabi is specified. 86210d565efSmrg --with-float is ignored if -mhard-float or -msoft-float are 86310d565efSmrg specified. 86410d565efSmrg --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are 86510d565efSmrg specified. 86610d565efSmrg --with-nan is ignored if -mnan is specified. 86710d565efSmrg --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are 86810d565efSmrg specified. 86910d565efSmrg --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg 87010d565efSmrg or -mno-odd-spreg are specified. 87110d565efSmrg --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 87210d565efSmrg specified. */ 87310d565efSmrg #define OPTION_DEFAULT_SPECS \ 87410d565efSmrg {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ 87510d565efSmrg {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 87610d565efSmrg {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ 87710d565efSmrg {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 87810d565efSmrg {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 87910d565efSmrg {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ 88010d565efSmrg {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 88110d565efSmrg {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 88210d565efSmrg {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \ 88310d565efSmrg {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \ 88410d565efSmrg {"fp_32", "%{" OPT_ARCH32 \ 88510d565efSmrg ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \ 88610d565efSmrg {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \ 88710d565efSmrg "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \ 88810d565efSmrg {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ 88910d565efSmrg {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ 89010d565efSmrg {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ 89110d565efSmrg {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ 89210d565efSmrg {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \ 89310d565efSmrg {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \ 89410d565efSmrg 89510d565efSmrg /* A spec that infers the: 89610d565efSmrg -mnan=2008 setting from a -mips argument, 8970fc04c29Smrg -mdsp setting from a -march argument. 8980fc04c29Smrg -mloongson-mmi setting from a -march argument. */ 89910d565efSmrg #define BASE_DRIVER_SELF_SPECS \ 90010d565efSmrg MIPS_ISA_NAN2008_SPEC, \ 9010fc04c29Smrg MIPS_ASE_DSP_SPEC, \ 9020fc04c29Smrg MIPS_ASE_LOONGSON_MMI_SPEC, \ 9030fc04c29Smrg MIPS_ASE_LOONGSON_EXT_SPEC, \ 9040fc04c29Smrg MIPS_ASE_MSA_SPEC 9050fc04c29Smrg 9060fc04c29Smrg 9070fc04c29Smrg #define MIPS_ASE_DSP_SPEC \ 90810d565efSmrg "%{!mno-dsp: \ 90910d565efSmrg %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ 91010d565efSmrg |march=interaptiv: -mdsp} \ 91110d565efSmrg %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" 91210d565efSmrg 9130fc04c29Smrg #define MIPS_ASE_LOONGSON_MMI_SPEC \ 9140fc04c29Smrg "%{!mno-loongson-mmi: \ 9150fc04c29Smrg %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}" 9160fc04c29Smrg 9170fc04c29Smrg #define MIPS_ASE_LOONGSON_EXT_SPEC \ 9180fc04c29Smrg "%{!mno-loongson-ext: \ 9190fc04c29Smrg %{march=loongson3a|march=gs464: -mloongson-ext} \ 9200fc04c29Smrg %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \ 9210fc04c29Smrg -mloongson-ext2 -mloongson-ext}}}" 9220fc04c29Smrg 9230fc04c29Smrg #define MIPS_ASE_MSA_SPEC \ 9240fc04c29Smrg "%{!mno-msa: \ 9250fc04c29Smrg %{march=gs264e: -mmsa}}" 9260fc04c29Smrg 92710d565efSmrg #define DRIVER_SELF_SPECS \ 92810d565efSmrg MIPS_ISA_LEVEL_SPEC, \ 92910d565efSmrg BASE_DRIVER_SELF_SPECS 93010d565efSmrg 93110d565efSmrg #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 93210d565efSmrg && ISA_HAS_COND_TRAP) 93310d565efSmrg 93410d565efSmrg #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) 93510d565efSmrg 93610d565efSmrg /* True if the ABI can only work with 64-bit integer registers. We 93710d565efSmrg generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 93810d565efSmrg otherwise floating-point registers must also be 64-bit. */ 93910d565efSmrg #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 94010d565efSmrg 94110d565efSmrg /* Likewise for 32-bit regs. */ 94210d565efSmrg #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 94310d565efSmrg 94410d565efSmrg /* True if the file format uses 64-bit symbols. At present, this is 94510d565efSmrg only true for n64, which uses 64-bit ELF. */ 94610d565efSmrg #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) 94710d565efSmrg 94810d565efSmrg /* True if symbols are 64 bits wide. This is usually determined by 94910d565efSmrg the ABI's file format, but it can be overridden by -msym32. Note that 95010d565efSmrg overriding the size with -msym32 changes the ABI of relocatable objects, 95110d565efSmrg although it doesn't change the ABI of a fully-linked object. */ 95210d565efSmrg #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \ 95310d565efSmrg && Pmode == DImode \ 95410d565efSmrg && !TARGET_SYM32) 95510d565efSmrg 95610d565efSmrg /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ 95710d565efSmrg #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 95810d565efSmrg || ISA_MIPS4 \ 95910d565efSmrg || ISA_MIPS64 \ 96010d565efSmrg || ISA_MIPS64R2 \ 96110d565efSmrg || ISA_MIPS64R3 \ 96210d565efSmrg || ISA_MIPS64R5 \ 96310d565efSmrg || ISA_MIPS64R6) 96410d565efSmrg 96510d565efSmrg #define ISA_HAS_JR (mips_isa_rev <= 5) 96610d565efSmrg 96710d565efSmrg #define ISA_HAS_DELAY_SLOTS 1 96810d565efSmrg 96910d565efSmrg #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6) 97010d565efSmrg 97110d565efSmrg /* ISA has branch likely instructions (e.g. mips2). */ 97210d565efSmrg /* Disable branchlikely for tx39 until compare rewrite. They haven't 97310d565efSmrg been generated up to this point. */ 97410d565efSmrg #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5) 97510d565efSmrg 97610d565efSmrg /* ISA has 32 single-precision registers. */ 97710d565efSmrg #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ 9780fc04c29Smrg && !TARGET_GS464) \ 97910d565efSmrg || TARGET_FLOAT64 \ 98010d565efSmrg || TARGET_MIPS5900) 98110d565efSmrg 98210d565efSmrg /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ 98310d565efSmrg #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ 98410d565efSmrg || TARGET_MIPS5400 \ 98510d565efSmrg || TARGET_MIPS5500 \ 98610d565efSmrg || TARGET_MIPS5900 \ 98710d565efSmrg || TARGET_MIPS7000 \ 98810d565efSmrg || TARGET_MIPS9000 \ 98910d565efSmrg || TARGET_MAD \ 99010d565efSmrg || (mips_isa_rev >= 1 \ 99110d565efSmrg && mips_isa_rev <= 5)) \ 99210d565efSmrg && !TARGET_MIPS16) 99310d565efSmrg 99410d565efSmrg /* ISA has a three-operand multiplication instruction. */ 99510d565efSmrg #define ISA_HAS_DMUL3 (TARGET_64BIT \ 99610d565efSmrg && TARGET_OCTEON \ 99710d565efSmrg && !TARGET_MIPS16) 99810d565efSmrg 99910d565efSmrg /* ISA has HI and LO registers. */ 100010d565efSmrg #define ISA_HAS_HILO (mips_isa_rev <= 5) 100110d565efSmrg 100210d565efSmrg /* ISA supports instructions DMULT and DMULTU. */ 100310d565efSmrg #define ISA_HAS_DMULT (TARGET_64BIT \ 100410d565efSmrg && !TARGET_MIPS5900 \ 100510d565efSmrg && mips_isa_rev <= 5) 100610d565efSmrg 100710d565efSmrg /* ISA supports instructions MULT and MULTU. */ 100810d565efSmrg #define ISA_HAS_MULT (mips_isa_rev <= 5) 100910d565efSmrg 101010d565efSmrg /* ISA supports instructions MUL, MULU, MUH, MUHU. */ 101110d565efSmrg #define ISA_HAS_R6MUL (mips_isa_rev >= 6) 101210d565efSmrg 101310d565efSmrg /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */ 101410d565efSmrg #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6) 101510d565efSmrg 101610d565efSmrg /* For Loongson, it is preferable to use the Loongson-specific division and 101710d565efSmrg modulo instructions instead of the regular (D)DIV(U) instruction, 101810d565efSmrg because the former are faster and can also have the effect of reducing 101910d565efSmrg code size. */ 102010d565efSmrg #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ 10210fc04c29Smrg || TARGET_GS464) \ 102210d565efSmrg && !TARGET_MIPS16) 102310d565efSmrg 102410d565efSmrg /* ISA supports instructions DDIV and DDIVU. */ 102510d565efSmrg #define ISA_HAS_DDIV (TARGET_64BIT \ 102610d565efSmrg && !TARGET_MIPS5900 \ 102710d565efSmrg && !ISA_AVOID_DIV_HILO \ 102810d565efSmrg && mips_isa_rev <= 5) 102910d565efSmrg 103010d565efSmrg /* ISA supports instructions DIV and DIVU. 103110d565efSmrg This is always true, but the macro is needed for ISA_HAS_<D>DIV 103210d565efSmrg in mips.md. */ 103310d565efSmrg #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \ 103410d565efSmrg && mips_isa_rev <= 5) 103510d565efSmrg 103610d565efSmrg /* ISA supports instructions DIV, DIVU, MOD and MODU. */ 103710d565efSmrg #define ISA_HAS_R6DIV (mips_isa_rev >= 6) 103810d565efSmrg 103910d565efSmrg /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */ 104010d565efSmrg #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6) 104110d565efSmrg 104210d565efSmrg /* ISA has the floating-point conditional move instructions introduced 104310d565efSmrg in mips4. */ 104410d565efSmrg #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ 104510d565efSmrg || (mips_isa_rev >= 1 \ 104610d565efSmrg && mips_isa_rev <= 5)) \ 104710d565efSmrg && !TARGET_MIPS5500 \ 104810d565efSmrg && !TARGET_MIPS16) 104910d565efSmrg 105010d565efSmrg /* ISA has the integer conditional move instructions introduced in mips4 and 105110d565efSmrg ST Loongson 2E/2F. */ 105210d565efSmrg #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ 105310d565efSmrg || TARGET_MIPS5900 \ 105410d565efSmrg || TARGET_LOONGSON_2EF) 105510d565efSmrg 105610d565efSmrg /* ISA has LDC1 and SDC1. */ 105710d565efSmrg #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \ 105810d565efSmrg && !TARGET_MIPS5900 \ 105910d565efSmrg && !TARGET_MIPS16) 106010d565efSmrg 106110d565efSmrg /* ISA has the mips4 FP condition code instructions: FP-compare to CC, 106210d565efSmrg branch on CC, and move (both FP and non-FP) on CC. */ 106310d565efSmrg #define ISA_HAS_8CC (ISA_MIPS4 \ 106410d565efSmrg || (mips_isa_rev >= 1 \ 106510d565efSmrg && mips_isa_rev <= 5)) 106610d565efSmrg 106710d565efSmrg /* ISA has the FP condition code instructions that store the flag in an 106810d565efSmrg FP register. */ 106910d565efSmrg #define ISA_HAS_CCF (mips_isa_rev >= 6) 107010d565efSmrg 107110d565efSmrg #define ISA_HAS_SEL (mips_isa_rev >= 6) 107210d565efSmrg 107310d565efSmrg /* This is a catch all for other mips4 instructions: indexed load, the 107410d565efSmrg FP madd and msub instructions, and the FP recip and recip sqrt 107510d565efSmrg instructions. Note that this macro should only be used by other 107610d565efSmrg ISA_HAS_* macros. */ 107710d565efSmrg #define ISA_HAS_FP4 ((ISA_MIPS4 \ 107810d565efSmrg || ISA_MIPS64 \ 107910d565efSmrg || (mips_isa_rev >= 2 \ 108010d565efSmrg && mips_isa_rev <= 5)) \ 108110d565efSmrg && !TARGET_MIPS16) 108210d565efSmrg 108310d565efSmrg /* ISA has floating-point indexed load and store instructions 108410d565efSmrg (LWXC1, LDXC1, SWXC1 and SDXC1). */ 108510d565efSmrg #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ 108610d565efSmrg && mips_lxc1_sxc1) 108710d565efSmrg 108810d565efSmrg /* ISA has paired-single instructions. */ 108910d565efSmrg #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ 109010d565efSmrg || (mips_isa_rev >= 2 \ 109110d565efSmrg && mips_isa_rev <= 5)) \ 109210d565efSmrg && !TARGET_OCTEON) 109310d565efSmrg 109410d565efSmrg /* ISA has conditional trap instructions. */ 109510d565efSmrg #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 109610d565efSmrg && !TARGET_MIPS16) 109710d565efSmrg 109810d565efSmrg /* ISA has conditional trap with immediate instructions. */ 109910d565efSmrg #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \ 110010d565efSmrg && mips_isa_rev <= 5 \ 110110d565efSmrg && !TARGET_MIPS16) 110210d565efSmrg 110310d565efSmrg /* ISA has integer multiply-accumulate instructions, madd and msub. */ 110410d565efSmrg #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \ 110510d565efSmrg && mips_isa_rev <= 5) 110610d565efSmrg 110710d565efSmrg /* Integer multiply-accumulate instructions should be generated. */ 110810d565efSmrg #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) 110910d565efSmrg 111010d565efSmrg /* ISA has 4 operand fused madd instructions of the form 111110d565efSmrg 'd = [+-] (a * b [+-] c)'. */ 111210d565efSmrg #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ 111310d565efSmrg && (TARGET_MIPS8000 \ 11140fc04c29Smrg || TARGET_GS464 \ 11150fc04c29Smrg || TARGET_GS464E \ 11160fc04c29Smrg || TARGET_GS264E)) 111710d565efSmrg 111810d565efSmrg /* ISA has 4 operand unfused madd instructions of the form 111910d565efSmrg 'd = [+-] (a * b [+-] c)'. */ 112010d565efSmrg #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ 112110d565efSmrg && ISA_HAS_FP4 \ 112210d565efSmrg && !TARGET_MIPS8000 \ 11230fc04c29Smrg && !TARGET_GS464 \ 11240fc04c29Smrg && !TARGET_GS464E \ 11250fc04c29Smrg && !TARGET_GS264E) 112610d565efSmrg 112710d565efSmrg /* ISA has 3 operand r6 fused madd instructions of the form 112810d565efSmrg 'c = c [+-] (a * b)'. */ 112910d565efSmrg #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6) 113010d565efSmrg 113110d565efSmrg /* ISA has 3 operand loongson fused madd instructions of the form 113210d565efSmrg 'c = [+-] (a * b [+-] c)'. */ 113310d565efSmrg #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF 113410d565efSmrg 113510d565efSmrg /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The 113610d565efSmrg MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when 113710d565efSmrg doubles are stored in pairs of FPRs, so for safety's sake, we apply 113810d565efSmrg this restriction to the MIPS IV ISA too. */ 113910d565efSmrg #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ 114010d565efSmrg (((ISA_HAS_FP4 \ 114110d565efSmrg && ((MODE) == SFmode \ 114210d565efSmrg || ((TARGET_FLOAT64 \ 114310d565efSmrg || mips_isa_rev >= 2) \ 114410d565efSmrg && (MODE) == DFmode))) \ 114510d565efSmrg || (((MODE) == SFmode \ 114610d565efSmrg || (MODE) == DFmode) \ 114710d565efSmrg && (mips_isa_rev >= 6)) \ 114810d565efSmrg || (TARGET_SB1 \ 114910d565efSmrg && (MODE) == V2SFmode)) \ 115010d565efSmrg && !TARGET_MIPS16) 115110d565efSmrg 115210d565efSmrg #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) 115310d565efSmrg 115410d565efSmrg #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) 115510d565efSmrg 115610d565efSmrg #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2) 115710d565efSmrg 115810d565efSmrg /* ISA has count leading zeroes/ones instruction (not implemented). */ 115910d565efSmrg #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) 116010d565efSmrg 11610fc04c29Smrg /* ISA has count trailing zeroes/ones instruction. */ 11620fc04c29Smrg #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) 11630fc04c29Smrg 116410d565efSmrg /* ISA has three operand multiply instructions that put 116510d565efSmrg the high part in an accumulator: mulhi or mulhiu. */ 116610d565efSmrg #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ 116710d565efSmrg || TARGET_MIPS5500 \ 116810d565efSmrg || TARGET_SR71K) \ 116910d565efSmrg && !TARGET_MIPS16) 117010d565efSmrg 117110d565efSmrg /* ISA has three operand multiply instructions that negate the 117210d565efSmrg result and put the result in an accumulator. */ 117310d565efSmrg #define ISA_HAS_MULS ((TARGET_MIPS5400 \ 117410d565efSmrg || TARGET_MIPS5500 \ 117510d565efSmrg || TARGET_SR71K) \ 117610d565efSmrg && !TARGET_MIPS16) 117710d565efSmrg 117810d565efSmrg /* ISA has three operand multiply instructions that subtract the 117910d565efSmrg result from a 4th operand and put the result in an accumulator. */ 118010d565efSmrg #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ 118110d565efSmrg || TARGET_MIPS5500 \ 118210d565efSmrg || TARGET_SR71K) \ 118310d565efSmrg && !TARGET_MIPS16) 118410d565efSmrg 118510d565efSmrg /* ISA has three operand multiply instructions that add the result 118610d565efSmrg to a 4th operand and put the result in an accumulator. */ 118710d565efSmrg #define ISA_HAS_MACC ((TARGET_MIPS4120 \ 118810d565efSmrg || TARGET_MIPS4130 \ 118910d565efSmrg || TARGET_MIPS5400 \ 119010d565efSmrg || TARGET_MIPS5500 \ 119110d565efSmrg || TARGET_SR71K) \ 119210d565efSmrg && !TARGET_MIPS16) 119310d565efSmrg 119410d565efSmrg /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 119510d565efSmrg #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ 119610d565efSmrg || TARGET_MIPS4130) \ 119710d565efSmrg && !TARGET_MIPS16) 119810d565efSmrg 119910d565efSmrg /* ISA has the "ror" (rotate right) instructions. */ 120010d565efSmrg #define ISA_HAS_ROR ((mips_isa_rev >= 2 \ 120110d565efSmrg || TARGET_MIPS5400 \ 120210d565efSmrg || TARGET_MIPS5500 \ 120310d565efSmrg || TARGET_SR71K \ 120410d565efSmrg || TARGET_SMARTMIPS) \ 120510d565efSmrg && !TARGET_MIPS16) 120610d565efSmrg 120710d565efSmrg /* ISA has the WSBH (word swap bytes within halfwords) instruction. 120810d565efSmrg 64-bit targets also provide DSBH and DSHD. */ 120910d565efSmrg #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16) 121010d565efSmrg 121110d565efSmrg /* ISA has data prefetch instructions. This controls use of 'pref'. */ 121210d565efSmrg #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 121310d565efSmrg || TARGET_LOONGSON_2EF \ 121410d565efSmrg || TARGET_MIPS5900 \ 121510d565efSmrg || mips_isa_rev >= 1) \ 121610d565efSmrg && !TARGET_MIPS16) 121710d565efSmrg 121810d565efSmrg /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ 121910d565efSmrg #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) 122010d565efSmrg 122110d565efSmrg /* ISA has data indexed prefetch instructions. This controls use of 122210d565efSmrg 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 122310d565efSmrg (prefx is a cop1x instruction, so can only be used if FP is 122410d565efSmrg enabled.) */ 12250fc04c29Smrg #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ 12260fc04c29Smrg || TARGET_LOONGSON_EXT \ 12270fc04c29Smrg || TARGET_LOONGSON_EXT2) 122810d565efSmrg 122910d565efSmrg /* True if trunc.w.s and trunc.w.d are real (not synthetic) 123010d565efSmrg instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 123110d565efSmrg also requires TARGET_DOUBLE_FLOAT. */ 123210d565efSmrg #define ISA_HAS_TRUNC_W (!ISA_MIPS1) 123310d565efSmrg 123410d565efSmrg /* ISA includes the MIPS32r2 seb and seh instructions. */ 123510d565efSmrg #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16) 123610d565efSmrg 123710d565efSmrg /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 123810d565efSmrg #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16) 123910d565efSmrg 124010d565efSmrg /* ISA has instructions for accessing top part of 64-bit fp regs. */ 124110d565efSmrg #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \ 124210d565efSmrg && mips_isa_rev >= 2) 124310d565efSmrg 124410d565efSmrg /* ISA has lwxs instruction (load w/scaled index address. */ 124510d565efSmrg #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ 124610d565efSmrg && !TARGET_MIPS16) 124710d565efSmrg 124810d565efSmrg /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ 124910d565efSmrg #define ISA_HAS_LBX (TARGET_OCTEON2) 125010d565efSmrg #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2) 125110d565efSmrg #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2) 125210d565efSmrg #define ISA_HAS_LHUX (TARGET_OCTEON2) 125310d565efSmrg #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2) 125410d565efSmrg #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT) 125510d565efSmrg #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \ 125610d565efSmrg && TARGET_64BIT) 125710d565efSmrg 125810d565efSmrg /* The DSP ASE is available. */ 125910d565efSmrg #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) 126010d565efSmrg 126110d565efSmrg /* Revision 2 of the DSP ASE is available. */ 126210d565efSmrg #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) 126310d565efSmrg 126410d565efSmrg /* The MSA ASE is available. */ 126510d565efSmrg #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) 126610d565efSmrg 126710d565efSmrg /* True if the result of a load is not available to the next instruction. 126810d565efSmrg A nop will then be needed between instructions like "lw $4,..." 126910d565efSmrg and "addiu $4,$4,1". */ 127010d565efSmrg #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ 127110d565efSmrg && !TARGET_MIPS3900 \ 127210d565efSmrg && !TARGET_MIPS5900 \ 127310d565efSmrg && !TARGET_MIPS16 \ 127410d565efSmrg && !TARGET_MICROMIPS) 127510d565efSmrg 127610d565efSmrg /* Likewise mtc1 and mfc1. */ 127710d565efSmrg #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ 127810d565efSmrg && !TARGET_MIPS5900 \ 127910d565efSmrg && !TARGET_LOONGSON_2EF) 128010d565efSmrg 128110d565efSmrg /* Likewise floating-point comparisons. */ 128210d565efSmrg #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \ 128310d565efSmrg && !TARGET_MIPS5900 \ 128410d565efSmrg && !TARGET_LOONGSON_2EF) 128510d565efSmrg 128610d565efSmrg /* True if mflo and mfhi can be immediately followed by instructions 128710d565efSmrg which write to the HI and LO registers. 128810d565efSmrg 128910d565efSmrg According to MIPS specifications, MIPS ISAs I, II, and III need 129010d565efSmrg (at least) two instructions between the reads of HI/LO and 129110d565efSmrg instructions which write them, and later ISAs do not. Contradicting 129210d565efSmrg the MIPS specifications, some MIPS IV processor user manuals (e.g. 129310d565efSmrg the UM for the NEC Vr5000) document needing the instructions between 129410d565efSmrg HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 129510d565efSmrg MIPS64 and later ISAs to have the interlocks, plus any specific 129610d565efSmrg earlier-ISA CPUs for which CPU documentation declares that the 129710d565efSmrg instructions are really interlocked. */ 129810d565efSmrg #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \ 129910d565efSmrg || TARGET_MIPS5500 \ 130010d565efSmrg || TARGET_MIPS5900 \ 130110d565efSmrg || TARGET_LOONGSON_2EF) 130210d565efSmrg 130310d565efSmrg /* ISA includes synci, jr.hb and jalr.hb. */ 130410d565efSmrg #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) 130510d565efSmrg 130610d565efSmrg /* ISA includes sync. */ 130710d565efSmrg #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) 130810d565efSmrg #define GENERATE_SYNC \ 130910d565efSmrg (target_flags_explicit & MASK_LLSC \ 131010d565efSmrg ? TARGET_LLSC && !TARGET_MIPS16 \ 131110d565efSmrg : ISA_HAS_SYNC) 131210d565efSmrg 131310d565efSmrg /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC 131410d565efSmrg because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC 131510d565efSmrg instructions. */ 131610d565efSmrg #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16) 131710d565efSmrg #define GENERATE_LL_SC \ 131810d565efSmrg (target_flags_explicit & MASK_LLSC \ 131910d565efSmrg ? TARGET_LLSC && !TARGET_MIPS16 \ 132010d565efSmrg : ISA_HAS_LL_SC) 132110d565efSmrg 132210d565efSmrg #define ISA_HAS_SWAP (TARGET_XLP) 132310d565efSmrg #define ISA_HAS_LDADD (TARGET_XLP) 132410d565efSmrg 132510d565efSmrg /* ISA includes the baddu instruction. */ 132610d565efSmrg #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) 132710d565efSmrg 132810d565efSmrg /* ISA includes the bbit* instructions. */ 132910d565efSmrg #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) 133010d565efSmrg 133110d565efSmrg /* ISA includes the cins instruction. */ 133210d565efSmrg #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) 133310d565efSmrg 133410d565efSmrg /* ISA includes the exts instruction. */ 133510d565efSmrg #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) 133610d565efSmrg 133710d565efSmrg /* ISA includes the seq and sne instructions. */ 133810d565efSmrg #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) 133910d565efSmrg 134010d565efSmrg /* ISA includes the pop instruction. */ 134110d565efSmrg #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) 134210d565efSmrg 134310d565efSmrg /* The CACHE instruction is available in non-MIPS16 code. */ 134410d565efSmrg #define TARGET_CACHE_BUILTIN (mips_isa >= 3) 134510d565efSmrg 134610d565efSmrg /* The CACHE instruction is available. */ 134710d565efSmrg #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) 134810d565efSmrg 134910d565efSmrg /* Tell collect what flags to pass to nm. */ 135010d565efSmrg #ifndef NM_FLAGS 135110d565efSmrg #define NM_FLAGS "-Bn" 135210d565efSmrg #endif 135310d565efSmrg 135410d565efSmrg 135510d565efSmrg /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 135610d565efSmrg the assembler. It may be overridden by subtargets. 135710d565efSmrg 135810d565efSmrg Beginning with gas 2.13, -mdebug must be passed to correctly handle 135910d565efSmrg COFF debugging info. */ 136010d565efSmrg 136110d565efSmrg #ifndef SUBTARGET_ASM_DEBUGGING_SPEC 136210d565efSmrg #define SUBTARGET_ASM_DEBUGGING_SPEC "\ 136310d565efSmrg %{g} %{g0} %{g1} %{g2} %{g3} \ 136410d565efSmrg %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 136510d565efSmrg %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 1366c7a68eb7Smrg %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}" 136710d565efSmrg #endif 136810d565efSmrg 136910d565efSmrg /* FP_ASM_SPEC represents the floating-point options that must be passed 137010d565efSmrg to the assembler when FPXX support exists. Prior to that point the 137110d565efSmrg assembler could accept the options but were not required for 137210d565efSmrg correctness. We only add the options when absolutely necessary 137310d565efSmrg because passing -msoft-float to the assembler will cause it to reject 137410d565efSmrg all hard-float instructions which may require some user code to be 137510d565efSmrg updated. */ 137610d565efSmrg 137710d565efSmrg #ifdef HAVE_AS_DOT_MODULE 137810d565efSmrg #define FP_ASM_SPEC "\ 137910d565efSmrg %{mhard-float} %{msoft-float} \ 138010d565efSmrg %{msingle-float} %{mdouble-float}" 138110d565efSmrg #else 138210d565efSmrg #define FP_ASM_SPEC 138310d565efSmrg #endif 138410d565efSmrg 138510d565efSmrg /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 138610d565efSmrg overridden by subtargets. */ 138710d565efSmrg 138810d565efSmrg #ifndef SUBTARGET_ASM_SPEC 138910d565efSmrg #define SUBTARGET_ASM_SPEC "" 139010d565efSmrg #endif 139110d565efSmrg 139210d565efSmrg #undef ASM_SPEC 139310d565efSmrg #define ASM_SPEC "\ 139410d565efSmrg %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 139510d565efSmrg %{mips32*} %{mips64*} \ 139610d565efSmrg %{mips16} %{mno-mips16:-no-mips16} \ 139710d565efSmrg %{mmicromips} %{mno-micromips} \ 139810d565efSmrg %{mips3d} %{mno-mips3d:-no-mips3d} \ 139910d565efSmrg %{mdmx} %{mno-mdmx:-no-mdmx} \ 140010d565efSmrg %{mdsp} %{mno-dsp} \ 140110d565efSmrg %{mdspr2} %{mno-dspr2} \ 140210d565efSmrg %{mmcu} %{mno-mcu} \ 140310d565efSmrg %{meva} %{mno-eva} \ 140410d565efSmrg %{mvirt} %{mno-virt} \ 140510d565efSmrg %{mxpa} %{mno-xpa} \ 14060fc04c29Smrg %{mcrc} %{mno-crc} \ 14070fc04c29Smrg %{mginv} %{mno-ginv} \ 140810d565efSmrg %{mmsa} %{mno-msa} \ 14090fc04c29Smrg %{mloongson-mmi} %{mno-loongson-mmi} \ 14100fc04c29Smrg %{mloongson-ext} %{mno-loongson-ext} \ 14110fc04c29Smrg %{mloongson-ext2} %{mno-loongson-ext2} \ 141210d565efSmrg %{msmartmips} %{mno-smartmips} \ 141310d565efSmrg %{mmt} %{mno-mt} \ 14140fc04c29Smrg %{mfix-r5900} %{mno-fix-r5900} \ 141510d565efSmrg %{mfix-rm7000} %{mno-fix-rm7000} \ 141610d565efSmrg %{mfix-vr4120} %{mfix-vr4130} \ 141710d565efSmrg %{mfix-24k} \ 141810d565efSmrg %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ 141910d565efSmrg %(subtarget_asm_debugging_spec) \ 142010d565efSmrg %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ 142110d565efSmrg %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 142210d565efSmrg %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \ 142310d565efSmrg %{modd-spreg} %{mno-odd-spreg} \ 142410d565efSmrg %{mshared} %{mno-shared} \ 142510d565efSmrg %{msym32} %{mno-sym32} \ 142610d565efSmrg %{mtune=*}" \ 142710d565efSmrg FP_ASM_SPEC "\ 142810d565efSmrg %(subtarget_asm_spec)" 142910d565efSmrg 143010d565efSmrg /* Extra switches sometimes passed to the linker. */ 143110d565efSmrg 143210d565efSmrg #ifndef LINK_SPEC 143310d565efSmrg #define LINK_SPEC "\ 143410d565efSmrg %(endian_spec) \ 143510d565efSmrg %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ 143610d565efSmrg %{shared}" 143710d565efSmrg #endif /* LINK_SPEC defined */ 143810d565efSmrg 143910d565efSmrg 144010d565efSmrg /* Specs for the compiler proper */ 144110d565efSmrg 144210d565efSmrg /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 144310d565efSmrg overridden by subtargets. */ 144410d565efSmrg #ifndef SUBTARGET_CC1_SPEC 144510d565efSmrg #define SUBTARGET_CC1_SPEC "" 144610d565efSmrg #endif 144710d565efSmrg 144810d565efSmrg /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 144910d565efSmrg 145010d565efSmrg #undef CC1_SPEC 145110d565efSmrg #define CC1_SPEC "\ 145210d565efSmrg %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 145310d565efSmrg %(subtarget_cc1_spec)" 145410d565efSmrg 145510d565efSmrg /* Preprocessor specs. */ 145610d565efSmrg 145710d565efSmrg /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 145810d565efSmrg overridden by subtargets. */ 145910d565efSmrg #ifndef SUBTARGET_CPP_SPEC 146010d565efSmrg #define SUBTARGET_CPP_SPEC "" 146110d565efSmrg #endif 146210d565efSmrg 146310d565efSmrg #define CPP_SPEC "%(subtarget_cpp_spec)" 146410d565efSmrg 146510d565efSmrg /* This macro defines names of additional specifications to put in the specs 146610d565efSmrg that can be used in various specifications like CC1_SPEC. Its definition 146710d565efSmrg is an initializer with a subgrouping for each command option. 146810d565efSmrg 146910d565efSmrg Each subgrouping contains a string constant, that defines the 147010d565efSmrg specification name, and a string constant that used by the GCC driver 147110d565efSmrg program. 147210d565efSmrg 147310d565efSmrg Do not define this macro if it does not need to do anything. */ 147410d565efSmrg 147510d565efSmrg #define EXTRA_SPECS \ 147610d565efSmrg { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 147710d565efSmrg { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 147810d565efSmrg { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 147910d565efSmrg { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 148010d565efSmrg { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 148110d565efSmrg { "endian_spec", ENDIAN_SPEC }, \ 148210d565efSmrg SUBTARGET_EXTRA_SPECS 148310d565efSmrg 148410d565efSmrg #ifndef SUBTARGET_EXTRA_SPECS 148510d565efSmrg #define SUBTARGET_EXTRA_SPECS 148610d565efSmrg #endif 148710d565efSmrg 148810d565efSmrg #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 148910d565efSmrg #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 149010d565efSmrg 149110d565efSmrg #ifndef PREFERRED_DEBUGGING_TYPE 149210d565efSmrg #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 149310d565efSmrg #endif 149410d565efSmrg 149510d565efSmrg /* The size of DWARF addresses should be the same as the size of symbols 149610d565efSmrg in the target file format. They shouldn't depend on things like -msym32, 149710d565efSmrg because many DWARF consumers do not allow the mixture of address sizes 149810d565efSmrg that one would then get from linking -msym32 code with -msym64 code. 149910d565efSmrg 150010d565efSmrg Note that the default POINTER_SIZE test is not appropriate for MIPS. 150110d565efSmrg EABI64 has 64-bit pointers but uses 32-bit ELF. */ 150210d565efSmrg #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) 150310d565efSmrg 150410d565efSmrg /* By default, turn on GDB extensions. */ 150510d565efSmrg #define DEFAULT_GDB_EXTENSIONS 1 150610d565efSmrg 150710d565efSmrg /* Registers may have a prefix which can be ignored when matching 150810d565efSmrg user asm and register definitions. */ 150910d565efSmrg #ifndef REGISTER_PREFIX 151010d565efSmrg #define REGISTER_PREFIX "$" 151110d565efSmrg #endif 151210d565efSmrg 151310d565efSmrg /* Local compiler-generated symbols must have a prefix that the assembler 151410d565efSmrg understands. By default, this is $, although some targets (e.g., 151510d565efSmrg NetBSD-ELF) need to override this. */ 151610d565efSmrg 151710d565efSmrg #ifndef LOCAL_LABEL_PREFIX 151810d565efSmrg #define LOCAL_LABEL_PREFIX "$" 151910d565efSmrg #endif 152010d565efSmrg 152110d565efSmrg /* By default on the mips, external symbols do not have an underscore 152210d565efSmrg prepended, but some targets (e.g., NetBSD) require this. */ 152310d565efSmrg 152410d565efSmrg #ifndef USER_LABEL_PREFIX 152510d565efSmrg #define USER_LABEL_PREFIX "" 152610d565efSmrg #endif 152710d565efSmrg 152810d565efSmrg /* On Sun 4, this limit is 2048. We use 1500 to be safe, 152910d565efSmrg since the length can run past this up to a continuation point. */ 153010d565efSmrg #undef DBX_CONTIN_LENGTH 153110d565efSmrg #define DBX_CONTIN_LENGTH 1500 153210d565efSmrg 153310d565efSmrg /* How to renumber registers for dbx and gdb. */ 153410d565efSmrg #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] 153510d565efSmrg 153610d565efSmrg /* The mapping from gcc register number to DWARF 2 CFA column number. */ 153710d565efSmrg #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] 153810d565efSmrg 153910d565efSmrg /* The DWARF 2 CFA column which tracks the return address. */ 154010d565efSmrg #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 154110d565efSmrg 154210d565efSmrg /* Before the prologue, RA lives in r31. */ 154310d565efSmrg #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 154410d565efSmrg 154510d565efSmrg /* Describe how we implement __builtin_eh_return. */ 154610d565efSmrg #define EH_RETURN_DATA_REGNO(N) \ 154710d565efSmrg ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 154810d565efSmrg 154910d565efSmrg #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 155010d565efSmrg 155110d565efSmrg #define EH_USES(N) mips_eh_uses (N) 155210d565efSmrg 155310d565efSmrg /* Offsets recorded in opcodes are a multiple of this alignment factor. 155410d565efSmrg The default for this in 64-bit mode is 8, which causes problems with 155510d565efSmrg SFmode register saves. */ 155610d565efSmrg #define DWARF_CIE_DATA_ALIGNMENT -4 155710d565efSmrg 155810d565efSmrg /* Correct the offset of automatic variables and arguments. Note that 155910d565efSmrg the MIPS debug format wants all automatic variables and arguments 156010d565efSmrg to be in terms of the virtual frame pointer (stack pointer before 156110d565efSmrg any adjustment in the function), while the MIPS 3.0 linker wants 156210d565efSmrg the frame pointer to be the stack pointer after the initial 156310d565efSmrg adjustment. */ 156410d565efSmrg 156510d565efSmrg #define DEBUGGER_AUTO_OFFSET(X) \ 156610d565efSmrg mips_debugger_offset (X, (HOST_WIDE_INT) 0) 156710d565efSmrg #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 156810d565efSmrg mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 156910d565efSmrg 157010d565efSmrg /* Target machine storage layout */ 157110d565efSmrg 157210d565efSmrg #define BITS_BIG_ENDIAN 0 157310d565efSmrg #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 157410d565efSmrg #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 157510d565efSmrg 157610d565efSmrg #define MAX_BITS_PER_WORD 64 157710d565efSmrg 157810d565efSmrg /* Width of a word, in units (bytes). */ 157910d565efSmrg #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 158010d565efSmrg #ifndef IN_LIBGCC2 158110d565efSmrg #define MIN_UNITS_PER_WORD 4 158210d565efSmrg #endif 158310d565efSmrg 158410d565efSmrg /* Width of a MSA vector register in bytes. */ 158510d565efSmrg #define UNITS_PER_MSA_REG 16 158610d565efSmrg /* Width of a MSA vector register in bits. */ 158710d565efSmrg #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT) 158810d565efSmrg 158910d565efSmrg /* For MIPS, width of a floating point register. */ 159010d565efSmrg #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 159110d565efSmrg 159210d565efSmrg /* The number of consecutive floating-point registers needed to store the 159310d565efSmrg largest format supported by the FPU. */ 159410d565efSmrg #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 159510d565efSmrg 159610d565efSmrg /* The number of consecutive floating-point registers needed to store the 159710d565efSmrg smallest format supported by the FPU. */ 159810d565efSmrg #define MIN_FPRS_PER_FMT \ 159910d565efSmrg (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT) 160010d565efSmrg 160110d565efSmrg /* The largest size of value that can be held in floating-point 160210d565efSmrg registers and moved with a single instruction. */ 160310d565efSmrg #define UNITS_PER_HWFPVALUE \ 160410d565efSmrg (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) 160510d565efSmrg 160610d565efSmrg /* The largest size of value that can be held in floating-point 160710d565efSmrg registers. */ 160810d565efSmrg #define UNITS_PER_FPVALUE \ 160910d565efSmrg (TARGET_SOFT_FLOAT_ABI ? 0 \ 161010d565efSmrg : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 161110d565efSmrg : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 161210d565efSmrg 161310d565efSmrg /* The number of bytes in a double. */ 161410d565efSmrg #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 161510d565efSmrg 161610d565efSmrg /* Set the sizes of the core types. */ 161710d565efSmrg #define SHORT_TYPE_SIZE 16 161810d565efSmrg #define INT_TYPE_SIZE 32 161910d565efSmrg #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 162010d565efSmrg #define LONG_LONG_TYPE_SIZE 64 162110d565efSmrg 162210d565efSmrg #define FLOAT_TYPE_SIZE 32 162310d565efSmrg #define DOUBLE_TYPE_SIZE 64 162410d565efSmrg #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 162510d565efSmrg 162610d565efSmrg /* Define the sizes of fixed-point types. */ 162710d565efSmrg #define SHORT_FRACT_TYPE_SIZE 8 162810d565efSmrg #define FRACT_TYPE_SIZE 16 162910d565efSmrg #define LONG_FRACT_TYPE_SIZE 32 163010d565efSmrg #define LONG_LONG_FRACT_TYPE_SIZE 64 163110d565efSmrg 163210d565efSmrg #define SHORT_ACCUM_TYPE_SIZE 16 163310d565efSmrg #define ACCUM_TYPE_SIZE 32 163410d565efSmrg #define LONG_ACCUM_TYPE_SIZE 64 163510d565efSmrg /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC 163610d565efSmrg doesn't support 128-bit integers for MIPS32 currently. */ 163710d565efSmrg #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) 163810d565efSmrg 163910d565efSmrg /* long double is not a fixed mode, but the idea is that, if we 164010d565efSmrg support long double, we also want a 128-bit integer type. */ 164110d565efSmrg #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 164210d565efSmrg 164310d565efSmrg /* Width in bits of a pointer. */ 164410d565efSmrg #ifndef POINTER_SIZE 164510d565efSmrg #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 164610d565efSmrg #endif 164710d565efSmrg 164810d565efSmrg /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 164910d565efSmrg #define PARM_BOUNDARY BITS_PER_WORD 165010d565efSmrg 165110d565efSmrg /* Allocation boundary (in *bits*) for the code of a function. */ 165210d565efSmrg #define FUNCTION_BOUNDARY 32 165310d565efSmrg 165410d565efSmrg /* Alignment of field after `int : 0' in a structure. */ 165510d565efSmrg #define EMPTY_FIELD_BOUNDARY 32 165610d565efSmrg 165710d565efSmrg /* Every structure's size must be a multiple of this. */ 165810d565efSmrg /* 8 is observed right on a DECstation and on riscos 4.02. */ 165910d565efSmrg #define STRUCTURE_SIZE_BOUNDARY 8 166010d565efSmrg 166110d565efSmrg /* There is no point aligning anything to a rounder boundary than 166210d565efSmrg LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is 166310d565efSmrg BITS_PER_MSA_REG. */ 166410d565efSmrg #define BIGGEST_ALIGNMENT \ 166510d565efSmrg (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE) 166610d565efSmrg 166710d565efSmrg /* All accesses must be aligned. */ 166810d565efSmrg #define STRICT_ALIGNMENT 1 166910d565efSmrg 167010d565efSmrg /* Define this if you wish to imitate the way many other C compilers 167110d565efSmrg handle alignment of bitfields and the structures that contain 167210d565efSmrg them. 167310d565efSmrg 167410d565efSmrg The behavior is that the type written for a bit-field (`int', 167510d565efSmrg `short', or other integer type) imposes an alignment for the 167610d565efSmrg entire structure, as if the structure really did contain an 167710d565efSmrg ordinary field of that type. In addition, the bit-field is placed 167810d565efSmrg within the structure so that it would fit within such a field, 167910d565efSmrg not crossing a boundary for it. 168010d565efSmrg 168110d565efSmrg Thus, on most machines, a bit-field whose type is written as `int' 168210d565efSmrg would not cross a four-byte boundary, and would force four-byte 168310d565efSmrg alignment for the whole structure. (The alignment used may not 168410d565efSmrg be four bytes; it is controlled by the other alignment 168510d565efSmrg parameters.) 168610d565efSmrg 168710d565efSmrg If the macro is defined, its definition should be a C expression; 168810d565efSmrg a nonzero value for the expression enables this behavior. */ 168910d565efSmrg 169010d565efSmrg #define PCC_BITFIELD_TYPE_MATTERS 1 169110d565efSmrg 169210d565efSmrg /* If defined, a C expression to compute the alignment for a static 169310d565efSmrg variable. TYPE is the data type, and ALIGN is the alignment that 169410d565efSmrg the object would ordinarily have. The value of this macro is used 169510d565efSmrg instead of that alignment to align the object. 169610d565efSmrg 169710d565efSmrg If this macro is not defined, then ALIGN is used. 169810d565efSmrg 169910d565efSmrg One use of this macro is to increase alignment of medium-size 170010d565efSmrg data to make it all fit in fewer cache lines. Another is to 170110d565efSmrg cause character arrays to be word-aligned so that `strcpy' calls 170210d565efSmrg that copy constants to character arrays can be done inline. */ 170310d565efSmrg 170410d565efSmrg #undef DATA_ALIGNMENT 170510d565efSmrg #define DATA_ALIGNMENT(TYPE, ALIGN) \ 170610d565efSmrg ((((ALIGN) < BITS_PER_WORD) \ 170710d565efSmrg && (TREE_CODE (TYPE) == ARRAY_TYPE \ 170810d565efSmrg || TREE_CODE (TYPE) == UNION_TYPE \ 170910d565efSmrg || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 171010d565efSmrg 171110d565efSmrg /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 171210d565efSmrg character arrays to be word-aligned so that `strcpy' calls that copy 171310d565efSmrg constants to character arrays can be done inline, and 'strcmp' can be 171410d565efSmrg optimised to use word loads. */ 171510d565efSmrg #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 171610d565efSmrg DATA_ALIGNMENT (TYPE, ALIGN) 171710d565efSmrg 171810d565efSmrg #define PAD_VARARGS_DOWN \ 1719c7a68eb7Smrg (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 172010d565efSmrg 172110d565efSmrg /* Define if operations between registers always perform the operation 172210d565efSmrg on the full register even if a narrower mode is specified. */ 172310d565efSmrg #define WORD_REGISTER_OPERATIONS 1 172410d565efSmrg 172510d565efSmrg /* When in 64-bit mode, move insns will sign extend SImode and CCmode 172610d565efSmrg moves. All other references are zero extended. */ 172710d565efSmrg #define LOAD_EXTEND_OP(MODE) \ 172810d565efSmrg (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 172910d565efSmrg ? SIGN_EXTEND : ZERO_EXTEND) 173010d565efSmrg 173110d565efSmrg /* Define this macro if it is advisable to hold scalars in registers 173210d565efSmrg in a wider mode than that declared by the program. In such cases, 173310d565efSmrg the value is constrained to be within the bounds of the declared 173410d565efSmrg type, but kept valid in the wider mode. The signedness of the 173510d565efSmrg extension may differ from that of the type. */ 173610d565efSmrg 173710d565efSmrg #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 173810d565efSmrg if (GET_MODE_CLASS (MODE) == MODE_INT \ 173910d565efSmrg && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 174010d565efSmrg { \ 174110d565efSmrg if ((MODE) == SImode) \ 174210d565efSmrg (UNSIGNEDP) = 0; \ 174310d565efSmrg (MODE) = Pmode; \ 174410d565efSmrg } 174510d565efSmrg 174610d565efSmrg /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 174710d565efSmrg Extensions of pointers to word_mode must be signed. */ 174810d565efSmrg #define POINTERS_EXTEND_UNSIGNED false 174910d565efSmrg 175010d565efSmrg /* Define if loading short immediate values into registers sign extends. */ 175110d565efSmrg #define SHORT_IMMEDIATES_SIGN_EXTEND 1 175210d565efSmrg 175310d565efSmrg /* The [d]clz instructions have the natural values at 0. */ 175410d565efSmrg 175510d565efSmrg #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 175610d565efSmrg ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 175710d565efSmrg 175810d565efSmrg /* Standard register usage. */ 175910d565efSmrg 176010d565efSmrg /* Number of hardware registers. We have: 176110d565efSmrg 176210d565efSmrg - 32 integer registers 176310d565efSmrg - 32 floating point registers 176410d565efSmrg - 8 condition code registers 176510d565efSmrg - 2 accumulator registers (hi and lo) 176610d565efSmrg - 32 registers each for coprocessors 0, 2 and 3 176710d565efSmrg - 4 fake registers: 176810d565efSmrg - ARG_POINTER_REGNUM 176910d565efSmrg - FRAME_POINTER_REGNUM 177010d565efSmrg - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) 177110d565efSmrg - CPRESTORE_SLOT_REGNUM 177210d565efSmrg - 2 dummy entries that were used at various times in the past. 177310d565efSmrg - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 177410d565efSmrg - 6 DSP control registers */ 177510d565efSmrg 177610d565efSmrg #define FIRST_PSEUDO_REGISTER 188 177710d565efSmrg 177810d565efSmrg /* By default, fix the kernel registers ($26 and $27), the global 177910d565efSmrg pointer ($28) and the stack pointer ($29). This can change 178010d565efSmrg depending on the command-line options. 178110d565efSmrg 178210d565efSmrg Regarding coprocessor registers: without evidence to the contrary, 178310d565efSmrg it's best to assume that each coprocessor register has a unique 178410d565efSmrg use. This can be overridden, in, e.g., mips_option_override or 178510d565efSmrg TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be 178610d565efSmrg inappropriate for a particular target. */ 178710d565efSmrg 178810d565efSmrg #define FIXED_REGISTERS \ 178910d565efSmrg { \ 179010d565efSmrg 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 179110d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 179210d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 179310d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 179410d565efSmrg 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 179510d565efSmrg /* COP0 registers */ \ 179610d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 179710d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 179810d565efSmrg /* COP2 registers */ \ 179910d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 180010d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 180110d565efSmrg /* COP3 registers */ \ 180210d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 180310d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 180410d565efSmrg /* 6 DSP accumulator registers & 6 control registers */ \ 180510d565efSmrg 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 180610d565efSmrg } 180710d565efSmrg 180810d565efSmrg 180910d565efSmrg /* Set up this array for o32 by default. 181010d565efSmrg 181110d565efSmrg Note that we don't mark $31 as a call-clobbered register. The idea is 181210d565efSmrg that it's really the call instructions themselves which clobber $31. 181310d565efSmrg We don't care what the called function does with it afterwards. 181410d565efSmrg 181510d565efSmrg This approach makes it easier to implement sibcalls. Unlike normal 181610d565efSmrg calls, sibcalls don't clobber $31, so the register reaches the 181710d565efSmrg called function in tact. EPILOGUE_USES says that $31 is useful 181810d565efSmrg to the called function. */ 181910d565efSmrg 182010d565efSmrg #define CALL_REALLY_USED_REGISTERS \ 182110d565efSmrg { /* General registers. */ \ 182210d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 182310d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 182410d565efSmrg /* Floating-point registers. */ \ 182510d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 182610d565efSmrg 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 182710d565efSmrg /* Others. */ \ 182810d565efSmrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ 182910d565efSmrg /* COP0 registers */ \ 183010d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183110d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183210d565efSmrg /* COP2 registers */ \ 183310d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183410d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183510d565efSmrg /* COP3 registers */ \ 183610d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183710d565efSmrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 183810d565efSmrg /* 6 DSP accumulator registers & 6 control registers */ \ 183910d565efSmrg 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 184010d565efSmrg } 184110d565efSmrg 184210d565efSmrg /* Internal macros to classify a register number as to whether it's a 184310d565efSmrg general purpose register, a floating point register, a 184410d565efSmrg multiply/divide register, or a status register. */ 184510d565efSmrg 184610d565efSmrg #define GP_REG_FIRST 0 184710d565efSmrg #define GP_REG_LAST 31 184810d565efSmrg #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 184910d565efSmrg #define GP_DBX_FIRST 0 185010d565efSmrg #define K0_REG_NUM (GP_REG_FIRST + 26) 185110d565efSmrg #define K1_REG_NUM (GP_REG_FIRST + 27) 185210d565efSmrg #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) 185310d565efSmrg 185410d565efSmrg #define FP_REG_FIRST 32 185510d565efSmrg #define FP_REG_LAST 63 185610d565efSmrg #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 185710d565efSmrg #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 185810d565efSmrg 185910d565efSmrg #define MD_REG_FIRST 64 186010d565efSmrg #define MD_REG_LAST 65 186110d565efSmrg #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 186210d565efSmrg #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 186310d565efSmrg 186410d565efSmrg #define MSA_REG_FIRST FP_REG_FIRST 186510d565efSmrg #define MSA_REG_LAST FP_REG_LAST 186610d565efSmrg #define MSA_REG_NUM FP_REG_NUM 186710d565efSmrg 186810d565efSmrg /* The DWARF 2 CFA column which tracks the return address from a 186910d565efSmrg signal handler context. This means that to maintain backwards 187010d565efSmrg compatibility, no hard register can be assigned this column if it 187110d565efSmrg would need to be handled by the DWARF unwinder. */ 187210d565efSmrg #define DWARF_ALT_FRAME_RETURN_COLUMN 66 187310d565efSmrg 187410d565efSmrg #define ST_REG_FIRST 67 187510d565efSmrg #define ST_REG_LAST 74 187610d565efSmrg #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 187710d565efSmrg 187810d565efSmrg 187910d565efSmrg /* FIXME: renumber. */ 188010d565efSmrg #define COP0_REG_FIRST 80 188110d565efSmrg #define COP0_REG_LAST 111 188210d565efSmrg #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 188310d565efSmrg 188410d565efSmrg #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) 188510d565efSmrg #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) 188610d565efSmrg #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) 188710d565efSmrg 188810d565efSmrg #define COP2_REG_FIRST 112 188910d565efSmrg #define COP2_REG_LAST 143 189010d565efSmrg #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 189110d565efSmrg 189210d565efSmrg #define COP3_REG_FIRST 144 189310d565efSmrg #define COP3_REG_LAST 175 189410d565efSmrg #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 189510d565efSmrg 189610d565efSmrg /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */ 189710d565efSmrg #define ALL_COP_REG_FIRST COP0_REG_FIRST 189810d565efSmrg #define ALL_COP_REG_LAST COP3_REG_LAST 189910d565efSmrg #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1) 190010d565efSmrg 190110d565efSmrg #define DSP_ACC_REG_FIRST 176 190210d565efSmrg #define DSP_ACC_REG_LAST 181 190310d565efSmrg #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 190410d565efSmrg 190510d565efSmrg #define AT_REGNUM (GP_REG_FIRST + 1) 190610d565efSmrg #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) 190710d565efSmrg #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) 190810d565efSmrg 190910d565efSmrg /* A few bitfield locations for the coprocessor registers. */ 191010d565efSmrg /* Request Interrupt Priority Level is from bit 10 to bit 15 of 191110d565efSmrg the cause register for the EIC interrupt mode. */ 191210d565efSmrg #define CAUSE_IPL 10 191310d565efSmrg /* COP1 Enable is at bit 29 of the status register. */ 191410d565efSmrg #define SR_COP1 29 191510d565efSmrg /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ 191610d565efSmrg #define SR_IPL 10 191710d565efSmrg /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status 191810d565efSmrg register. */ 191910d565efSmrg #define SR_IM0 8 192010d565efSmrg /* Exception Level is at bit 1 of the status register. */ 192110d565efSmrg #define SR_EXL 1 192210d565efSmrg /* Interrupt Enable is at bit 0 of the status register. */ 192310d565efSmrg #define SR_IE 0 192410d565efSmrg 192510d565efSmrg /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 192610d565efSmrg If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 192710d565efSmrg should be used instead. */ 192810d565efSmrg #define FPSW_REGNUM ST_REG_FIRST 192910d565efSmrg 193010d565efSmrg #define GP_REG_P(REGNO) \ 193110d565efSmrg ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 193210d565efSmrg #define M16_REG_P(REGNO) \ 193310d565efSmrg (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 193410d565efSmrg #define M16STORE_REG_P(REGNO) \ 193510d565efSmrg (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17) 193610d565efSmrg #define FP_REG_P(REGNO) \ 193710d565efSmrg ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 193810d565efSmrg #define MD_REG_P(REGNO) \ 193910d565efSmrg ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 194010d565efSmrg #define ST_REG_P(REGNO) \ 194110d565efSmrg ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 194210d565efSmrg #define COP0_REG_P(REGNO) \ 194310d565efSmrg ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 194410d565efSmrg #define COP2_REG_P(REGNO) \ 194510d565efSmrg ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 194610d565efSmrg #define COP3_REG_P(REGNO) \ 194710d565efSmrg ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 194810d565efSmrg #define ALL_COP_REG_P(REGNO) \ 194910d565efSmrg ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 195010d565efSmrg /* Test if REGNO is one of the 6 new DSP accumulators. */ 195110d565efSmrg #define DSP_ACC_REG_P(REGNO) \ 195210d565efSmrg ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 195310d565efSmrg /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 195410d565efSmrg #define ACC_REG_P(REGNO) \ 195510d565efSmrg (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 195610d565efSmrg #define MSA_REG_P(REGNO) \ 195710d565efSmrg ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM) 195810d565efSmrg 195910d565efSmrg #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 196010d565efSmrg #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X))) 196110d565efSmrg 196210d565efSmrg /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 196310d565efSmrg to initialize the mips16 gp pseudo register. */ 196410d565efSmrg #define CONST_GP_P(X) \ 196510d565efSmrg (GET_CODE (X) == CONST \ 196610d565efSmrg && GET_CODE (XEXP (X, 0)) == UNSPEC \ 196710d565efSmrg && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 196810d565efSmrg 196910d565efSmrg /* Return coprocessor number from register number. */ 197010d565efSmrg 197110d565efSmrg #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 197210d565efSmrg (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 197310d565efSmrg : COP3_REG_P (REGNO) ? '3' : '?') 197410d565efSmrg 197510d565efSmrg 197610d565efSmrg #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 197710d565efSmrg mips_hard_regno_rename_ok (OLD_REG, NEW_REG) 197810d565efSmrg 197910d565efSmrg /* Select a register mode required for caller save of hard regno REGNO. */ 198010d565efSmrg #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 198110d565efSmrg mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE) 198210d565efSmrg 198310d565efSmrg /* Register to use for pushing function arguments. */ 198410d565efSmrg #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 198510d565efSmrg 198610d565efSmrg /* These two registers don't really exist: they get eliminated to either 198710d565efSmrg the stack or hard frame pointer. */ 198810d565efSmrg #define ARG_POINTER_REGNUM 77 198910d565efSmrg #define FRAME_POINTER_REGNUM 78 199010d565efSmrg 199110d565efSmrg /* $30 is not available on the mips16, so we use $17 as the frame 199210d565efSmrg pointer. */ 199310d565efSmrg #define HARD_FRAME_POINTER_REGNUM \ 199410d565efSmrg (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 199510d565efSmrg 199610d565efSmrg #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 199710d565efSmrg #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 199810d565efSmrg 199910d565efSmrg /* Register in which static-chain is passed to a function. */ 200010d565efSmrg #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) 200110d565efSmrg 200210d565efSmrg /* Registers used as temporaries in prologue/epilogue code: 200310d565efSmrg 200410d565efSmrg - If a MIPS16 PIC function needs access to _gp, it first loads 200510d565efSmrg the value into MIPS16_PIC_TEMP and then copies it to $gp. 200610d565efSmrg 200710d565efSmrg - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary 200810d565efSmrg register. The register must not conflict with MIPS16_PIC_TEMP. 200910d565efSmrg 201010d565efSmrg - If we aren't generating MIPS16 code, the prologue can also use 201110d565efSmrg MIPS_PROLOGUE_TEMP2 as a general temporary register. 201210d565efSmrg 201310d565efSmrg - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary 201410d565efSmrg register. 201510d565efSmrg 201610d565efSmrg If we're generating MIPS16 code, these registers must come from the 201710d565efSmrg core set of 8. The prologue registers mustn't conflict with any 201810d565efSmrg incoming arguments, the static chain pointer, or the frame pointer. 201910d565efSmrg The epilogue temporary mustn't conflict with the return registers, 202010d565efSmrg the PIC call register ($25), the frame pointer, the EH stack adjustment, 202110d565efSmrg or the EH data registers. 202210d565efSmrg 202310d565efSmrg If we're generating interrupt handlers, we use K0 as a temporary register 202410d565efSmrg in prologue/epilogue code. */ 202510d565efSmrg 202610d565efSmrg #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) 202710d565efSmrg #define MIPS_PROLOGUE_TEMP_REGNUM \ 202810d565efSmrg (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) 202910d565efSmrg #define MIPS_PROLOGUE_TEMP2_REGNUM \ 203010d565efSmrg (TARGET_MIPS16 \ 203110d565efSmrg ? (gcc_unreachable (), INVALID_REGNUM) \ 203210d565efSmrg : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12) 203310d565efSmrg #define MIPS_EPILOGUE_TEMP_REGNUM \ 203410d565efSmrg (cfun->machine->interrupt_handler_p \ 203510d565efSmrg ? K0_REG_NUM \ 203610d565efSmrg : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 203710d565efSmrg 203810d565efSmrg #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) 203910d565efSmrg #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 204010d565efSmrg #define MIPS_PROLOGUE_TEMP2(MODE) \ 204110d565efSmrg gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM) 204210d565efSmrg #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 204310d565efSmrg 204410d565efSmrg /* Define this macro if it is as good or better to call a constant 204510d565efSmrg function address than to call an address kept in a register. */ 204610d565efSmrg #define NO_FUNCTION_CSE 1 204710d565efSmrg 204810d565efSmrg /* The ABI-defined global pointer. Sometimes we use a different 204910d565efSmrg register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 205010d565efSmrg #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 205110d565efSmrg 205210d565efSmrg /* We normally use $28 as the global pointer. However, when generating 205310d565efSmrg n32/64 PIC, it is better for leaf functions to use a call-clobbered 205410d565efSmrg register instead. They can then avoid saving and restoring $28 205510d565efSmrg and perhaps avoid using a frame at all. 205610d565efSmrg 205710d565efSmrg When a leaf function uses something other than $28, mips_expand_prologue 205810d565efSmrg will modify pic_offset_table_rtx in place. Take the register number 205910d565efSmrg from there after reload. */ 206010d565efSmrg #define PIC_OFFSET_TABLE_REGNUM \ 206110d565efSmrg (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 206210d565efSmrg 206310d565efSmrg /* Define the classes of registers for register constraints in the 206410d565efSmrg machine description. Also define ranges of constants. 206510d565efSmrg 206610d565efSmrg One of the classes must always be named ALL_REGS and include all hard regs. 206710d565efSmrg If there is more than one class, another class must be named NO_REGS 206810d565efSmrg and contain no registers. 206910d565efSmrg 207010d565efSmrg The name GENERAL_REGS must be the name of a class (or an alias for 207110d565efSmrg another name such as ALL_REGS). This is the class of registers 207210d565efSmrg that is allowed by "g" or "r" in a register constraint. 207310d565efSmrg Also, registers outside this class are allocated only when 207410d565efSmrg instructions express preferences for them. 207510d565efSmrg 207610d565efSmrg The classes must be numbered in nondecreasing order; that is, 207710d565efSmrg a larger-numbered class must never be contained completely 207810d565efSmrg in a smaller-numbered class. 207910d565efSmrg 208010d565efSmrg For any two classes, it is very desirable that there be another 208110d565efSmrg class that represents their union. */ 208210d565efSmrg 208310d565efSmrg enum reg_class 208410d565efSmrg { 208510d565efSmrg NO_REGS, /* no registers in set */ 208610d565efSmrg M16_STORE_REGS, /* microMIPS store registers */ 208710d565efSmrg M16_REGS, /* mips16 directly accessible registers */ 208810d565efSmrg M16_SP_REGS, /* mips16 + $sp */ 208910d565efSmrg T_REG, /* mips16 T register ($24) */ 209010d565efSmrg M16_T_REGS, /* mips16 registers plus T register */ 209110d565efSmrg PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 209210d565efSmrg V1_REG, /* Register $v1 ($3) used for TLS access. */ 209310d565efSmrg SPILL_REGS, /* All but $sp and call preserved regs are in here */ 209410d565efSmrg LEA_REGS, /* Every GPR except $25 */ 209510d565efSmrg GR_REGS, /* integer registers */ 209610d565efSmrg FP_REGS, /* floating point registers */ 209710d565efSmrg MD0_REG, /* first multiply/divide register */ 209810d565efSmrg MD1_REG, /* second multiply/divide register */ 209910d565efSmrg MD_REGS, /* multiply/divide registers (hi/lo) */ 210010d565efSmrg COP0_REGS, /* generic coprocessor classes */ 210110d565efSmrg COP2_REGS, 210210d565efSmrg COP3_REGS, 210310d565efSmrg ST_REGS, /* status registers (fp status) */ 210410d565efSmrg DSP_ACC_REGS, /* DSP accumulator registers */ 210510d565efSmrg ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 210610d565efSmrg FRAME_REGS, /* $arg and $frame */ 210710d565efSmrg GR_AND_MD0_REGS, /* union classes */ 210810d565efSmrg GR_AND_MD1_REGS, 210910d565efSmrg GR_AND_MD_REGS, 211010d565efSmrg GR_AND_ACC_REGS, 211110d565efSmrg ALL_REGS, /* all registers */ 211210d565efSmrg LIM_REG_CLASSES /* max value + 1 */ 211310d565efSmrg }; 211410d565efSmrg 211510d565efSmrg #define N_REG_CLASSES (int) LIM_REG_CLASSES 211610d565efSmrg 211710d565efSmrg #define GENERAL_REGS GR_REGS 211810d565efSmrg 211910d565efSmrg /* An initializer containing the names of the register classes as C 212010d565efSmrg string constants. These names are used in writing some of the 212110d565efSmrg debugging dumps. */ 212210d565efSmrg 212310d565efSmrg #define REG_CLASS_NAMES \ 212410d565efSmrg { \ 212510d565efSmrg "NO_REGS", \ 212610d565efSmrg "M16_STORE_REGS", \ 212710d565efSmrg "M16_REGS", \ 212810d565efSmrg "M16_SP_REGS", \ 212910d565efSmrg "T_REG", \ 213010d565efSmrg "M16_T_REGS", \ 213110d565efSmrg "PIC_FN_ADDR_REG", \ 213210d565efSmrg "V1_REG", \ 213310d565efSmrg "SPILL_REGS", \ 213410d565efSmrg "LEA_REGS", \ 213510d565efSmrg "GR_REGS", \ 213610d565efSmrg "FP_REGS", \ 213710d565efSmrg "MD0_REG", \ 213810d565efSmrg "MD1_REG", \ 213910d565efSmrg "MD_REGS", \ 214010d565efSmrg /* coprocessor registers */ \ 214110d565efSmrg "COP0_REGS", \ 214210d565efSmrg "COP2_REGS", \ 214310d565efSmrg "COP3_REGS", \ 214410d565efSmrg "ST_REGS", \ 214510d565efSmrg "DSP_ACC_REGS", \ 214610d565efSmrg "ACC_REGS", \ 214710d565efSmrg "FRAME_REGS", \ 214810d565efSmrg "GR_AND_MD0_REGS", \ 214910d565efSmrg "GR_AND_MD1_REGS", \ 215010d565efSmrg "GR_AND_MD_REGS", \ 215110d565efSmrg "GR_AND_ACC_REGS", \ 215210d565efSmrg "ALL_REGS" \ 215310d565efSmrg } 215410d565efSmrg 215510d565efSmrg /* An initializer containing the contents of the register classes, 215610d565efSmrg as integers which are bit masks. The Nth integer specifies the 215710d565efSmrg contents of class N. The way the integer MASK is interpreted is 215810d565efSmrg that register R is in the class if `MASK & (1 << R)' is 1. 215910d565efSmrg 216010d565efSmrg When the machine has more than 32 registers, an integer does not 216110d565efSmrg suffice. Then the integers are replaced by sub-initializers, 216210d565efSmrg braced groupings containing several integers. Each 216310d565efSmrg sub-initializer must be suitable as an initializer for the type 216410d565efSmrg `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 216510d565efSmrg 216610d565efSmrg #define REG_CLASS_CONTENTS \ 216710d565efSmrg { \ 216810d565efSmrg { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 216910d565efSmrg { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \ 217010d565efSmrg { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ 217110d565efSmrg { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \ 217210d565efSmrg { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ 217310d565efSmrg { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ 217410d565efSmrg { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ 217510d565efSmrg { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ 217610d565efSmrg { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \ 217710d565efSmrg { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ 217810d565efSmrg { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 217910d565efSmrg { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ 218010d565efSmrg { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ 218110d565efSmrg { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ 218210d565efSmrg { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ 218310d565efSmrg { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ 218410d565efSmrg { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ 218510d565efSmrg { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ 218610d565efSmrg { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ 218710d565efSmrg { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ 218810d565efSmrg { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ 218910d565efSmrg { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ 219010d565efSmrg { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ 219110d565efSmrg { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ 219210d565efSmrg { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ 219310d565efSmrg { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ 219410d565efSmrg { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ 219510d565efSmrg } 219610d565efSmrg 219710d565efSmrg 219810d565efSmrg /* A C expression whose value is a register class containing hard 219910d565efSmrg register REGNO. In general there is more that one such class; 220010d565efSmrg choose a class which is "minimal", meaning that no smaller class 220110d565efSmrg also contains the register. */ 220210d565efSmrg 220310d565efSmrg #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 220410d565efSmrg 220510d565efSmrg /* A macro whose definition is the name of the class to which a 220610d565efSmrg valid base register must belong. A base register is one used in 220710d565efSmrg an address which is the register value plus a displacement. */ 220810d565efSmrg 220910d565efSmrg #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS) 221010d565efSmrg 221110d565efSmrg /* A macro whose definition is the name of the class to which a 221210d565efSmrg valid index register must belong. An index register is one used 221310d565efSmrg in an address where its value is either multiplied by a scale 221410d565efSmrg factor or added to another register (as well as added to a 221510d565efSmrg displacement). */ 221610d565efSmrg 221710d565efSmrg #define INDEX_REG_CLASS NO_REGS 221810d565efSmrg 221910d565efSmrg /* We generally want to put call-clobbered registers ahead of 222010d565efSmrg call-saved ones. (IRA expects this.) */ 222110d565efSmrg 222210d565efSmrg #define REG_ALLOC_ORDER \ 222310d565efSmrg { /* Accumulator registers. When GPRs and accumulators have equal \ 222410d565efSmrg cost, we generally prefer to use accumulators. For example, \ 222510d565efSmrg a division of multiplication result is better allocated to LO, \ 222610d565efSmrg so that we put the MFLO at the point of use instead of at the \ 222710d565efSmrg point of definition. It's also needed if we're to take advantage \ 222810d565efSmrg of the extra accumulators available with -mdspr2. In some cases, \ 222910d565efSmrg it can also help to reduce register pressure. */ \ 223010d565efSmrg 64, 65,176,177,178,179,180,181, \ 223110d565efSmrg /* Call-clobbered GPRs. */ \ 223210d565efSmrg 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 223310d565efSmrg 24, 25, 31, \ 223410d565efSmrg /* The global pointer. This is call-clobbered for o32 and o64 \ 223510d565efSmrg abicalls, call-saved for n32 and n64 abicalls, and a program \ 223610d565efSmrg invariant otherwise. Putting it between the call-clobbered \ 223710d565efSmrg and call-saved registers should cope with all eventualities. */ \ 223810d565efSmrg 28, \ 223910d565efSmrg /* Call-saved GPRs. */ \ 224010d565efSmrg 16, 17, 18, 19, 20, 21, 22, 23, 30, \ 224110d565efSmrg /* GPRs that can never be exposed to the register allocator. */ \ 224210d565efSmrg 0, 26, 27, 29, \ 224310d565efSmrg /* Call-clobbered FPRs. */ \ 224410d565efSmrg 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 224510d565efSmrg 48, 49, 50, 51, \ 224610d565efSmrg /* FPRs that are usually call-saved. The odd ones are actually \ 224710d565efSmrg call-clobbered for n32, but listing them ahead of the even \ 224810d565efSmrg registers might encourage the register allocator to fragment \ 224910d565efSmrg the available FPR pairs. We need paired FPRs to store long \ 225010d565efSmrg doubles, so it isn't clear that using a different order \ 225110d565efSmrg for n32 would be a win. */ \ 225210d565efSmrg 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 225310d565efSmrg /* None of the remaining classes have defined call-saved \ 225410d565efSmrg registers. */ \ 225510d565efSmrg 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 225610d565efSmrg 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 225710d565efSmrg 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 225810d565efSmrg 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 225910d565efSmrg 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 226010d565efSmrg 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 226110d565efSmrg 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 226210d565efSmrg 182,183,184,185,186,187 \ 226310d565efSmrg } 226410d565efSmrg 226510d565efSmrg /* True if VALUE is an unsigned 6-bit number. */ 226610d565efSmrg 226710d565efSmrg #define UIMM6_OPERAND(VALUE) \ 226810d565efSmrg (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 226910d565efSmrg 227010d565efSmrg /* True if VALUE is a signed 10-bit number. */ 227110d565efSmrg 227210d565efSmrg #define IMM10_OPERAND(VALUE) \ 227310d565efSmrg ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 227410d565efSmrg 227510d565efSmrg /* True if VALUE is a signed 16-bit number. */ 227610d565efSmrg 227710d565efSmrg #define SMALL_OPERAND(VALUE) \ 227810d565efSmrg ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 227910d565efSmrg 228010d565efSmrg /* True if VALUE is an unsigned 16-bit number. */ 228110d565efSmrg 228210d565efSmrg #define SMALL_OPERAND_UNSIGNED(VALUE) \ 228310d565efSmrg (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 228410d565efSmrg 228510d565efSmrg /* True if VALUE can be loaded into a register using LUI. */ 228610d565efSmrg 228710d565efSmrg #define LUI_OPERAND(VALUE) \ 228810d565efSmrg (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 228910d565efSmrg || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 229010d565efSmrg 229110d565efSmrg /* Return a value X with the low 16 bits clear, and such that 229210d565efSmrg VALUE - X is a signed 16-bit value. */ 229310d565efSmrg 229410d565efSmrg #define CONST_HIGH_PART(VALUE) \ 229510d565efSmrg (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 229610d565efSmrg 229710d565efSmrg #define CONST_LOW_PART(VALUE) \ 229810d565efSmrg ((VALUE) - CONST_HIGH_PART (VALUE)) 229910d565efSmrg 230010d565efSmrg #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 230110d565efSmrg #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 230210d565efSmrg #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 230310d565efSmrg #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) 230410d565efSmrg #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) 230510d565efSmrg 230610d565efSmrg /* The HI and LO registers can only be reloaded via the general 230710d565efSmrg registers. Condition code registers can only be loaded to the 230810d565efSmrg general registers, and from the floating point registers. */ 230910d565efSmrg 231010d565efSmrg #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 231110d565efSmrg mips_secondary_reload_class (CLASS, MODE, X, true) 231210d565efSmrg #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 231310d565efSmrg mips_secondary_reload_class (CLASS, MODE, X, false) 231410d565efSmrg 231510d565efSmrg /* Return the maximum number of consecutive registers 231610d565efSmrg needed to represent mode MODE in a register of class CLASS. */ 231710d565efSmrg 231810d565efSmrg #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 231910d565efSmrg 232010d565efSmrg /* Stack layout; function entry, exit and calling. */ 232110d565efSmrg 232210d565efSmrg #define STACK_GROWS_DOWNWARD 1 232310d565efSmrg 23240fc04c29Smrg #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 23250fc04c29Smrg || (flag_sanitize & SANITIZE_ADDRESS) != 0) 232610d565efSmrg 232710d565efSmrg /* Size of the area allocated in the frame to save the GP. */ 232810d565efSmrg 232910d565efSmrg #define MIPS_GP_SAVE_AREA_SIZE \ 233010d565efSmrg (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) 233110d565efSmrg 233210d565efSmrg #define RETURN_ADDR_RTX mips_return_addr 233310d565efSmrg 233410d565efSmrg /* Mask off the MIPS16 ISA bit in unwind addresses. 233510d565efSmrg 233610d565efSmrg The reason for this is a little subtle. When unwinding a call, 233710d565efSmrg we are given the call's return address, which on most targets 233810d565efSmrg is the address of the following instruction. However, what we 233910d565efSmrg actually want to find is the EH region for the call itself. 234010d565efSmrg The target-independent unwind code therefore searches for "RA - 1". 234110d565efSmrg 234210d565efSmrg In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. 234310d565efSmrg RA - 1 is therefore the real (even-valued) start of the return 234410d565efSmrg instruction. EH region labels are usually odd-valued MIPS16 symbols 234510d565efSmrg too, so a search for an even address within a MIPS16 region would 234610d565efSmrg usually work. 234710d565efSmrg 234810d565efSmrg However, there is an exception. If the end of an EH region is also 234910d565efSmrg the end of a function, the end label is allowed to be even. This is 235010d565efSmrg necessary because a following non-MIPS16 function may also need EH 235110d565efSmrg information for its first instruction. 235210d565efSmrg 235310d565efSmrg Thus a MIPS16 region may be terminated by an ISA-encoded or a 235410d565efSmrg non-ISA-encoded address. This probably isn't ideal, but it is 235510d565efSmrg the traditional (legacy) behavior. It is therefore only safe 235610d565efSmrg to search MIPS EH regions for an _odd-valued_ address. 235710d565efSmrg 235810d565efSmrg Masking off the ISA bit means that the target-independent code 235910d565efSmrg will search for "(RA & -2) - 1", which is guaranteed to be odd. */ 236010d565efSmrg #define MASK_RETURN_ADDR GEN_INT (-2) 236110d565efSmrg 236210d565efSmrg 236310d565efSmrg /* Similarly, don't use the least-significant bit to tell pointers to 236410d565efSmrg code from vtable index. */ 236510d565efSmrg 236610d565efSmrg #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 236710d565efSmrg 236810d565efSmrg /* The eliminations to $17 are only used for mips16 code. See the 236910d565efSmrg definition of HARD_FRAME_POINTER_REGNUM. */ 237010d565efSmrg 237110d565efSmrg #define ELIMINABLE_REGS \ 237210d565efSmrg {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 237310d565efSmrg { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 237410d565efSmrg { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 237510d565efSmrg { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 237610d565efSmrg { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 237710d565efSmrg { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 237810d565efSmrg 237910d565efSmrg #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 238010d565efSmrg (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 238110d565efSmrg 238210d565efSmrg /* Allocate stack space for arguments at the beginning of each function. */ 238310d565efSmrg #define ACCUMULATE_OUTGOING_ARGS 1 238410d565efSmrg 238510d565efSmrg /* The argument pointer always points to the first argument. */ 238610d565efSmrg #define FIRST_PARM_OFFSET(FNDECL) 0 238710d565efSmrg 238810d565efSmrg /* o32 and o64 reserve stack space for all argument registers. */ 238910d565efSmrg #define REG_PARM_STACK_SPACE(FNDECL) \ 239010d565efSmrg (TARGET_OLDABI \ 239110d565efSmrg ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 239210d565efSmrg : 0) 239310d565efSmrg 239410d565efSmrg /* Define this if it is the responsibility of the caller to 239510d565efSmrg allocate the area reserved for arguments passed in registers. 239610d565efSmrg If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 239710d565efSmrg of this macro is to determine whether the space is included in 239810d565efSmrg `crtl->outgoing_args_size'. */ 239910d565efSmrg #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 240010d565efSmrg 240110d565efSmrg #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 240210d565efSmrg 240310d565efSmrg /* Symbolic macros for the registers used to return integer and floating 240410d565efSmrg point values. */ 240510d565efSmrg 240610d565efSmrg #define GP_RETURN (GP_REG_FIRST + 2) 240710d565efSmrg #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 240810d565efSmrg 240910d565efSmrg #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 241010d565efSmrg 241110d565efSmrg /* Symbolic macros for the first/last argument registers. */ 241210d565efSmrg 241310d565efSmrg #define GP_ARG_FIRST (GP_REG_FIRST + 4) 241410d565efSmrg #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 241510d565efSmrg #define FP_ARG_FIRST (FP_REG_FIRST + 12) 241610d565efSmrg #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 241710d565efSmrg 241810d565efSmrg /* True if MODE is vector and supported in a MSA vector register. */ 241910d565efSmrg #define MSA_SUPPORTED_MODE_P(MODE) \ 242010d565efSmrg (ISA_HAS_MSA \ 242110d565efSmrg && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \ 242210d565efSmrg && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ 242310d565efSmrg || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)) 242410d565efSmrg 242510d565efSmrg /* Temporary register that is used when restoring $gp after a call. $4 and $5 242610d565efSmrg are used for returning complex double values in soft-float code, so $6 is the 242710d565efSmrg first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use 242810d565efSmrg $gp itself as the temporary. */ 242910d565efSmrg #define POST_CALL_TMP_REG \ 243010d565efSmrg (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM) 243110d565efSmrg 243210d565efSmrg /* 1 if N is a possible register number for function argument passing. 243310d565efSmrg We have no FP argument registers when soft-float. Special handling 243410d565efSmrg is required for O32 where only even numbered registers are used for 243510d565efSmrg O32-FPXX and O32-FP64. */ 243610d565efSmrg 243710d565efSmrg #define FUNCTION_ARG_REGNO_P(N) \ 243810d565efSmrg ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 243910d565efSmrg || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \ 244010d565efSmrg && (mips_abi != ABI_32 \ 244110d565efSmrg || TARGET_FLOAT32 \ 244210d565efSmrg || ((N) % 2 == 0)))) \ 244310d565efSmrg && !fixed_regs[N]) 244410d565efSmrg 244510d565efSmrg /* This structure has to cope with two different argument allocation 244610d565efSmrg schemes. Most MIPS ABIs view the arguments as a structure, of which 244710d565efSmrg the first N words go in registers and the rest go on the stack. If I 244810d565efSmrg < N, the Ith word might go in Ith integer argument register or in a 244910d565efSmrg floating-point register. For these ABIs, we only need to remember 245010d565efSmrg the offset of the current argument into the structure. 245110d565efSmrg 245210d565efSmrg The EABI instead allocates the integer and floating-point arguments 245310d565efSmrg separately. The first N words of FP arguments go in FP registers, 245410d565efSmrg the rest go on the stack. Likewise, the first N words of the other 245510d565efSmrg arguments go in integer registers, and the rest go on the stack. We 245610d565efSmrg need to maintain three counts: the number of integer registers used, 245710d565efSmrg the number of floating-point registers used, and the number of words 245810d565efSmrg passed on the stack. 245910d565efSmrg 246010d565efSmrg We could keep separate information for the two ABIs (a word count for 246110d565efSmrg the standard ABIs, and three separate counts for the EABI). But it 246210d565efSmrg seems simpler to view the standard ABIs as forms of EABI that do not 246310d565efSmrg allocate floating-point registers. 246410d565efSmrg 246510d565efSmrg So for the standard ABIs, the first N words are allocated to integer 246610d565efSmrg registers, and mips_function_arg decides on an argument-by-argument 246710d565efSmrg basis whether that argument should really go in an integer register, 246810d565efSmrg or in a floating-point one. */ 246910d565efSmrg 247010d565efSmrg typedef struct mips_args { 247110d565efSmrg /* Always true for varargs functions. Otherwise true if at least 247210d565efSmrg one argument has been passed in an integer register. */ 247310d565efSmrg int gp_reg_found; 247410d565efSmrg 247510d565efSmrg /* The number of arguments seen so far. */ 247610d565efSmrg unsigned int arg_number; 247710d565efSmrg 247810d565efSmrg /* The number of integer registers used so far. For all ABIs except 247910d565efSmrg EABI, this is the number of words that have been added to the 248010d565efSmrg argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 248110d565efSmrg unsigned int num_gprs; 248210d565efSmrg 248310d565efSmrg /* For EABI, the number of floating-point registers used so far. */ 248410d565efSmrg unsigned int num_fprs; 248510d565efSmrg 248610d565efSmrg /* The number of words passed on the stack. */ 248710d565efSmrg unsigned int stack_words; 248810d565efSmrg 248910d565efSmrg /* On the mips16, we need to keep track of which floating point 249010d565efSmrg arguments were passed in general registers, but would have been 249110d565efSmrg passed in the FP regs if this were a 32-bit function, so that we 249210d565efSmrg can move them to the FP regs if we wind up calling a 32-bit 249310d565efSmrg function. We record this information in fp_code, encoded in base 249410d565efSmrg four. A zero digit means no floating point argument, a one digit 249510d565efSmrg means an SFmode argument, and a two digit means a DFmode argument, 249610d565efSmrg and a three digit is not used. The low order digit is the first 249710d565efSmrg argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 249810d565efSmrg an SFmode argument. ??? A more sophisticated approach will be 249910d565efSmrg needed if MIPS_ABI != ABI_32. */ 250010d565efSmrg int fp_code; 250110d565efSmrg 250210d565efSmrg /* True if the function has a prototype. */ 250310d565efSmrg int prototype; 250410d565efSmrg } CUMULATIVE_ARGS; 250510d565efSmrg 250610d565efSmrg /* Initialize a variable CUM of type CUMULATIVE_ARGS 250710d565efSmrg for a call to a function whose data type is FNTYPE. 250810d565efSmrg For a library call, FNTYPE is 0. */ 250910d565efSmrg 251010d565efSmrg #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 251110d565efSmrg mips_init_cumulative_args (&CUM, FNTYPE) 251210d565efSmrg 251310d565efSmrg #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 2514c7a68eb7Smrg (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD) 251510d565efSmrg 251610d565efSmrg /* True if using EABI and varargs can be passed in floating-point 251710d565efSmrg registers. Under these conditions, we need a more complex form 251810d565efSmrg of va_list, which tracks GPR, FPR and stack arguments separately. */ 251910d565efSmrg #define EABI_FLOAT_VARARGS_P \ 252010d565efSmrg (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 252110d565efSmrg 252210d565efSmrg 252310d565efSmrg #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) 252410d565efSmrg 252510d565efSmrg /* Treat LOC as a byte offset from the stack pointer and round it up 252610d565efSmrg to the next fully-aligned offset. */ 252710d565efSmrg #define MIPS_STACK_ALIGN(LOC) \ 252810d565efSmrg (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) 252910d565efSmrg 253010d565efSmrg 253110d565efSmrg /* Output assembler code to FILE to increment profiler label # LABELNO 253210d565efSmrg for profiling a function entry. */ 253310d565efSmrg 253410d565efSmrg #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) 253510d565efSmrg 253610d565efSmrg /* The profiler preserves all interesting registers, including $31. */ 253710d565efSmrg #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false 253810d565efSmrg 253910d565efSmrg /* No mips port has ever used the profiler counter word, so don't emit it 254010d565efSmrg or the label for it. */ 254110d565efSmrg 254210d565efSmrg #define NO_PROFILE_COUNTERS 1 254310d565efSmrg 254410d565efSmrg /* Define this macro if the code for function profiling should come 254510d565efSmrg before the function prologue. Normally, the profiling code comes 254610d565efSmrg after. */ 254710d565efSmrg 254810d565efSmrg /* #define PROFILE_BEFORE_PROLOGUE */ 254910d565efSmrg 255010d565efSmrg /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 255110d565efSmrg the stack pointer does not matter. The value is tested only in 255210d565efSmrg functions that have frame pointers. 255310d565efSmrg No definition is equivalent to always zero. */ 255410d565efSmrg 255510d565efSmrg #define EXIT_IGNORE_STACK 1 255610d565efSmrg 255710d565efSmrg 255810d565efSmrg /* Trampolines are a block of code followed by two pointers. */ 255910d565efSmrg 256010d565efSmrg #define TRAMPOLINE_SIZE \ 256110d565efSmrg (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) 256210d565efSmrg 256310d565efSmrg /* Forcing a 64-bit alignment for 32-bit targets allows us to load two 256410d565efSmrg pointers from a single LUI base. */ 256510d565efSmrg 256610d565efSmrg #define TRAMPOLINE_ALIGNMENT 64 256710d565efSmrg 256810d565efSmrg /* mips_trampoline_init calls this library function to flush 256910d565efSmrg program and data caches. */ 257010d565efSmrg 257110d565efSmrg #ifndef CACHE_FLUSH_FUNC 257210d565efSmrg #define CACHE_FLUSH_FUNC "_flush_cache" 257310d565efSmrg #endif 257410d565efSmrg 257510d565efSmrg #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ 257610d565efSmrg /* Flush both caches. We need to flush the data cache in case \ 257710d565efSmrg the system has a write-back cache. */ \ 257810d565efSmrg emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2579c7a68eb7Smrg LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \ 258010d565efSmrg GEN_INT (3), TYPE_MODE (integer_type_node)) 258110d565efSmrg 258210d565efSmrg 258310d565efSmrg /* Addressing modes, and classification of registers for them. */ 258410d565efSmrg 258510d565efSmrg #define REGNO_OK_FOR_INDEX_P(REGNO) 0 258610d565efSmrg #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 258710d565efSmrg mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 258810d565efSmrg 258910d565efSmrg /* Maximum number of registers that can appear in a valid memory address. */ 259010d565efSmrg 259110d565efSmrg #define MAX_REGS_PER_ADDRESS 1 259210d565efSmrg 259310d565efSmrg /* Check for constness inline but use mips_legitimate_address_p 259410d565efSmrg to check whether a constant really is an address. */ 259510d565efSmrg 259610d565efSmrg #define CONSTANT_ADDRESS_P(X) \ 259710d565efSmrg (CONSTANT_P (X) && memory_address_p (SImode, X)) 259810d565efSmrg 259910d565efSmrg /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 260010d565efSmrg 'the start of the function that this code is output in'. */ 260110d565efSmrg 260210d565efSmrg #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2603c7a68eb7Smrg do { \ 260410d565efSmrg if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 260510d565efSmrg asm_fprintf ((FILE), "%U%s", \ 2606c7a68eb7Smrg XSTR (XEXP (DECL_RTL (current_function_decl), \ 2607c7a68eb7Smrg 0), 0)); \ 260810d565efSmrg else \ 2609c7a68eb7Smrg asm_fprintf ((FILE), "%U%s", (NAME)); \ 2610c7a68eb7Smrg } while (0) 261110d565efSmrg 261210d565efSmrg /* Flag to mark a function decl symbol that requires a long call. */ 261310d565efSmrg #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 261410d565efSmrg #define SYMBOL_REF_LONG_CALL_P(X) \ 261510d565efSmrg ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 261610d565efSmrg 261710d565efSmrg /* This flag marks functions that cannot be lazily bound. */ 261810d565efSmrg #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) 261910d565efSmrg #define SYMBOL_REF_BIND_NOW_P(RTX) \ 262010d565efSmrg ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) 262110d565efSmrg 262210d565efSmrg /* True if we're generating a form of MIPS16 code in which jump tables 262310d565efSmrg are stored in the text section and encoded as 16-bit PC-relative 262410d565efSmrg offsets. This is only possible when general text loads are allowed, 262510d565efSmrg since the table access itself will be an "lh" instruction. If the 262610d565efSmrg PC-relative offsets grow too large, 32-bit offsets are used instead. */ 262710d565efSmrg #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS 262810d565efSmrg 262910d565efSmrg #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES 263010d565efSmrg 263110d565efSmrg #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode) 263210d565efSmrg 263310d565efSmrg /* Only use short offsets if their range will not overflow. */ 263410d565efSmrg #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \ 263510d565efSmrg (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \ 263610d565efSmrg : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \ 263710d565efSmrg : SImode) 263810d565efSmrg 263910d565efSmrg #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES 264010d565efSmrg 264110d565efSmrg /* Define this as 1 if `char' should by default be signed; else as 0. */ 264210d565efSmrg #ifndef DEFAULT_SIGNED_CHAR 264310d565efSmrg #define DEFAULT_SIGNED_CHAR 1 264410d565efSmrg #endif 264510d565efSmrg 264610d565efSmrg /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, 264710d565efSmrg we generally don't want to use them for copying arbitrary data. 264810d565efSmrg A single N-word move is usually the same cost as N single-word moves. */ 264910d565efSmrg #define MOVE_MAX UNITS_PER_WORD 265010d565efSmrg /* We don't modify it for MSA as it is only used by the classic reload. */ 265110d565efSmrg #define MAX_MOVE_MAX 8 265210d565efSmrg 265310d565efSmrg /* Define this macro as a C expression which is nonzero if 265410d565efSmrg accessing less than a word of memory (i.e. a `char' or a 265510d565efSmrg `short') is no faster than accessing a word of memory, i.e., if 265610d565efSmrg such access require more than one instruction or if there is no 265710d565efSmrg difference in cost between byte and (aligned) word loads. 265810d565efSmrg 265910d565efSmrg On RISC machines, it tends to generate better code to define 266010d565efSmrg this as 1, since it avoids making a QI or HI mode register. 266110d565efSmrg 266210d565efSmrg But, generating word accesses for -mips16 is generally bad as shifts 266310d565efSmrg (often extended) would be needed for byte accesses. */ 266410d565efSmrg #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) 266510d565efSmrg 266610d565efSmrg /* Standard MIPS integer shifts truncate the shift amount to the 26670fc04c29Smrg width of the shifted operand. However, Loongson MMI shifts 266810d565efSmrg do not truncate the shift amount at all. */ 26690fc04c29Smrg #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) 267010d565efSmrg 267110d565efSmrg 267210d565efSmrg /* Specify the machine mode that pointers have. 267310d565efSmrg After generation of rtl, the compiler makes no further distinction 267410d565efSmrg between pointers and any other objects of this machine mode. */ 267510d565efSmrg 267610d565efSmrg #ifndef Pmode 267710d565efSmrg #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 267810d565efSmrg #endif 267910d565efSmrg 268010d565efSmrg /* Give call MEMs SImode since it is the "most permissive" mode 268110d565efSmrg for both 32-bit and 64-bit targets. */ 268210d565efSmrg 268310d565efSmrg #define FUNCTION_MODE SImode 268410d565efSmrg 268510d565efSmrg 268610d565efSmrg /* We allocate $fcc registers by hand and can't cope with moves of 268710d565efSmrg CCmode registers to and from pseudos (or memory). */ 268810d565efSmrg #define AVOID_CCMODE_COPIES 268910d565efSmrg 269010d565efSmrg /* A C expression for the cost of a branch instruction. A value of 269110d565efSmrg 1 is the default; other values are interpreted relative to that. */ 269210d565efSmrg 269310d565efSmrg #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost 269410d565efSmrg #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 269510d565efSmrg 269610d565efSmrg /* The MIPS port has several functions that return an instruction count. 269710d565efSmrg Multiplying the count by this value gives the number of bytes that 269810d565efSmrg the instructions occupy. */ 269910d565efSmrg #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4) 270010d565efSmrg 270110d565efSmrg /* The length of a NOP in bytes. */ 270210d565efSmrg #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4) 270310d565efSmrg 270410d565efSmrg /* If defined, modifies the length assigned to instruction INSN as a 270510d565efSmrg function of the context in which it is used. LENGTH is an lvalue 270610d565efSmrg that contains the initially computed length of the insn and should 270710d565efSmrg be updated with the correct length of the insn. */ 270810d565efSmrg #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 270910d565efSmrg ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 271010d565efSmrg 271110d565efSmrg /* Return the asm template for a non-MIPS16 conditional branch instruction. 271210d565efSmrg OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 271310d565efSmrg its operands. */ 271410d565efSmrg #define MIPS_BRANCH(OPCODE, OPERANDS) \ 271510d565efSmrg "%*" OPCODE "%?\t" OPERANDS "%/" 271610d565efSmrg 271710d565efSmrg #define MIPS_BRANCH_C(OPCODE, OPERANDS) \ 271810d565efSmrg "%*" OPCODE "%:\t" OPERANDS 271910d565efSmrg 272010d565efSmrg /* Return an asm string that forces INSN to be treated as an absolute 272110d565efSmrg J or JAL instruction instead of an assembler macro. */ 272210d565efSmrg #define MIPS_ABSOLUTE_JUMP(INSN) \ 272310d565efSmrg (TARGET_ABICALLS_PIC2 \ 272410d565efSmrg ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ 272510d565efSmrg : INSN) 272610d565efSmrg 272710d565efSmrg 272810d565efSmrg /* Control the assembler format that we output. */ 272910d565efSmrg 273010d565efSmrg /* Output to assembler file text saying following lines 273110d565efSmrg may contain character constants, extra white space, comments, etc. */ 273210d565efSmrg 273310d565efSmrg #ifndef ASM_APP_ON 273410d565efSmrg #define ASM_APP_ON " #APP\n" 273510d565efSmrg #endif 273610d565efSmrg 273710d565efSmrg /* Output to assembler file text saying following lines 273810d565efSmrg no longer contain unusual constructs. */ 273910d565efSmrg 274010d565efSmrg #ifndef ASM_APP_OFF 274110d565efSmrg #define ASM_APP_OFF " #NO_APP\n" 274210d565efSmrg #endif 274310d565efSmrg 274410d565efSmrg #define REGISTER_NAMES \ 274510d565efSmrg { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 274610d565efSmrg "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 274710d565efSmrg "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 274810d565efSmrg "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 274910d565efSmrg "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 275010d565efSmrg "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 275110d565efSmrg "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 275210d565efSmrg "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 275310d565efSmrg "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 275410d565efSmrg "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ 275510d565efSmrg "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 275610d565efSmrg "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 275710d565efSmrg "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 275810d565efSmrg "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 275910d565efSmrg "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 276010d565efSmrg "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 276110d565efSmrg "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 276210d565efSmrg "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 276310d565efSmrg "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 276410d565efSmrg "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 276510d565efSmrg "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 276610d565efSmrg "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 276710d565efSmrg "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 276810d565efSmrg "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 276910d565efSmrg 277010d565efSmrg /* List the "software" names for each register. Also list the numerical 277110d565efSmrg names for $fp and $sp. */ 277210d565efSmrg 277310d565efSmrg #define ADDITIONAL_REGISTER_NAMES \ 277410d565efSmrg { \ 277510d565efSmrg { "$29", 29 + GP_REG_FIRST }, \ 277610d565efSmrg { "$30", 30 + GP_REG_FIRST }, \ 277710d565efSmrg { "at", 1 + GP_REG_FIRST }, \ 277810d565efSmrg { "v0", 2 + GP_REG_FIRST }, \ 277910d565efSmrg { "v1", 3 + GP_REG_FIRST }, \ 278010d565efSmrg { "a0", 4 + GP_REG_FIRST }, \ 278110d565efSmrg { "a1", 5 + GP_REG_FIRST }, \ 278210d565efSmrg { "a2", 6 + GP_REG_FIRST }, \ 278310d565efSmrg { "a3", 7 + GP_REG_FIRST }, \ 278410d565efSmrg { "t0", 8 + GP_REG_FIRST }, \ 278510d565efSmrg { "t1", 9 + GP_REG_FIRST }, \ 278610d565efSmrg { "t2", 10 + GP_REG_FIRST }, \ 278710d565efSmrg { "t3", 11 + GP_REG_FIRST }, \ 278810d565efSmrg { "t4", 12 + GP_REG_FIRST }, \ 278910d565efSmrg { "t5", 13 + GP_REG_FIRST }, \ 279010d565efSmrg { "t6", 14 + GP_REG_FIRST }, \ 279110d565efSmrg { "t7", 15 + GP_REG_FIRST }, \ 279210d565efSmrg { "s0", 16 + GP_REG_FIRST }, \ 279310d565efSmrg { "s1", 17 + GP_REG_FIRST }, \ 279410d565efSmrg { "s2", 18 + GP_REG_FIRST }, \ 279510d565efSmrg { "s3", 19 + GP_REG_FIRST }, \ 279610d565efSmrg { "s4", 20 + GP_REG_FIRST }, \ 279710d565efSmrg { "s5", 21 + GP_REG_FIRST }, \ 279810d565efSmrg { "s6", 22 + GP_REG_FIRST }, \ 279910d565efSmrg { "s7", 23 + GP_REG_FIRST }, \ 280010d565efSmrg { "t8", 24 + GP_REG_FIRST }, \ 280110d565efSmrg { "t9", 25 + GP_REG_FIRST }, \ 280210d565efSmrg { "k0", 26 + GP_REG_FIRST }, \ 280310d565efSmrg { "k1", 27 + GP_REG_FIRST }, \ 280410d565efSmrg { "gp", 28 + GP_REG_FIRST }, \ 280510d565efSmrg { "sp", 29 + GP_REG_FIRST }, \ 280610d565efSmrg { "fp", 30 + GP_REG_FIRST }, \ 280710d565efSmrg { "ra", 31 + GP_REG_FIRST }, \ 280810d565efSmrg { "$w0", 0 + FP_REG_FIRST }, \ 280910d565efSmrg { "$w1", 1 + FP_REG_FIRST }, \ 281010d565efSmrg { "$w2", 2 + FP_REG_FIRST }, \ 281110d565efSmrg { "$w3", 3 + FP_REG_FIRST }, \ 281210d565efSmrg { "$w4", 4 + FP_REG_FIRST }, \ 281310d565efSmrg { "$w5", 5 + FP_REG_FIRST }, \ 281410d565efSmrg { "$w6", 6 + FP_REG_FIRST }, \ 281510d565efSmrg { "$w7", 7 + FP_REG_FIRST }, \ 281610d565efSmrg { "$w8", 8 + FP_REG_FIRST }, \ 281710d565efSmrg { "$w9", 9 + FP_REG_FIRST }, \ 281810d565efSmrg { "$w10", 10 + FP_REG_FIRST }, \ 281910d565efSmrg { "$w11", 11 + FP_REG_FIRST }, \ 282010d565efSmrg { "$w12", 12 + FP_REG_FIRST }, \ 282110d565efSmrg { "$w13", 13 + FP_REG_FIRST }, \ 282210d565efSmrg { "$w14", 14 + FP_REG_FIRST }, \ 282310d565efSmrg { "$w15", 15 + FP_REG_FIRST }, \ 282410d565efSmrg { "$w16", 16 + FP_REG_FIRST }, \ 282510d565efSmrg { "$w17", 17 + FP_REG_FIRST }, \ 282610d565efSmrg { "$w18", 18 + FP_REG_FIRST }, \ 282710d565efSmrg { "$w19", 19 + FP_REG_FIRST }, \ 282810d565efSmrg { "$w20", 20 + FP_REG_FIRST }, \ 282910d565efSmrg { "$w21", 21 + FP_REG_FIRST }, \ 283010d565efSmrg { "$w22", 22 + FP_REG_FIRST }, \ 283110d565efSmrg { "$w23", 23 + FP_REG_FIRST }, \ 283210d565efSmrg { "$w24", 24 + FP_REG_FIRST }, \ 283310d565efSmrg { "$w25", 25 + FP_REG_FIRST }, \ 283410d565efSmrg { "$w26", 26 + FP_REG_FIRST }, \ 283510d565efSmrg { "$w27", 27 + FP_REG_FIRST }, \ 283610d565efSmrg { "$w28", 28 + FP_REG_FIRST }, \ 283710d565efSmrg { "$w29", 29 + FP_REG_FIRST }, \ 283810d565efSmrg { "$w30", 30 + FP_REG_FIRST }, \ 283910d565efSmrg { "$w31", 31 + FP_REG_FIRST } \ 284010d565efSmrg } 284110d565efSmrg 284210d565efSmrg #define DBR_OUTPUT_SEQEND(STREAM) \ 284310d565efSmrg do \ 284410d565efSmrg { \ 284510d565efSmrg /* Undo the effect of '%*'. */ \ 284610d565efSmrg mips_pop_asm_switch (&mips_nomacro); \ 284710d565efSmrg mips_pop_asm_switch (&mips_noreorder); \ 284810d565efSmrg /* Emit a blank line after the delay slot for emphasis. */ \ 284910d565efSmrg fputs ("\n", STREAM); \ 285010d565efSmrg } \ 285110d565efSmrg while (0) 285210d565efSmrg 285310d565efSmrg /* The MIPS implementation uses some labels for its own purpose. The 285410d565efSmrg following lists what labels are created, and are all formed by the 285510d565efSmrg pattern $L[a-z].*. The machine independent portion of GCC creates 285610d565efSmrg labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 285710d565efSmrg 285810d565efSmrg LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 285910d565efSmrg $Lb[0-9]+ Begin blocks for MIPS debug support 286010d565efSmrg $Lc[0-9]+ Label for use in s<xx> operation. 286110d565efSmrg $Le[0-9]+ End blocks for MIPS debug support */ 286210d565efSmrg 286310d565efSmrg #undef ASM_DECLARE_OBJECT_NAME 286410d565efSmrg #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 286510d565efSmrg mips_declare_object (STREAM, NAME, "", ":\n") 286610d565efSmrg 286710d565efSmrg /* Globalizing directive for a label. */ 286810d565efSmrg #define GLOBAL_ASM_OP "\t.globl\t" 286910d565efSmrg 287010d565efSmrg /* This says how to define a global common symbol. */ 287110d565efSmrg 287210d565efSmrg #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 287310d565efSmrg 287410d565efSmrg /* This says how to define a local common symbol (i.e., not visible to 287510d565efSmrg linker). */ 287610d565efSmrg 287710d565efSmrg #ifndef ASM_OUTPUT_ALIGNED_LOCAL 287810d565efSmrg #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 287910d565efSmrg mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 288010d565efSmrg #endif 288110d565efSmrg 288210d565efSmrg /* This says how to output an external. It would be possible not to 288310d565efSmrg output anything and let undefined symbol become external. However 288410d565efSmrg the assembler uses length information on externals to allocate in 288510d565efSmrg data/sdata bss/sbss, thereby saving exec time. */ 288610d565efSmrg 288710d565efSmrg #undef ASM_OUTPUT_EXTERNAL 288810d565efSmrg #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 288910d565efSmrg mips_output_external(STREAM,DECL,NAME) 289010d565efSmrg 289110d565efSmrg /* This is how to declare a function name. The actual work of 289210d565efSmrg emitting the label is moved to function_prologue, so that we can 289310d565efSmrg get the line number correctly emitted before the .ent directive, 289410d565efSmrg and after any .file directives. Define as empty so that the function 289510d565efSmrg is not declared before the .ent directive elsewhere. */ 289610d565efSmrg 289710d565efSmrg #undef ASM_DECLARE_FUNCTION_NAME 289810d565efSmrg #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 289910d565efSmrg 290010d565efSmrg /* This is how to store into the string LABEL 290110d565efSmrg the symbol_ref name of an internal numbered label where 290210d565efSmrg PREFIX is the class of label and NUM is the number within the class. 290310d565efSmrg This is suitable for output with `assemble_name'. */ 290410d565efSmrg 290510d565efSmrg #undef ASM_GENERATE_INTERNAL_LABEL 290610d565efSmrg #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 290710d565efSmrg sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 290810d565efSmrg 290910d565efSmrg /* Print debug labels as "foo = ." rather than "foo:" because they should 291010d565efSmrg represent a byte pointer rather than an ISA-encoded address. This is 291110d565efSmrg particularly important for code like: 291210d565efSmrg 291310d565efSmrg $LFBxxx = . 291410d565efSmrg .cfi_startproc 291510d565efSmrg ... 291610d565efSmrg .section .gcc_except_table,... 291710d565efSmrg ... 291810d565efSmrg .uleb128 foo-$LFBxxx 291910d565efSmrg 292010d565efSmrg The .uleb128 requies $LFBxxx to match the FDE start address, which is 292110d565efSmrg likewise a byte pointer rather than an ISA-encoded address. 292210d565efSmrg 292310d565efSmrg At the time of writing, this hook is not used for the function end 292410d565efSmrg label: 292510d565efSmrg 292610d565efSmrg $LFExxx: 292710d565efSmrg .end foo 292810d565efSmrg 292910d565efSmrg But this doesn't matter, because GAS doesn't treat a pre-.end label 293010d565efSmrg as a MIPS16 one anyway. */ 293110d565efSmrg 293210d565efSmrg #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 293310d565efSmrg fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) 293410d565efSmrg 293510d565efSmrg /* This is how to output an element of a case-vector that is absolute. */ 293610d565efSmrg 293710d565efSmrg #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 293810d565efSmrg fprintf (STREAM, "\t%s\t%sL%d\n", \ 293910d565efSmrg ptr_mode == DImode ? ".dword" : ".word", \ 294010d565efSmrg LOCAL_LABEL_PREFIX, \ 294110d565efSmrg VALUE) 294210d565efSmrg 294310d565efSmrg /* This is how to output an element of a case-vector. We can make the 294410d565efSmrg entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 294510d565efSmrg is supported. */ 294610d565efSmrg 294710d565efSmrg #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 294810d565efSmrg do { \ 294910d565efSmrg if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ 295010d565efSmrg { \ 295110d565efSmrg if (GET_MODE (BODY) == HImode) \ 295210d565efSmrg fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 295310d565efSmrg LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 295410d565efSmrg else \ 295510d565efSmrg fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 295610d565efSmrg LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 295710d565efSmrg } \ 295810d565efSmrg else if (TARGET_GPWORD) \ 295910d565efSmrg fprintf (STREAM, "\t%s\t%sL%d\n", \ 296010d565efSmrg ptr_mode == DImode ? ".gpdword" : ".gpword", \ 296110d565efSmrg LOCAL_LABEL_PREFIX, VALUE); \ 296210d565efSmrg else if (TARGET_RTP_PIC) \ 296310d565efSmrg { \ 296410d565efSmrg /* Make the entry relative to the start of the function. */ \ 296510d565efSmrg rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ 296610d565efSmrg fprintf (STREAM, "\t%s\t%sL%d-", \ 296710d565efSmrg Pmode == DImode ? ".dword" : ".word", \ 296810d565efSmrg LOCAL_LABEL_PREFIX, VALUE); \ 296910d565efSmrg assemble_name (STREAM, XSTR (fnsym, 0)); \ 297010d565efSmrg fprintf (STREAM, "\n"); \ 297110d565efSmrg } \ 297210d565efSmrg else \ 297310d565efSmrg fprintf (STREAM, "\t%s\t%sL%d\n", \ 297410d565efSmrg ptr_mode == DImode ? ".dword" : ".word", \ 297510d565efSmrg LOCAL_LABEL_PREFIX, VALUE); \ 297610d565efSmrg } while (0) 297710d565efSmrg 297810d565efSmrg /* Mark inline jump tables as data for the purpose of disassembly. For 297910d565efSmrg simplicity embed the jump table's label number in the local symbol 298010d565efSmrg produced so that multiple jump tables within a single function end 298110d565efSmrg up marked with unique symbols. Retain the alignment setting from 298210d565efSmrg `elfos.h' as we are replacing the definition from there. */ 298310d565efSmrg 298410d565efSmrg #undef ASM_OUTPUT_BEFORE_CASE_LABEL 298510d565efSmrg #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \ 298610d565efSmrg do \ 298710d565efSmrg { \ 298810d565efSmrg ASM_OUTPUT_ALIGN ((STREAM), 2); \ 298910d565efSmrg if (JUMP_TABLES_IN_TEXT_SECTION) \ 299010d565efSmrg mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \ 299110d565efSmrg } \ 2992c7a68eb7Smrg while (0) 299310d565efSmrg 299410d565efSmrg /* Reset text marking to code after an inline jump table. Like with 299510d565efSmrg the beginning of a jump table use the label number to keep symbols 299610d565efSmrg unique. */ 299710d565efSmrg 299810d565efSmrg #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \ 299910d565efSmrg do \ 300010d565efSmrg if (JUMP_TABLES_IN_TEXT_SECTION) \ 300110d565efSmrg mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \ 3002c7a68eb7Smrg while (0) 300310d565efSmrg 300410d565efSmrg /* This is how to output an assembler line 300510d565efSmrg that says to advance the location counter 300610d565efSmrg to a multiple of 2**LOG bytes. */ 300710d565efSmrg 300810d565efSmrg #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 300910d565efSmrg fprintf (STREAM, "\t.align\t%d\n", (LOG)) 301010d565efSmrg 301110d565efSmrg /* This is how to output an assembler line to advance the location 301210d565efSmrg counter by SIZE bytes. */ 301310d565efSmrg 301410d565efSmrg #undef ASM_OUTPUT_SKIP 301510d565efSmrg #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 301610d565efSmrg fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 301710d565efSmrg 301810d565efSmrg /* This is how to output a string. */ 301910d565efSmrg #undef ASM_OUTPUT_ASCII 302010d565efSmrg #define ASM_OUTPUT_ASCII mips_output_ascii 302110d565efSmrg 302210d565efSmrg 302310d565efSmrg /* Default to -G 8 */ 302410d565efSmrg #ifndef MIPS_DEFAULT_GVALUE 302510d565efSmrg #define MIPS_DEFAULT_GVALUE 8 302610d565efSmrg #endif 302710d565efSmrg 302810d565efSmrg /* Define the strings to put out for each section in the object file. */ 302910d565efSmrg #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 303010d565efSmrg #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 303110d565efSmrg 303210d565efSmrg #undef READONLY_DATA_SECTION_ASM_OP 303310d565efSmrg #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 303410d565efSmrg 303510d565efSmrg #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 303610d565efSmrg do \ 303710d565efSmrg { \ 303810d565efSmrg fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 303910d565efSmrg TARGET_64BIT ? "daddiu" : "addiu", \ 304010d565efSmrg reg_names[STACK_POINTER_REGNUM], \ 304110d565efSmrg reg_names[STACK_POINTER_REGNUM], \ 304210d565efSmrg TARGET_64BIT ? "sd" : "sw", \ 304310d565efSmrg reg_names[REGNO], \ 304410d565efSmrg reg_names[STACK_POINTER_REGNUM]); \ 304510d565efSmrg } \ 304610d565efSmrg while (0) 304710d565efSmrg 304810d565efSmrg #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 304910d565efSmrg do \ 305010d565efSmrg { \ 305110d565efSmrg mips_push_asm_switch (&mips_noreorder); \ 305210d565efSmrg fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 305310d565efSmrg TARGET_64BIT ? "ld" : "lw", \ 305410d565efSmrg reg_names[REGNO], \ 305510d565efSmrg reg_names[STACK_POINTER_REGNUM], \ 305610d565efSmrg TARGET_64BIT ? "daddu" : "addu", \ 305710d565efSmrg reg_names[STACK_POINTER_REGNUM], \ 305810d565efSmrg reg_names[STACK_POINTER_REGNUM]); \ 305910d565efSmrg mips_pop_asm_switch (&mips_noreorder); \ 306010d565efSmrg } \ 306110d565efSmrg while (0) 306210d565efSmrg 306310d565efSmrg /* How to start an assembler comment. 306410d565efSmrg The leading space is important (the mips native assembler requires it). */ 306510d565efSmrg #ifndef ASM_COMMENT_START 306610d565efSmrg #define ASM_COMMENT_START " #" 306710d565efSmrg #endif 306810d565efSmrg 306910d565efSmrg #undef SIZE_TYPE 307010d565efSmrg #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 307110d565efSmrg 307210d565efSmrg #undef PTRDIFF_TYPE 307310d565efSmrg #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 307410d565efSmrg 307510d565efSmrg /* The minimum alignment of any expanded block move. */ 307610d565efSmrg #define MIPS_MIN_MOVE_MEM_ALIGN 16 307710d565efSmrg 307810d565efSmrg /* The maximum number of bytes that can be copied by one iteration of 3079*ec02198aSmrg a cpymemsi loop; see mips_block_move_loop. */ 308010d565efSmrg #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ 308110d565efSmrg (UNITS_PER_WORD * 4) 308210d565efSmrg 308310d565efSmrg /* The maximum number of bytes that can be copied by a straight-line 3084*ec02198aSmrg implementation of cpymemsi; see mips_block_move_straight. We want 308510d565efSmrg to make sure that any loop-based implementation will iterate at 308610d565efSmrg least twice. */ 308710d565efSmrg #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ 308810d565efSmrg (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) 308910d565efSmrg 309010d565efSmrg /* The base cost of a memcpy call, for MOVE_RATIO and friends. These 309110d565efSmrg values were determined experimentally by benchmarking with CSiBE. 309210d565efSmrg In theory, the call overhead is higher for TARGET_ABICALLS (especially 309310d565efSmrg for o32 where we have to restore $gp afterwards as well as make an 309410d565efSmrg indirect call), but in practice, bumping this up higher for 309510d565efSmrg TARGET_ABICALLS doesn't make much difference to code size. */ 309610d565efSmrg 309710d565efSmrg #define MIPS_CALL_RATIO 8 309810d565efSmrg 3099*ec02198aSmrg /* Any loop-based implementation of cpymemsi will have at least 310010d565efSmrg MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory 310110d565efSmrg moves, so allow individual copies of fewer elements. 310210d565efSmrg 3103*ec02198aSmrg When cpymemsi is not available, use a value approximating 310410d565efSmrg the length of a memcpy call sequence, so that move_by_pieces 310510d565efSmrg will generate inline code if it is shorter than a function call. 310610d565efSmrg Since move_by_pieces_ninsns counts memory-to-memory moves, but 310710d565efSmrg we'll have to generate a load/store pair for each, halve the 310810d565efSmrg value of MIPS_CALL_RATIO to take that into account. */ 310910d565efSmrg 311010d565efSmrg #define MOVE_RATIO(speed) \ 3111*ec02198aSmrg (HAVE_cpymemsi \ 311210d565efSmrg ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ 311310d565efSmrg : MIPS_CALL_RATIO / 2) 311410d565efSmrg 311510d565efSmrg /* For CLEAR_RATIO, when optimizing for size, give a better estimate 311610d565efSmrg of the length of a memset call, but use the default otherwise. */ 311710d565efSmrg 311810d565efSmrg #define CLEAR_RATIO(speed)\ 311910d565efSmrg ((speed) ? 15 : MIPS_CALL_RATIO) 312010d565efSmrg 312110d565efSmrg /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 312210d565efSmrg optimizing for size adjust the ratio to account for the overhead of 312310d565efSmrg loading the constant and replicating it across the word. */ 312410d565efSmrg 312510d565efSmrg #define SET_RATIO(speed) \ 312610d565efSmrg ((speed) ? 15 : MIPS_CALL_RATIO - 2) 312710d565efSmrg 312810d565efSmrg /* Since the bits of the _init and _fini function is spread across 312910d565efSmrg many object files, each potentially with its own GP, we must assume 313010d565efSmrg we need to load our GP. We don't preserve $gp or $ra, since each 313110d565efSmrg init/fini chunk is supposed to initialize $gp, and crti/crtn 313210d565efSmrg already take care of preserving $ra and, when appropriate, $gp. */ 313310d565efSmrg #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 313410d565efSmrg #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 313510d565efSmrg asm (SECTION_OP "\n\ 313610d565efSmrg .set push\n\ 313710d565efSmrg .set nomips16\n\ 313810d565efSmrg .set noreorder\n\ 313910d565efSmrg bal 1f\n\ 314010d565efSmrg nop\n\ 314110d565efSmrg 1: .cpload $31\n\ 314210d565efSmrg .set reorder\n\ 314310d565efSmrg la $25, " USER_LABEL_PREFIX #FUNC "\n\ 314410d565efSmrg jalr $25\n\ 314510d565efSmrg .set pop\n\ 314610d565efSmrg " TEXT_SECTION_ASM_OP); 314710d565efSmrg #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32) 314810d565efSmrg #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 314910d565efSmrg asm (SECTION_OP "\n\ 315010d565efSmrg .set push\n\ 315110d565efSmrg .set nomips16\n\ 315210d565efSmrg .set noreorder\n\ 315310d565efSmrg bal 1f\n\ 315410d565efSmrg nop\n\ 315510d565efSmrg 1: .set reorder\n\ 315610d565efSmrg .cpsetup $31, $2, 1b\n\ 315710d565efSmrg la $25, " USER_LABEL_PREFIX #FUNC "\n\ 315810d565efSmrg jalr $25\n\ 315910d565efSmrg .set pop\n\ 316010d565efSmrg " TEXT_SECTION_ASM_OP); 316110d565efSmrg #elif (defined _ABI64 && _MIPS_SIM == _ABI64) 316210d565efSmrg #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 316310d565efSmrg asm (SECTION_OP "\n\ 316410d565efSmrg .set push\n\ 316510d565efSmrg .set nomips16\n\ 316610d565efSmrg .set noreorder\n\ 316710d565efSmrg bal 1f\n\ 316810d565efSmrg nop\n\ 316910d565efSmrg 1: .set reorder\n\ 317010d565efSmrg .cpsetup $31, $2, 1b\n\ 317110d565efSmrg dla $25, " USER_LABEL_PREFIX #FUNC "\n\ 317210d565efSmrg jalr $25\n\ 317310d565efSmrg .set pop\n\ 317410d565efSmrg " TEXT_SECTION_ASM_OP); 317510d565efSmrg #endif 317610d565efSmrg 317710d565efSmrg #ifndef HAVE_AS_TLS 317810d565efSmrg #define HAVE_AS_TLS 0 317910d565efSmrg #endif 318010d565efSmrg 318110d565efSmrg #ifndef HAVE_AS_NAN 318210d565efSmrg #define HAVE_AS_NAN 0 318310d565efSmrg #endif 318410d565efSmrg 318510d565efSmrg #ifndef USED_FOR_TARGET 318610d565efSmrg /* Information about ".set noFOO; ...; .set FOO" blocks. */ 318710d565efSmrg struct mips_asm_switch { 318810d565efSmrg /* The FOO in the description above. */ 318910d565efSmrg const char *name; 319010d565efSmrg 319110d565efSmrg /* The current block nesting level, or 0 if we aren't in a block. */ 319210d565efSmrg int nesting_level; 319310d565efSmrg }; 319410d565efSmrg 319510d565efSmrg extern const enum reg_class mips_regno_to_class[]; 319610d565efSmrg extern const char *current_function_file; /* filename current function is in */ 319710d565efSmrg extern int num_source_filenames; /* current .file # */ 319810d565efSmrg extern struct mips_asm_switch mips_noreorder; 319910d565efSmrg extern struct mips_asm_switch mips_nomacro; 320010d565efSmrg extern struct mips_asm_switch mips_noat; 320110d565efSmrg extern int mips_dbx_regno[]; 320210d565efSmrg extern int mips_dwarf_regno[]; 320310d565efSmrg extern bool mips_split_p[]; 320410d565efSmrg extern bool mips_split_hi_p[]; 320510d565efSmrg extern bool mips_use_pcrel_pool_p[]; 320610d565efSmrg extern const char *mips_lo_relocs[]; 320710d565efSmrg extern const char *mips_hi_relocs[]; 320810d565efSmrg extern enum processor mips_arch; /* which cpu to codegen for */ 320910d565efSmrg extern enum processor mips_tune; /* which cpu to schedule for */ 321010d565efSmrg extern int mips_isa; /* architectural level */ 321110d565efSmrg extern int mips_isa_rev; 321210d565efSmrg extern const struct mips_cpu_info *mips_arch_info; 321310d565efSmrg extern const struct mips_cpu_info *mips_tune_info; 321410d565efSmrg extern unsigned int mips_base_compression_flags; 321510d565efSmrg extern GTY(()) struct target_globals *mips16_globals; 321610d565efSmrg extern GTY(()) struct target_globals *micromips_globals; 321710d565efSmrg 321810d565efSmrg /* Information about a function's frame layout. */ 321910d565efSmrg struct GTY(()) mips_frame_info { 322010d565efSmrg /* The size of the frame in bytes. */ 322110d565efSmrg HOST_WIDE_INT total_size; 322210d565efSmrg 322310d565efSmrg /* The number of bytes allocated to variables. */ 322410d565efSmrg HOST_WIDE_INT var_size; 322510d565efSmrg 322610d565efSmrg /* The number of bytes allocated to outgoing function arguments. */ 322710d565efSmrg HOST_WIDE_INT args_size; 322810d565efSmrg 322910d565efSmrg /* The number of bytes allocated to the .cprestore slot, or 0 if there 323010d565efSmrg is no such slot. */ 323110d565efSmrg HOST_WIDE_INT cprestore_size; 323210d565efSmrg 323310d565efSmrg /* Bit X is set if the function saves or restores GPR X. */ 323410d565efSmrg unsigned int mask; 323510d565efSmrg 323610d565efSmrg /* Likewise FPR X. */ 323710d565efSmrg unsigned int fmask; 323810d565efSmrg 323910d565efSmrg /* Likewise doubleword accumulator X ($acX). */ 324010d565efSmrg unsigned int acc_mask; 324110d565efSmrg 324210d565efSmrg /* The number of GPRs, FPRs, doubleword accumulators and COP0 324310d565efSmrg registers saved. */ 324410d565efSmrg unsigned int num_gp; 324510d565efSmrg unsigned int num_fp; 324610d565efSmrg unsigned int num_acc; 324710d565efSmrg unsigned int num_cop0_regs; 324810d565efSmrg 324910d565efSmrg /* The offset of the topmost GPR, FPR, accumulator and COP0-register 325010d565efSmrg save slots from the top of the frame, or zero if no such slots are 325110d565efSmrg needed. */ 325210d565efSmrg HOST_WIDE_INT gp_save_offset; 325310d565efSmrg HOST_WIDE_INT fp_save_offset; 325410d565efSmrg HOST_WIDE_INT acc_save_offset; 325510d565efSmrg HOST_WIDE_INT cop0_save_offset; 325610d565efSmrg 325710d565efSmrg /* Likewise, but giving offsets from the bottom of the frame. */ 325810d565efSmrg HOST_WIDE_INT gp_sp_offset; 325910d565efSmrg HOST_WIDE_INT fp_sp_offset; 326010d565efSmrg HOST_WIDE_INT acc_sp_offset; 326110d565efSmrg HOST_WIDE_INT cop0_sp_offset; 326210d565efSmrg 326310d565efSmrg /* Similar, but the value passed to _mcount. */ 326410d565efSmrg HOST_WIDE_INT ra_fp_offset; 326510d565efSmrg 326610d565efSmrg /* The offset of arg_pointer_rtx from the bottom of the frame. */ 326710d565efSmrg HOST_WIDE_INT arg_pointer_offset; 326810d565efSmrg 326910d565efSmrg /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ 327010d565efSmrg HOST_WIDE_INT hard_frame_pointer_offset; 327110d565efSmrg }; 327210d565efSmrg 327310d565efSmrg /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */ 327410d565efSmrg enum mips_int_mask 327510d565efSmrg { 327610d565efSmrg INT_MASK_EIC = -1, 327710d565efSmrg INT_MASK_SW0 = 0, 327810d565efSmrg INT_MASK_SW1 = 1, 327910d565efSmrg INT_MASK_HW0 = 2, 328010d565efSmrg INT_MASK_HW1 = 3, 328110d565efSmrg INT_MASK_HW2 = 4, 328210d565efSmrg INT_MASK_HW3 = 5, 328310d565efSmrg INT_MASK_HW4 = 6, 328410d565efSmrg INT_MASK_HW5 = 7 328510d565efSmrg }; 328610d565efSmrg 328710d565efSmrg /* Enumeration to mark the existence of the shadow register set. 328810d565efSmrg SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack 328910d565efSmrg pointer. */ 329010d565efSmrg enum mips_shadow_set 329110d565efSmrg { 329210d565efSmrg SHADOW_SET_NO, 329310d565efSmrg SHADOW_SET_YES, 329410d565efSmrg SHADOW_SET_INTSTACK 329510d565efSmrg }; 329610d565efSmrg 329710d565efSmrg struct GTY(()) machine_function { 329810d565efSmrg /* The next floating-point condition-code register to allocate 329910d565efSmrg for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ 330010d565efSmrg unsigned int next_fcc; 330110d565efSmrg 330210d565efSmrg /* The register returned by mips16_gp_pseudo_reg; see there for details. */ 330310d565efSmrg rtx mips16_gp_pseudo_rtx; 330410d565efSmrg 330510d565efSmrg /* The number of extra stack bytes taken up by register varargs. 330610d565efSmrg This area is allocated by the callee at the very top of the frame. */ 330710d565efSmrg int varargs_size; 330810d565efSmrg 330910d565efSmrg /* The current frame information, calculated by mips_compute_frame_info. */ 331010d565efSmrg struct mips_frame_info frame; 331110d565efSmrg 331210d565efSmrg /* The register to use as the function's global pointer, or INVALID_REGNUM 331310d565efSmrg if the function doesn't need one. */ 331410d565efSmrg unsigned int global_pointer; 331510d565efSmrg 331610d565efSmrg /* How many instructions it takes to load a label into $AT, or 0 if 331710d565efSmrg this property hasn't yet been calculated. */ 331810d565efSmrg unsigned int load_label_num_insns; 331910d565efSmrg 332010d565efSmrg /* True if mips_adjust_insn_length should ignore an instruction's 332110d565efSmrg hazard attribute. */ 332210d565efSmrg bool ignore_hazard_length_p; 332310d565efSmrg 332410d565efSmrg /* True if the whole function is suitable for .set noreorder and 332510d565efSmrg .set nomacro. */ 332610d565efSmrg bool all_noreorder_p; 332710d565efSmrg 332810d565efSmrg /* True if the function has "inflexible" and "flexible" references 332910d565efSmrg to the global pointer. See mips_cfun_has_inflexible_gp_ref_p 333010d565efSmrg and mips_cfun_has_flexible_gp_ref_p for details. */ 333110d565efSmrg bool has_inflexible_gp_insn_p; 333210d565efSmrg bool has_flexible_gp_insn_p; 333310d565efSmrg 333410d565efSmrg /* True if the function's prologue must load the global pointer 333510d565efSmrg value into pic_offset_table_rtx and store the same value in 333610d565efSmrg the function's cprestore slot (if any). Even if this value 333710d565efSmrg is currently false, we may decide to set it to true later; 333810d565efSmrg see mips_must_initialize_gp_p () for details. */ 333910d565efSmrg bool must_initialize_gp_p; 334010d565efSmrg 334110d565efSmrg /* True if the current function must restore $gp after any potential 334210d565efSmrg clobber. This value is only meaningful during the first post-epilogue 334310d565efSmrg split_insns pass; see mips_must_initialize_gp_p () for details. */ 334410d565efSmrg bool must_restore_gp_when_clobbered_p; 334510d565efSmrg 334610d565efSmrg /* True if this is an interrupt handler. */ 334710d565efSmrg bool interrupt_handler_p; 334810d565efSmrg 334910d565efSmrg /* Records the way in which interrupts should be masked. Only used if 335010d565efSmrg interrupts are not kept masked. */ 335110d565efSmrg enum mips_int_mask int_mask; 335210d565efSmrg 335310d565efSmrg /* Records if this is an interrupt handler that uses shadow registers. */ 335410d565efSmrg enum mips_shadow_set use_shadow_register_set; 335510d565efSmrg 335610d565efSmrg /* True if this is an interrupt handler that should keep interrupts 335710d565efSmrg masked. */ 335810d565efSmrg bool keep_interrupts_masked_p; 335910d565efSmrg 336010d565efSmrg /* True if this is an interrupt handler that should use DERET 336110d565efSmrg instead of ERET. */ 336210d565efSmrg bool use_debug_exception_return_p; 336310d565efSmrg 336410d565efSmrg /* True if at least one of the formal parameters to a function must be 336510d565efSmrg written to the frame header (probably so its address can be taken). */ 336610d565efSmrg bool does_not_use_frame_header; 336710d565efSmrg 336810d565efSmrg /* True if none of the functions that are called by this function need 336910d565efSmrg stack space allocated for their arguments. */ 337010d565efSmrg bool optimize_call_stack; 337110d565efSmrg 337210d565efSmrg /* True if one of the functions calling this function may not allocate 337310d565efSmrg a frame header. */ 337410d565efSmrg bool callers_may_not_allocate_frame; 337510d565efSmrg 337610d565efSmrg /* True if GCC stored callee saved registers in the frame header. */ 337710d565efSmrg bool use_frame_header_for_callee_saved_regs; 337810d565efSmrg }; 337910d565efSmrg #endif 338010d565efSmrg 338110d565efSmrg /* Enable querying of DFA units. */ 338210d565efSmrg #define CPU_UNITS_QUERY 1 338310d565efSmrg 338410d565efSmrg #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 338510d565efSmrg mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) 338610d565efSmrg 338710d565efSmrg /* As on most targets, we want the .eh_frame section to be read-only where 338810d565efSmrg possible. And as on most targets, this means two things: 338910d565efSmrg 339010d565efSmrg (a) Non-locally-binding pointers must have an indirect encoding, 339110d565efSmrg so that the addresses in the .eh_frame section itself become 339210d565efSmrg locally-binding. 339310d565efSmrg 339410d565efSmrg (b) A shared library's .eh_frame section must encode locally-binding 339510d565efSmrg pointers in a relative (relocation-free) form. 339610d565efSmrg 339710d565efSmrg However, MIPS has traditionally not allowed directives like: 339810d565efSmrg 339910d565efSmrg .long x-. 340010d565efSmrg 340110d565efSmrg in cases where "x" is in a different section, or is not defined in the 340210d565efSmrg same assembly file. We are therefore unable to emit the PC-relative 340310d565efSmrg form required by (b) at assembly time. 340410d565efSmrg 340510d565efSmrg Fortunately, the linker is able to convert absolute addresses into 340610d565efSmrg PC-relative addresses on our behalf. Unfortunately, only certain 340710d565efSmrg versions of the linker know how to do this for indirect pointers, 340810d565efSmrg and for personality data. We must fall back on using writable 340910d565efSmrg .eh_frame sections for shared libraries if the linker does not 341010d565efSmrg support this feature. */ 341110d565efSmrg #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 341210d565efSmrg (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) 341310d565efSmrg 341410d565efSmrg /* For switching between MIPS16 and non-MIPS16 modes. */ 341510d565efSmrg #define SWITCHABLE_TARGET 1 341610d565efSmrg 341710d565efSmrg /* Several named MIPS patterns depend on Pmode. These patterns have the 341810d565efSmrg form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode. 341910d565efSmrg Add the appropriate suffix to generator function NAME and invoke it 342010d565efSmrg with arguments ARGS. */ 342110d565efSmrg #define PMODE_INSN(NAME, ARGS) \ 342210d565efSmrg (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS) 342310d565efSmrg 342410d565efSmrg /* If we are *not* using multilibs and the default ABI is not ABI_32 we 342510d565efSmrg need to change these from /lib and /usr/lib. */ 342610d565efSmrg #if MIPS_ABI_DEFAULT == ABI_N32 342710d565efSmrg #define STANDARD_STARTFILE_PREFIX_1 "/lib32/" 342810d565efSmrg #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/" 342910d565efSmrg #elif MIPS_ABI_DEFAULT == ABI_64 343010d565efSmrg #define STANDARD_STARTFILE_PREFIX_1 "/lib64/" 343110d565efSmrg #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/" 343210d565efSmrg #endif 343310d565efSmrg 343410d565efSmrg /* Load store bonding is not supported by micromips and fix_24k. The 343510d565efSmrg performance can be degraded for those targets. Hence, do not bond for 343610d565efSmrg micromips or fix_24k. */ 343710d565efSmrg #define ENABLE_LD_ST_PAIRS \ 34380fc04c29Smrg (TARGET_LOAD_STORE_PAIRS \ 34390fc04c29Smrg && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \ 344010d565efSmrg && !TARGET_MICROMIPS && !TARGET_FIX_24K) 3441*ec02198aSmrg 3442*ec02198aSmrg #define NEED_INDICATE_EXEC_STACK 0 3443