163d1a8abSmrg /* GCC backend definitions for the Renesas RL78 processor. 2*ec02198aSmrg Copyright (C) 2011-2020 Free Software Foundation, Inc. 363d1a8abSmrg Contributed by Red Hat. 463d1a8abSmrg 563d1a8abSmrg This file is part of GCC. 663d1a8abSmrg 763d1a8abSmrg GCC is free software; you can redistribute it and/or modify it 863d1a8abSmrg under the terms of the GNU General Public License as published 963d1a8abSmrg by the Free Software Foundation; either version 3, or (at your 1063d1a8abSmrg option) any later version. 1163d1a8abSmrg 1263d1a8abSmrg GCC is distributed in the hope that it will be useful, but WITHOUT 1363d1a8abSmrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 1463d1a8abSmrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 1563d1a8abSmrg License for more details. 1663d1a8abSmrg 1763d1a8abSmrg You should have received a copy of the GNU General Public License 1863d1a8abSmrg along with GCC; see the file COPYING3. If not see 1963d1a8abSmrg <http://www.gnu.org/licenses/>. */ 2063d1a8abSmrg 2163d1a8abSmrg 2263d1a8abSmrg #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE) 2363d1a8abSmrg #define RL78_MUL_G13 (rl78_mul_type == MUL_G13) 2463d1a8abSmrg #define RL78_MUL_G14 (rl78_mul_type == MUL_G14) 2563d1a8abSmrg 2663d1a8abSmrg #define TARGET_G10 (rl78_cpu_type == CPU_G10) 2763d1a8abSmrg #define TARGET_G13 (rl78_cpu_type == CPU_G13) 2863d1a8abSmrg #define TARGET_G14 (rl78_cpu_type == CPU_G14) 2963d1a8abSmrg 3063d1a8abSmrg #define TARGET_CPU_CPP_BUILTINS() \ 3163d1a8abSmrg do \ 3263d1a8abSmrg { \ 3363d1a8abSmrg builtin_define ("__RL78__"); \ 3463d1a8abSmrg builtin_assert ("cpu=RL78"); \ 3563d1a8abSmrg \ 3663d1a8abSmrg if (RL78_MUL_NONE) \ 3763d1a8abSmrg builtin_define ("__RL78_MUL_NONE__"); \ 3863d1a8abSmrg else if (RL78_MUL_G13) \ 3963d1a8abSmrg builtin_define ("__RL78_MUL_G13__"); \ 4063d1a8abSmrg else if (RL78_MUL_G14) \ 4163d1a8abSmrg builtin_define ("__RL78_MUL_G14__"); \ 4263d1a8abSmrg \ 4363d1a8abSmrg if (TARGET_G10) \ 4463d1a8abSmrg builtin_define ("__RL78_G10__"); \ 4563d1a8abSmrg else if (TARGET_G13) \ 4663d1a8abSmrg builtin_define ("__RL78_G13__"); \ 4763d1a8abSmrg else if (TARGET_G14) \ 4863d1a8abSmrg builtin_define ("__RL78_G14__"); \ 4963d1a8abSmrg } \ 5063d1a8abSmrg while (0) 5163d1a8abSmrg 5263d1a8abSmrg #undef STARTFILE_SPEC 5363d1a8abSmrg #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s" 5463d1a8abSmrg 5563d1a8abSmrg #undef ENDFILE_SPEC 5663d1a8abSmrg #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 5763d1a8abSmrg 5863d1a8abSmrg #undef ASM_SPEC 5963d1a8abSmrg #define ASM_SPEC "\ 6063d1a8abSmrg %{mrelax:-relax} \ 6163d1a8abSmrg %{mg10:--mg10} \ 6263d1a8abSmrg %{mg13:--mg13} \ 6363d1a8abSmrg %{mg14:--mg14} \ 6463d1a8abSmrg %{mrl78:--mg14} \ 6563d1a8abSmrg %{mcpu=g10:--mg10} \ 6663d1a8abSmrg %{mcpu=g13:--mg13} \ 6763d1a8abSmrg %{mcpu=g14:--mg14} \ 6863d1a8abSmrg %{mcpu=rl78:--mg14} \ 6963d1a8abSmrg " 7063d1a8abSmrg 7163d1a8abSmrg #undef LINK_SPEC 7263d1a8abSmrg #define LINK_SPEC "\ 7363d1a8abSmrg %{mrelax:-relax} \ 7463d1a8abSmrg %{!r:--gc-sections} \ 7563d1a8abSmrg " 7663d1a8abSmrg 7763d1a8abSmrg #undef LIB_SPEC 7863d1a8abSmrg #define LIB_SPEC " \ 7963d1a8abSmrg --start-group \ 8063d1a8abSmrg -lc \ 8163d1a8abSmrg -lsim \ 8263d1a8abSmrg %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \ 8363d1a8abSmrg --end-group \ 8463d1a8abSmrg %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \ 8563d1a8abSmrg " 8663d1a8abSmrg 8763d1a8abSmrg 8863d1a8abSmrg #define BITS_BIG_ENDIAN 0 8963d1a8abSmrg #define BYTES_BIG_ENDIAN 0 9063d1a8abSmrg #define WORDS_BIG_ENDIAN 0 9163d1a8abSmrg 9263d1a8abSmrg #ifdef IN_LIBGCC2 9363d1a8abSmrg /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */ 9463d1a8abSmrg #define UNITS_PER_WORD 4 9563d1a8abSmrg /* We have a problem with libgcc2. It only defines two versions of 9663d1a8abSmrg each function, one for "int" and one for "long long". Ie it assumes 9763d1a8abSmrg that "sizeof (int) == sizeof (long)". For the RL78 this is not true 9863d1a8abSmrg and we need a third set of functions. We explicitly define 9963d1a8abSmrg LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting 10063d1a8abSmrg to get the SI and DI versions from the libgcc2.c sources, and we 10163d1a8abSmrg provide our own set of HI functions, which is why this 10263d1a8abSmrg definition is surrounded by #ifndef..#endif. */ 10363d1a8abSmrg #ifndef LIBGCC2_UNITS_PER_WORD 10463d1a8abSmrg #define LIBGCC2_UNITS_PER_WORD 4 10563d1a8abSmrg #endif 10663d1a8abSmrg #else 10763d1a8abSmrg /* Actual width of a word, in units (bytes). */ 10863d1a8abSmrg #define UNITS_PER_WORD 1 10963d1a8abSmrg #endif 11063d1a8abSmrg 11163d1a8abSmrg #define SHORT_TYPE_SIZE 16 11263d1a8abSmrg #define INT_TYPE_SIZE 16 11363d1a8abSmrg #define LONG_TYPE_SIZE 32 11463d1a8abSmrg #define LONG_LONG_TYPE_SIZE 64 11563d1a8abSmrg 11663d1a8abSmrg #define FLOAT_TYPE_SIZE 32 11763d1a8abSmrg #define DOUBLE_TYPE_SIZE 32 /*64*/ 11863d1a8abSmrg #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/ 11963d1a8abSmrg 12063d1a8abSmrg #define DEFAULT_SIGNED_CHAR 0 12163d1a8abSmrg 12263d1a8abSmrg #define STRICT_ALIGNMENT 1 12363d1a8abSmrg #define FUNCTION_BOUNDARY 8 12463d1a8abSmrg #define BIGGEST_ALIGNMENT 16 12563d1a8abSmrg #define STACK_BOUNDARY 16 12663d1a8abSmrg #define PARM_BOUNDARY 16 12763d1a8abSmrg 12863d1a8abSmrg #define STACK_GROWS_DOWNWARD 1 12963d1a8abSmrg #define FRAME_GROWS_DOWNWARD 1 13063d1a8abSmrg #define FIRST_PARM_OFFSET(FNDECL) 0 13163d1a8abSmrg 13263d1a8abSmrg #define MAX_REGS_PER_ADDRESS 1 13363d1a8abSmrg 13463d1a8abSmrg #define Pmode HImode 13563d1a8abSmrg #define POINTER_SIZE 16 13663d1a8abSmrg #undef SIZE_TYPE 13763d1a8abSmrg #define SIZE_TYPE "unsigned int" 13863d1a8abSmrg #undef PTRDIFF_TYPE 13963d1a8abSmrg #define PTRDIFF_TYPE "int" 14063d1a8abSmrg #undef WCHAR_TYPE 14163d1a8abSmrg #define WCHAR_TYPE "long int" 14263d1a8abSmrg #undef WCHAR_TYPE_SIZE 14363d1a8abSmrg #define WCHAR_TYPE_SIZE BITS_PER_WORD 14463d1a8abSmrg #define POINTERS_EXTEND_UNSIGNED 1 14563d1a8abSmrg #define FUNCTION_MODE HImode 14663d1a8abSmrg #define CASE_VECTOR_MODE Pmode 14763d1a8abSmrg #define WORD_REGISTER_OPERATIONS 1 14863d1a8abSmrg #define HAS_LONG_COND_BRANCH 0 14963d1a8abSmrg #define HAS_LONG_UNCOND_BRANCH 0 15063d1a8abSmrg 15163d1a8abSmrg #define MOVE_MAX 2 15263d1a8abSmrg 15363d1a8abSmrg #define ADDR_SPACE_NEAR 1 15463d1a8abSmrg #define ADDR_SPACE_FAR 2 15563d1a8abSmrg 15663d1a8abSmrg #define HAVE_PRE_DECCREMENT 0 15763d1a8abSmrg #define HAVE_POST_INCREMENT 0 15863d1a8abSmrg 15963d1a8abSmrg #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16) 16063d1a8abSmrg #define SLOW_BYTE_ACCESS 0 16163d1a8abSmrg 16263d1a8abSmrg #define STORE_FLAG_VALUE 1 16363d1a8abSmrg #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 16463d1a8abSmrg 16563d1a8abSmrg 16663d1a8abSmrg /* The RL78 has four register banks. Normal operation uses RB0 as 16763d1a8abSmrg real registers, RB1 and RB2 as "virtual" registers (because we know 16863d1a8abSmrg they'll be there, and not used as variables), and RB3 is reserved 16963d1a8abSmrg for interrupt handlers. The virtual registers are accessed as 17063d1a8abSmrg SADDRs: 17163d1a8abSmrg 17263d1a8abSmrg FFEE0-FFEE7 RB0 17363d1a8abSmrg FFEE8-FFEEF RB1 17463d1a8abSmrg FFEF0-FFEF7 RB2 17563d1a8abSmrg FFEF8-FFEFF RB3 17663d1a8abSmrg */ 17763d1a8abSmrg #define REGISTER_NAMES \ 17863d1a8abSmrg { \ 17963d1a8abSmrg "x", "a", "c", "b", "e", "d", "l", "h", \ 18063d1a8abSmrg "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 18163d1a8abSmrg "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 18263d1a8abSmrg "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 18363d1a8abSmrg "sp", "ap", "psw", "es", "cs" \ 18463d1a8abSmrg } 18563d1a8abSmrg 18663d1a8abSmrg #define ADDITIONAL_REGISTER_NAMES \ 18763d1a8abSmrg { \ 18863d1a8abSmrg { "ax", 0 }, \ 18963d1a8abSmrg { "bc", 2 }, \ 19063d1a8abSmrg { "de", 4 }, \ 19163d1a8abSmrg { "hl", 6 }, \ 19263d1a8abSmrg { "rp0", 0 }, \ 19363d1a8abSmrg { "rp1", 2 }, \ 19463d1a8abSmrg { "rp2", 4 }, \ 19563d1a8abSmrg { "rp3", 6 }, \ 19663d1a8abSmrg { "r0", 0 }, \ 19763d1a8abSmrg { "r1", 1 }, \ 19863d1a8abSmrg { "r2", 2 }, \ 19963d1a8abSmrg { "r3", 3 }, \ 20063d1a8abSmrg { "r4", 4 }, \ 20163d1a8abSmrg { "r5", 5 }, \ 20263d1a8abSmrg { "r6", 6 }, \ 20363d1a8abSmrg { "r7", 7 }, \ 20463d1a8abSmrg } 20563d1a8abSmrg 20663d1a8abSmrg enum reg_class 20763d1a8abSmrg { 20863d1a8abSmrg NO_REGS, /* No registers in set. */ 20963d1a8abSmrg XREG, 21063d1a8abSmrg AREG, 21163d1a8abSmrg AXREG, 21263d1a8abSmrg CREG, 21363d1a8abSmrg BREG, 21463d1a8abSmrg BCREG, 21563d1a8abSmrg EREG, 21663d1a8abSmrg DREG, 21763d1a8abSmrg DEREG, 21863d1a8abSmrg LREG, 21963d1a8abSmrg HREG, 22063d1a8abSmrg HLREG, 22163d1a8abSmrg IDX_REGS, 22263d1a8abSmrg QI_REGS, 22363d1a8abSmrg SPREG, 22463d1a8abSmrg R8W_REGS, 22563d1a8abSmrg R10W_REGS, 22663d1a8abSmrg INT_REGS, 22763d1a8abSmrg V_REGS, /* Virtual registers. */ 22863d1a8abSmrg GR_REGS, /* Integer registers. */ 22963d1a8abSmrg PSWREG, 23063d1a8abSmrg ALL_REGS, /* All registers. */ 23163d1a8abSmrg LIM_REG_CLASSES /* Max value + 1. */ 23263d1a8abSmrg }; 23363d1a8abSmrg 23463d1a8abSmrg #define REG_CLASS_NAMES \ 23563d1a8abSmrg { \ 23663d1a8abSmrg "NO_REGS", \ 23763d1a8abSmrg "XREG", \ 23863d1a8abSmrg "AREG", \ 23963d1a8abSmrg "AXREG", \ 24063d1a8abSmrg "CREG", \ 24163d1a8abSmrg "BREG", \ 24263d1a8abSmrg "BCREG", \ 24363d1a8abSmrg "EREG", \ 24463d1a8abSmrg "DREG", \ 24563d1a8abSmrg "DEREG", \ 24663d1a8abSmrg "LREG", \ 24763d1a8abSmrg "HREG", \ 24863d1a8abSmrg "HLREG", \ 24963d1a8abSmrg "IDX_REGS", \ 25063d1a8abSmrg "QI_REGS", \ 25163d1a8abSmrg "SPREG", \ 25263d1a8abSmrg "R8W_REGS", \ 25363d1a8abSmrg "R10W_REGS", \ 25463d1a8abSmrg "INT_REGS", \ 25563d1a8abSmrg "V_REGS", \ 25663d1a8abSmrg "GR_REGS", \ 25763d1a8abSmrg "PSWREG", \ 25863d1a8abSmrg "ALL_REGS" \ 25963d1a8abSmrg } 26063d1a8abSmrg 26163d1a8abSmrg /* Note that no class may include the second register in $fp, because 26263d1a8abSmrg we treat $fp as a single HImode register. */ 26363d1a8abSmrg #define REG_CLASS_CONTENTS \ 26463d1a8abSmrg { \ 26563d1a8abSmrg { 0x00000000, 0x00000000 }, /* No registers, */ \ 26663d1a8abSmrg { 0x00000001, 0x00000000 }, \ 26763d1a8abSmrg { 0x00000002, 0x00000000 }, \ 26863d1a8abSmrg { 0x00000003, 0x00000000 }, \ 26963d1a8abSmrg { 0x00000004, 0x00000000 }, \ 27063d1a8abSmrg { 0x00000008, 0x00000000 }, \ 27163d1a8abSmrg { 0x0000000c, 0x00000000 }, \ 27263d1a8abSmrg { 0x00000010, 0x00000000 }, \ 27363d1a8abSmrg { 0x00000020, 0x00000000 }, \ 27463d1a8abSmrg { 0x00000030, 0x00000000 }, \ 27563d1a8abSmrg { 0x00000040, 0x00000000 }, \ 27663d1a8abSmrg { 0x00000080, 0x00000000 }, \ 27763d1a8abSmrg { 0x000000c0, 0x00000000 }, \ 27863d1a8abSmrg { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \ 27963d1a8abSmrg { 0x000000ff, 0x00000000 }, /* all real registers. */ \ 28063d1a8abSmrg { 0x00000000, 0x00000001 }, /* SP */ \ 28163d1a8abSmrg { 0x00000300, 0x00000000 }, /* R8 - HImode */ \ 28263d1a8abSmrg { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \ 28363d1a8abSmrg { 0xff000000, 0x00000000 }, /* INT - HImode */ \ 28463d1a8abSmrg { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \ 28563d1a8abSmrg { 0xff7fff00, 0x00000002 }, /* General registers. */ \ 28663d1a8abSmrg { 0x04000000, 0x00000004 }, /* PSW. */ \ 28763d1a8abSmrg { 0xff7fffff, 0x0000001f } /* All registers. */ \ 28863d1a8abSmrg } 28963d1a8abSmrg 29063d1a8abSmrg #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 29163d1a8abSmrg #define N_REG_CLASSES (int) LIM_REG_CLASSES 29263d1a8abSmrg #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \ 29363d1a8abSmrg + UNITS_PER_WORD - 1) \ 29463d1a8abSmrg / UNITS_PER_WORD) 29563d1a8abSmrg 29663d1a8abSmrg #define GENERAL_REGS GR_REGS 29763d1a8abSmrg #define BASE_REG_CLASS V_REGS 29863d1a8abSmrg #define INDEX_REG_CLASS V_REGS 29963d1a8abSmrg 30063d1a8abSmrg #define FIRST_PSEUDO_REGISTER 37 30163d1a8abSmrg 30263d1a8abSmrg #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \ 30363d1a8abSmrg ? GR_REGS : NO_REGS) 30463d1a8abSmrg 30563d1a8abSmrg #define FRAME_POINTER_REGNUM 22 30663d1a8abSmrg #define STACK_POINTER_REGNUM 32 30763d1a8abSmrg #define ARG_POINTER_REGNUM 33 30863d1a8abSmrg #define CC_REGNUM 34 30963d1a8abSmrg #define FUNC_RETURN_REGNUM 8 31063d1a8abSmrg #define STATIC_CHAIN_REGNUM 14 31163d1a8abSmrg 31263d1a8abSmrg /* Trampolines are implemented with a separate data stack. The memory 31363d1a8abSmrg on stack only holds the function pointer for the chosen stub. 31463d1a8abSmrg */ 31563d1a8abSmrg 31663d1a8abSmrg #define TRAMPOLINE_SIZE 4 31763d1a8abSmrg #define TRAMPOLINE_ALIGNMENT 16 31863d1a8abSmrg 31963d1a8abSmrg #define ELIMINABLE_REGS \ 32063d1a8abSmrg {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 32163d1a8abSmrg { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 32263d1a8abSmrg { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 32363d1a8abSmrg 32463d1a8abSmrg #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 32563d1a8abSmrg (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO)) 32663d1a8abSmrg 32763d1a8abSmrg 32863d1a8abSmrg #define FUNCTION_ARG_REGNO_P(N) 0 32963d1a8abSmrg #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8) 33063d1a8abSmrg #define DEFAULT_PCC_STRUCT_RETURN 0 33163d1a8abSmrg 33263d1a8abSmrg #define FIXED_REGISTERS \ 33363d1a8abSmrg { \ 33463d1a8abSmrg 1,1,1,1, 1,1,1,1, \ 33563d1a8abSmrg 0,0,0,0, 0,0,0,0, \ 33663d1a8abSmrg 0,0,0,0, 0,0,1,1, \ 33763d1a8abSmrg 1,1,1,1, 1,1,1,1, \ 33863d1a8abSmrg 0, 1, 0, 1, 1 \ 33963d1a8abSmrg } 34063d1a8abSmrg 34163d1a8abSmrg #define CALL_USED_REGISTERS \ 34263d1a8abSmrg { \ 34363d1a8abSmrg 1,1,1,1, 1,1,1,1, \ 34463d1a8abSmrg 1,1,1,1, 1,1,1,1, \ 34563d1a8abSmrg 0,0,0,0, 0,0,1,1, \ 34663d1a8abSmrg 1,1,1,1, 1,1,1,1, \ 34763d1a8abSmrg 0, 1, 1, 1, 1 \ 34863d1a8abSmrg } 34963d1a8abSmrg 35063d1a8abSmrg #define LIBCALL_VALUE(MODE) \ 35163d1a8abSmrg gen_rtx_REG ((MODE), \ 35263d1a8abSmrg FUNC_RETURN_REGNUM) 35363d1a8abSmrg 35463d1a8abSmrg /* Order of allocation of registers. */ 35563d1a8abSmrg 35663d1a8abSmrg #define REG_ALLOC_ORDER \ 35763d1a8abSmrg { 8, 9, 10, 11, 12, 13, 14, 15, \ 35863d1a8abSmrg 16, 17, 18, 19, 20, 21, 22, 23, \ 35963d1a8abSmrg 0, 1, 6, 7, 2, 3, 4, 5, \ 36063d1a8abSmrg 24, 25, 26, 27, 28, 29, 30, 31, \ 36163d1a8abSmrg 32, 33, 34 \ 36263d1a8abSmrg } 36363d1a8abSmrg 36463d1a8abSmrg #define REGNO_IN_RANGE(REGNO, MIN, MAX) \ 36563d1a8abSmrg (IN_RANGE ((REGNO), (MIN), (MAX)) \ 36663d1a8abSmrg || (reg_renumber != NULL \ 36763d1a8abSmrg && reg_renumber[(REGNO)] >= (MIN) \ 36863d1a8abSmrg && reg_renumber[(REGNO)] <= (MAX))) 36963d1a8abSmrg 37063d1a8abSmrg #ifdef REG_OK_STRICT 37163d1a8abSmrg #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31) 37263d1a8abSmrg #else 37363d1a8abSmrg #define REGNO_OK_FOR_BASE_P(regno) 1 37463d1a8abSmrg #endif 37563d1a8abSmrg 37663d1a8abSmrg #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno) 37763d1a8abSmrg 37863d1a8abSmrg #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \ 37963d1a8abSmrg rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code) 38063d1a8abSmrg 38163d1a8abSmrg #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \ 38263d1a8abSmrg rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code) 38363d1a8abSmrg 38463d1a8abSmrg #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ 38563d1a8abSmrg ((COUNT) == 0 \ 38663d1a8abSmrg ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \ 38763d1a8abSmrg : NULL_RTX) 38863d1a8abSmrg 38963d1a8abSmrg #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx) 39063d1a8abSmrg 39163d1a8abSmrg #define ACCUMULATE_OUTGOING_ARGS 1 39263d1a8abSmrg 39363d1a8abSmrg typedef unsigned int CUMULATIVE_ARGS; 39463d1a8abSmrg 39563d1a8abSmrg #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 39663d1a8abSmrg (CUM) = 0 39763d1a8abSmrg 39863d1a8abSmrg 39963d1a8abSmrg /* FIXME */ 40063d1a8abSmrg #define NO_PROFILE_COUNTERS 1 40163d1a8abSmrg #define PROFILE_BEFORE_PROLOGUE 1 40263d1a8abSmrg 40363d1a8abSmrg #define FUNCTION_PROFILER(FILE, LABELNO) \ 40463d1a8abSmrg fprintf (FILE, "\tbsr\t__mcount\n"); 40563d1a8abSmrg 40663d1a8abSmrg 40763d1a8abSmrg #define TEXT_SECTION_ASM_OP ".text" 40863d1a8abSmrg #define DATA_SECTION_ASM_OP ".data" 40963d1a8abSmrg #define BSS_SECTION_ASM_OP ".bss" 41063d1a8abSmrg #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\"" 41163d1a8abSmrg #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\"" 41263d1a8abSmrg 41363d1a8abSmrg #define ASM_COMMENT_START " ;" 41463d1a8abSmrg #define ASM_APP_ON "" 41563d1a8abSmrg #define ASM_APP_OFF "" 41663d1a8abSmrg #define LOCAL_LABEL_PREFIX ".L" 41763d1a8abSmrg #undef USER_LABEL_PREFIX 41863d1a8abSmrg #define USER_LABEL_PREFIX "_" 41963d1a8abSmrg 42063d1a8abSmrg #define GLOBAL_ASM_OP "\t.global\t" 42163d1a8abSmrg 42263d1a8abSmrg #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 42363d1a8abSmrg fprintf (FILE, "\t.long .L%d\n", VALUE) 42463d1a8abSmrg 42563d1a8abSmrg /* This is how to output an element of a case-vector that is relative. 42663d1a8abSmrg Note: The local label referenced by the "3b" below is emitted by 42763d1a8abSmrg the tablejump insn. */ 42863d1a8abSmrg 42963d1a8abSmrg #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 43063d1a8abSmrg fprintf (FILE, "\t.long .L%d - 1b\n", VALUE) 43163d1a8abSmrg 43263d1a8abSmrg 43363d1a8abSmrg #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM)) 43463d1a8abSmrg 43563d1a8abSmrg #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM)) 43663d1a8abSmrg 43763d1a8abSmrg #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 43863d1a8abSmrg rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) 43963d1a8abSmrg 44063d1a8abSmrg #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 44163d1a8abSmrg rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) 44263d1a8abSmrg 44363d1a8abSmrg #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 44463d1a8abSmrg do \ 44563d1a8abSmrg { \ 44663d1a8abSmrg if ((LOG) == 0) \ 44763d1a8abSmrg break; \ 44863d1a8abSmrg fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \ 44963d1a8abSmrg } \ 45063d1a8abSmrg while (0) 45163d1a8abSmrg 45263d1a8abSmrg /* For PIC put jump tables into the text section so that the offsets that 45363d1a8abSmrg they contain are always computed between two same-section symbols. */ 45463d1a8abSmrg #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 45563d1a8abSmrg 45663d1a8abSmrg /* This is a version of REG_P that also returns TRUE for SUBREGs. */ 45763d1a8abSmrg #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG) 45863d1a8abSmrg 45963d1a8abSmrg /* Like REG_P except that this macro is true for SET expressions. */ 46063d1a8abSmrg #define SET_P(rtl) (GET_CODE (rtl) == SET) 46163d1a8abSmrg 46263d1a8abSmrg #undef PREFERRED_DEBUGGING_TYPE 46363d1a8abSmrg #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 46463d1a8abSmrg 46563d1a8abSmrg #undef DWARF2_ADDR_SIZE 46663d1a8abSmrg #define DWARF2_ADDR_SIZE 4 46763d1a8abSmrg 46863d1a8abSmrg #define DWARF2_ASM_LINE_DEBUG_INFO 1 46963d1a8abSmrg 47063d1a8abSmrg #define EXIT_IGNORE_STACK 0 47163d1a8abSmrg #define INCOMING_FRAME_SP_OFFSET 4 47263d1a8abSmrg 47363d1a8abSmrg 47463d1a8abSmrg #define BRANCH_COST(SPEED,PREDICT) 1 47563d1a8abSmrg #define REGISTER_MOVE_COST(MODE,FROM,TO) 2 47663d1a8abSmrg 47763d1a8abSmrg #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM) 47863d1a8abSmrg #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20) 47963d1a8abSmrg 48063d1a8abSmrg #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4 48163d1a8abSmrg 48263d1a8abSmrg /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */ 48363d1a8abSmrg #define DWARF2_UNWIND_INFO 0 48463d1a8abSmrg 48563d1a8abSmrg #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas() 486