110d565efSmrg;; Constraint definitions for RS6000 2*ec02198aSmrg;; Copyright (C) 2006-2020 Free Software Foundation, Inc. 310d565efSmrg;; 410d565efSmrg;; This file is part of GCC. 510d565efSmrg;; 610d565efSmrg;; GCC is free software; you can redistribute it and/or modify 710d565efSmrg;; it under the terms of the GNU General Public License as published by 810d565efSmrg;; the Free Software Foundation; either version 3, or (at your option) 910d565efSmrg;; any later version. 1010d565efSmrg;; 1110d565efSmrg;; GCC is distributed in the hope that it will be useful, 1210d565efSmrg;; but WITHOUT ANY WARRANTY; without even the implied warranty of 1310d565efSmrg;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1410d565efSmrg;; GNU General Public License for more details. 1510d565efSmrg;; 1610d565efSmrg;; You should have received a copy of the GNU General Public License 1710d565efSmrg;; along with GCC; see the file COPYING3. If not see 1810d565efSmrg;; <http://www.gnu.org/licenses/>. 1910d565efSmrg 2010d565efSmrg;; Available constraint letters: e k q t u A B C D S T 2110d565efSmrg 2210d565efSmrg;; Register constraints 2310d565efSmrg 24*ec02198aSmrg; Actually defined in common.md: 25*ec02198aSmrg; (define_register_constraint "r" "GENERAL_REGS" 26*ec02198aSmrg; "A general purpose register (GPR), @code{r0}@dots{}@code{r31}.") 2710d565efSmrg 2810d565efSmrg(define_register_constraint "b" "BASE_REGS" 29*ec02198aSmrg "A base register. Like @code{r}, but @code{r0} is not allowed, so 30*ec02198aSmrg @code{r1}@dots{}@code{r31}.") 3110d565efSmrg 32*ec02198aSmrg(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" 33*ec02198aSmrg "A floating point register (FPR), @code{f0}@dots{}@code{f31}.") 3410d565efSmrg 35*ec02198aSmrg(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" 36*ec02198aSmrg "A floating point register. This is the same as @code{f} nowadays; 37*ec02198aSmrg historically @code{f} was for single-precision and @code{d} was for 38*ec02198aSmrg double-precision floating point.") 3910d565efSmrg 4010d565efSmrg(define_register_constraint "v" "ALTIVEC_REGS" 41*ec02198aSmrg "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.") 42*ec02198aSmrg 43*ec02198aSmrg(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 44*ec02198aSmrg "A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an 45*ec02198aSmrg FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR 46*ec02198aSmrg (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}).") 47*ec02198aSmrg 48*ec02198aSmrg(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 49*ec02198aSmrg "@internal A compatibility alias for @code{wa}.") 50*ec02198aSmrg(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 51*ec02198aSmrg "@internal A compatibility alias for @code{wa}.") 52*ec02198aSmrg(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 53*ec02198aSmrg "@internal A compatibility alias for @code{wa}.") 54*ec02198aSmrg(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 55*ec02198aSmrg "@internal A compatibility alias for @code{wa}.") 56*ec02198aSmrg(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 57*ec02198aSmrg "@internal A compatibility alias for @code{wa}.") 58*ec02198aSmrg 59*ec02198aSmrg(define_register_constraint "h" "SPECIAL_REGS" 60*ec02198aSmrg "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).") 61*ec02198aSmrg 62*ec02198aSmrg(define_register_constraint "c" "CTR_REGS" 63*ec02198aSmrg "The count register, @code{ctr}.") 64*ec02198aSmrg 65*ec02198aSmrg(define_register_constraint "l" "LINK_REGS" 66*ec02198aSmrg "The link register, @code{lr}.") 6710d565efSmrg 6810d565efSmrg(define_register_constraint "x" "CR0_REGS" 69*ec02198aSmrg "Condition register field 0, @code{cr0}.") 7010d565efSmrg 7110d565efSmrg(define_register_constraint "y" "CR_REGS" 72*ec02198aSmrg "Any condition register field, @code{cr0}@dots{}@code{cr7}.") 7310d565efSmrg 7410d565efSmrg(define_register_constraint "z" "CA_REGS" 75*ec02198aSmrg "@internal The carry bit, @code{XER[CA]}.") 7610d565efSmrg 7710d565efSmrg;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. 7810d565efSmrg;; It is currently used for that purpose in LLVM. 7910d565efSmrg 8010d565efSmrg(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]" 81*ec02198aSmrg "@internal Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are 82*ec02198aSmrg used; otherwise, @code{NO_REGS}.") 8310d565efSmrg 8410d565efSmrg;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use 8510d565efSmrg;; direct move directly, and movsf can't to move between the register sets. 86*ec02198aSmrg;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode 87*ec02198aSmrg(define_register_constraint "wn" "NO_REGS" 88*ec02198aSmrg "@internal No register (@code{NO_REGS}).") 8910d565efSmrg 9010d565efSmrg(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" 91*ec02198aSmrg "@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise, 92*ec02198aSmrg @code{NO_REGS}.") 9310d565efSmrg 9410d565efSmrg(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" 95*ec02198aSmrg "@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, 96*ec02198aSmrg @code{NO_REGS}.") 9710d565efSmrg 9810d565efSmrg(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" 99*ec02198aSmrg "@internal Like @code{b}, if @option{-mpowerpc64} is used; otherwise, 100*ec02198aSmrg @code{NO_REGS}.") 10110d565efSmrg 10210d565efSmrg;; wB needs ISA 2.07 VUPKHSW 10310d565efSmrg(define_constraint "wB" 104*ec02198aSmrg "@internal Signed 5-bit constant integer that can be loaded into an 105*ec02198aSmrg Altivec register." 10610d565efSmrg (and (match_code "const_int") 107*ec02198aSmrg (match_test "TARGET_P8_VECTOR") 108*ec02198aSmrg (match_operand 0 "s5bit_cint_operand"))) 10910d565efSmrg 11010d565efSmrg(define_constraint "wD" 111*ec02198aSmrg "@internal Int constant that is the element number of the 64-bit scalar 112*ec02198aSmrg in a vector." 11310d565efSmrg (and (match_code "const_int") 11410d565efSmrg (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) 11510d565efSmrg 11610d565efSmrg(define_constraint "wE" 117*ec02198aSmrg "@internal Vector constant that can be loaded with the XXSPLTIB instruction." 11810d565efSmrg (match_test "xxspltib_constant_nosplit (op, mode)")) 11910d565efSmrg 12010d565efSmrg;; Extended fusion store 12110d565efSmrg(define_memory_constraint "wF" 122*ec02198aSmrg "@internal Memory operand suitable for power8 GPR load fusion." 12310d565efSmrg (match_operand 0 "fusion_addis_mem_combo_load")) 12410d565efSmrg 12510d565efSmrg(define_constraint "wL" 126*ec02198aSmrg "@internal Int constant that is the element number mfvsrld accesses in 127*ec02198aSmrg a vector." 12810d565efSmrg (and (match_code "const_int") 129*ec02198aSmrg (match_test "TARGET_DIRECT_MOVE_128") 130*ec02198aSmrg (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))) 13110d565efSmrg 13210d565efSmrg;; Generate the XXORC instruction to set a register to all 1's 13310d565efSmrg(define_constraint "wM" 134*ec02198aSmrg "@internal Match vector constant with all 1's if the XXLORC instruction 135*ec02198aSmrg is available." 13610d565efSmrg (and (match_test "TARGET_P8_VECTOR") 13710d565efSmrg (match_operand 0 "all_ones_constant"))) 13810d565efSmrg 13910d565efSmrg;; ISA 3.0 vector d-form addresses 14010d565efSmrg(define_memory_constraint "wO" 141*ec02198aSmrg "@internal Memory operand suitable for the ISA 3.0 vector d-form instructions." 14210d565efSmrg (match_operand 0 "vsx_quad_dform_memory_operand")) 14310d565efSmrg 14410d565efSmrg;; Lq/stq validates the address for load/store quad 14510d565efSmrg(define_memory_constraint "wQ" 146*ec02198aSmrg "@internal Memory operand suitable for the load/store quad instructions." 14710d565efSmrg (match_operand 0 "quad_memory_operand")) 14810d565efSmrg 14910d565efSmrg(define_constraint "wS" 150*ec02198aSmrg "@internal Vector constant that can be loaded with XXSPLTIB & sign extension." 15110d565efSmrg (match_test "xxspltib_constant_split (op, mode)")) 15210d565efSmrg 15310d565efSmrg;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. 15410d565efSmrg;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four 15510d565efSmrg;; offset is enforced for 32-bit too. 15610d565efSmrg(define_memory_constraint "wY" 157*ec02198aSmrg "@internal A memory operand for a DS-form instruction." 15810d565efSmrg (and (match_code "mem") 15910d565efSmrg (not (match_test "update_address_mem (op, mode)")) 16010d565efSmrg (match_test "mem_operand_ds_form (op, mode)"))) 16110d565efSmrg 16210d565efSmrg;; Altivec style load/store that ignores the bottom bits of the address 16310d565efSmrg(define_memory_constraint "wZ" 164*ec02198aSmrg "@internal An indexed or indirect memory operand, ignoring the bottom 4 bits." 16510d565efSmrg (match_operand 0 "altivec_indexed_or_indirect_operand")) 16610d565efSmrg 16710d565efSmrg;; Integer constraints 16810d565efSmrg 16910d565efSmrg(define_constraint "I" 170*ec02198aSmrg "A signed 16-bit constant." 17110d565efSmrg (and (match_code "const_int") 17210d565efSmrg (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000"))) 17310d565efSmrg 17410d565efSmrg(define_constraint "J" 175*ec02198aSmrg "An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead 176*ec02198aSmrg for @code{SImode} constants)." 17710d565efSmrg (and (match_code "const_int") 17810d565efSmrg (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) 17910d565efSmrg 18010d565efSmrg(define_constraint "K" 181*ec02198aSmrg "An unsigned 16-bit constant." 18210d565efSmrg (and (match_code "const_int") 18310d565efSmrg (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) 18410d565efSmrg 18510d565efSmrg(define_constraint "L" 186*ec02198aSmrg "A signed 16-bit constant shifted left 16 bits." 18710d565efSmrg (and (match_code "const_int") 18810d565efSmrg (match_test "((ival & 0xffff) == 0 18910d565efSmrg && (ival >> 31 == -1 || ival >> 31 == 0))"))) 19010d565efSmrg 19110d565efSmrg(define_constraint "M" 192*ec02198aSmrg "@internal A constant greater than 31." 19310d565efSmrg (and (match_code "const_int") 19410d565efSmrg (match_test "ival > 31"))) 19510d565efSmrg 19610d565efSmrg(define_constraint "N" 197*ec02198aSmrg "@internal An exact power of two." 19810d565efSmrg (and (match_code "const_int") 19910d565efSmrg (match_test "ival > 0 && exact_log2 (ival) >= 0"))) 20010d565efSmrg 20110d565efSmrg(define_constraint "O" 202*ec02198aSmrg "@internal The integer constant zero." 20310d565efSmrg (and (match_code "const_int") 20410d565efSmrg (match_test "ival == 0"))) 20510d565efSmrg 20610d565efSmrg(define_constraint "P" 207*ec02198aSmrg "@internal A constant whose negation is a signed 16-bit constant." 20810d565efSmrg (and (match_code "const_int") 20910d565efSmrg (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) 21010d565efSmrg 211*ec02198aSmrg;; 34-bit signed integer constant 212*ec02198aSmrg(define_constraint "eI" 213*ec02198aSmrg "A signed 34-bit integer constant if prefixed instructions are supported." 214*ec02198aSmrg (match_operand 0 "cint34_operand")) 215*ec02198aSmrg 2160fc04c29Smrg;; Floating-point constraints. These two are defined so that insn 2170fc04c29Smrg;; length attributes can be calculated exactly. 21810d565efSmrg 21910d565efSmrg(define_constraint "G" 220*ec02198aSmrg "@internal A floating point constant that can be loaded into a register 221*ec02198aSmrg with one instruction per word." 22210d565efSmrg (and (match_code "const_double") 22310d565efSmrg (match_test "num_insns_constant (op, mode) 2240fc04c29Smrg == (mode == SFmode || mode == SDmode ? 1 : 2)"))) 22510d565efSmrg 22610d565efSmrg(define_constraint "H" 227*ec02198aSmrg "@internal A floating point constant that can be loaded into a register 228*ec02198aSmrg using three instructions." 22910d565efSmrg (and (match_code "const_double") 23010d565efSmrg (match_test "num_insns_constant (op, mode) == 3"))) 23110d565efSmrg 23210d565efSmrg;; Memory constraints 23310d565efSmrg 234*ec02198aSmrg; Actually defined in common.md: 235*ec02198aSmrg; (define_memory_constraint "m" 236*ec02198aSmrg; "A memory operand." 237*ec02198aSmrg 23810d565efSmrg(define_memory_constraint "es" 239*ec02198aSmrg "@internal 240*ec02198aSmrg A ``stable'' memory operand; that is, one which does not include any 241*ec02198aSmrg automodification of the base register. This used to be useful when 242*ec02198aSmrg @code{m} allowed automodification of the base register, but as those 243*ec02198aSmrg are now only allowed when @code{<} or @code{>} is used, @code{es} is 244*ec02198aSmrg basically the same as @code{m} without @code{<} and @code{>}." 24510d565efSmrg (and (match_code "mem") 24610d565efSmrg (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) 24710d565efSmrg 24810d565efSmrg(define_memory_constraint "Q" 249*ec02198aSmrg "A memory operand addressed by just a base register." 25010d565efSmrg (and (match_code "mem") 2510fc04c29Smrg (match_test "REG_P (XEXP (op, 0))"))) 25210d565efSmrg 25310d565efSmrg(define_memory_constraint "Y" 254*ec02198aSmrg "@internal A memory operand for a DQ-form instruction." 25510d565efSmrg (and (match_code "mem") 25610d565efSmrg (match_test "mem_operand_gpr (op, mode)"))) 25710d565efSmrg 25810d565efSmrg(define_memory_constraint "Z" 259*ec02198aSmrg "A memory operand accessed with indexed or indirect addressing." 26010d565efSmrg (match_operand 0 "indexed_or_indirect_operand")) 26110d565efSmrg 26210d565efSmrg;; Address constraints 26310d565efSmrg 26410d565efSmrg(define_constraint "R" 265*ec02198aSmrg "@internal An AIX TOC entry." 26610d565efSmrg (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) 26710d565efSmrg 268*ec02198aSmrg(define_address_constraint "a" 269*ec02198aSmrg "An indexed or indirect address." 270*ec02198aSmrg (match_operand 0 "indexed_or_indirect_address")) 271*ec02198aSmrg 27210d565efSmrg;; General constraints 27310d565efSmrg 27410d565efSmrg(define_constraint "U" 275*ec02198aSmrg "@internal A V.4 small data reference." 27610d565efSmrg (and (match_test "DEFAULT_ABI == ABI_V4") 27710d565efSmrg (match_test "small_data_operand (op, mode)"))) 27810d565efSmrg 27910d565efSmrg(define_constraint "W" 280*ec02198aSmrg "@internal A vector constant that does not require memory." 28110d565efSmrg (match_operand 0 "easy_vector_constant")) 28210d565efSmrg 28310d565efSmrg(define_constraint "j" 284*ec02198aSmrg "@internal The zero vector constant." 28510d565efSmrg (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) 286