1*10d565efSmrg;; Constraint definitions for RS6000 2*10d565efSmrg;; Copyright (C) 2006-2017 Free Software Foundation, Inc. 3*10d565efSmrg;; 4*10d565efSmrg;; This file is part of GCC. 5*10d565efSmrg;; 6*10d565efSmrg;; GCC is free software; you can redistribute it and/or modify 7*10d565efSmrg;; it under the terms of the GNU General Public License as published by 8*10d565efSmrg;; the Free Software Foundation; either version 3, or (at your option) 9*10d565efSmrg;; any later version. 10*10d565efSmrg;; 11*10d565efSmrg;; GCC is distributed in the hope that it will be useful, 12*10d565efSmrg;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13*10d565efSmrg;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*10d565efSmrg;; GNU General Public License for more details. 15*10d565efSmrg;; 16*10d565efSmrg;; You should have received a copy of the GNU General Public License 17*10d565efSmrg;; along with GCC; see the file COPYING3. If not see 18*10d565efSmrg;; <http://www.gnu.org/licenses/>. 19*10d565efSmrg 20*10d565efSmrg;; Available constraint letters: e k q t u A B C D S T 21*10d565efSmrg 22*10d565efSmrg;; Register constraints 23*10d565efSmrg 24*10d565efSmrg(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" 25*10d565efSmrg "@internal") 26*10d565efSmrg 27*10d565efSmrg(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" 28*10d565efSmrg "@internal") 29*10d565efSmrg 30*10d565efSmrg(define_register_constraint "b" "BASE_REGS" 31*10d565efSmrg "@internal") 32*10d565efSmrg 33*10d565efSmrg(define_register_constraint "h" "SPECIAL_REGS" 34*10d565efSmrg "@internal") 35*10d565efSmrg 36*10d565efSmrg(define_register_constraint "c" "CTR_REGS" 37*10d565efSmrg "@internal") 38*10d565efSmrg 39*10d565efSmrg(define_register_constraint "l" "LINK_REGS" 40*10d565efSmrg "@internal") 41*10d565efSmrg 42*10d565efSmrg(define_register_constraint "v" "ALTIVEC_REGS" 43*10d565efSmrg "@internal") 44*10d565efSmrg 45*10d565efSmrg(define_register_constraint "x" "CR0_REGS" 46*10d565efSmrg "@internal") 47*10d565efSmrg 48*10d565efSmrg(define_register_constraint "y" "CR_REGS" 49*10d565efSmrg "@internal") 50*10d565efSmrg 51*10d565efSmrg(define_register_constraint "z" "CA_REGS" 52*10d565efSmrg "@internal") 53*10d565efSmrg 54*10d565efSmrg;; Use w as a prefix to add VSX modes 55*10d565efSmrg;; any VSX register 56*10d565efSmrg(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 57*10d565efSmrg "Any VSX register if the -mvsx option was used or NO_REGS.") 58*10d565efSmrg 59*10d565efSmrg(define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]" 60*10d565efSmrg "Altivec register if the -mpower9-dform option was used or NO_REGS.") 61*10d565efSmrg 62*10d565efSmrg;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. 63*10d565efSmrg;; It is currently used for that purpose in LLVM. 64*10d565efSmrg 65*10d565efSmrg(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" 66*10d565efSmrg "VSX vector register to hold vector double data or NO_REGS.") 67*10d565efSmrg 68*10d565efSmrg(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]" 69*10d565efSmrg "VSX register if the -mpower9-vector -m64 options were used or NO_REGS.") 70*10d565efSmrg 71*10d565efSmrg(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" 72*10d565efSmrg "VSX vector register to hold vector float data or NO_REGS.") 73*10d565efSmrg 74*10d565efSmrg(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" 75*10d565efSmrg "If -mmfpgpr was used, a floating point register or NO_REGS.") 76*10d565efSmrg 77*10d565efSmrg(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" 78*10d565efSmrg "Floating point register if direct moves are available, or NO_REGS.") 79*10d565efSmrg 80*10d565efSmrg(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" 81*10d565efSmrg "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") 82*10d565efSmrg 83*10d565efSmrg(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" 84*10d565efSmrg "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") 85*10d565efSmrg 86*10d565efSmrg(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" 87*10d565efSmrg "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") 88*10d565efSmrg 89*10d565efSmrg(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" 90*10d565efSmrg "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") 91*10d565efSmrg 92*10d565efSmrg(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" 93*10d565efSmrg "VSX register if direct move instructions are enabled, or NO_REGS.") 94*10d565efSmrg 95*10d565efSmrg;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use 96*10d565efSmrg;; direct move directly, and movsf can't to move between the register sets. 97*10d565efSmrg;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode 98*10d565efSmrg(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") 99*10d565efSmrg 100*10d565efSmrg(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]" 101*10d565efSmrg "VSX register if the -mpower9-vector option was used or NO_REGS.") 102*10d565efSmrg 103*10d565efSmrg(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]" 104*10d565efSmrg "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.") 105*10d565efSmrg 106*10d565efSmrg(define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]" 107*10d565efSmrg "VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.") 108*10d565efSmrg 109*10d565efSmrg(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" 110*10d565efSmrg "General purpose register if 64-bit instructions are enabled or NO_REGS.") 111*10d565efSmrg 112*10d565efSmrg(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" 113*10d565efSmrg "VSX vector register to hold scalar double values or NO_REGS.") 114*10d565efSmrg 115*10d565efSmrg(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" 116*10d565efSmrg "VSX vector register to hold 128 bit integer or NO_REGS.") 117*10d565efSmrg 118*10d565efSmrg(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" 119*10d565efSmrg "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") 120*10d565efSmrg 121*10d565efSmrg(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" 122*10d565efSmrg "Altivec register to use for double loads/stores or NO_REGS.") 123*10d565efSmrg 124*10d565efSmrg(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" 125*10d565efSmrg "FP or VSX register to perform float operations under -mvsx or NO_REGS.") 126*10d565efSmrg 127*10d565efSmrg(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" 128*10d565efSmrg "Floating point register if the STFIWX instruction is enabled or NO_REGS.") 129*10d565efSmrg 130*10d565efSmrg(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" 131*10d565efSmrg "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") 132*10d565efSmrg 133*10d565efSmrg(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" 134*10d565efSmrg "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") 135*10d565efSmrg 136*10d565efSmrg(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" 137*10d565efSmrg "BASE_REGS if 64-bit instructions are enabled or NO_REGS.") 138*10d565efSmrg 139*10d565efSmrg;; wB needs ISA 2.07 VUPKHSW 140*10d565efSmrg(define_constraint "wB" 141*10d565efSmrg "Signed 5-bit constant integer that can be loaded into an altivec register." 142*10d565efSmrg (and (match_code "const_int") 143*10d565efSmrg (and (match_test "TARGET_P8_VECTOR") 144*10d565efSmrg (match_operand 0 "s5bit_cint_operand")))) 145*10d565efSmrg 146*10d565efSmrg(define_constraint "wD" 147*10d565efSmrg "Int constant that is the element number of the 64-bit scalar in a vector." 148*10d565efSmrg (and (match_code "const_int") 149*10d565efSmrg (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) 150*10d565efSmrg 151*10d565efSmrg(define_constraint "wE" 152*10d565efSmrg "Vector constant that can be loaded with the XXSPLTIB instruction." 153*10d565efSmrg (match_test "xxspltib_constant_nosplit (op, mode)")) 154*10d565efSmrg 155*10d565efSmrg;; Extended fusion store 156*10d565efSmrg(define_memory_constraint "wF" 157*10d565efSmrg "Memory operand suitable for power9 fusion load/stores" 158*10d565efSmrg (match_operand 0 "fusion_addis_mem_combo_load")) 159*10d565efSmrg 160*10d565efSmrg;; Fusion gpr load. 161*10d565efSmrg(define_memory_constraint "wG" 162*10d565efSmrg "Memory operand suitable for TOC fusion memory references" 163*10d565efSmrg (match_operand 0 "toc_fusion_mem_wrapped")) 164*10d565efSmrg 165*10d565efSmrg(define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]" 166*10d565efSmrg "Altivec register to hold 32-bit integers or NO_REGS.") 167*10d565efSmrg 168*10d565efSmrg(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]" 169*10d565efSmrg "FPR register to hold 32-bit integers or NO_REGS.") 170*10d565efSmrg 171*10d565efSmrg(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]" 172*10d565efSmrg "FPR register to hold 8/16-bit integers or NO_REGS.") 173*10d565efSmrg 174*10d565efSmrg(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]" 175*10d565efSmrg "Altivec register to hold 8/16-bit integers or NO_REGS.") 176*10d565efSmrg 177*10d565efSmrg(define_constraint "wL" 178*10d565efSmrg "Int constant that is the element number mfvsrld accesses in a vector." 179*10d565efSmrg (and (match_code "const_int") 180*10d565efSmrg (and (match_test "TARGET_DIRECT_MOVE_128") 181*10d565efSmrg (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))) 182*10d565efSmrg 183*10d565efSmrg;; Generate the XXORC instruction to set a register to all 1's 184*10d565efSmrg(define_constraint "wM" 185*10d565efSmrg "Match vector constant with all 1's if the XXLORC instruction is available" 186*10d565efSmrg (and (match_test "TARGET_P8_VECTOR") 187*10d565efSmrg (match_operand 0 "all_ones_constant"))) 188*10d565efSmrg 189*10d565efSmrg;; ISA 3.0 vector d-form addresses 190*10d565efSmrg(define_memory_constraint "wO" 191*10d565efSmrg "Memory operand suitable for the ISA 3.0 vector d-form instructions." 192*10d565efSmrg (match_operand 0 "vsx_quad_dform_memory_operand")) 193*10d565efSmrg 194*10d565efSmrg;; Lq/stq validates the address for load/store quad 195*10d565efSmrg(define_memory_constraint "wQ" 196*10d565efSmrg "Memory operand suitable for the load/store quad instructions" 197*10d565efSmrg (match_operand 0 "quad_memory_operand")) 198*10d565efSmrg 199*10d565efSmrg(define_constraint "wS" 200*10d565efSmrg "Vector constant that can be loaded with XXSPLTIB & sign extension." 201*10d565efSmrg (match_test "xxspltib_constant_split (op, mode)")) 202*10d565efSmrg 203*10d565efSmrg;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. 204*10d565efSmrg;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four 205*10d565efSmrg;; offset is enforced for 32-bit too. 206*10d565efSmrg(define_memory_constraint "wY" 207*10d565efSmrg "Offsettable memory operand, with bottom 2 bits 0" 208*10d565efSmrg (and (match_code "mem") 209*10d565efSmrg (not (match_test "update_address_mem (op, mode)")) 210*10d565efSmrg (match_test "mem_operand_ds_form (op, mode)"))) 211*10d565efSmrg 212*10d565efSmrg;; Altivec style load/store that ignores the bottom bits of the address 213*10d565efSmrg(define_memory_constraint "wZ" 214*10d565efSmrg "Indexed or indirect memory operand, ignoring the bottom 4 bits" 215*10d565efSmrg (match_operand 0 "altivec_indexed_or_indirect_operand")) 216*10d565efSmrg 217*10d565efSmrg;; Integer constraints 218*10d565efSmrg 219*10d565efSmrg(define_constraint "I" 220*10d565efSmrg "A signed 16-bit constant" 221*10d565efSmrg (and (match_code "const_int") 222*10d565efSmrg (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000"))) 223*10d565efSmrg 224*10d565efSmrg(define_constraint "J" 225*10d565efSmrg "high-order 16 bits nonzero" 226*10d565efSmrg (and (match_code "const_int") 227*10d565efSmrg (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) 228*10d565efSmrg 229*10d565efSmrg(define_constraint "K" 230*10d565efSmrg "low-order 16 bits nonzero" 231*10d565efSmrg (and (match_code "const_int") 232*10d565efSmrg (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) 233*10d565efSmrg 234*10d565efSmrg(define_constraint "L" 235*10d565efSmrg "signed 16-bit constant shifted left 16 bits" 236*10d565efSmrg (and (match_code "const_int") 237*10d565efSmrg (match_test "((ival & 0xffff) == 0 238*10d565efSmrg && (ival >> 31 == -1 || ival >> 31 == 0))"))) 239*10d565efSmrg 240*10d565efSmrg(define_constraint "M" 241*10d565efSmrg "constant greater than 31" 242*10d565efSmrg (and (match_code "const_int") 243*10d565efSmrg (match_test "ival > 31"))) 244*10d565efSmrg 245*10d565efSmrg(define_constraint "N" 246*10d565efSmrg "positive constant that is an exact power of two" 247*10d565efSmrg (and (match_code "const_int") 248*10d565efSmrg (match_test "ival > 0 && exact_log2 (ival) >= 0"))) 249*10d565efSmrg 250*10d565efSmrg(define_constraint "O" 251*10d565efSmrg "constant zero" 252*10d565efSmrg (and (match_code "const_int") 253*10d565efSmrg (match_test "ival == 0"))) 254*10d565efSmrg 255*10d565efSmrg(define_constraint "P" 256*10d565efSmrg "constant whose negation is signed 16-bit constant" 257*10d565efSmrg (and (match_code "const_int") 258*10d565efSmrg (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) 259*10d565efSmrg 260*10d565efSmrg;; Floating-point constraints 261*10d565efSmrg 262*10d565efSmrg(define_constraint "G" 263*10d565efSmrg "Constant that can be copied into GPR with two insns for DF/DI 264*10d565efSmrg and one for SF." 265*10d565efSmrg (and (match_code "const_double") 266*10d565efSmrg (match_test "num_insns_constant (op, mode) 267*10d565efSmrg == (mode == SFmode ? 1 : 2)"))) 268*10d565efSmrg 269*10d565efSmrg(define_constraint "H" 270*10d565efSmrg "DF/DI constant that takes three insns." 271*10d565efSmrg (and (match_code "const_double") 272*10d565efSmrg (match_test "num_insns_constant (op, mode) == 3"))) 273*10d565efSmrg 274*10d565efSmrg;; Memory constraints 275*10d565efSmrg 276*10d565efSmrg(define_memory_constraint "es" 277*10d565efSmrg "A ``stable'' memory operand; that is, one which does not include any 278*10d565efSmrgautomodification of the base register. Unlike @samp{m}, this constraint 279*10d565efSmrgcan be used in @code{asm} statements that might access the operand 280*10d565efSmrgseveral times, or that might not access it at all." 281*10d565efSmrg (and (match_code "mem") 282*10d565efSmrg (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) 283*10d565efSmrg 284*10d565efSmrg(define_memory_constraint "Q" 285*10d565efSmrg "Memory operand that is an offset from a register (it is usually better 286*10d565efSmrgto use @samp{m} or @samp{es} in @code{asm} statements)" 287*10d565efSmrg (and (match_code "mem") 288*10d565efSmrg (match_test "GET_CODE (XEXP (op, 0)) == REG"))) 289*10d565efSmrg 290*10d565efSmrg(define_memory_constraint "Y" 291*10d565efSmrg "memory operand for 8 byte and 16 byte gpr load/store" 292*10d565efSmrg (and (match_code "mem") 293*10d565efSmrg (match_test "mem_operand_gpr (op, mode)"))) 294*10d565efSmrg 295*10d565efSmrg(define_memory_constraint "Z" 296*10d565efSmrg "Memory operand that is an indexed or indirect from a register (it is 297*10d565efSmrgusually better to use @samp{m} or @samp{es} in @code{asm} statements)" 298*10d565efSmrg (match_operand 0 "indexed_or_indirect_operand")) 299*10d565efSmrg 300*10d565efSmrg;; Address constraints 301*10d565efSmrg 302*10d565efSmrg(define_address_constraint "a" 303*10d565efSmrg "Indexed or indirect address operand" 304*10d565efSmrg (match_operand 0 "indexed_or_indirect_address")) 305*10d565efSmrg 306*10d565efSmrg(define_constraint "R" 307*10d565efSmrg "AIX TOC entry" 308*10d565efSmrg (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) 309*10d565efSmrg 310*10d565efSmrg;; General constraints 311*10d565efSmrg 312*10d565efSmrg(define_constraint "U" 313*10d565efSmrg "V.4 small data reference" 314*10d565efSmrg (and (match_test "DEFAULT_ABI == ABI_V4") 315*10d565efSmrg (match_test "small_data_operand (op, mode)"))) 316*10d565efSmrg 317*10d565efSmrg(define_constraint "W" 318*10d565efSmrg "vector constant that does not require memory" 319*10d565efSmrg (match_operand 0 "easy_vector_constant")) 320*10d565efSmrg 321*10d565efSmrg(define_constraint "j" 322*10d565efSmrg "Zero vector constant" 323*10d565efSmrg (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) 324