110d565efSmrg;; Predicate definitions for SPARC. 2*ec02198aSmrg;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 310d565efSmrg;; 410d565efSmrg;; This file is part of GCC. 510d565efSmrg;; 610d565efSmrg;; GCC is free software; you can redistribute it and/or modify 710d565efSmrg;; it under the terms of the GNU General Public License as published by 810d565efSmrg;; the Free Software Foundation; either version 3, or (at your option) 910d565efSmrg;; any later version. 1010d565efSmrg;; 1110d565efSmrg;; GCC is distributed in the hope that it will be useful, 1210d565efSmrg;; but WITHOUT ANY WARRANTY; without even the implied warranty of 1310d565efSmrg;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1410d565efSmrg;; GNU General Public License for more details. 1510d565efSmrg;; 1610d565efSmrg;; You should have received a copy of the GNU General Public License 1710d565efSmrg;; along with GCC; see the file COPYING3. If not see 1810d565efSmrg;; <http://www.gnu.org/licenses/>. 1910d565efSmrg 2010d565efSmrg;; Predicates for numerical constants. 2110d565efSmrg 2210d565efSmrg;; Return true if OP is the zero constant for MODE. 2310d565efSmrg(define_predicate "const_zero_operand" 2410d565efSmrg (and (match_code "const_int,const_wide_int,const_double,const_vector") 2510d565efSmrg (match_test "op == CONST0_RTX (mode)"))) 2610d565efSmrg 2710d565efSmrg;; Return true if the integer representation of OP is all ones. 2810d565efSmrg(define_predicate "const_all_ones_operand" 2910d565efSmrg (and (match_code "const_int,const_wide_int,const_double,const_vector") 3010d565efSmrg (match_test "INTEGRAL_MODE_P (GET_MODE (op))") 3110d565efSmrg (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) 3210d565efSmrg 3310d565efSmrg;; Return true if OP is the integer constant 4096. 3410d565efSmrg(define_predicate "const_4096_operand" 3510d565efSmrg (and (match_code "const_int") 3610d565efSmrg (match_test "INTVAL (op) == 4096"))) 3710d565efSmrg 3810d565efSmrg;; Return true if OP is a constant that is representable by a 13-bit 3910d565efSmrg;; signed field. This is an acceptable immediate operand for most 4010d565efSmrg;; 3-address instructions. 4110d565efSmrg(define_predicate "small_int_operand" 4210d565efSmrg (and (match_code "const_int") 4310d565efSmrg (match_test "SPARC_SIMM13_P (INTVAL (op))"))) 4410d565efSmrg 4510d565efSmrg;; Return true if OP is a constant operand for the umul instruction. That 4610d565efSmrg;; instruction sign-extends immediate values just like all other SPARC 4710d565efSmrg;; instructions, but interprets the extended result as an unsigned number. 4810d565efSmrg(define_predicate "uns_small_int_operand" 4910d565efSmrg (and (match_code "const_int") 5010d565efSmrg (match_test "((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 5110d565efSmrg || (INTVAL (op) >= 0xFFFFF000 5210d565efSmrg && INTVAL (op) <= 0xFFFFFFFF))"))) 5310d565efSmrg 5410d565efSmrg;; Return true if OP is a constant that can be loaded by the sethi instruction. 5510d565efSmrg;; The first test avoids emitting sethi to load zero for example. 5610d565efSmrg(define_predicate "const_high_operand" 5710d565efSmrg (and (match_code "const_int") 5810d565efSmrg (and (not (match_operand 0 "small_int_operand")) 5910d565efSmrg (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))")))) 6010d565efSmrg 6110d565efSmrg;; Return true if OP is a constant whose 1's complement can be loaded by the 6210d565efSmrg;; sethi instruction. 6310d565efSmrg(define_predicate "const_compl_high_operand" 6410d565efSmrg (and (match_code "const_int") 6510d565efSmrg (and (not (match_operand 0 "small_int_operand")) 6610d565efSmrg (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))")))) 6710d565efSmrg 6810d565efSmrg;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum 6910d565efSmrg;; pair of instructions. 7010d565efSmrg(define_predicate "fp_const_high_losum_operand" 7110d565efSmrg (match_operand 0 "const_double_operand") 7210d565efSmrg{ 7310d565efSmrg gcc_assert (mode == SFmode); 7410d565efSmrg return fp_high_losum_p (op); 7510d565efSmrg}) 7610d565efSmrg 7710d565efSmrg;; Return true if OP is a const_double or const_vector. 7810d565efSmrg(define_predicate "const_double_or_vector_operand" 7910d565efSmrg (match_code "const_double,const_vector")) 8010d565efSmrg 8110d565efSmrg;; Return true if OP is Zero, or if the target is V7. 8210d565efSmrg(define_predicate "zero_or_v7_operand" 8310d565efSmrg (and (match_code "const_int") 8410d565efSmrg (ior (match_test "INTVAL (op) == 0") 8510d565efSmrg (match_test "!TARGET_V8 && !TARGET_V9")))) 8610d565efSmrg 8710d565efSmrg;; Predicates for symbolic constants. 8810d565efSmrg 8910d565efSmrg;; Return true if OP is either a symbol reference or a sum of a symbol 9010d565efSmrg;; reference and a constant. 9110d565efSmrg(define_predicate "symbolic_operand" 9210d565efSmrg (match_code "symbol_ref,label_ref,const") 9310d565efSmrg{ 9410d565efSmrg machine_mode omode = GET_MODE (op); 9510d565efSmrg 9610d565efSmrg if (omode != mode && omode != VOIDmode && mode != VOIDmode) 9710d565efSmrg return false; 9810d565efSmrg 9910d565efSmrg switch (GET_CODE (op)) 10010d565efSmrg { 10110d565efSmrg case SYMBOL_REF: 10210d565efSmrg return !SYMBOL_REF_TLS_MODEL (op); 10310d565efSmrg 10410d565efSmrg case LABEL_REF: 10510d565efSmrg return true; 10610d565efSmrg 10710d565efSmrg case CONST: 10810d565efSmrg op = XEXP (op, 0); 10910d565efSmrg return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 11010d565efSmrg && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) 11110d565efSmrg || GET_CODE (XEXP (op, 0)) == LABEL_REF) 11210d565efSmrg && GET_CODE (XEXP (op, 1)) == CONST_INT); 11310d565efSmrg 11410d565efSmrg default: 11510d565efSmrg gcc_unreachable (); 11610d565efSmrg } 11710d565efSmrg}) 11810d565efSmrg 11910d565efSmrg;; Return true if OP is a symbolic operand for the TLS Global Dynamic model. 12010d565efSmrg(define_predicate "tgd_symbolic_operand" 12110d565efSmrg (and (match_code "symbol_ref") 12210d565efSmrg (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC"))) 12310d565efSmrg 12410d565efSmrg;; Return true if OP is a symbolic operand for the TLS Local Dynamic model. 12510d565efSmrg(define_predicate "tld_symbolic_operand" 12610d565efSmrg (and (match_code "symbol_ref") 12710d565efSmrg (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC"))) 12810d565efSmrg 12910d565efSmrg;; Return true if OP is a symbolic operand for the TLS Initial Exec model. 13010d565efSmrg(define_predicate "tie_symbolic_operand" 13110d565efSmrg (and (match_code "symbol_ref") 13210d565efSmrg (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC"))) 13310d565efSmrg 13410d565efSmrg;; Return true if OP is a symbolic operand for the TLS Local Exec model. 13510d565efSmrg(define_predicate "tle_symbolic_operand" 13610d565efSmrg (and (match_code "symbol_ref") 13710d565efSmrg (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC"))) 13810d565efSmrg 13910d565efSmrg;; Return true if the operand is an argument used in generating PIC references 14010d565efSmrg;; in either the medium/low or embedded medium/anywhere code models on V9. 14110d565efSmrg;; Check for (const (minus (symbol_ref:GOT) 14210d565efSmrg;; (const (minus (label) (pc))))) 14310d565efSmrg(define_predicate "medium_pic_operand" 14410d565efSmrg (match_code "const") 14510d565efSmrg{ 14610d565efSmrg /* Check for (const (minus (symbol_ref:GOT) 14710d565efSmrg (const (minus (label) (pc))))). */ 14810d565efSmrg op = XEXP (op, 0); 14910d565efSmrg return GET_CODE (op) == MINUS 15010d565efSmrg && GET_CODE (XEXP (op, 0)) == SYMBOL_REF 15110d565efSmrg && GET_CODE (XEXP (op, 1)) == CONST 15210d565efSmrg && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS; 15310d565efSmrg}) 15410d565efSmrg 15510d565efSmrg;; Return true if OP is a LABEL_REF of mode MODE. 15610d565efSmrg(define_predicate "label_ref_operand" 15710d565efSmrg (and (match_code "label_ref") 15810d565efSmrg (match_test "GET_MODE (op) == mode"))) 15910d565efSmrg 16010d565efSmrg;; Return true if OP is a data segment reference. This includes the readonly 16110d565efSmrg;; data segment or, in other words, anything but the text segment. 16210d565efSmrg;; This is needed in the embedded medium/anywhere code model on V9. These 16310d565efSmrg;; values are accessed with EMBMEDANY_BASE_REG. */ 16410d565efSmrg(define_predicate "data_segment_operand" 16510d565efSmrg (match_code "symbol_ref,plus,const") 16610d565efSmrg{ 16710d565efSmrg switch (GET_CODE (op)) 16810d565efSmrg { 16910d565efSmrg case SYMBOL_REF : 17010d565efSmrg return ! SYMBOL_REF_FUNCTION_P (op); 17110d565efSmrg case PLUS : 17210d565efSmrg /* Assume canonical format of symbol + constant. 17310d565efSmrg Fall through. */ 17410d565efSmrg case CONST : 17510d565efSmrg return data_segment_operand (XEXP (op, 0), VOIDmode); 17610d565efSmrg default : 17710d565efSmrg gcc_unreachable (); 17810d565efSmrg } 17910d565efSmrg}) 18010d565efSmrg 18110d565efSmrg;; Return true if OP is a text segment reference. 18210d565efSmrg;; This is needed in the embedded medium/anywhere code model on V9. 18310d565efSmrg(define_predicate "text_segment_operand" 18410d565efSmrg (match_code "label_ref,symbol_ref,plus,const") 18510d565efSmrg{ 18610d565efSmrg switch (GET_CODE (op)) 18710d565efSmrg { 18810d565efSmrg case LABEL_REF : 18910d565efSmrg return true; 19010d565efSmrg case SYMBOL_REF : 19110d565efSmrg return SYMBOL_REF_FUNCTION_P (op); 19210d565efSmrg case PLUS : 19310d565efSmrg /* Assume canonical format of symbol + constant. 19410d565efSmrg Fall through. */ 19510d565efSmrg case CONST : 19610d565efSmrg return text_segment_operand (XEXP (op, 0), VOIDmode); 19710d565efSmrg default : 19810d565efSmrg gcc_unreachable (); 19910d565efSmrg } 20010d565efSmrg}) 20110d565efSmrg 20210d565efSmrg 20310d565efSmrg;; Predicates for registers. 20410d565efSmrg 20510d565efSmrg;; Return true if OP is either the zero constant or a register. 20610d565efSmrg(define_predicate "register_or_zero_operand" 20710d565efSmrg (ior (match_operand 0 "register_operand") 20810d565efSmrg (match_operand 0 "const_zero_operand"))) 20910d565efSmrg 21010d565efSmrg(define_predicate "register_or_v9_zero_operand" 21110d565efSmrg (ior (match_operand 0 "register_operand") 21210d565efSmrg (and (match_test "TARGET_V9") 21310d565efSmrg (match_operand 0 "const_zero_operand")))) 21410d565efSmrg 21510d565efSmrg;; Return true if OP is either the zero constant, the all-ones 21610d565efSmrg;; constant, or a register. 21710d565efSmrg(define_predicate "register_or_zero_or_all_ones_operand" 21810d565efSmrg (ior (match_operand 0 "register_or_zero_operand") 21910d565efSmrg (match_operand 0 "const_all_ones_operand"))) 22010d565efSmrg 22110d565efSmrg;; Return true if OP is a register operand in a floating point register. 22210d565efSmrg(define_predicate "fp_register_operand" 22310d565efSmrg (match_operand 0 "register_operand") 22410d565efSmrg{ 22510d565efSmrg if (GET_CODE (op) == SUBREG) 22610d565efSmrg op = SUBREG_REG (op); /* Possibly a MEM */ 22710d565efSmrg return REG_P (op) && SPARC_FP_REG_P (REGNO (op)); 22810d565efSmrg}) 22910d565efSmrg 23010d565efSmrg;; Return true if OP is an integer register of the appropriate mode 23110d565efSmrg;; for a cstore result. 23210d565efSmrg(define_special_predicate "cstore_result_operand" 23310d565efSmrg (match_test "register_operand (op, TARGET_ARCH64 ? DImode : SImode)")) 23410d565efSmrg 23510d565efSmrg;; Return true if OP is a floating point condition code register. 23610d565efSmrg(define_predicate "fcc_register_operand" 23710d565efSmrg (and (match_code "reg") 23810d565efSmrg (match_test "((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4"))) 23910d565efSmrg 24010d565efSmrg;; Return true if OP is the floating point condition code register fcc0. 24110d565efSmrg(define_predicate "fcc0_register_operand" 24210d565efSmrg (and (match_code "reg") 24310d565efSmrg (match_test "REGNO (op) == SPARC_FCC_REG"))) 24410d565efSmrg 24510d565efSmrg;; Return true if OP is an integer condition code register. 24610d565efSmrg(define_predicate "icc_register_operand" 24710d565efSmrg (and (match_code "reg") 24810d565efSmrg (match_test "REGNO (op) == SPARC_ICC_REG"))) 24910d565efSmrg 25010d565efSmrg;; Return true if OP is an integer or floating point condition code register. 25110d565efSmrg(define_predicate "icc_or_fcc_register_operand" 25210d565efSmrg (ior (match_operand 0 "icc_register_operand") 25310d565efSmrg (match_operand 0 "fcc_register_operand"))) 25410d565efSmrg 25510d565efSmrg 25610d565efSmrg;; Predicates for arithmetic instructions. 25710d565efSmrg 25810d565efSmrg;; Return true if OP is a register, or is a constant that is representable 25910d565efSmrg;; by a 13-bit signed field. This is an acceptable operand for most 26010d565efSmrg;; 3-address instructions. 26110d565efSmrg(define_predicate "arith_operand" 26210d565efSmrg (ior (match_operand 0 "register_operand") 26310d565efSmrg (match_operand 0 "small_int_operand"))) 26410d565efSmrg 26510d565efSmrg;; 64-bit: Same as above. 26610d565efSmrg;; 32-bit: Return true if OP is a register, or is a constant that is 26710d565efSmrg;; representable by a couple of 13-bit signed fields. This is an 26810d565efSmrg;; acceptable operand for most 3-address splitters. 26910d565efSmrg(define_predicate "arith_double_operand" 27010d565efSmrg (match_code "const_int,reg,subreg") 27110d565efSmrg{ 27210d565efSmrg bool arith_simple_operand = arith_operand (op, mode); 27310d565efSmrg HOST_WIDE_INT m1, m2; 27410d565efSmrg 27510d565efSmrg if (TARGET_ARCH64 || arith_simple_operand) 27610d565efSmrg return arith_simple_operand; 27710d565efSmrg 27810d565efSmrg if (GET_CODE (op) != CONST_INT) 27910d565efSmrg return false; 28010d565efSmrg 28110d565efSmrg m1 = trunc_int_for_mode (INTVAL (op), SImode); 28210d565efSmrg m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode); 28310d565efSmrg 28410d565efSmrg return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2); 28510d565efSmrg}) 28610d565efSmrg 28710d565efSmrg;; Return true if OP is suitable as second operand for add/sub. 28810d565efSmrg(define_predicate "arith_add_operand" 28910d565efSmrg (ior (match_operand 0 "arith_operand") 29010d565efSmrg (match_operand 0 "const_4096_operand"))) 29110d565efSmrg 29210d565efSmrg;; Return true if OP is suitable as second double operand for add/sub. 29310d565efSmrg(define_predicate "arith_double_add_operand" 29410d565efSmrg (match_code "const_int,reg,subreg") 29510d565efSmrg{ 29610d565efSmrg if (arith_double_operand (op, mode)) 29710d565efSmrg return true; 29810d565efSmrg 299*ec02198aSmrg /* Turning an add/sub instruction into the other changes the Carry flag 300*ec02198aSmrg so the 4096 trick cannot be used for double operations in 32-bit mode. */ 30110d565efSmrg return TARGET_ARCH64 && const_4096_operand (op, mode); 30210d565efSmrg}) 30310d565efSmrg 30410d565efSmrg;; Return true if OP is a register, or is a CONST_INT that can fit in a 30510d565efSmrg;; signed 10-bit immediate field. This is an acceptable SImode operand for 30610d565efSmrg;; the movrcc instructions. 30710d565efSmrg(define_predicate "arith10_operand" 30810d565efSmrg (ior (match_operand 0 "register_operand") 30910d565efSmrg (and (match_code "const_int") 31010d565efSmrg (match_test "SPARC_SIMM10_P (INTVAL (op))")))) 31110d565efSmrg 31210d565efSmrg;; Return true if OP is a register, or is a CONST_INT that can fit in a 31310d565efSmrg;; signed 11-bit immediate field. This is an acceptable SImode operand for 31410d565efSmrg;; the movcc instructions. 31510d565efSmrg(define_predicate "arith11_operand" 31610d565efSmrg (ior (match_operand 0 "register_operand") 31710d565efSmrg (and (match_code "const_int") 31810d565efSmrg (match_test "SPARC_SIMM11_P (INTVAL (op))")))) 31910d565efSmrg 32010d565efSmrg;; Return true if OP is a register or a constant for the umul instruction. 32110d565efSmrg(define_predicate "uns_arith_operand" 32210d565efSmrg (ior (match_operand 0 "register_operand") 32310d565efSmrg (match_operand 0 "uns_small_int_operand"))) 32410d565efSmrg 32510d565efSmrg;; Return true if OP is a register, or is a CONST_INT that can fit in a 32610d565efSmrg;; signed 5-bit immediate field. This is an acceptable second operand for 32710d565efSmrg;; the cbcond instructions. 32810d565efSmrg(define_predicate "arith5_operand" 32910d565efSmrg (ior (match_operand 0 "register_operand") 33010d565efSmrg (and (match_code "const_int") 33110d565efSmrg (match_test "SPARC_SIMM5_P (INTVAL (op))")))) 33210d565efSmrg 33310d565efSmrg;; Return true if OP is a constant in the range 0..7. This is an 33410d565efSmrg;; acceptable second operand for dictunpack instructions setting a 33510d565efSmrg;; V8QI mode in the destination register. 33610d565efSmrg(define_predicate "imm5_operand_dictunpack8" 33710d565efSmrg (and (match_code "const_int") 33810d565efSmrg (match_test "(INTVAL (op) >= 0 && INTVAL (op) < 8)"))) 33910d565efSmrg 34010d565efSmrg;; Return true if OP is a constant in the range 7..15. This is an 34110d565efSmrg;; acceptable second operand for dictunpack instructions setting a 34210d565efSmrg;; V4HI mode in the destination register. 34310d565efSmrg(define_predicate "imm5_operand_dictunpack16" 34410d565efSmrg (and (match_code "const_int") 34510d565efSmrg (match_test "(INTVAL (op) >= 8 && INTVAL (op) < 16)"))) 34610d565efSmrg 34710d565efSmrg;; Return true if OP is a constant in the range 15..31. This is an 34810d565efSmrg;; acceptable second operand for dictunpack instructions setting a 34910d565efSmrg;; V2SI mode in the destination register. 35010d565efSmrg(define_predicate "imm5_operand_dictunpack32" 35110d565efSmrg (and (match_code "const_int") 35210d565efSmrg (match_test "(INTVAL (op) >= 16 && INTVAL (op) < 32)"))) 35310d565efSmrg 35410d565efSmrg;; Return true if OP is a constant that is representable by a 2-bit 35510d565efSmrg;; unsigned field. This is an acceptable third operand for 35610d565efSmrg;; fpcmp*shl instructions. 35710d565efSmrg(define_predicate "imm2_operand" 35810d565efSmrg (and (match_code "const_int") 35910d565efSmrg (match_test "SPARC_IMM2_P (INTVAL (op))"))) 36010d565efSmrg 36110d565efSmrg;; Predicates for miscellaneous instructions. 36210d565efSmrg 36310d565efSmrg;; Return true if OP is valid for the lhs of a comparison insn. 36410d565efSmrg(define_predicate "compare_operand" 36510d565efSmrg (match_code "reg,subreg,zero_extract") 36610d565efSmrg{ 36710d565efSmrg if (GET_CODE (op) == ZERO_EXTRACT) 36810d565efSmrg return (register_operand (XEXP (op, 0), mode) 36910d565efSmrg && small_int_operand (XEXP (op, 1), mode) 37010d565efSmrg && small_int_operand (XEXP (op, 2), mode) 37110d565efSmrg /* This matches cmp_zero_extract. */ 37210d565efSmrg && ((mode == SImode 37310d565efSmrg && INTVAL (XEXP (op, 2)) > 19) 37410d565efSmrg /* This matches cmp_zero_extract_sp64. */ 37510d565efSmrg || (TARGET_ARCH64 37610d565efSmrg && mode == DImode 37710d565efSmrg && INTVAL (XEXP (op, 2)) > 51))); 37810d565efSmrg 37910d565efSmrg return register_operand (op, mode); 38010d565efSmrg}) 38110d565efSmrg 38210d565efSmrg;; Return true if OP is a valid operand for the source of a move insn. 38310d565efSmrg(define_predicate "input_operand" 38410d565efSmrg (match_code "const_int,const_double,const_vector,reg,subreg,mem") 38510d565efSmrg{ 38610d565efSmrg enum mode_class mclass; 38710d565efSmrg 38810d565efSmrg /* If both modes are non-void they must be the same. */ 38910d565efSmrg if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 39010d565efSmrg return false; 39110d565efSmrg 39210d565efSmrg mclass = GET_MODE_CLASS (mode); 39310d565efSmrg 39410d565efSmrg /* Allow any 1-instruction integer constant. */ 39510d565efSmrg if (mclass == MODE_INT 39610d565efSmrg && mode != TImode 39710d565efSmrg && (small_int_operand (op, mode) || const_high_operand (op, mode))) 39810d565efSmrg return true; 39910d565efSmrg 40010d565efSmrg /* If 32-bit mode and this is a DImode constant, allow it 40110d565efSmrg so that the splits can be generated. */ 40210d565efSmrg if (TARGET_ARCH32 && mode == DImode && GET_CODE (op) == CONST_INT) 40310d565efSmrg return true; 40410d565efSmrg 40510d565efSmrg /* Allow FP constants to be built in integer registers. */ 40610d565efSmrg if (mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE) 40710d565efSmrg return true; 40810d565efSmrg 40910d565efSmrg if (mclass == MODE_VECTOR_INT && const_all_ones_operand (op, mode)) 41010d565efSmrg return true; 41110d565efSmrg 41210d565efSmrg if (register_or_zero_operand (op, mode)) 41310d565efSmrg return true; 41410d565efSmrg 41510d565efSmrg /* If this is a SUBREG, look inside so that we handle paradoxical ones. */ 41610d565efSmrg if (GET_CODE (op) == SUBREG) 41710d565efSmrg op = SUBREG_REG (op); 41810d565efSmrg 41910d565efSmrg /* Check for valid MEM forms. */ 42010d565efSmrg if (GET_CODE (op) == MEM) 42110d565efSmrg { 42210d565efSmrg /* Except when LRA is precisely working hard to make them valid 42310d565efSmrg and relying entirely on the constraints. */ 42410d565efSmrg if (lra_in_progress) 42510d565efSmrg return true; 42610d565efSmrg 42710d565efSmrg return memory_address_p (mode, XEXP (op, 0)); 42810d565efSmrg } 42910d565efSmrg 43010d565efSmrg return false; 43110d565efSmrg}) 43210d565efSmrg 43310d565efSmrg;; Return true if OP is an address suitable for a call insn. 43410d565efSmrg;; Call insn on SPARC can take a PC-relative constant address 43510d565efSmrg;; or any regular memory address. 43610d565efSmrg(define_predicate "call_address_operand" 43710d565efSmrg (ior (match_operand 0 "symbolic_operand") 43810d565efSmrg (match_test "memory_address_p (Pmode, op)"))) 43910d565efSmrg 44010d565efSmrg;; Return true if OP is an operand suitable for a call insn. 44110d565efSmrg(define_predicate "call_operand" 44210d565efSmrg (and (match_code "mem") 44310d565efSmrg (match_test "call_address_operand (XEXP (op, 0), mode)"))) 44410d565efSmrg 44510d565efSmrg 44610d565efSmrg(define_predicate "mem_noofs_operand" 44710d565efSmrg (and (match_code "mem") 44810d565efSmrg (match_code "reg" "0"))) 44910d565efSmrg 45010d565efSmrg;; Predicates for operators. 45110d565efSmrg 45210d565efSmrg;; Return true if OP is a valid comparison operator for CCNZmode. 45310d565efSmrg(define_predicate "nz_comparison_operator" 45410d565efSmrg (match_code "eq,ne,lt,ge")) 45510d565efSmrg 45610d565efSmrg;; Return true if OP is a valid comparison operator for CCCmode. 45710d565efSmrg(define_predicate "c_comparison_operator" 45810d565efSmrg (match_code "ltu,geu")) 45910d565efSmrg 46010d565efSmrg;; Return true if OP is a valid comparison operator for CCVmode. 46110d565efSmrg(define_predicate "v_comparison_operator" 46210d565efSmrg (match_code "eq,ne")) 46310d565efSmrg 46410d565efSmrg;; Return true if OP is an integer comparison operator. This allows 46510d565efSmrg;; the use of MATCH_OPERATOR to recognize all the branch insns. 46610d565efSmrg(define_predicate "icc_comparison_operator" 46710d565efSmrg (match_operand 0 "ordered_comparison_operator") 46810d565efSmrg{ 46910d565efSmrg switch (GET_MODE (XEXP (op, 0))) 47010d565efSmrg { 471c7a68eb7Smrg case E_CCmode: 472c7a68eb7Smrg case E_CCXmode: 47310d565efSmrg return true; 474c7a68eb7Smrg case E_CCNZmode: 475c7a68eb7Smrg case E_CCXNZmode: 47610d565efSmrg return nz_comparison_operator (op, mode); 477c7a68eb7Smrg case E_CCCmode: 478c7a68eb7Smrg case E_CCXCmode: 47910d565efSmrg return c_comparison_operator (op, mode); 480c7a68eb7Smrg case E_CCVmode: 481c7a68eb7Smrg case E_CCXVmode: 48210d565efSmrg return v_comparison_operator (op, mode); 48310d565efSmrg default: 48410d565efSmrg return false; 48510d565efSmrg } 48610d565efSmrg}) 48710d565efSmrg 48810d565efSmrg;; Return true if OP is a FP comparison operator. 48910d565efSmrg(define_predicate "fcc_comparison_operator" 49010d565efSmrg (match_operand 0 "comparison_operator") 49110d565efSmrg{ 49210d565efSmrg switch (GET_MODE (XEXP (op, 0))) 49310d565efSmrg { 494c7a68eb7Smrg case E_CCFPmode: 495c7a68eb7Smrg case E_CCFPEmode: 49610d565efSmrg return true; 49710d565efSmrg default: 49810d565efSmrg return false; 49910d565efSmrg } 50010d565efSmrg}) 50110d565efSmrg 50210d565efSmrg;; Return true if OP is an integer or FP comparison operator. This allows 50310d565efSmrg;; the use of MATCH_OPERATOR to recognize all the conditional move insns. 50410d565efSmrg(define_predicate "icc_or_fcc_comparison_operator" 50510d565efSmrg (ior (match_operand 0 "icc_comparison_operator") 50610d565efSmrg (match_operand 0 "fcc_comparison_operator"))) 50710d565efSmrg 50810d565efSmrg;; Return true if OP is an integer comparison operator for V9. 50910d565efSmrg(define_predicate "v9_comparison_operator" 51010d565efSmrg (and (match_operand 0 "ordered_comparison_operator") 51110d565efSmrg (match_test "TARGET_V9"))) 51210d565efSmrg 51310d565efSmrg;; Return true if OP is a comparison operator suitable for use in V9 51410d565efSmrg;; conditional move or branch on register contents instructions. 51510d565efSmrg(define_predicate "v9_register_comparison_operator" 51610d565efSmrg (match_code "eq,ne,ge,lt,le,gt")) 51710d565efSmrg 51810d565efSmrg;; Return true if OP is an operator which can set the condition codes 51910d565efSmrg;; explicitly. We do not include PLUS/MINUS/NEG/ASHIFT because these 52010d565efSmrg;; require CCNZmode, which we handle explicitly. 52110d565efSmrg(define_predicate "cc_arith_operator" 52210d565efSmrg (match_code "and,ior,xor")) 52310d565efSmrg 52410d565efSmrg;; Return true if OP is an operator which can bitwise complement its 52510d565efSmrg;; second operand and set the condition codes explicitly. 52610d565efSmrg;; XOR is not here because combine canonicalizes (xor (not ...) ...) 52710d565efSmrg;; and (xor ... (not ...)) to (not (xor ...)). 52810d565efSmrg(define_predicate "cc_arith_not_operator" 52910d565efSmrg (match_code "and,ior")) 530