1*0fc04c29Smrg;; Copyright (C) 2006-2019 Free Software Foundation, Inc. 263d1a8abSmrg 363d1a8abSmrg;; This file is free software; you can redistribute it and/or modify it under 463d1a8abSmrg;; the terms of the GNU General Public License as published by the Free 563d1a8abSmrg;; Software Foundation; either version 3 of the License, or (at your option) 663d1a8abSmrg;; any later version. 763d1a8abSmrg 863d1a8abSmrg;; This file is distributed in the hope that it will be useful, but WITHOUT 963d1a8abSmrg;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1063d1a8abSmrg;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1163d1a8abSmrg;; for more details. 1263d1a8abSmrg 1363d1a8abSmrg;; You should have received a copy of the GNU General Public License 1463d1a8abSmrg;; along with GCC; see the file COPYING3. If not see 1563d1a8abSmrg;; <http://www.gnu.org/licenses/>. 1663d1a8abSmrg 1763d1a8abSmrg 1863d1a8abSmrg;; This includes expands for all the intrinsics. 1963d1a8abSmrg;; spu_expand_builtin looks at the mode of match_operand. 2063d1a8abSmrg 2163d1a8abSmrg 2263d1a8abSmrg;; load/store 2363d1a8abSmrg 2463d1a8abSmrg(define_expand "spu_lqd" 2563d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 2663d1a8abSmrg (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 2763d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "")) 2863d1a8abSmrg (const_int -16))))] 2963d1a8abSmrg "" 3063d1a8abSmrg { 3163d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 3263d1a8abSmrg && (INTVAL (operands[2]) & 15) != 0) 3363d1a8abSmrg operands[2] = GEN_INT (INTVAL (operands[2]) & -16); 3463d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 3563d1a8abSmrg { 3663d1a8abSmrg rtx op2 = operands[2]; 3763d1a8abSmrg operands[2] = force_reg (Pmode, operands[2]); 3863d1a8abSmrg if (!ALIGNED_SYMBOL_REF_P (op2)) 3963d1a8abSmrg emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16))); 4063d1a8abSmrg } 4163d1a8abSmrg }) 4263d1a8abSmrg 4363d1a8abSmrg(define_expand "spu_lqx" 4463d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 4563d1a8abSmrg (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 4663d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "")) 4763d1a8abSmrg (const_int -16))))] 4863d1a8abSmrg "" 4963d1a8abSmrg "") 5063d1a8abSmrg 5163d1a8abSmrg(define_expand "spu_lqa" 5263d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 5363d1a8abSmrg (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "") 5463d1a8abSmrg (const_int -16))))] 5563d1a8abSmrg "" 5663d1a8abSmrg { 5763d1a8abSmrg if (GET_CODE (operands[1]) == CONST_INT 5863d1a8abSmrg && (INTVAL (operands[1]) & 15) != 0) 5963d1a8abSmrg operands[1] = GEN_INT (INTVAL (operands[1]) & -16); 6063d1a8abSmrg }) 6163d1a8abSmrg 6263d1a8abSmrg(define_expand "spu_lqr" 6363d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 6463d1a8abSmrg (mem:TI (and:SI (match_operand:SI 1 "address_operand" "") 6563d1a8abSmrg (const_int -16))))] 6663d1a8abSmrg "" 6763d1a8abSmrg "") 6863d1a8abSmrg 6963d1a8abSmrg(define_expand "spu_stqd" 7063d1a8abSmrg [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 7163d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "")) 7263d1a8abSmrg (const_int -16))) 7363d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r,r"))] 7463d1a8abSmrg "" 7563d1a8abSmrg { 7663d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 7763d1a8abSmrg && (INTVAL (operands[2]) & 15) != 0) 7863d1a8abSmrg operands[2] = GEN_INT (INTVAL (operands[2]) & -16); 7963d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 8063d1a8abSmrg { 8163d1a8abSmrg rtx op2 = operands[2]; 8263d1a8abSmrg operands[2] = force_reg (Pmode, operands[2]); 8363d1a8abSmrg if (!ALIGNED_SYMBOL_REF_P (op2)) 8463d1a8abSmrg emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16))); 8563d1a8abSmrg } 8663d1a8abSmrg }) 8763d1a8abSmrg 8863d1a8abSmrg(define_expand "spu_stqx" 8963d1a8abSmrg [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 9063d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "")) 9163d1a8abSmrg (const_int -16))) 9263d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r"))] 9363d1a8abSmrg "" 9463d1a8abSmrg "") 9563d1a8abSmrg 9663d1a8abSmrg(define_expand "spu_stqa" 9763d1a8abSmrg [(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "") 9863d1a8abSmrg (const_int -16))) 9963d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r"))] 10063d1a8abSmrg "" 10163d1a8abSmrg { 10263d1a8abSmrg if (GET_CODE (operands[1]) == CONST_INT 10363d1a8abSmrg && (INTVAL (operands[1]) & 15) != 0) 10463d1a8abSmrg operands[1] = GEN_INT (INTVAL (operands[1]) & -16); 10563d1a8abSmrg }) 10663d1a8abSmrg 10763d1a8abSmrg(define_expand "spu_stqr" 10863d1a8abSmrg [(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "") 10963d1a8abSmrg (const_int -16))) 11063d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" ""))] 11163d1a8abSmrg "" 11263d1a8abSmrg "") 11363d1a8abSmrg 11463d1a8abSmrg 11563d1a8abSmrg;; generate control word 11663d1a8abSmrg 11763d1a8abSmrg(define_expand "spu_cbx" 11863d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 11963d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 12063d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 12163d1a8abSmrg (const_int 1)] UNSPEC_CPAT))] 12263d1a8abSmrg "" 12363d1a8abSmrg "") 12463d1a8abSmrg 12563d1a8abSmrg(define_expand "spu_chx" 12663d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 12763d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 12863d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 12963d1a8abSmrg (const_int 2)] UNSPEC_CPAT))] 13063d1a8abSmrg "" 13163d1a8abSmrg "") 13263d1a8abSmrg 13363d1a8abSmrg(define_expand "spu_cwx" 13463d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 13563d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 13663d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 13763d1a8abSmrg (const_int 4)] UNSPEC_CPAT))] 13863d1a8abSmrg "" 13963d1a8abSmrg "") 14063d1a8abSmrg 14163d1a8abSmrg(define_expand "spu_cdx" 14263d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 14363d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 14463d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 14563d1a8abSmrg (const_int 8)] UNSPEC_CPAT))] 14663d1a8abSmrg "" 14763d1a8abSmrg "") 14863d1a8abSmrg 14963d1a8abSmrg 15063d1a8abSmrg 15163d1a8abSmrg;; Constant formation 15263d1a8abSmrg 15363d1a8abSmrg(define_expand "spu_ilhu" 15463d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 15563d1a8abSmrg (const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))] 15663d1a8abSmrg "" 15763d1a8abSmrg "{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16)))); 15863d1a8abSmrg DONE; 15963d1a8abSmrg }") 16063d1a8abSmrg 16163d1a8abSmrg 16263d1a8abSmrg;; integer subtract 16363d1a8abSmrg(define_expand "spu_sfh" 16463d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "") 16563d1a8abSmrg (minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "") 16663d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "")))] 16763d1a8abSmrg "" 16863d1a8abSmrg "") 16963d1a8abSmrg 17063d1a8abSmrg(define_expand "spu_sf" 17163d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 17263d1a8abSmrg (minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "") 17363d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")))] 17463d1a8abSmrg "" 17563d1a8abSmrg "") 17663d1a8abSmrg 17763d1a8abSmrg(define_expand "spu_sfx" 17863d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 17963d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 18063d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "") 18163d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))] 18263d1a8abSmrg "" 18363d1a8abSmrg "") 18463d1a8abSmrg 18563d1a8abSmrg(define_expand "spu_bg" 18663d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 18763d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 18863d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))] 18963d1a8abSmrg "" 19063d1a8abSmrg "") 19163d1a8abSmrg 19263d1a8abSmrg(define_expand "spu_bgx" 19363d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 19463d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 19563d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "") 19663d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))] 19763d1a8abSmrg "" 19863d1a8abSmrg "") 19963d1a8abSmrg 20063d1a8abSmrg(define_insn "spu_mpya" 20163d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 20263d1a8abSmrg (plus:V4SI 20363d1a8abSmrg (mult:V4SI 20463d1a8abSmrg (sign_extend:V4SI 20563d1a8abSmrg (vec_select:V4HI 20663d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 20763d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))) 20863d1a8abSmrg (sign_extend:V4SI 20963d1a8abSmrg (vec_select:V4HI 21063d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 21163d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 21263d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "r")))] 21363d1a8abSmrg "" 21463d1a8abSmrg "mpya\t%0,%1,%2,%3" 21563d1a8abSmrg [(set_attr "type" "fp7")]) 21663d1a8abSmrg 21763d1a8abSmrg(define_insn "spu_mpyh" 21863d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 21963d1a8abSmrg (ashift:V4SI 22063d1a8abSmrg (mult:V4SI 22163d1a8abSmrg (sign_extend:V4SI 22263d1a8abSmrg (vec_select:V4HI 22363d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 22463d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 22563d1a8abSmrg (sign_extend:V4SI 22663d1a8abSmrg (vec_select:V4HI 22763d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 22863d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 22963d1a8abSmrg (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))] 23063d1a8abSmrg "" 23163d1a8abSmrg "mpyh\t%0,%1,%2" 23263d1a8abSmrg [(set_attr "type" "fp7")]) 23363d1a8abSmrg 23463d1a8abSmrg(define_insn "spu_mpys" 23563d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 23663d1a8abSmrg (ashiftrt:V4SI 23763d1a8abSmrg (mult:V4SI 23863d1a8abSmrg (sign_extend:V4SI 23963d1a8abSmrg (vec_select:V4HI 24063d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 24163d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))) 24263d1a8abSmrg (sign_extend:V4SI 24363d1a8abSmrg (vec_select:V4HI 24463d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 24563d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 24663d1a8abSmrg (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))] 24763d1a8abSmrg "" 24863d1a8abSmrg "mpys\t%0,%1,%2" 24963d1a8abSmrg [(set_attr "type" "fp7")]) 25063d1a8abSmrg 25163d1a8abSmrg(define_insn "spu_mpyhhau" 25263d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 25363d1a8abSmrg (plus:V4SI 25463d1a8abSmrg (mult:V4SI 25563d1a8abSmrg (zero_extend:V4SI 25663d1a8abSmrg (vec_select:V4HI 25763d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 25863d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 25963d1a8abSmrg (zero_extend:V4SI 26063d1a8abSmrg (vec_select:V4HI 26163d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 26263d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))) 26363d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "0")))] 26463d1a8abSmrg "" 26563d1a8abSmrg "mpyhhau\t%0,%1,%2" 26663d1a8abSmrg [(set_attr "type" "fp7")]) 26763d1a8abSmrg 26863d1a8abSmrg(define_insn "spu_mpyhha" 26963d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 27063d1a8abSmrg (plus:V4SI 27163d1a8abSmrg (mult:V4SI 27263d1a8abSmrg (sign_extend:V4SI 27363d1a8abSmrg (vec_select:V4HI 27463d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 27563d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 27663d1a8abSmrg (sign_extend:V4SI 27763d1a8abSmrg (vec_select:V4HI 27863d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 27963d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))) 28063d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "0")))] 28163d1a8abSmrg "" 28263d1a8abSmrg "mpyhha\t%0,%1,%2" 28363d1a8abSmrg [(set_attr "type" "fp7")]) 28463d1a8abSmrg 28563d1a8abSmrg;; form select mask 28663d1a8abSmrg(define_insn "spu_fsmb" 28763d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r") 28863d1a8abSmrg (unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))] 28963d1a8abSmrg "" 29063d1a8abSmrg "@ 29163d1a8abSmrg fsmb\t%0,%1 29263d1a8abSmrg fsmbi\t%0,%1" 29363d1a8abSmrg [(set_attr "type" "shuf")]) 29463d1a8abSmrg 29563d1a8abSmrg(define_insn "spu_fsmh" 29663d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 29763d1a8abSmrg (unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))] 29863d1a8abSmrg "" 29963d1a8abSmrg "fsmh\t%0,%1" 30063d1a8abSmrg [(set_attr "type" "shuf")]) 30163d1a8abSmrg 30263d1a8abSmrg(define_insn "spu_fsm" 30363d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 30463d1a8abSmrg (unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))] 30563d1a8abSmrg "" 30663d1a8abSmrg "fsm\t%0,%1" 30763d1a8abSmrg [(set_attr "type" "shuf")]) 30863d1a8abSmrg 30963d1a8abSmrg 31063d1a8abSmrg;; gather bits 31163d1a8abSmrg(define_insn "spu_gbb" 31263d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 31363d1a8abSmrg (unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))] 31463d1a8abSmrg "" 31563d1a8abSmrg "gbb\t%0,%1" 31663d1a8abSmrg [(set_attr "type" "shuf")]) 31763d1a8abSmrg 31863d1a8abSmrg(define_insn "spu_gbh" 31963d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 32063d1a8abSmrg (unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))] 32163d1a8abSmrg "" 32263d1a8abSmrg "gbh\t%0,%1" 32363d1a8abSmrg [(set_attr "type" "shuf")]) 32463d1a8abSmrg 32563d1a8abSmrg(define_insn "spu_gb" 32663d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 32763d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))] 32863d1a8abSmrg "" 32963d1a8abSmrg "gb\t%0,%1" 33063d1a8abSmrg [(set_attr "type" "shuf")]) 33163d1a8abSmrg 33263d1a8abSmrg;; misc byte operations 33363d1a8abSmrg(define_insn "spu_avgb" 33463d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") 33563d1a8abSmrg (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r") 33663d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))] 33763d1a8abSmrg "" 33863d1a8abSmrg "avgb\t%0,%1,%2" 33963d1a8abSmrg [(set_attr "type" "fxb")]) 34063d1a8abSmrg 34163d1a8abSmrg(define_insn "spu_absdb" 34263d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") 34363d1a8abSmrg (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r") 34463d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))] 34563d1a8abSmrg "" 34663d1a8abSmrg "absdb\t%0,%1,%2" 34763d1a8abSmrg [(set_attr "type" "fxb")]) 34863d1a8abSmrg 34963d1a8abSmrg(define_insn "spu_sumb" 35063d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 35163d1a8abSmrg (unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r") 35263d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))] 35363d1a8abSmrg "" 35463d1a8abSmrg "sumb\t%0,%1,%2" 35563d1a8abSmrg [(set_attr "type" "fxb")]) 35663d1a8abSmrg 35763d1a8abSmrg;; sign extend 35863d1a8abSmrg(define_insn "spu_xsbh" 35963d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 36063d1a8abSmrg (sign_extend:V8HI 36163d1a8abSmrg (vec_select:V8QI 36263d1a8abSmrg (match_operand:V16QI 1 "spu_reg_operand" "r") 36363d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7) 36463d1a8abSmrg (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))] 36563d1a8abSmrg "" 36663d1a8abSmrg "xsbh\t%0,%1") 36763d1a8abSmrg 36863d1a8abSmrg(define_insn "spu_xshw" 36963d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 37063d1a8abSmrg (sign_extend:V4SI 37163d1a8abSmrg (vec_select:V4HI 37263d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 37363d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))] 37463d1a8abSmrg "" 37563d1a8abSmrg "xshw\t%0,%1") 37663d1a8abSmrg 37763d1a8abSmrg(define_insn "spu_xswd" 37863d1a8abSmrg [(set (match_operand:V2DI 0 "spu_reg_operand" "=r") 37963d1a8abSmrg (sign_extend:V2DI 38063d1a8abSmrg (vec_select:V2SI 38163d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r") 38263d1a8abSmrg (parallel [(const_int 1)(const_int 3)]))))] 38363d1a8abSmrg "" 38463d1a8abSmrg "xswd\t%0,%1") 38563d1a8abSmrg 38663d1a8abSmrg;; or across 38763d1a8abSmrg 38863d1a8abSmrg(define_insn "spu_orx" 38963d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 39063d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))] 39163d1a8abSmrg "" 39263d1a8abSmrg "orx\t%0,%1") 39363d1a8abSmrg 39463d1a8abSmrg 39563d1a8abSmrg;; compare & halt 39663d1a8abSmrg(define_insn "spu_heq" 39763d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 39863d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)] 39963d1a8abSmrg "" 40063d1a8abSmrg "@ 40163d1a8abSmrg heq\t%0,%1 40263d1a8abSmrg heqi\t%0,%1") 40363d1a8abSmrg 40463d1a8abSmrg(define_insn "spu_hgt" 40563d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 40663d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)] 40763d1a8abSmrg "" 40863d1a8abSmrg "@ 40963d1a8abSmrg hgt\t%0,%1 41063d1a8abSmrg hgti\t%0,%1") 41163d1a8abSmrg 41263d1a8abSmrg(define_insn "spu_hlgt" 41363d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 41463d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)] 41563d1a8abSmrg "" 41663d1a8abSmrg "@ 41763d1a8abSmrg hlgt\t%0,%1 41863d1a8abSmrg hlgti\t%0,%1") 41963d1a8abSmrg 42063d1a8abSmrg;; branches 42163d1a8abSmrg 42263d1a8abSmrg;; The description below hides the fact that bisled conditionally 42363d1a8abSmrg;; executes the call depending on the value in channel 0. This was 42463d1a8abSmrg;; done so that the description would conform to the format of a call 42563d1a8abSmrg;; insn. Otherwise (if this were not part of call insn), the link 42663d1a8abSmrg;; register, $lr, would not be saved/restored in the prologue/epilogue. 42763d1a8abSmrg 42863d1a8abSmrg(define_insn "spu_bisled" 42963d1a8abSmrg [(parallel 43063d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 43163d1a8abSmrg (const_int 0)) 43263d1a8abSmrg (clobber (reg:SI 0)) 43363d1a8abSmrg (clobber (reg:SI 130)) 43463d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 43563d1a8abSmrg (use (const_int 0))])] 43663d1a8abSmrg "" 43763d1a8abSmrg "bisled\t$lr,%0" 43863d1a8abSmrg [(set_attr "type" "br")]) 43963d1a8abSmrg 44063d1a8abSmrg(define_insn "spu_bisledd" 44163d1a8abSmrg [(parallel 44263d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 44363d1a8abSmrg (const_int 0)) 44463d1a8abSmrg (clobber (reg:SI 0)) 44563d1a8abSmrg (clobber (reg:SI 130)) 44663d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 44763d1a8abSmrg (use (const_int 1))])] 44863d1a8abSmrg "" 44963d1a8abSmrg "bisledd\t$lr,%0" 45063d1a8abSmrg [(set_attr "type" "br")]) 45163d1a8abSmrg 45263d1a8abSmrg(define_insn "spu_bislede" 45363d1a8abSmrg [(parallel 45463d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 45563d1a8abSmrg (const_int 0)) 45663d1a8abSmrg (clobber (reg:SI 0)) 45763d1a8abSmrg (clobber (reg:SI 130)) 45863d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 45963d1a8abSmrg (use (const_int 2))])] 46063d1a8abSmrg "" 46163d1a8abSmrg "bislede\t$lr,%0" 46263d1a8abSmrg [(set_attr "type" "br")]) 46363d1a8abSmrg 46463d1a8abSmrg;; float convert 46563d1a8abSmrg(define_expand "spu_csflt" 46663d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand") 46763d1a8abSmrg (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand") 46863d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 46963d1a8abSmrg "" 47063d1a8abSmrg{ 47163d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 47263d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 47363d1a8abSmrg { 47463d1a8abSmrg error ("spu_convtf expects an integer literal in the range [0, 127]."); 47563d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 47663d1a8abSmrg } 47763d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 47863d1a8abSmrg { 47963d1a8abSmrg rtx exp2; 48063d1a8abSmrg rtx cnv = gen_reg_rtx (V4SFmode); 48163d1a8abSmrg rtx scale = gen_reg_rtx (SImode); 48263d1a8abSmrg rtx op2 = force_reg (SImode, operands[2]); 48363d1a8abSmrg rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1)); 48463d1a8abSmrg emit_insn (gen_subsi3 (scale, const1_rtx, op2)); 48563d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, scale); 48663d1a8abSmrg emit_insn (gen_floatv4siv4sf2_mul (cnv, operands[1], m1)); 48763d1a8abSmrg emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2)); 48863d1a8abSmrg } 48963d1a8abSmrg else 49063d1a8abSmrg { 49163d1a8abSmrg rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 49263d1a8abSmrg emit_insn (gen_floatv4siv4sf2_div (operands[0], operands[1], exp2)); 49363d1a8abSmrg } 49463d1a8abSmrg DONE; 49563d1a8abSmrg}) 49663d1a8abSmrg 49763d1a8abSmrg(define_expand "spu_cflts" 49863d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand") 49963d1a8abSmrg (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand") 50063d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 50163d1a8abSmrg "" 50263d1a8abSmrg{ 50363d1a8abSmrg rtx exp2; 50463d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 50563d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 50663d1a8abSmrg { 50763d1a8abSmrg error ("spu_convts expects an integer literal in the range [0, 127]."); 50863d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 50963d1a8abSmrg } 51063d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 51163d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 51263d1a8abSmrg { 51363d1a8abSmrg rtx mul = gen_reg_rtx (V4SFmode); 51463d1a8abSmrg emit_insn (gen_mulv4sf3 (mul, operands[1], exp2)); 51563d1a8abSmrg emit_insn (gen_fix_truncv4sfv4si2 (operands[0], mul)); 51663d1a8abSmrg } 51763d1a8abSmrg else 51863d1a8abSmrg emit_insn (gen_fix_truncv4sfv4si2_mul (operands[0], operands[1], exp2)); 51963d1a8abSmrg DONE; 52063d1a8abSmrg}) 52163d1a8abSmrg 52263d1a8abSmrg(define_expand "spu_cuflt" 52363d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 52463d1a8abSmrg (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand") 52563d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 52663d1a8abSmrg "" 52763d1a8abSmrg{ 52863d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 52963d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 53063d1a8abSmrg { 53163d1a8abSmrg error ("spu_convtf expects an integer literal in the range [0, 127]."); 53263d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 53363d1a8abSmrg } 53463d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 53563d1a8abSmrg { 53663d1a8abSmrg rtx exp2; 53763d1a8abSmrg rtx cnv = gen_reg_rtx (V4SFmode); 53863d1a8abSmrg rtx scale = gen_reg_rtx (SImode); 53963d1a8abSmrg rtx op2 = force_reg (SImode, operands[2]); 54063d1a8abSmrg rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1)); 54163d1a8abSmrg emit_insn (gen_subsi3 (scale, const1_rtx, op2)); 54263d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, scale); 54363d1a8abSmrg emit_insn (gen_floatunsv4siv4sf2_mul (cnv, operands[1], m1)); 54463d1a8abSmrg emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2)); 54563d1a8abSmrg } 54663d1a8abSmrg else 54763d1a8abSmrg { 54863d1a8abSmrg rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 54963d1a8abSmrg emit_insn (gen_floatunsv4siv4sf2_div (operands[0], operands[1], exp2)); 55063d1a8abSmrg } 55163d1a8abSmrg DONE; 55263d1a8abSmrg}) 55363d1a8abSmrg 55463d1a8abSmrg(define_expand "spu_cfltu" 55563d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand") 55663d1a8abSmrg (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand") 55763d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 55863d1a8abSmrg "" 55963d1a8abSmrg{ 56063d1a8abSmrg rtx exp2; 56163d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 56263d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 56363d1a8abSmrg { 56463d1a8abSmrg error ("spu_convtu expects an integer literal in the range [0, 127]."); 56563d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 56663d1a8abSmrg } 56763d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 56863d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 56963d1a8abSmrg { 57063d1a8abSmrg rtx mul = gen_reg_rtx (V4SFmode); 57163d1a8abSmrg emit_insn (gen_mulv4sf3 (mul, operands[1], exp2)); 57263d1a8abSmrg emit_insn (gen_fixuns_truncv4sfv4si2 (operands[0], mul)); 57363d1a8abSmrg } 57463d1a8abSmrg else 57563d1a8abSmrg emit_insn (gen_fixuns_truncv4sfv4si2_mul (operands[0], operands[1], exp2)); 57663d1a8abSmrg DONE; 57763d1a8abSmrg}) 57863d1a8abSmrg 57963d1a8abSmrg(define_expand "spu_frds" 58063d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "") 58163d1a8abSmrg (vec_select:V4SF 58263d1a8abSmrg (vec_concat:V4SF 58363d1a8abSmrg (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "")) 58463d1a8abSmrg (match_dup:V2SF 2)) 58563d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] 58663d1a8abSmrg "" 58763d1a8abSmrg "operands[2] = spu_const(V2SFmode, 0);") 58863d1a8abSmrg 58963d1a8abSmrg(define_insn "_frds" 59063d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 59163d1a8abSmrg (vec_select:V4SF 59263d1a8abSmrg (vec_concat:V4SF 59363d1a8abSmrg (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r")) 59463d1a8abSmrg (match_operand:V2SF 2 "vec_imm_operand" "i")) 59563d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] 59663d1a8abSmrg "" 59763d1a8abSmrg "frds\t%0,%1" 59863d1a8abSmrg [(set_attr "type" "fpd")]) 59963d1a8abSmrg 60063d1a8abSmrg(define_insn "spu_fesd" 60163d1a8abSmrg [(set (match_operand:V2DF 0 "spu_reg_operand" "=r") 60263d1a8abSmrg (float_extend:V2DF 60363d1a8abSmrg (vec_select:V2SF 60463d1a8abSmrg (match_operand:V4SF 1 "spu_reg_operand" "r") 60563d1a8abSmrg (parallel [(const_int 0)(const_int 2)]))))] 60663d1a8abSmrg "" 60763d1a8abSmrg "fesd\t%0,%1" 60863d1a8abSmrg [(set_attr "type" "fpd")]) 60963d1a8abSmrg 61063d1a8abSmrg;; control 61163d1a8abSmrg(define_insn "spu_stop" 61263d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)] 61363d1a8abSmrg "" 61463d1a8abSmrg "stop\t%0" 61563d1a8abSmrg [(set_attr "type" "br")]) 61663d1a8abSmrg 61763d1a8abSmrg(define_insn "spu_stopd" 61863d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r") 61963d1a8abSmrg (match_operand:SI 1 "spu_reg_operand" "r") 62063d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)] 62163d1a8abSmrg "" 62263d1a8abSmrg "stopd\t%0,%1,%2" 62363d1a8abSmrg [(set_attr "type" "br")]) 62463d1a8abSmrg 62563d1a8abSmrg;; interrupt disable/enable 62663d1a8abSmrg(define_expand "spu_idisable" 62763d1a8abSmrg [(parallel 62863d1a8abSmrg [(unspec_volatile [(const_int 0)] UNSPEC_SET_INTR) 62963d1a8abSmrg (clobber (match_dup:SI 0)) 63063d1a8abSmrg (clobber (mem:BLK (scratch)))])] 63163d1a8abSmrg "" 63263d1a8abSmrg "operands[0] = gen_reg_rtx (SImode);") 63363d1a8abSmrg 63463d1a8abSmrg(define_expand "spu_ienable" 63563d1a8abSmrg [(parallel 63663d1a8abSmrg [(unspec_volatile [(const_int 1)] UNSPEC_SET_INTR) 63763d1a8abSmrg (clobber (match_dup:SI 0)) 63863d1a8abSmrg (clobber (mem:BLK (scratch)))])] 63963d1a8abSmrg "" 64063d1a8abSmrg "operands[0] = gen_reg_rtx (SImode);") 64163d1a8abSmrg 64263d1a8abSmrg(define_insn "set_intr" 64363d1a8abSmrg [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR) 64463d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 64563d1a8abSmrg (clobber (mem:BLK (scratch)))] 64663d1a8abSmrg "! flag_pic" 64763d1a8abSmrg "ila\t%0,.+8\;bi%I1\t%0" 64863d1a8abSmrg [(set_attr "length" "8") 64963d1a8abSmrg (set_attr "type" "multi0")]) 65063d1a8abSmrg 65163d1a8abSmrg(define_insn "set_intr_pic" 65263d1a8abSmrg [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR) 65363d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 65463d1a8abSmrg (clobber (mem:BLK (scratch)))] 65563d1a8abSmrg "flag_pic" 65663d1a8abSmrg "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0" 65763d1a8abSmrg [(set_attr "length" "12") 65863d1a8abSmrg (set_attr "type" "multi1")]) 65963d1a8abSmrg 66063d1a8abSmrg(define_insn "set_intr_cc" 66163d1a8abSmrg [(cond_exec (match_operator 1 "branch_comparison_operator" 66263d1a8abSmrg [(match_operand 2 "spu_reg_operand" "r") 66363d1a8abSmrg (const_int 0)]) 66463d1a8abSmrg (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR) 66563d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 66663d1a8abSmrg (clobber (mem:BLK (scratch)))]))] 66763d1a8abSmrg "! flag_pic" 66863d1a8abSmrg "ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0" 66963d1a8abSmrg [(set_attr "length" "8") 67063d1a8abSmrg (set_attr "type" "multi0")]) 67163d1a8abSmrg 67263d1a8abSmrg(define_insn "set_intr_cc_pic" 67363d1a8abSmrg [(cond_exec (match_operator 1 "branch_comparison_operator" 67463d1a8abSmrg [(match_operand 2 "spu_reg_operand" "r") 67563d1a8abSmrg (const_int 0)]) 67663d1a8abSmrg (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR) 67763d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 67863d1a8abSmrg (clobber (mem:BLK (scratch)))]))] 67963d1a8abSmrg "flag_pic" 68063d1a8abSmrg "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%b2%b1z%I3\t%2,%0" 68163d1a8abSmrg [(set_attr "length" "12") 68263d1a8abSmrg (set_attr "type" "multi1")]) 68363d1a8abSmrg 68463d1a8abSmrg(define_insn "set_intr_return" 68563d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")] UNSPEC_SET_INTR) 68663d1a8abSmrg (return)] 68763d1a8abSmrg "" 68863d1a8abSmrg "bi%I0\t$lr" 68963d1a8abSmrg [(set_attr "type" "br")]) 69063d1a8abSmrg 69163d1a8abSmrg(define_peephole2 69263d1a8abSmrg [(parallel 69363d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPEC_SET_INTR) 69463d1a8abSmrg (clobber (match_operand:SI 1 "spu_reg_operand")) 69563d1a8abSmrg (clobber (mem:BLK (scratch)))]) 69663d1a8abSmrg (use (reg:SI 0)) 69763d1a8abSmrg (return)] 69863d1a8abSmrg "" 69963d1a8abSmrg [(use (reg:SI 0)) 70063d1a8abSmrg (parallel 70163d1a8abSmrg [(unspec_volatile [(match_dup:SI 0)] UNSPEC_SET_INTR) 70263d1a8abSmrg (return)])] 70363d1a8abSmrg "") 70463d1a8abSmrg 70563d1a8abSmrg;; special purpose registers 70663d1a8abSmrg(define_insn "spu_fscrrd" 70763d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 70863d1a8abSmrg (unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))] 70963d1a8abSmrg "" 71063d1a8abSmrg "fscrrd\t%0" 71163d1a8abSmrg [(set_attr "type" "spr")]) 71263d1a8abSmrg 71363d1a8abSmrg(define_insn "spu_fscrwr" 71463d1a8abSmrg [(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)] 71563d1a8abSmrg "" 71663d1a8abSmrg "fscrwr\t$0,%0" 71763d1a8abSmrg [(set_attr "type" "spr")]) 71863d1a8abSmrg 71963d1a8abSmrg(define_insn "spu_mfspr" 72063d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 72163d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))] 72263d1a8abSmrg "" 72363d1a8abSmrg "mfspr\t%0,$sp%1" 72463d1a8abSmrg [(set_attr "type" "spr")]) 72563d1a8abSmrg 72663d1a8abSmrg(define_insn "spu_mtspr" 72763d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 72863d1a8abSmrg (match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)] 72963d1a8abSmrg "" 73063d1a8abSmrg "mtspr\t$sp%0,%1" 73163d1a8abSmrg [(set_attr "type" "spr")]) 73263d1a8abSmrg 73363d1a8abSmrg;; channels 73463d1a8abSmrg(define_expand "spu_rdch" 73563d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 73663d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))] 73763d1a8abSmrg "" 73863d1a8abSmrg "{ 73963d1a8abSmrg if (spu_safe_dma (INTVAL (operands[1]))) 74063d1a8abSmrg { 74163d1a8abSmrg emit_insn (gen_spu_rdch_clobber (operands[0], operands[1])); 74263d1a8abSmrg DONE; 74363d1a8abSmrg } 74463d1a8abSmrg }") 74563d1a8abSmrg 74663d1a8abSmrg(define_expand "spu_rchcnt" 74763d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "") 74863d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))] 74963d1a8abSmrg "" 75063d1a8abSmrg "{ 75163d1a8abSmrg if (spu_safe_dma (INTVAL (operands[1]))) 75263d1a8abSmrg { 75363d1a8abSmrg emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1])); 75463d1a8abSmrg DONE; 75563d1a8abSmrg } 75663d1a8abSmrg }") 75763d1a8abSmrg 75863d1a8abSmrg(define_expand "spu_wrch" 75963d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "") 76063d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)] 76163d1a8abSmrg "" 76263d1a8abSmrg "{ 76363d1a8abSmrg if (spu_safe_dma (INTVAL (operands[0]))) 76463d1a8abSmrg { 76563d1a8abSmrg emit_insn (gen_spu_wrch_clobber (operands[0], operands[1])); 76663d1a8abSmrg DONE; 76763d1a8abSmrg } 76863d1a8abSmrg }") 76963d1a8abSmrg 77063d1a8abSmrg(define_insn "spu_rdch_noclobber" 77163d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 77263d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))] 77363d1a8abSmrg "" 77463d1a8abSmrg "rdch\t%0,$ch%1" 77563d1a8abSmrg [(set_attr "type" "spr")]) 77663d1a8abSmrg 77763d1a8abSmrg(define_insn "spu_rchcnt_noclobber" 77863d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 77963d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))] 78063d1a8abSmrg "" 78163d1a8abSmrg "rchcnt\t%0,$ch%1" 78263d1a8abSmrg [(set_attr "type" "spr")]) 78363d1a8abSmrg 78463d1a8abSmrg(define_insn "spu_wrch_noclobber" 78563d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 78663d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)] 78763d1a8abSmrg "" 78863d1a8abSmrg "wrch\t$ch%0,%1" 78963d1a8abSmrg [(set_attr "type" "spr")]) 79063d1a8abSmrg 79163d1a8abSmrg(define_insn "spu_rdch_clobber" 79263d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 79363d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH)) 79463d1a8abSmrg (clobber (mem:BLK (scratch)))] 79563d1a8abSmrg "" 79663d1a8abSmrg "rdch\t%0,$ch%1" 79763d1a8abSmrg [(set_attr "type" "spr")]) 79863d1a8abSmrg 79963d1a8abSmrg(define_insn "spu_rchcnt_clobber" 80063d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 80163d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT)) 80263d1a8abSmrg (clobber (mem:BLK (scratch)))] 80363d1a8abSmrg "" 80463d1a8abSmrg "rchcnt\t%0,$ch%1" 80563d1a8abSmrg [(set_attr "type" "spr")]) 80663d1a8abSmrg 80763d1a8abSmrg(define_insn "spu_wrch_clobber" 80863d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 80963d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH) 81063d1a8abSmrg (clobber (mem:BLK (scratch)))] 81163d1a8abSmrg "" 81263d1a8abSmrg "wrch\t$ch%0,%1" 81363d1a8abSmrg [(set_attr "type" "spr")]) 81463d1a8abSmrg 81563d1a8abSmrg(define_expand "spu_splats" 81663d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 81763d1a8abSmrg (vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))] 81863d1a8abSmrg "" 81963d1a8abSmrg { 82063d1a8abSmrg spu_builtin_splats(operands); 82163d1a8abSmrg DONE; 82263d1a8abSmrg }) 82363d1a8abSmrg 82463d1a8abSmrg(define_expand "spu_extract" 82563d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 82663d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 82763d1a8abSmrg (match_operand 2 "spu_nonmem_operand" "")] 0))] 82863d1a8abSmrg "" 82963d1a8abSmrg { 83063d1a8abSmrg spu_builtin_extract (operands); 83163d1a8abSmrg DONE; 83263d1a8abSmrg }) 83363d1a8abSmrg 83463d1a8abSmrg(define_expand "spu_insert" 83563d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 83663d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 83763d1a8abSmrg (match_operand 2 "spu_reg_operand" "") 83863d1a8abSmrg (match_operand:SI 3 "spu_nonmem_operand" "")] 0))] 83963d1a8abSmrg "" 84063d1a8abSmrg { 84163d1a8abSmrg spu_builtin_insert(operands); 84263d1a8abSmrg DONE; 84363d1a8abSmrg }) 84463d1a8abSmrg 84563d1a8abSmrg(define_expand "spu_promote" 84663d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 84763d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 84863d1a8abSmrg (match_operand:SI 2 "immediate_operand" "")] 0))] 84963d1a8abSmrg "" 85063d1a8abSmrg { 85163d1a8abSmrg spu_builtin_promote(operands); 85263d1a8abSmrg DONE; 85363d1a8abSmrg }) 85463d1a8abSmrg 85563d1a8abSmrg;; Currently doing nothing with this but expanding its args. 85663d1a8abSmrg(define_expand "spu_align_hint" 85763d1a8abSmrg [(unspec [(match_operand:SI 0 "address_operand" "") 85863d1a8abSmrg (match_operand:SI 1 "immediate_operand" "") 85963d1a8abSmrg (match_operand:SI 2 "immediate_operand" "")] 0)] 86063d1a8abSmrg "" 86163d1a8abSmrg { 86263d1a8abSmrg DONE; 86363d1a8abSmrg }) 86463d1a8abSmrg 865