1*63d1a8abSmrg;; Copyright (C) 2006-2017 Free Software Foundation, Inc. 2*63d1a8abSmrg 3*63d1a8abSmrg;; This file is free software; you can redistribute it and/or modify it under 4*63d1a8abSmrg;; the terms of the GNU General Public License as published by the Free 5*63d1a8abSmrg;; Software Foundation; either version 3 of the License, or (at your option) 6*63d1a8abSmrg;; any later version. 7*63d1a8abSmrg 8*63d1a8abSmrg;; This file is distributed in the hope that it will be useful, but WITHOUT 9*63d1a8abSmrg;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10*63d1a8abSmrg;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11*63d1a8abSmrg;; for more details. 12*63d1a8abSmrg 13*63d1a8abSmrg;; You should have received a copy of the GNU General Public License 14*63d1a8abSmrg;; along with GCC; see the file COPYING3. If not see 15*63d1a8abSmrg;; <http://www.gnu.org/licenses/>. 16*63d1a8abSmrg 17*63d1a8abSmrg 18*63d1a8abSmrg;; This includes expands for all the intrinsics. 19*63d1a8abSmrg;; spu_expand_builtin looks at the mode of match_operand. 20*63d1a8abSmrg 21*63d1a8abSmrg 22*63d1a8abSmrg;; load/store 23*63d1a8abSmrg 24*63d1a8abSmrg(define_expand "spu_lqd" 25*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 26*63d1a8abSmrg (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 27*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "")) 28*63d1a8abSmrg (const_int -16))))] 29*63d1a8abSmrg "" 30*63d1a8abSmrg { 31*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 32*63d1a8abSmrg && (INTVAL (operands[2]) & 15) != 0) 33*63d1a8abSmrg operands[2] = GEN_INT (INTVAL (operands[2]) & -16); 34*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 35*63d1a8abSmrg { 36*63d1a8abSmrg rtx op2 = operands[2]; 37*63d1a8abSmrg operands[2] = force_reg (Pmode, operands[2]); 38*63d1a8abSmrg if (!ALIGNED_SYMBOL_REF_P (op2)) 39*63d1a8abSmrg emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16))); 40*63d1a8abSmrg } 41*63d1a8abSmrg }) 42*63d1a8abSmrg 43*63d1a8abSmrg(define_expand "spu_lqx" 44*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 45*63d1a8abSmrg (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 46*63d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "")) 47*63d1a8abSmrg (const_int -16))))] 48*63d1a8abSmrg "" 49*63d1a8abSmrg "") 50*63d1a8abSmrg 51*63d1a8abSmrg(define_expand "spu_lqa" 52*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 53*63d1a8abSmrg (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "") 54*63d1a8abSmrg (const_int -16))))] 55*63d1a8abSmrg "" 56*63d1a8abSmrg { 57*63d1a8abSmrg if (GET_CODE (operands[1]) == CONST_INT 58*63d1a8abSmrg && (INTVAL (operands[1]) & 15) != 0) 59*63d1a8abSmrg operands[1] = GEN_INT (INTVAL (operands[1]) & -16); 60*63d1a8abSmrg }) 61*63d1a8abSmrg 62*63d1a8abSmrg(define_expand "spu_lqr" 63*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 64*63d1a8abSmrg (mem:TI (and:SI (match_operand:SI 1 "address_operand" "") 65*63d1a8abSmrg (const_int -16))))] 66*63d1a8abSmrg "" 67*63d1a8abSmrg "") 68*63d1a8abSmrg 69*63d1a8abSmrg(define_expand "spu_stqd" 70*63d1a8abSmrg [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 71*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "")) 72*63d1a8abSmrg (const_int -16))) 73*63d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r,r"))] 74*63d1a8abSmrg "" 75*63d1a8abSmrg { 76*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 77*63d1a8abSmrg && (INTVAL (operands[2]) & 15) != 0) 78*63d1a8abSmrg operands[2] = GEN_INT (INTVAL (operands[2]) & -16); 79*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 80*63d1a8abSmrg { 81*63d1a8abSmrg rtx op2 = operands[2]; 82*63d1a8abSmrg operands[2] = force_reg (Pmode, operands[2]); 83*63d1a8abSmrg if (!ALIGNED_SYMBOL_REF_P (op2)) 84*63d1a8abSmrg emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16))); 85*63d1a8abSmrg } 86*63d1a8abSmrg }) 87*63d1a8abSmrg 88*63d1a8abSmrg(define_expand "spu_stqx" 89*63d1a8abSmrg [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "") 90*63d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "")) 91*63d1a8abSmrg (const_int -16))) 92*63d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r"))] 93*63d1a8abSmrg "" 94*63d1a8abSmrg "") 95*63d1a8abSmrg 96*63d1a8abSmrg(define_expand "spu_stqa" 97*63d1a8abSmrg [(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "") 98*63d1a8abSmrg (const_int -16))) 99*63d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" "r"))] 100*63d1a8abSmrg "" 101*63d1a8abSmrg { 102*63d1a8abSmrg if (GET_CODE (operands[1]) == CONST_INT 103*63d1a8abSmrg && (INTVAL (operands[1]) & 15) != 0) 104*63d1a8abSmrg operands[1] = GEN_INT (INTVAL (operands[1]) & -16); 105*63d1a8abSmrg }) 106*63d1a8abSmrg 107*63d1a8abSmrg(define_expand "spu_stqr" 108*63d1a8abSmrg [(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "") 109*63d1a8abSmrg (const_int -16))) 110*63d1a8abSmrg (match_operand:TI 0 "spu_reg_operand" ""))] 111*63d1a8abSmrg "" 112*63d1a8abSmrg "") 113*63d1a8abSmrg 114*63d1a8abSmrg 115*63d1a8abSmrg;; generate control word 116*63d1a8abSmrg 117*63d1a8abSmrg(define_expand "spu_cbx" 118*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 119*63d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 120*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 121*63d1a8abSmrg (const_int 1)] UNSPEC_CPAT))] 122*63d1a8abSmrg "" 123*63d1a8abSmrg "") 124*63d1a8abSmrg 125*63d1a8abSmrg(define_expand "spu_chx" 126*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 127*63d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 128*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 129*63d1a8abSmrg (const_int 2)] UNSPEC_CPAT))] 130*63d1a8abSmrg "" 131*63d1a8abSmrg "") 132*63d1a8abSmrg 133*63d1a8abSmrg(define_expand "spu_cwx" 134*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 135*63d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 136*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 137*63d1a8abSmrg (const_int 4)] UNSPEC_CPAT))] 138*63d1a8abSmrg "" 139*63d1a8abSmrg "") 140*63d1a8abSmrg 141*63d1a8abSmrg(define_expand "spu_cdx" 142*63d1a8abSmrg [(set (match_operand:TI 0 "spu_reg_operand" "") 143*63d1a8abSmrg (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "") 144*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand" "") 145*63d1a8abSmrg (const_int 8)] UNSPEC_CPAT))] 146*63d1a8abSmrg "" 147*63d1a8abSmrg "") 148*63d1a8abSmrg 149*63d1a8abSmrg 150*63d1a8abSmrg 151*63d1a8abSmrg;; Constant formation 152*63d1a8abSmrg 153*63d1a8abSmrg(define_expand "spu_ilhu" 154*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 155*63d1a8abSmrg (const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))] 156*63d1a8abSmrg "" 157*63d1a8abSmrg "{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16)))); 158*63d1a8abSmrg DONE; 159*63d1a8abSmrg }") 160*63d1a8abSmrg 161*63d1a8abSmrg 162*63d1a8abSmrg;; integer subtract 163*63d1a8abSmrg(define_expand "spu_sfh" 164*63d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "") 165*63d1a8abSmrg (minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "") 166*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "")))] 167*63d1a8abSmrg "" 168*63d1a8abSmrg "") 169*63d1a8abSmrg 170*63d1a8abSmrg(define_expand "spu_sf" 171*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 172*63d1a8abSmrg (minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "") 173*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")))] 174*63d1a8abSmrg "" 175*63d1a8abSmrg "") 176*63d1a8abSmrg 177*63d1a8abSmrg(define_expand "spu_sfx" 178*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 179*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 180*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "") 181*63d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))] 182*63d1a8abSmrg "" 183*63d1a8abSmrg "") 184*63d1a8abSmrg 185*63d1a8abSmrg(define_expand "spu_bg" 186*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 187*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 188*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))] 189*63d1a8abSmrg "" 190*63d1a8abSmrg "") 191*63d1a8abSmrg 192*63d1a8abSmrg(define_expand "spu_bgx" 193*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 194*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "") 195*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "") 196*63d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))] 197*63d1a8abSmrg "" 198*63d1a8abSmrg "") 199*63d1a8abSmrg 200*63d1a8abSmrg(define_insn "spu_mpya" 201*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 202*63d1a8abSmrg (plus:V4SI 203*63d1a8abSmrg (mult:V4SI 204*63d1a8abSmrg (sign_extend:V4SI 205*63d1a8abSmrg (vec_select:V4HI 206*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 207*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))) 208*63d1a8abSmrg (sign_extend:V4SI 209*63d1a8abSmrg (vec_select:V4HI 210*63d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 211*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 212*63d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "r")))] 213*63d1a8abSmrg "" 214*63d1a8abSmrg "mpya\t%0,%1,%2,%3" 215*63d1a8abSmrg [(set_attr "type" "fp7")]) 216*63d1a8abSmrg 217*63d1a8abSmrg(define_insn "spu_mpyh" 218*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 219*63d1a8abSmrg (ashift:V4SI 220*63d1a8abSmrg (mult:V4SI 221*63d1a8abSmrg (sign_extend:V4SI 222*63d1a8abSmrg (vec_select:V4HI 223*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 224*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 225*63d1a8abSmrg (sign_extend:V4SI 226*63d1a8abSmrg (vec_select:V4HI 227*63d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 228*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 229*63d1a8abSmrg (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))] 230*63d1a8abSmrg "" 231*63d1a8abSmrg "mpyh\t%0,%1,%2" 232*63d1a8abSmrg [(set_attr "type" "fp7")]) 233*63d1a8abSmrg 234*63d1a8abSmrg(define_insn "spu_mpys" 235*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 236*63d1a8abSmrg (ashiftrt:V4SI 237*63d1a8abSmrg (mult:V4SI 238*63d1a8abSmrg (sign_extend:V4SI 239*63d1a8abSmrg (vec_select:V4HI 240*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 241*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))) 242*63d1a8abSmrg (sign_extend:V4SI 243*63d1a8abSmrg (vec_select:V4HI 244*63d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 245*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))) 246*63d1a8abSmrg (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))] 247*63d1a8abSmrg "" 248*63d1a8abSmrg "mpys\t%0,%1,%2" 249*63d1a8abSmrg [(set_attr "type" "fp7")]) 250*63d1a8abSmrg 251*63d1a8abSmrg(define_insn "spu_mpyhhau" 252*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 253*63d1a8abSmrg (plus:V4SI 254*63d1a8abSmrg (mult:V4SI 255*63d1a8abSmrg (zero_extend:V4SI 256*63d1a8abSmrg (vec_select:V4HI 257*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 258*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 259*63d1a8abSmrg (zero_extend:V4SI 260*63d1a8abSmrg (vec_select:V4HI 261*63d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 262*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))) 263*63d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "0")))] 264*63d1a8abSmrg "" 265*63d1a8abSmrg "mpyhhau\t%0,%1,%2" 266*63d1a8abSmrg [(set_attr "type" "fp7")]) 267*63d1a8abSmrg 268*63d1a8abSmrg(define_insn "spu_mpyhha" 269*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 270*63d1a8abSmrg (plus:V4SI 271*63d1a8abSmrg (mult:V4SI 272*63d1a8abSmrg (sign_extend:V4SI 273*63d1a8abSmrg (vec_select:V4HI 274*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 275*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))) 276*63d1a8abSmrg (sign_extend:V4SI 277*63d1a8abSmrg (vec_select:V4HI 278*63d1a8abSmrg (match_operand:V8HI 2 "spu_reg_operand" "r") 279*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))) 280*63d1a8abSmrg (match_operand:V4SI 3 "spu_reg_operand" "0")))] 281*63d1a8abSmrg "" 282*63d1a8abSmrg "mpyhha\t%0,%1,%2" 283*63d1a8abSmrg [(set_attr "type" "fp7")]) 284*63d1a8abSmrg 285*63d1a8abSmrg;; form select mask 286*63d1a8abSmrg(define_insn "spu_fsmb" 287*63d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r") 288*63d1a8abSmrg (unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))] 289*63d1a8abSmrg "" 290*63d1a8abSmrg "@ 291*63d1a8abSmrg fsmb\t%0,%1 292*63d1a8abSmrg fsmbi\t%0,%1" 293*63d1a8abSmrg [(set_attr "type" "shuf")]) 294*63d1a8abSmrg 295*63d1a8abSmrg(define_insn "spu_fsmh" 296*63d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 297*63d1a8abSmrg (unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))] 298*63d1a8abSmrg "" 299*63d1a8abSmrg "fsmh\t%0,%1" 300*63d1a8abSmrg [(set_attr "type" "shuf")]) 301*63d1a8abSmrg 302*63d1a8abSmrg(define_insn "spu_fsm" 303*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 304*63d1a8abSmrg (unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))] 305*63d1a8abSmrg "" 306*63d1a8abSmrg "fsm\t%0,%1" 307*63d1a8abSmrg [(set_attr "type" "shuf")]) 308*63d1a8abSmrg 309*63d1a8abSmrg 310*63d1a8abSmrg;; gather bits 311*63d1a8abSmrg(define_insn "spu_gbb" 312*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 313*63d1a8abSmrg (unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))] 314*63d1a8abSmrg "" 315*63d1a8abSmrg "gbb\t%0,%1" 316*63d1a8abSmrg [(set_attr "type" "shuf")]) 317*63d1a8abSmrg 318*63d1a8abSmrg(define_insn "spu_gbh" 319*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 320*63d1a8abSmrg (unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))] 321*63d1a8abSmrg "" 322*63d1a8abSmrg "gbh\t%0,%1" 323*63d1a8abSmrg [(set_attr "type" "shuf")]) 324*63d1a8abSmrg 325*63d1a8abSmrg(define_insn "spu_gb" 326*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 327*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))] 328*63d1a8abSmrg "" 329*63d1a8abSmrg "gb\t%0,%1" 330*63d1a8abSmrg [(set_attr "type" "shuf")]) 331*63d1a8abSmrg 332*63d1a8abSmrg;; misc byte operations 333*63d1a8abSmrg(define_insn "spu_avgb" 334*63d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") 335*63d1a8abSmrg (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r") 336*63d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))] 337*63d1a8abSmrg "" 338*63d1a8abSmrg "avgb\t%0,%1,%2" 339*63d1a8abSmrg [(set_attr "type" "fxb")]) 340*63d1a8abSmrg 341*63d1a8abSmrg(define_insn "spu_absdb" 342*63d1a8abSmrg [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") 343*63d1a8abSmrg (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r") 344*63d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))] 345*63d1a8abSmrg "" 346*63d1a8abSmrg "absdb\t%0,%1,%2" 347*63d1a8abSmrg [(set_attr "type" "fxb")]) 348*63d1a8abSmrg 349*63d1a8abSmrg(define_insn "spu_sumb" 350*63d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 351*63d1a8abSmrg (unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r") 352*63d1a8abSmrg (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))] 353*63d1a8abSmrg "" 354*63d1a8abSmrg "sumb\t%0,%1,%2" 355*63d1a8abSmrg [(set_attr "type" "fxb")]) 356*63d1a8abSmrg 357*63d1a8abSmrg;; sign extend 358*63d1a8abSmrg(define_insn "spu_xsbh" 359*63d1a8abSmrg [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") 360*63d1a8abSmrg (sign_extend:V8HI 361*63d1a8abSmrg (vec_select:V8QI 362*63d1a8abSmrg (match_operand:V16QI 1 "spu_reg_operand" "r") 363*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7) 364*63d1a8abSmrg (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))] 365*63d1a8abSmrg "" 366*63d1a8abSmrg "xsbh\t%0,%1") 367*63d1a8abSmrg 368*63d1a8abSmrg(define_insn "spu_xshw" 369*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 370*63d1a8abSmrg (sign_extend:V4SI 371*63d1a8abSmrg (vec_select:V4HI 372*63d1a8abSmrg (match_operand:V8HI 1 "spu_reg_operand" "r") 373*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))] 374*63d1a8abSmrg "" 375*63d1a8abSmrg "xshw\t%0,%1") 376*63d1a8abSmrg 377*63d1a8abSmrg(define_insn "spu_xswd" 378*63d1a8abSmrg [(set (match_operand:V2DI 0 "spu_reg_operand" "=r") 379*63d1a8abSmrg (sign_extend:V2DI 380*63d1a8abSmrg (vec_select:V2SI 381*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r") 382*63d1a8abSmrg (parallel [(const_int 1)(const_int 3)]))))] 383*63d1a8abSmrg "" 384*63d1a8abSmrg "xswd\t%0,%1") 385*63d1a8abSmrg 386*63d1a8abSmrg;; or across 387*63d1a8abSmrg 388*63d1a8abSmrg(define_insn "spu_orx" 389*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 390*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))] 391*63d1a8abSmrg "" 392*63d1a8abSmrg "orx\t%0,%1") 393*63d1a8abSmrg 394*63d1a8abSmrg 395*63d1a8abSmrg;; compare & halt 396*63d1a8abSmrg(define_insn "spu_heq" 397*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 398*63d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)] 399*63d1a8abSmrg "" 400*63d1a8abSmrg "@ 401*63d1a8abSmrg heq\t%0,%1 402*63d1a8abSmrg heqi\t%0,%1") 403*63d1a8abSmrg 404*63d1a8abSmrg(define_insn "spu_hgt" 405*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 406*63d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)] 407*63d1a8abSmrg "" 408*63d1a8abSmrg "@ 409*63d1a8abSmrg hgt\t%0,%1 410*63d1a8abSmrg hgti\t%0,%1") 411*63d1a8abSmrg 412*63d1a8abSmrg(define_insn "spu_hlgt" 413*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r") 414*63d1a8abSmrg (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)] 415*63d1a8abSmrg "" 416*63d1a8abSmrg "@ 417*63d1a8abSmrg hlgt\t%0,%1 418*63d1a8abSmrg hlgti\t%0,%1") 419*63d1a8abSmrg 420*63d1a8abSmrg;; branches 421*63d1a8abSmrg 422*63d1a8abSmrg;; The description below hides the fact that bisled conditionally 423*63d1a8abSmrg;; executes the call depending on the value in channel 0. This was 424*63d1a8abSmrg;; done so that the description would conform to the format of a call 425*63d1a8abSmrg;; insn. Otherwise (if this were not part of call insn), the link 426*63d1a8abSmrg;; register, $lr, would not be saved/restored in the prologue/epilogue. 427*63d1a8abSmrg 428*63d1a8abSmrg(define_insn "spu_bisled" 429*63d1a8abSmrg [(parallel 430*63d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 431*63d1a8abSmrg (const_int 0)) 432*63d1a8abSmrg (clobber (reg:SI 0)) 433*63d1a8abSmrg (clobber (reg:SI 130)) 434*63d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 435*63d1a8abSmrg (use (const_int 0))])] 436*63d1a8abSmrg "" 437*63d1a8abSmrg "bisled\t$lr,%0" 438*63d1a8abSmrg [(set_attr "type" "br")]) 439*63d1a8abSmrg 440*63d1a8abSmrg(define_insn "spu_bisledd" 441*63d1a8abSmrg [(parallel 442*63d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 443*63d1a8abSmrg (const_int 0)) 444*63d1a8abSmrg (clobber (reg:SI 0)) 445*63d1a8abSmrg (clobber (reg:SI 130)) 446*63d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 447*63d1a8abSmrg (use (const_int 1))])] 448*63d1a8abSmrg "" 449*63d1a8abSmrg "bisledd\t$lr,%0" 450*63d1a8abSmrg [(set_attr "type" "br")]) 451*63d1a8abSmrg 452*63d1a8abSmrg(define_insn "spu_bislede" 453*63d1a8abSmrg [(parallel 454*63d1a8abSmrg [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r")) 455*63d1a8abSmrg (const_int 0)) 456*63d1a8abSmrg (clobber (reg:SI 0)) 457*63d1a8abSmrg (clobber (reg:SI 130)) 458*63d1a8abSmrg (use (match_operand:SI 1 "address_operand" "")) 459*63d1a8abSmrg (use (const_int 2))])] 460*63d1a8abSmrg "" 461*63d1a8abSmrg "bislede\t$lr,%0" 462*63d1a8abSmrg [(set_attr "type" "br")]) 463*63d1a8abSmrg 464*63d1a8abSmrg;; float convert 465*63d1a8abSmrg(define_expand "spu_csflt" 466*63d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand") 467*63d1a8abSmrg (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand") 468*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 469*63d1a8abSmrg "" 470*63d1a8abSmrg{ 471*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 472*63d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 473*63d1a8abSmrg { 474*63d1a8abSmrg error ("spu_convtf expects an integer literal in the range [0, 127]."); 475*63d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 476*63d1a8abSmrg } 477*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 478*63d1a8abSmrg { 479*63d1a8abSmrg rtx exp2; 480*63d1a8abSmrg rtx cnv = gen_reg_rtx (V4SFmode); 481*63d1a8abSmrg rtx scale = gen_reg_rtx (SImode); 482*63d1a8abSmrg rtx op2 = force_reg (SImode, operands[2]); 483*63d1a8abSmrg rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1)); 484*63d1a8abSmrg emit_insn (gen_subsi3 (scale, const1_rtx, op2)); 485*63d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, scale); 486*63d1a8abSmrg emit_insn (gen_floatv4siv4sf2_mul (cnv, operands[1], m1)); 487*63d1a8abSmrg emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2)); 488*63d1a8abSmrg } 489*63d1a8abSmrg else 490*63d1a8abSmrg { 491*63d1a8abSmrg rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 492*63d1a8abSmrg emit_insn (gen_floatv4siv4sf2_div (operands[0], operands[1], exp2)); 493*63d1a8abSmrg } 494*63d1a8abSmrg DONE; 495*63d1a8abSmrg}) 496*63d1a8abSmrg 497*63d1a8abSmrg(define_expand "spu_cflts" 498*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand") 499*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand") 500*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 501*63d1a8abSmrg "" 502*63d1a8abSmrg{ 503*63d1a8abSmrg rtx exp2; 504*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 505*63d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 506*63d1a8abSmrg { 507*63d1a8abSmrg error ("spu_convts expects an integer literal in the range [0, 127]."); 508*63d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 509*63d1a8abSmrg } 510*63d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 511*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 512*63d1a8abSmrg { 513*63d1a8abSmrg rtx mul = gen_reg_rtx (V4SFmode); 514*63d1a8abSmrg emit_insn (gen_mulv4sf3 (mul, operands[1], exp2)); 515*63d1a8abSmrg emit_insn (gen_fix_truncv4sfv4si2 (operands[0], mul)); 516*63d1a8abSmrg } 517*63d1a8abSmrg else 518*63d1a8abSmrg emit_insn (gen_fix_truncv4sfv4si2_mul (operands[0], operands[1], exp2)); 519*63d1a8abSmrg DONE; 520*63d1a8abSmrg}) 521*63d1a8abSmrg 522*63d1a8abSmrg(define_expand "spu_cuflt" 523*63d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 524*63d1a8abSmrg (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand") 525*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 526*63d1a8abSmrg "" 527*63d1a8abSmrg{ 528*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 529*63d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 530*63d1a8abSmrg { 531*63d1a8abSmrg error ("spu_convtf expects an integer literal in the range [0, 127]."); 532*63d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 533*63d1a8abSmrg } 534*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 535*63d1a8abSmrg { 536*63d1a8abSmrg rtx exp2; 537*63d1a8abSmrg rtx cnv = gen_reg_rtx (V4SFmode); 538*63d1a8abSmrg rtx scale = gen_reg_rtx (SImode); 539*63d1a8abSmrg rtx op2 = force_reg (SImode, operands[2]); 540*63d1a8abSmrg rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1)); 541*63d1a8abSmrg emit_insn (gen_subsi3 (scale, const1_rtx, op2)); 542*63d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, scale); 543*63d1a8abSmrg emit_insn (gen_floatunsv4siv4sf2_mul (cnv, operands[1], m1)); 544*63d1a8abSmrg emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2)); 545*63d1a8abSmrg } 546*63d1a8abSmrg else 547*63d1a8abSmrg { 548*63d1a8abSmrg rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 549*63d1a8abSmrg emit_insn (gen_floatunsv4siv4sf2_div (operands[0], operands[1], exp2)); 550*63d1a8abSmrg } 551*63d1a8abSmrg DONE; 552*63d1a8abSmrg}) 553*63d1a8abSmrg 554*63d1a8abSmrg(define_expand "spu_cfltu" 555*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand") 556*63d1a8abSmrg (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand") 557*63d1a8abSmrg (match_operand:SI 2 "spu_nonmem_operand")] 0 ))] 558*63d1a8abSmrg "" 559*63d1a8abSmrg{ 560*63d1a8abSmrg rtx exp2; 561*63d1a8abSmrg if (GET_CODE (operands[2]) == CONST_INT 562*63d1a8abSmrg && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127)) 563*63d1a8abSmrg { 564*63d1a8abSmrg error ("spu_convtu expects an integer literal in the range [0, 127]."); 565*63d1a8abSmrg operands[2] = force_reg (SImode, operands[2]); 566*63d1a8abSmrg } 567*63d1a8abSmrg exp2 = spu_gen_exp2 (V4SFmode, operands[2]); 568*63d1a8abSmrg if (GET_CODE (operands[2]) != CONST_INT) 569*63d1a8abSmrg { 570*63d1a8abSmrg rtx mul = gen_reg_rtx (V4SFmode); 571*63d1a8abSmrg emit_insn (gen_mulv4sf3 (mul, operands[1], exp2)); 572*63d1a8abSmrg emit_insn (gen_fixuns_truncv4sfv4si2 (operands[0], mul)); 573*63d1a8abSmrg } 574*63d1a8abSmrg else 575*63d1a8abSmrg emit_insn (gen_fixuns_truncv4sfv4si2_mul (operands[0], operands[1], exp2)); 576*63d1a8abSmrg DONE; 577*63d1a8abSmrg}) 578*63d1a8abSmrg 579*63d1a8abSmrg(define_expand "spu_frds" 580*63d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "") 581*63d1a8abSmrg (vec_select:V4SF 582*63d1a8abSmrg (vec_concat:V4SF 583*63d1a8abSmrg (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "")) 584*63d1a8abSmrg (match_dup:V2SF 2)) 585*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] 586*63d1a8abSmrg "" 587*63d1a8abSmrg "operands[2] = spu_const(V2SFmode, 0);") 588*63d1a8abSmrg 589*63d1a8abSmrg(define_insn "_frds" 590*63d1a8abSmrg [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 591*63d1a8abSmrg (vec_select:V4SF 592*63d1a8abSmrg (vec_concat:V4SF 593*63d1a8abSmrg (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r")) 594*63d1a8abSmrg (match_operand:V2SF 2 "vec_imm_operand" "i")) 595*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] 596*63d1a8abSmrg "" 597*63d1a8abSmrg "frds\t%0,%1" 598*63d1a8abSmrg [(set_attr "type" "fpd")]) 599*63d1a8abSmrg 600*63d1a8abSmrg(define_insn "spu_fesd" 601*63d1a8abSmrg [(set (match_operand:V2DF 0 "spu_reg_operand" "=r") 602*63d1a8abSmrg (float_extend:V2DF 603*63d1a8abSmrg (vec_select:V2SF 604*63d1a8abSmrg (match_operand:V4SF 1 "spu_reg_operand" "r") 605*63d1a8abSmrg (parallel [(const_int 0)(const_int 2)]))))] 606*63d1a8abSmrg "" 607*63d1a8abSmrg "fesd\t%0,%1" 608*63d1a8abSmrg [(set_attr "type" "fpd")]) 609*63d1a8abSmrg 610*63d1a8abSmrg;; control 611*63d1a8abSmrg(define_insn "spu_stop" 612*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)] 613*63d1a8abSmrg "" 614*63d1a8abSmrg "stop\t%0" 615*63d1a8abSmrg [(set_attr "type" "br")]) 616*63d1a8abSmrg 617*63d1a8abSmrg(define_insn "spu_stopd" 618*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r") 619*63d1a8abSmrg (match_operand:SI 1 "spu_reg_operand" "r") 620*63d1a8abSmrg (match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)] 621*63d1a8abSmrg "" 622*63d1a8abSmrg "stopd\t%0,%1,%2" 623*63d1a8abSmrg [(set_attr "type" "br")]) 624*63d1a8abSmrg 625*63d1a8abSmrg;; interrupt disable/enable 626*63d1a8abSmrg(define_expand "spu_idisable" 627*63d1a8abSmrg [(parallel 628*63d1a8abSmrg [(unspec_volatile [(const_int 0)] UNSPEC_SET_INTR) 629*63d1a8abSmrg (clobber (match_dup:SI 0)) 630*63d1a8abSmrg (clobber (mem:BLK (scratch)))])] 631*63d1a8abSmrg "" 632*63d1a8abSmrg "operands[0] = gen_reg_rtx (SImode);") 633*63d1a8abSmrg 634*63d1a8abSmrg(define_expand "spu_ienable" 635*63d1a8abSmrg [(parallel 636*63d1a8abSmrg [(unspec_volatile [(const_int 1)] UNSPEC_SET_INTR) 637*63d1a8abSmrg (clobber (match_dup:SI 0)) 638*63d1a8abSmrg (clobber (mem:BLK (scratch)))])] 639*63d1a8abSmrg "" 640*63d1a8abSmrg "operands[0] = gen_reg_rtx (SImode);") 641*63d1a8abSmrg 642*63d1a8abSmrg(define_insn "set_intr" 643*63d1a8abSmrg [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR) 644*63d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 645*63d1a8abSmrg (clobber (mem:BLK (scratch)))] 646*63d1a8abSmrg "! flag_pic" 647*63d1a8abSmrg "ila\t%0,.+8\;bi%I1\t%0" 648*63d1a8abSmrg [(set_attr "length" "8") 649*63d1a8abSmrg (set_attr "type" "multi0")]) 650*63d1a8abSmrg 651*63d1a8abSmrg(define_insn "set_intr_pic" 652*63d1a8abSmrg [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR) 653*63d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 654*63d1a8abSmrg (clobber (mem:BLK (scratch)))] 655*63d1a8abSmrg "flag_pic" 656*63d1a8abSmrg "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0" 657*63d1a8abSmrg [(set_attr "length" "12") 658*63d1a8abSmrg (set_attr "type" "multi1")]) 659*63d1a8abSmrg 660*63d1a8abSmrg(define_insn "set_intr_cc" 661*63d1a8abSmrg [(cond_exec (match_operator 1 "branch_comparison_operator" 662*63d1a8abSmrg [(match_operand 2 "spu_reg_operand" "r") 663*63d1a8abSmrg (const_int 0)]) 664*63d1a8abSmrg (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR) 665*63d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 666*63d1a8abSmrg (clobber (mem:BLK (scratch)))]))] 667*63d1a8abSmrg "! flag_pic" 668*63d1a8abSmrg "ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0" 669*63d1a8abSmrg [(set_attr "length" "8") 670*63d1a8abSmrg (set_attr "type" "multi0")]) 671*63d1a8abSmrg 672*63d1a8abSmrg(define_insn "set_intr_cc_pic" 673*63d1a8abSmrg [(cond_exec (match_operator 1 "branch_comparison_operator" 674*63d1a8abSmrg [(match_operand 2 "spu_reg_operand" "r") 675*63d1a8abSmrg (const_int 0)]) 676*63d1a8abSmrg (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR) 677*63d1a8abSmrg (clobber (match_operand:SI 0 "spu_reg_operand" "=&r")) 678*63d1a8abSmrg (clobber (mem:BLK (scratch)))]))] 679*63d1a8abSmrg "flag_pic" 680*63d1a8abSmrg "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%b2%b1z%I3\t%2,%0" 681*63d1a8abSmrg [(set_attr "length" "12") 682*63d1a8abSmrg (set_attr "type" "multi1")]) 683*63d1a8abSmrg 684*63d1a8abSmrg(define_insn "set_intr_return" 685*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")] UNSPEC_SET_INTR) 686*63d1a8abSmrg (return)] 687*63d1a8abSmrg "" 688*63d1a8abSmrg "bi%I0\t$lr" 689*63d1a8abSmrg [(set_attr "type" "br")]) 690*63d1a8abSmrg 691*63d1a8abSmrg(define_peephole2 692*63d1a8abSmrg [(parallel 693*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPEC_SET_INTR) 694*63d1a8abSmrg (clobber (match_operand:SI 1 "spu_reg_operand")) 695*63d1a8abSmrg (clobber (mem:BLK (scratch)))]) 696*63d1a8abSmrg (use (reg:SI 0)) 697*63d1a8abSmrg (return)] 698*63d1a8abSmrg "" 699*63d1a8abSmrg [(use (reg:SI 0)) 700*63d1a8abSmrg (parallel 701*63d1a8abSmrg [(unspec_volatile [(match_dup:SI 0)] UNSPEC_SET_INTR) 702*63d1a8abSmrg (return)])] 703*63d1a8abSmrg "") 704*63d1a8abSmrg 705*63d1a8abSmrg;; special purpose registers 706*63d1a8abSmrg(define_insn "spu_fscrrd" 707*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 708*63d1a8abSmrg (unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))] 709*63d1a8abSmrg "" 710*63d1a8abSmrg "fscrrd\t%0" 711*63d1a8abSmrg [(set_attr "type" "spr")]) 712*63d1a8abSmrg 713*63d1a8abSmrg(define_insn "spu_fscrwr" 714*63d1a8abSmrg [(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)] 715*63d1a8abSmrg "" 716*63d1a8abSmrg "fscrwr\t$0,%0" 717*63d1a8abSmrg [(set_attr "type" "spr")]) 718*63d1a8abSmrg 719*63d1a8abSmrg(define_insn "spu_mfspr" 720*63d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 721*63d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))] 722*63d1a8abSmrg "" 723*63d1a8abSmrg "mfspr\t%0,$sp%1" 724*63d1a8abSmrg [(set_attr "type" "spr")]) 725*63d1a8abSmrg 726*63d1a8abSmrg(define_insn "spu_mtspr" 727*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 728*63d1a8abSmrg (match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)] 729*63d1a8abSmrg "" 730*63d1a8abSmrg "mtspr\t$sp%0,%1" 731*63d1a8abSmrg [(set_attr "type" "spr")]) 732*63d1a8abSmrg 733*63d1a8abSmrg;; channels 734*63d1a8abSmrg(define_expand "spu_rdch" 735*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "") 736*63d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))] 737*63d1a8abSmrg "" 738*63d1a8abSmrg "{ 739*63d1a8abSmrg if (spu_safe_dma (INTVAL (operands[1]))) 740*63d1a8abSmrg { 741*63d1a8abSmrg emit_insn (gen_spu_rdch_clobber (operands[0], operands[1])); 742*63d1a8abSmrg DONE; 743*63d1a8abSmrg } 744*63d1a8abSmrg }") 745*63d1a8abSmrg 746*63d1a8abSmrg(define_expand "spu_rchcnt" 747*63d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "") 748*63d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))] 749*63d1a8abSmrg "" 750*63d1a8abSmrg "{ 751*63d1a8abSmrg if (spu_safe_dma (INTVAL (operands[1]))) 752*63d1a8abSmrg { 753*63d1a8abSmrg emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1])); 754*63d1a8abSmrg DONE; 755*63d1a8abSmrg } 756*63d1a8abSmrg }") 757*63d1a8abSmrg 758*63d1a8abSmrg(define_expand "spu_wrch" 759*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "") 760*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)] 761*63d1a8abSmrg "" 762*63d1a8abSmrg "{ 763*63d1a8abSmrg if (spu_safe_dma (INTVAL (operands[0]))) 764*63d1a8abSmrg { 765*63d1a8abSmrg emit_insn (gen_spu_wrch_clobber (operands[0], operands[1])); 766*63d1a8abSmrg DONE; 767*63d1a8abSmrg } 768*63d1a8abSmrg }") 769*63d1a8abSmrg 770*63d1a8abSmrg(define_insn "spu_rdch_noclobber" 771*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 772*63d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))] 773*63d1a8abSmrg "" 774*63d1a8abSmrg "rdch\t%0,$ch%1" 775*63d1a8abSmrg [(set_attr "type" "spr")]) 776*63d1a8abSmrg 777*63d1a8abSmrg(define_insn "spu_rchcnt_noclobber" 778*63d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 779*63d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))] 780*63d1a8abSmrg "" 781*63d1a8abSmrg "rchcnt\t%0,$ch%1" 782*63d1a8abSmrg [(set_attr "type" "spr")]) 783*63d1a8abSmrg 784*63d1a8abSmrg(define_insn "spu_wrch_noclobber" 785*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 786*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)] 787*63d1a8abSmrg "" 788*63d1a8abSmrg "wrch\t$ch%0,%1" 789*63d1a8abSmrg [(set_attr "type" "spr")]) 790*63d1a8abSmrg 791*63d1a8abSmrg(define_insn "spu_rdch_clobber" 792*63d1a8abSmrg [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 793*63d1a8abSmrg (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH)) 794*63d1a8abSmrg (clobber (mem:BLK (scratch)))] 795*63d1a8abSmrg "" 796*63d1a8abSmrg "rdch\t%0,$ch%1" 797*63d1a8abSmrg [(set_attr "type" "spr")]) 798*63d1a8abSmrg 799*63d1a8abSmrg(define_insn "spu_rchcnt_clobber" 800*63d1a8abSmrg [(set (match_operand:SI 0 "spu_reg_operand" "=r") 801*63d1a8abSmrg (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT)) 802*63d1a8abSmrg (clobber (mem:BLK (scratch)))] 803*63d1a8abSmrg "" 804*63d1a8abSmrg "rchcnt\t%0,$ch%1" 805*63d1a8abSmrg [(set_attr "type" "spr")]) 806*63d1a8abSmrg 807*63d1a8abSmrg(define_insn "spu_wrch_clobber" 808*63d1a8abSmrg [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J") 809*63d1a8abSmrg (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH) 810*63d1a8abSmrg (clobber (mem:BLK (scratch)))] 811*63d1a8abSmrg "" 812*63d1a8abSmrg "wrch\t$ch%0,%1" 813*63d1a8abSmrg [(set_attr "type" "spr")]) 814*63d1a8abSmrg 815*63d1a8abSmrg(define_expand "spu_splats" 816*63d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 817*63d1a8abSmrg (vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))] 818*63d1a8abSmrg "" 819*63d1a8abSmrg { 820*63d1a8abSmrg spu_builtin_splats(operands); 821*63d1a8abSmrg DONE; 822*63d1a8abSmrg }) 823*63d1a8abSmrg 824*63d1a8abSmrg(define_expand "spu_extract" 825*63d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 826*63d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 827*63d1a8abSmrg (match_operand 2 "spu_nonmem_operand" "")] 0))] 828*63d1a8abSmrg "" 829*63d1a8abSmrg { 830*63d1a8abSmrg spu_builtin_extract (operands); 831*63d1a8abSmrg DONE; 832*63d1a8abSmrg }) 833*63d1a8abSmrg 834*63d1a8abSmrg(define_expand "spu_insert" 835*63d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 836*63d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 837*63d1a8abSmrg (match_operand 2 "spu_reg_operand" "") 838*63d1a8abSmrg (match_operand:SI 3 "spu_nonmem_operand" "")] 0))] 839*63d1a8abSmrg "" 840*63d1a8abSmrg { 841*63d1a8abSmrg spu_builtin_insert(operands); 842*63d1a8abSmrg DONE; 843*63d1a8abSmrg }) 844*63d1a8abSmrg 845*63d1a8abSmrg(define_expand "spu_promote" 846*63d1a8abSmrg [(set (match_operand 0 "spu_reg_operand" "") 847*63d1a8abSmrg (unspec [(match_operand 1 "spu_reg_operand" "") 848*63d1a8abSmrg (match_operand:SI 2 "immediate_operand" "")] 0))] 849*63d1a8abSmrg "" 850*63d1a8abSmrg { 851*63d1a8abSmrg spu_builtin_promote(operands); 852*63d1a8abSmrg DONE; 853*63d1a8abSmrg }) 854*63d1a8abSmrg 855*63d1a8abSmrg;; Currently doing nothing with this but expanding its args. 856*63d1a8abSmrg(define_expand "spu_align_hint" 857*63d1a8abSmrg [(unspec [(match_operand:SI 0 "address_operand" "") 858*63d1a8abSmrg (match_operand:SI 1 "immediate_operand" "") 859*63d1a8abSmrg (match_operand:SI 2 "immediate_operand" "")] 0)] 860*63d1a8abSmrg "" 861*63d1a8abSmrg { 862*63d1a8abSmrg DONE; 863*63d1a8abSmrg }) 864*63d1a8abSmrg 865