1*0fc04c29Smrg /* Copyright (C) 2006-2019 Free Software Foundation, Inc.
263d1a8abSmrg
363d1a8abSmrg This file is free software; you can redistribute it and/or modify it under
463d1a8abSmrg the terms of the GNU General Public License as published by the Free
563d1a8abSmrg Software Foundation; either version 3 of the License, or (at your option)
663d1a8abSmrg any later version.
763d1a8abSmrg
863d1a8abSmrg This file is distributed in the hope that it will be useful, but WITHOUT
963d1a8abSmrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1063d1a8abSmrg FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1163d1a8abSmrg for more details.
1263d1a8abSmrg
1363d1a8abSmrg Under Section 7 of GPL version 3, you are granted additional
1463d1a8abSmrg permissions described in the GCC Runtime Library Exception, version
1563d1a8abSmrg 3.1, as published by the Free Software Foundation.
1663d1a8abSmrg
1763d1a8abSmrg You should have received a copy of the GNU General Public License and
1863d1a8abSmrg a copy of the GCC Runtime Library Exception along with this program;
1963d1a8abSmrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2063d1a8abSmrg <http://www.gnu.org/licenses/>. */
2163d1a8abSmrg
2263d1a8abSmrg #ifndef __SPU_MFCIO_H__
2363d1a8abSmrg #define __SPU_MFCIO_H__ 1
2463d1a8abSmrg
2563d1a8abSmrg #include <spu_intrinsics.h>
2663d1a8abSmrg #ifdef __IN_LIBGCC2
2763d1a8abSmrg typedef unsigned long long uint64_t;
2863d1a8abSmrg #else
2963d1a8abSmrg #include <stdint.h>
3063d1a8abSmrg #endif
3163d1a8abSmrg
3263d1a8abSmrg #ifdef __cplusplus
3363d1a8abSmrg extern "C" {
3463d1a8abSmrg #endif
3563d1a8abSmrg
3663d1a8abSmrg
3763d1a8abSmrg /****************************************************************/
3863d1a8abSmrg /* DMA list element structure*/
3963d1a8abSmrg /****************************************************************/
4063d1a8abSmrg
4163d1a8abSmrg #ifdef __GNUC__
4263d1a8abSmrg __extension__
4363d1a8abSmrg #endif
4463d1a8abSmrg typedef struct mfc_list_element {
4563d1a8abSmrg uint64_t notify : 1; /** Stall-and-notify bit */
4663d1a8abSmrg uint64_t reserved : 16;
4763d1a8abSmrg uint64_t size : 15; /** Transfer size */
4863d1a8abSmrg uint64_t eal : 32; /** Lower word of effective address */
4963d1a8abSmrg } mfc_list_element_t;
5063d1a8abSmrg
5163d1a8abSmrg /****************************************************************/
5263d1a8abSmrg /* DMA max/min size definitions. */
5363d1a8abSmrg /****************************************************************/
5463d1a8abSmrg
5563d1a8abSmrg #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
5663d1a8abSmrg #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
5763d1a8abSmrg
5863d1a8abSmrg #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
5963d1a8abSmrg #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
6063d1a8abSmrg
6163d1a8abSmrg #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
6263d1a8abSmrg #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
6363d1a8abSmrg
6463d1a8abSmrg #define MFC_MIN_DMA_LIST_ELEMENTS 1
6563d1a8abSmrg #define MFC_MAX_DMA_LIST_ELEMENTS 2048
6663d1a8abSmrg
6763d1a8abSmrg #define MFC_MIN_DMA_LIST_SIZE (MFC_MIN_DMA_LIST_ELEMENTS << 3) /* 8 bytes */
6863d1a8abSmrg #define MFC_MAX_DMA_LIST_SIZE (MFC_MAX_DMA_LIST_ELEMENTS << 3) /* 16K bytes */
6963d1a8abSmrg
7063d1a8abSmrg /****************************************************************/
7163d1a8abSmrg /* MFC DMA command modifiers to identify classes of operations. */
7263d1a8abSmrg /****************************************************************/
7363d1a8abSmrg
7463d1a8abSmrg /* Note: These commands modifier may be used in conjunction with the base
7563d1a8abSmrg command types (i.e. MFC_PUT_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
7663d1a8abSmrg to construct the various command permutations. */
7763d1a8abSmrg
7863d1a8abSmrg #define MFC_BARRIER_ENABLE 0x0001
7963d1a8abSmrg #define MFC_FENCE_ENABLE 0x0002
8063d1a8abSmrg #define MFC_LIST_ENABLE 0x0004
8163d1a8abSmrg #define MFC_RESULT_ENABLE 0x0010
8263d1a8abSmrg
8363d1a8abSmrg /****************************************************************/
8463d1a8abSmrg /* MFC DMA Put Commands */
8563d1a8abSmrg /****************************************************************/
8663d1a8abSmrg
8763d1a8abSmrg #define MFC_PUT_CMD 0x0020
8863d1a8abSmrg #define MFC_PUTB_CMD (MFC_PUT_CMD | MFC_BARRIER_ENABLE)
8963d1a8abSmrg #define MFC_PUTF_CMD (MFC_PUT_CMD | MFC_FENCE_ENABLE)
9063d1a8abSmrg #define MFC_PUTL_CMD (MFC_PUT_CMD | MFC_LIST_ENABLE)
9163d1a8abSmrg #define MFC_PUTLB_CMD (MFC_PUTL_CMD | MFC_BARRIER_ENABLE)
9263d1a8abSmrg #define MFC_PUTLF_CMD (MFC_PUTL_CMD | MFC_FENCE_ENABLE)
9363d1a8abSmrg
9463d1a8abSmrg #define MFC_PUTR_CMD (MFC_PUT_CMD | MFC_RESULT_ENABLE)
9563d1a8abSmrg #define MFC_PUTRB_CMD (MFC_PUTR_CMD | MFC_BARRIER_ENABLE)
9663d1a8abSmrg #define MFC_PUTRF_CMD (MFC_PUTR_CMD | MFC_FENCE_ENABLE)
9763d1a8abSmrg #define MFC_PUTRL_CMD (MFC_PUTR_CMD | MFC_LIST_ENABLE)
9863d1a8abSmrg #define MFC_PUTRLB_CMD (MFC_PUTRL_CMD | MFC_BARRIER_ENABLE)
9963d1a8abSmrg #define MFC_PUTRLF_CMD (MFC_PUTRL_CMD | MFC_FENCE_ENABLE)
10063d1a8abSmrg
10163d1a8abSmrg /****************************************************************/
10263d1a8abSmrg /* MFC DMA Get Commands */
10363d1a8abSmrg /****************************************************************/
10463d1a8abSmrg
10563d1a8abSmrg #define MFC_GET_CMD 0x0040
10663d1a8abSmrg #define MFC_GETB_CMD (MFC_GET_CMD | MFC_BARRIER_ENABLE)
10763d1a8abSmrg #define MFC_GETF_CMD (MFC_GET_CMD | MFC_FENCE_ENABLE)
10863d1a8abSmrg #define MFC_GETL_CMD (MFC_GET_CMD | MFC_LIST_ENABLE)
10963d1a8abSmrg #define MFC_GETLB_CMD (MFC_GETL_CMD | MFC_BARRIER_ENABLE)
11063d1a8abSmrg #define MFC_GETLF_CMD (MFC_GETL_CMD | MFC_FENCE_ENABLE)
11163d1a8abSmrg
11263d1a8abSmrg /****************************************************************/
11363d1a8abSmrg /* MFC Synchronization Commands */
11463d1a8abSmrg /****************************************************************/
11563d1a8abSmrg
11663d1a8abSmrg #define MFC_SNDSIG_CMD 0x00A0
11763d1a8abSmrg #define MFC_SNDSIGB_CMD (MFC_SNDSIG_CMD | MFC_BARRIER_ENABLE)
11863d1a8abSmrg #define MFC_SNDSIGF_CMD (MFC_SNDSIG_CMD | MFC_FENCE_ENABLE)
11963d1a8abSmrg #define MFC_BARRIER_CMD 0x00C0
12063d1a8abSmrg #define MFC_EIEIO_CMD 0x00C8
12163d1a8abSmrg #define MFC_SYNC_CMD 0x00CC
12263d1a8abSmrg
12363d1a8abSmrg /****************************************************************/
12463d1a8abSmrg /* MFC Atomic Commands */
12563d1a8abSmrg /****************************************************************/
12663d1a8abSmrg
12763d1a8abSmrg #define MFC_GETLLAR_CMD 0x00D0
12863d1a8abSmrg #define MFC_PUTLLC_CMD 0x00B4
12963d1a8abSmrg #define MFC_PUTLLUC_CMD 0x00B0
13063d1a8abSmrg #define MFC_PUTQLLUC_CMD 0x00B8
13163d1a8abSmrg
13263d1a8abSmrg /****************************************************************/
13363d1a8abSmrg /* MFC SL1 Storage Control Commands */
13463d1a8abSmrg /****************************************************************/
13563d1a8abSmrg
13663d1a8abSmrg #define MFC_SDCRT_CMD 0x0080
13763d1a8abSmrg #define MFC_SDCRTST_CMD 0x0081
13863d1a8abSmrg #define MFC_SDCRZ_CMD 0x0089
13963d1a8abSmrg #define MFC_SDCRST_CMD 0x008D
14063d1a8abSmrg #define MFC_SDCRF_CMD 0x008F
14163d1a8abSmrg
14263d1a8abSmrg /****************************************************************/
14363d1a8abSmrg /* Channel Defines */
14463d1a8abSmrg /****************************************************************/
14563d1a8abSmrg
14663d1a8abSmrg /* Events Defines for channels
14763d1a8abSmrg * 0 (SPU_RdEventStat),
14863d1a8abSmrg * 1 (SPU_WrEventMask), and
14963d1a8abSmrg * 2 (SPU_WrEventAck).
15063d1a8abSmrg */
15163d1a8abSmrg #define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
15263d1a8abSmrg #define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
15363d1a8abSmrg #define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
15463d1a8abSmrg #define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
15563d1a8abSmrg #define MFC_DECREMENTER_EVENT 0x00000020
15663d1a8abSmrg #define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
15763d1a8abSmrg #define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
15863d1a8abSmrg #define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
15963d1a8abSmrg #define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
16063d1a8abSmrg #define MFC_LLR_LOST_EVENT 0x00000400
16163d1a8abSmrg #define MFC_PRIV_ATTN_EVENT 0x00000800
16263d1a8abSmrg #define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
16363d1a8abSmrg
16463d1a8abSmrg /* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
16563d1a8abSmrg #define MFC_TAG_UPDATE_IMMEDIATE 0x0
16663d1a8abSmrg #define MFC_TAG_UPDATE_ANY 0x1
16763d1a8abSmrg #define MFC_TAG_UPDATE_ALL 0x2
16863d1a8abSmrg
16963d1a8abSmrg /* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
17063d1a8abSmrg #define MFC_PUTLLC_STATUS 0x00000001
17163d1a8abSmrg #define MFC_PUTLLUC_STATUS 0x00000002
17263d1a8abSmrg #define MFC_GETLLAR_STATUS 0x00000004
17363d1a8abSmrg
17463d1a8abSmrg
17563d1a8abSmrg /****************************************************************/
17663d1a8abSmrg /* Definitions for constructing a 32-bit command word */
17763d1a8abSmrg /* including the transfer and replacement class id and the */
17863d1a8abSmrg /* command opcode. */
17963d1a8abSmrg /****************************************************************/
18063d1a8abSmrg #define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
18163d1a8abSmrg
18263d1a8abSmrg
18363d1a8abSmrg /* Addressing Utilities */
18463d1a8abSmrg #define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
18563d1a8abSmrg #define mfc_ea2l(ea) (unsigned int)(ea)
18663d1a8abSmrg #define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
18763d1a8abSmrg si_rotqbyi(si_from_uint(l), -4),\
18863d1a8abSmrg si_fsmbi(0x0f0f)))
18963d1a8abSmrg #define mfc_ceil128(v) (((v) + 127) & ~127)
19063d1a8abSmrg
19163d1a8abSmrg /* MFC DMA */
19263d1a8abSmrg #define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
19363d1a8abSmrg #define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
19463d1a8abSmrg #define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
19563d1a8abSmrg #define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
19663d1a8abSmrg #define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
19763d1a8abSmrg #define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
19863d1a8abSmrg
19963d1a8abSmrg /* MFC list DMA */
20063d1a8abSmrg #define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
20163d1a8abSmrg #define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
20263d1a8abSmrg #define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
20363d1a8abSmrg #define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
20463d1a8abSmrg #define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
20563d1a8abSmrg #define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
20663d1a8abSmrg
20763d1a8abSmrg /* MFC Atomic Update DMA */
20863d1a8abSmrg #define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
20963d1a8abSmrg #define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
21063d1a8abSmrg #define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
21163d1a8abSmrg #define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
21263d1a8abSmrg
21363d1a8abSmrg /* MFC Synchronization Commands */
21463d1a8abSmrg #define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
21563d1a8abSmrg #define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
21663d1a8abSmrg #define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
21763d1a8abSmrg #define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
21863d1a8abSmrg #define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
21963d1a8abSmrg #define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
22063d1a8abSmrg
22163d1a8abSmrg /* MFC SL1 Storage Control Commands */
22263d1a8abSmrg #define mfc_sdcrt( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRT_CMD))
22363d1a8abSmrg #define mfc_sdcrtst(ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRTST_CMD))
22463d1a8abSmrg #define mfc_sdcrz( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRZ_CMD))
22563d1a8abSmrg #define mfc_sdcrst( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRST_CMD))
22663d1a8abSmrg #define mfc_sdcrf( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRF_CMD))
22763d1a8abSmrg
22863d1a8abSmrg /* DMA Queue */
22963d1a8abSmrg #define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
23063d1a8abSmrg
23163d1a8abSmrg /* MFC Tag-Status */
23263d1a8abSmrg #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
23363d1a8abSmrg #define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
23463d1a8abSmrg
23563d1a8abSmrg #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
23663d1a8abSmrg #define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
23763d1a8abSmrg #define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
23863d1a8abSmrg #define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
23963d1a8abSmrg #define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
24063d1a8abSmrg
24163d1a8abSmrg #define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
24263d1a8abSmrg #define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
24363d1a8abSmrg #define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
24463d1a8abSmrg #define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
24563d1a8abSmrg #define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
24663d1a8abSmrg
24763d1a8abSmrg /* MFC List Stall-and-Notify Tag */
24863d1a8abSmrg #define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
24963d1a8abSmrg #define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
25063d1a8abSmrg #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
25163d1a8abSmrg
25263d1a8abSmrg /* Atomic DMA */
25363d1a8abSmrg #define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
25463d1a8abSmrg #define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
25563d1a8abSmrg
25663d1a8abSmrg /* MFC Multi-source Synchronization */
25763d1a8abSmrg #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
25863d1a8abSmrg #define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
25963d1a8abSmrg
26063d1a8abSmrg /* SPU Signal */
26163d1a8abSmrg #define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
26263d1a8abSmrg #define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
26363d1a8abSmrg #define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
26463d1a8abSmrg #define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
26563d1a8abSmrg
26663d1a8abSmrg /* SPU/PPE Mailbox */
26763d1a8abSmrg #define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
26863d1a8abSmrg #define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
26963d1a8abSmrg #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
27063d1a8abSmrg #define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
27163d1a8abSmrg #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
27263d1a8abSmrg #define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
27363d1a8abSmrg
27463d1a8abSmrg /* SPU Decrementer */
27563d1a8abSmrg #define spu_read_decrementer() spu_readch(SPU_RdDec)
27663d1a8abSmrg #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
27763d1a8abSmrg
27863d1a8abSmrg /* SPU Event */
27963d1a8abSmrg #define spu_read_event_status() spu_readch(SPU_RdEventStat)
28063d1a8abSmrg #define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
28163d1a8abSmrg #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
28263d1a8abSmrg #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
28363d1a8abSmrg #define spu_read_event_mask() spu_readch(SPU_RdEventMask)
28463d1a8abSmrg
28563d1a8abSmrg /* SPU State Management */
28663d1a8abSmrg #define spu_read_machine_status() spu_readch(SPU_RdMachStat)
28763d1a8abSmrg #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
28863d1a8abSmrg #define spu_read_srr0() spu_readch(SPU_RdSRR0)
28963d1a8abSmrg
29063d1a8abSmrg /* Interrupt-Safe Critical Sections */
29163d1a8abSmrg
29263d1a8abSmrg static __inline__ unsigned int mfc_begin_critical_section (void)
29363d1a8abSmrg __attribute__ ((__always_inline__));
29463d1a8abSmrg
29563d1a8abSmrg static __inline__ unsigned int
mfc_begin_critical_section(void)29663d1a8abSmrg mfc_begin_critical_section (void)
29763d1a8abSmrg {
29863d1a8abSmrg #ifdef SPU_MFCIO_INTERRUPT_SAFE
29963d1a8abSmrg unsigned int __status = spu_read_machine_status ();
30063d1a8abSmrg spu_idisable ();
30163d1a8abSmrg return __status;
30263d1a8abSmrg #else
30363d1a8abSmrg return 0;
30463d1a8abSmrg #endif
30563d1a8abSmrg }
30663d1a8abSmrg
30763d1a8abSmrg static __inline__ void mfc_end_critical_section (unsigned int)
30863d1a8abSmrg __attribute__ ((__always_inline__));
30963d1a8abSmrg
31063d1a8abSmrg static __inline__ void
mfc_end_critical_section(unsigned int __status)31163d1a8abSmrg mfc_end_critical_section (unsigned int __status __attribute__ ((__unused__)))
31263d1a8abSmrg {
31363d1a8abSmrg #ifdef SPU_MFCIO_INTERRUPT_SAFE
31463d1a8abSmrg if (__status & 1)
31563d1a8abSmrg spu_ienable ();
31663d1a8abSmrg #endif
31763d1a8abSmrg }
31863d1a8abSmrg
31963d1a8abSmrg /* MFC Tag Manager */
32063d1a8abSmrg
32163d1a8abSmrg #define MFC_TAG_INVALID 0xFFFFFFFF
32263d1a8abSmrg #define MFC_TAG_VALID 0x00000000
32363d1a8abSmrg
32463d1a8abSmrg #define mfc_tag_reserve() \
32563d1a8abSmrg __mfc_tag_reserve()
32663d1a8abSmrg #define mfc_tag_release(tag) \
32763d1a8abSmrg __mfc_tag_release((tag))
32863d1a8abSmrg #define mfc_multi_tag_reserve(nr_tags) \
32963d1a8abSmrg __mfc_multi_tag_reserve((nr_tags))
33063d1a8abSmrg #define mfc_multi_tag_release(tag, nr_tags) \
33163d1a8abSmrg __mfc_multi_tag_release((tag),(nr_tags))
33263d1a8abSmrg
33363d1a8abSmrg extern unsigned int __mfc_tag_reserve (void);
33463d1a8abSmrg extern unsigned int __mfc_tag_release (unsigned int);
33563d1a8abSmrg extern unsigned int __mfc_multi_tag_reserve (unsigned int);
33663d1a8abSmrg extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int);
33763d1a8abSmrg
33863d1a8abSmrg #ifdef __cplusplus
33963d1a8abSmrg }
34063d1a8abSmrg #endif
34163d1a8abSmrg
34263d1a8abSmrg #endif /* __SPU_MFCIO_H__ */
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