1c3d31fe1Smrg /* Definitions of target machine for GNU compiler, for DEC Alpha. 2*af526226Smrg Copyright (C) 1992-2013 Free Software Foundation, Inc. 3c3d31fe1Smrg Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4c3d31fe1Smrg 5c3d31fe1Smrg This file is part of GCC. 6c3d31fe1Smrg 7c3d31fe1Smrg GCC is free software; you can redistribute it and/or modify 8c3d31fe1Smrg it under the terms of the GNU General Public License as published by 9c3d31fe1Smrg the Free Software Foundation; either version 3, or (at your option) 10c3d31fe1Smrg any later version. 11c3d31fe1Smrg 12c3d31fe1Smrg GCC is distributed in the hope that it will be useful, 13c3d31fe1Smrg but WITHOUT ANY WARRANTY; without even the implied warranty of 14c3d31fe1Smrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15c3d31fe1Smrg GNU General Public License for more details. 16c3d31fe1Smrg 17c3d31fe1Smrg You should have received a copy of the GNU General Public License 18c3d31fe1Smrg along with GCC; see the file COPYING3. If not see 19c3d31fe1Smrg <http://www.gnu.org/licenses/>. */ 20c3d31fe1Smrg 21c3d31fe1Smrg /* Target CPU builtins. */ 22c3d31fe1Smrg #define TARGET_CPU_CPP_BUILTINS() \ 23c3d31fe1Smrg do \ 24c3d31fe1Smrg { \ 25c3d31fe1Smrg builtin_define ("__alpha"); \ 26c3d31fe1Smrg builtin_define ("__alpha__"); \ 27c3d31fe1Smrg builtin_assert ("cpu=alpha"); \ 28c3d31fe1Smrg builtin_assert ("machine=alpha"); \ 29c3d31fe1Smrg if (TARGET_CIX) \ 30c3d31fe1Smrg { \ 31c3d31fe1Smrg builtin_define ("__alpha_cix__"); \ 32c3d31fe1Smrg builtin_assert ("cpu=cix"); \ 33c3d31fe1Smrg } \ 34c3d31fe1Smrg if (TARGET_FIX) \ 35c3d31fe1Smrg { \ 36c3d31fe1Smrg builtin_define ("__alpha_fix__"); \ 37c3d31fe1Smrg builtin_assert ("cpu=fix"); \ 38c3d31fe1Smrg } \ 39c3d31fe1Smrg if (TARGET_BWX) \ 40c3d31fe1Smrg { \ 41c3d31fe1Smrg builtin_define ("__alpha_bwx__"); \ 42c3d31fe1Smrg builtin_assert ("cpu=bwx"); \ 43c3d31fe1Smrg } \ 44c3d31fe1Smrg if (TARGET_MAX) \ 45c3d31fe1Smrg { \ 46c3d31fe1Smrg builtin_define ("__alpha_max__"); \ 47c3d31fe1Smrg builtin_assert ("cpu=max"); \ 48c3d31fe1Smrg } \ 49c3d31fe1Smrg if (alpha_cpu == PROCESSOR_EV6) \ 50c3d31fe1Smrg { \ 51c3d31fe1Smrg builtin_define ("__alpha_ev6__"); \ 52c3d31fe1Smrg builtin_assert ("cpu=ev6"); \ 53c3d31fe1Smrg } \ 54c3d31fe1Smrg else if (alpha_cpu == PROCESSOR_EV5) \ 55c3d31fe1Smrg { \ 56c3d31fe1Smrg builtin_define ("__alpha_ev5__"); \ 57c3d31fe1Smrg builtin_assert ("cpu=ev5"); \ 58c3d31fe1Smrg } \ 59c3d31fe1Smrg else /* Presumably ev4. */ \ 60c3d31fe1Smrg { \ 61c3d31fe1Smrg builtin_define ("__alpha_ev4__"); \ 62c3d31fe1Smrg builtin_assert ("cpu=ev4"); \ 63c3d31fe1Smrg } \ 64c3d31fe1Smrg if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ 65c3d31fe1Smrg builtin_define ("_IEEE_FP"); \ 66c3d31fe1Smrg if (TARGET_IEEE_WITH_INEXACT) \ 67c3d31fe1Smrg builtin_define ("_IEEE_FP_INEXACT"); \ 68c3d31fe1Smrg if (TARGET_LONG_DOUBLE_128) \ 69c3d31fe1Smrg builtin_define ("__LONG_DOUBLE_128__"); \ 70c3d31fe1Smrg \ 71c3d31fe1Smrg /* Macros dependent on the C dialect. */ \ 72c3d31fe1Smrg SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ 73c3d31fe1Smrg } while (0) 74c3d31fe1Smrg 75c3d31fe1Smrg #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS 76c3d31fe1Smrg #define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ 77c3d31fe1Smrg do \ 78c3d31fe1Smrg { \ 79c3d31fe1Smrg if (preprocessing_asm_p ()) \ 80c3d31fe1Smrg builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 81c3d31fe1Smrg else if (c_dialect_cxx ()) \ 82c3d31fe1Smrg { \ 83c3d31fe1Smrg builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 84c3d31fe1Smrg builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 85c3d31fe1Smrg } \ 86c3d31fe1Smrg else \ 87c3d31fe1Smrg builtin_define_std ("LANGUAGE_C"); \ 88c3d31fe1Smrg if (c_dialect_objc ()) \ 89c3d31fe1Smrg { \ 90c3d31fe1Smrg builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 91c3d31fe1Smrg builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ 92c3d31fe1Smrg } \ 93c3d31fe1Smrg } \ 94c3d31fe1Smrg while (0) 95c3d31fe1Smrg #endif 96c3d31fe1Smrg 97c3d31fe1Smrg /* Run-time compilation parameters selecting different hardware subsets. */ 98c3d31fe1Smrg 99c3d31fe1Smrg /* Which processor to schedule for. The cpu attribute defines a list that 100c3d31fe1Smrg mirrors this list, so changes to alpha.md must be made at the same time. */ 101c3d31fe1Smrg 102c3d31fe1Smrg enum processor_type 103c3d31fe1Smrg { 104c3d31fe1Smrg PROCESSOR_EV4, /* 2106[46]{a,} */ 105c3d31fe1Smrg PROCESSOR_EV5, /* 21164{a,pc,} */ 106c3d31fe1Smrg PROCESSOR_EV6, /* 21264 */ 107c3d31fe1Smrg PROCESSOR_MAX 108c3d31fe1Smrg }; 109c3d31fe1Smrg 110c3d31fe1Smrg extern enum processor_type alpha_cpu; 111c3d31fe1Smrg extern enum processor_type alpha_tune; 112c3d31fe1Smrg 113c3d31fe1Smrg enum alpha_trap_precision 114c3d31fe1Smrg { 115c3d31fe1Smrg ALPHA_TP_PROG, /* No precision (default). */ 116c3d31fe1Smrg ALPHA_TP_FUNC, /* Trap contained within originating function. */ 117c3d31fe1Smrg ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ 118c3d31fe1Smrg }; 119c3d31fe1Smrg 120c3d31fe1Smrg enum alpha_fp_rounding_mode 121c3d31fe1Smrg { 122c3d31fe1Smrg ALPHA_FPRM_NORM, /* Normal rounding mode. */ 123c3d31fe1Smrg ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ 124c3d31fe1Smrg ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ 125c3d31fe1Smrg ALPHA_FPRM_DYN /* Dynamic rounding mode. */ 126c3d31fe1Smrg }; 127c3d31fe1Smrg 128c3d31fe1Smrg enum alpha_fp_trap_mode 129c3d31fe1Smrg { 130c3d31fe1Smrg ALPHA_FPTM_N, /* Normal trap mode. */ 131c3d31fe1Smrg ALPHA_FPTM_U, /* Underflow traps enabled. */ 132c3d31fe1Smrg ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ 133c3d31fe1Smrg ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ 134c3d31fe1Smrg }; 135c3d31fe1Smrg 136c3d31fe1Smrg extern enum alpha_trap_precision alpha_tp; 137c3d31fe1Smrg extern enum alpha_fp_rounding_mode alpha_fprm; 138c3d31fe1Smrg extern enum alpha_fp_trap_mode alpha_fptm; 139c3d31fe1Smrg 140c3d31fe1Smrg /* Invert the easy way to make options work. */ 141c3d31fe1Smrg #define TARGET_FP (!TARGET_SOFT_FP) 142c3d31fe1Smrg 143c3d31fe1Smrg /* These are for target os support and cannot be changed at runtime. */ 144c3d31fe1Smrg #define TARGET_ABI_OPEN_VMS 0 145*af526226Smrg #define TARGET_ABI_OSF (!TARGET_ABI_OPEN_VMS) 146c3d31fe1Smrg 147c3d31fe1Smrg #ifndef TARGET_CAN_FAULT_IN_PROLOGUE 148c3d31fe1Smrg #define TARGET_CAN_FAULT_IN_PROLOGUE 0 149c3d31fe1Smrg #endif 150c3d31fe1Smrg #ifndef TARGET_HAS_XFLOATING_LIBS 151c3d31fe1Smrg #define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128 152c3d31fe1Smrg #endif 153c3d31fe1Smrg #ifndef TARGET_PROFILING_NEEDS_GP 154c3d31fe1Smrg #define TARGET_PROFILING_NEEDS_GP 0 155c3d31fe1Smrg #endif 156c3d31fe1Smrg #ifndef TARGET_FIXUP_EV5_PREFETCH 157c3d31fe1Smrg #define TARGET_FIXUP_EV5_PREFETCH 0 158c3d31fe1Smrg #endif 159c3d31fe1Smrg #ifndef HAVE_AS_TLS 160c3d31fe1Smrg #define HAVE_AS_TLS 0 161c3d31fe1Smrg #endif 162c3d31fe1Smrg 163c3d31fe1Smrg #define TARGET_DEFAULT MASK_FPREGS 164c3d31fe1Smrg 165c3d31fe1Smrg #ifndef TARGET_CPU_DEFAULT 166c3d31fe1Smrg #define TARGET_CPU_DEFAULT 0 167c3d31fe1Smrg #endif 168c3d31fe1Smrg 169c3d31fe1Smrg #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS 170c3d31fe1Smrg #ifdef HAVE_AS_EXPLICIT_RELOCS 171c3d31fe1Smrg #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS 172c3d31fe1Smrg #define TARGET_SUPPORT_ARCH 1 173c3d31fe1Smrg #else 174c3d31fe1Smrg #define TARGET_DEFAULT_EXPLICIT_RELOCS 0 175c3d31fe1Smrg #endif 176c3d31fe1Smrg #endif 177c3d31fe1Smrg 178c3d31fe1Smrg #ifndef TARGET_SUPPORT_ARCH 179c3d31fe1Smrg #define TARGET_SUPPORT_ARCH 0 180c3d31fe1Smrg #endif 181c3d31fe1Smrg 182c3d31fe1Smrg /* Support for a compile-time default CPU, et cetera. The rules are: 183c3d31fe1Smrg --with-cpu is ignored if -mcpu is specified. 184c3d31fe1Smrg --with-tune is ignored if -mtune is specified. */ 185c3d31fe1Smrg #define OPTION_DEFAULT_SPECS \ 186c3d31fe1Smrg {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 187c3d31fe1Smrg {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } 188c3d31fe1Smrg 189c3d31fe1Smrg 190c3d31fe1Smrg /* target machine storage layout */ 191c3d31fe1Smrg 192c3d31fe1Smrg /* Define the size of `int'. The default is the same as the word size. */ 193c3d31fe1Smrg #define INT_TYPE_SIZE 32 194c3d31fe1Smrg 195c3d31fe1Smrg /* Define the size of `long long'. The default is the twice the word size. */ 196c3d31fe1Smrg #define LONG_LONG_TYPE_SIZE 64 197c3d31fe1Smrg 198c3d31fe1Smrg /* The two floating-point formats we support are S-floating, which is 199c3d31fe1Smrg 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' 200c3d31fe1Smrg and `long double' are T. */ 201c3d31fe1Smrg 202c3d31fe1Smrg #define FLOAT_TYPE_SIZE 32 203c3d31fe1Smrg #define DOUBLE_TYPE_SIZE 64 204c3d31fe1Smrg #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 205c3d31fe1Smrg 206c3d31fe1Smrg /* Define this to set long double type size to use in libgcc2.c, which can 207c3d31fe1Smrg not depend on target_flags. */ 208c3d31fe1Smrg #ifdef __LONG_DOUBLE_128__ 209c3d31fe1Smrg #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 210c3d31fe1Smrg #else 211c3d31fe1Smrg #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 212c3d31fe1Smrg #endif 213c3d31fe1Smrg 214c3d31fe1Smrg /* Work around target_flags dependency in ada/targtyps.c. */ 215c3d31fe1Smrg #define WIDEST_HARDWARE_FP_SIZE 64 216c3d31fe1Smrg 217c3d31fe1Smrg #define WCHAR_TYPE "unsigned int" 218c3d31fe1Smrg #define WCHAR_TYPE_SIZE 32 219c3d31fe1Smrg 220c3d31fe1Smrg /* Define this macro if it is advisable to hold scalars in registers 221c3d31fe1Smrg in a wider mode than that declared by the program. In such cases, 222c3d31fe1Smrg the value is constrained to be within the bounds of the declared 223c3d31fe1Smrg type, but kept valid in the wider mode. The signedness of the 224c3d31fe1Smrg extension may differ from that of the type. 225c3d31fe1Smrg 226c3d31fe1Smrg For Alpha, we always store objects in a full register. 32-bit integers 227c3d31fe1Smrg are always sign-extended, but smaller objects retain their signedness. 228c3d31fe1Smrg 229c3d31fe1Smrg Note that small vector types can get mapped onto integer modes at the 230c3d31fe1Smrg whim of not appearing in alpha-modes.def. We never promoted these 231c3d31fe1Smrg values before; don't do so now that we've trimmed the set of modes to 232c3d31fe1Smrg those actually implemented in the backend. */ 233c3d31fe1Smrg 234c3d31fe1Smrg #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 235c3d31fe1Smrg if (GET_MODE_CLASS (MODE) == MODE_INT \ 236c3d31fe1Smrg && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \ 237c3d31fe1Smrg && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 238c3d31fe1Smrg { \ 239c3d31fe1Smrg if ((MODE) == SImode) \ 240c3d31fe1Smrg (UNSIGNEDP) = 0; \ 241c3d31fe1Smrg (MODE) = DImode; \ 242c3d31fe1Smrg } 243c3d31fe1Smrg 244c3d31fe1Smrg /* Define this if most significant bit is lowest numbered 245c3d31fe1Smrg in instructions that operate on numbered bit-fields. 246c3d31fe1Smrg 247c3d31fe1Smrg There are no such instructions on the Alpha, but the documentation 248c3d31fe1Smrg is little endian. */ 249c3d31fe1Smrg #define BITS_BIG_ENDIAN 0 250c3d31fe1Smrg 251c3d31fe1Smrg /* Define this if most significant byte of a word is the lowest numbered. 252c3d31fe1Smrg This is false on the Alpha. */ 253c3d31fe1Smrg #define BYTES_BIG_ENDIAN 0 254c3d31fe1Smrg 255c3d31fe1Smrg /* Define this if most significant word of a multiword number is lowest 256c3d31fe1Smrg numbered. 257c3d31fe1Smrg 258c3d31fe1Smrg For Alpha we can decide arbitrarily since there are no machine instructions 259c3d31fe1Smrg for them. Might as well be consistent with bytes. */ 260c3d31fe1Smrg #define WORDS_BIG_ENDIAN 0 261c3d31fe1Smrg 262c3d31fe1Smrg /* Width of a word, in units (bytes). */ 263c3d31fe1Smrg #define UNITS_PER_WORD 8 264c3d31fe1Smrg 265c3d31fe1Smrg /* Width in bits of a pointer. 266c3d31fe1Smrg See also the macro `Pmode' defined below. */ 267c3d31fe1Smrg #define POINTER_SIZE 64 268c3d31fe1Smrg 269c3d31fe1Smrg /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 270c3d31fe1Smrg #define PARM_BOUNDARY 64 271c3d31fe1Smrg 272c3d31fe1Smrg /* Boundary (in *bits*) on which stack pointer should be aligned. */ 273c3d31fe1Smrg #define STACK_BOUNDARY 128 274c3d31fe1Smrg 275c3d31fe1Smrg /* Allocation boundary (in *bits*) for the code of a function. */ 276c3d31fe1Smrg #define FUNCTION_BOUNDARY 32 277c3d31fe1Smrg 278c3d31fe1Smrg /* Alignment of field after `int : 0' in a structure. */ 279c3d31fe1Smrg #define EMPTY_FIELD_BOUNDARY 64 280c3d31fe1Smrg 281c3d31fe1Smrg /* Every structure's size must be a multiple of this. */ 282c3d31fe1Smrg #define STRUCTURE_SIZE_BOUNDARY 8 283c3d31fe1Smrg 284c3d31fe1Smrg /* A bit-field declared as `int' forces `int' alignment for the struct. */ 285*af526226Smrg #undef PCC_BITFILED_TYPE_MATTERS 286c3d31fe1Smrg #define PCC_BITFIELD_TYPE_MATTERS 1 287c3d31fe1Smrg 288c3d31fe1Smrg /* No data type wants to be aligned rounder than this. */ 289c3d31fe1Smrg #define BIGGEST_ALIGNMENT 128 290c3d31fe1Smrg 291c3d31fe1Smrg /* For atomic access to objects, must have at least 32-bit alignment 292c3d31fe1Smrg unless the machine has byte operations. */ 293c3d31fe1Smrg #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) 294c3d31fe1Smrg 295c3d31fe1Smrg /* Align all constants and variables to at least a word boundary so 296c3d31fe1Smrg we can pick up pieces of them faster. */ 297c3d31fe1Smrg /* ??? Only if block-move stuff knows about different source/destination 298c3d31fe1Smrg alignment. */ 299c3d31fe1Smrg #if 0 300c3d31fe1Smrg #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 301c3d31fe1Smrg #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 302c3d31fe1Smrg #endif 303c3d31fe1Smrg 304c3d31fe1Smrg /* Set this nonzero if move instructions will actually fail to work 305c3d31fe1Smrg when given unaligned data. 306c3d31fe1Smrg 307c3d31fe1Smrg Since we get an error message when we do one, call them invalid. */ 308c3d31fe1Smrg 309c3d31fe1Smrg #define STRICT_ALIGNMENT 1 310c3d31fe1Smrg 311c3d31fe1Smrg /* Set this nonzero if unaligned move instructions are extremely slow. 312c3d31fe1Smrg 313c3d31fe1Smrg On the Alpha, they trap. */ 314c3d31fe1Smrg 315c3d31fe1Smrg #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 316c3d31fe1Smrg 317c3d31fe1Smrg /* Standard register usage. */ 318c3d31fe1Smrg 319c3d31fe1Smrg /* Number of actual hardware registers. 320c3d31fe1Smrg The hardware registers are assigned numbers for the compiler 321c3d31fe1Smrg from 0 to just below FIRST_PSEUDO_REGISTER. 322c3d31fe1Smrg All registers that the compiler knows about must be given numbers, 323c3d31fe1Smrg even those that are not normally considered general registers. 324c3d31fe1Smrg 325c3d31fe1Smrg We define all 32 integer registers, even though $31 is always zero, 326c3d31fe1Smrg and all 32 floating-point registers, even though $f31 is also 327c3d31fe1Smrg always zero. We do not bother defining the FP status register and 328c3d31fe1Smrg there are no other registers. 329c3d31fe1Smrg 330c3d31fe1Smrg Since $31 is always zero, we will use register number 31 as the 331c3d31fe1Smrg argument pointer. It will never appear in the generated code 332c3d31fe1Smrg because we will always be eliminating it in favor of the stack 333c3d31fe1Smrg pointer or hardware frame pointer. 334c3d31fe1Smrg 335c3d31fe1Smrg Likewise, we use $f31 for the frame pointer, which will always 336c3d31fe1Smrg be eliminated in favor of the hardware frame pointer or the 337c3d31fe1Smrg stack pointer. */ 338c3d31fe1Smrg 339c3d31fe1Smrg #define FIRST_PSEUDO_REGISTER 64 340c3d31fe1Smrg 341c3d31fe1Smrg /* 1 for registers that have pervasive standard uses 342c3d31fe1Smrg and are not available for the register allocator. */ 343c3d31fe1Smrg 344c3d31fe1Smrg #define FIXED_REGISTERS \ 345c3d31fe1Smrg {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 346c3d31fe1Smrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ 347c3d31fe1Smrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 348c3d31fe1Smrg 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } 349c3d31fe1Smrg 350c3d31fe1Smrg /* 1 for registers not available across function calls. 351c3d31fe1Smrg These must include the FIXED_REGISTERS and also any 352c3d31fe1Smrg registers that can be used without being saved. 353c3d31fe1Smrg The latter must include the registers where values are returned 354c3d31fe1Smrg and the register where structure-value addresses are passed. 355c3d31fe1Smrg Aside from that, you can include as many other registers as you like. */ 356c3d31fe1Smrg #define CALL_USED_REGISTERS \ 357c3d31fe1Smrg {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 358c3d31fe1Smrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ 359c3d31fe1Smrg 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 360c3d31fe1Smrg 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } 361c3d31fe1Smrg 362c3d31fe1Smrg /* List the order in which to allocate registers. Each register must be 363c3d31fe1Smrg listed once, even those in FIXED_REGISTERS. */ 364c3d31fe1Smrg 365c3d31fe1Smrg #define REG_ALLOC_ORDER { \ 366c3d31fe1Smrg 1, 2, 3, 4, 5, 6, 7, 8, /* nonsaved integer registers */ \ 367c3d31fe1Smrg 22, 23, 24, 25, 28, /* likewise */ \ 368c3d31fe1Smrg 0, /* likewise, but return value */ \ 369c3d31fe1Smrg 21, 20, 19, 18, 17, 16, /* likewise, but input args */ \ 370c3d31fe1Smrg 27, /* likewise, but OSF procedure value */ \ 371c3d31fe1Smrg \ 372c3d31fe1Smrg 42, 43, 44, 45, 46, 47, /* nonsaved floating-point registers */ \ 373c3d31fe1Smrg 54, 55, 56, 57, 58, 59, /* likewise */ \ 374c3d31fe1Smrg 60, 61, 62, /* likewise */ \ 375c3d31fe1Smrg 32, 33, /* likewise, but return values */ \ 376c3d31fe1Smrg 53, 52, 51, 50, 49, 48, /* likewise, but input args */ \ 377c3d31fe1Smrg \ 378c3d31fe1Smrg 9, 10, 11, 12, 13, 14, /* saved integer registers */ \ 379c3d31fe1Smrg 26, /* return address */ \ 380c3d31fe1Smrg 15, /* hard frame pointer */ \ 381c3d31fe1Smrg \ 382c3d31fe1Smrg 34, 35, 36, 37, 38, 39, /* saved floating-point registers */ \ 383c3d31fe1Smrg 40, 41, /* likewise */ \ 384c3d31fe1Smrg \ 385c3d31fe1Smrg 29, 30, 31, 63 /* gp, sp, ap, sfp */ \ 386c3d31fe1Smrg } 387c3d31fe1Smrg 388c3d31fe1Smrg /* Return number of consecutive hard regs needed starting at reg REGNO 389c3d31fe1Smrg to hold something of mode MODE. 390c3d31fe1Smrg This is ordinarily the length in words of a value of mode MODE 391c3d31fe1Smrg but can be less for certain modes in special long registers. */ 392c3d31fe1Smrg 393c3d31fe1Smrg #define HARD_REGNO_NREGS(REGNO, MODE) \ 394c3d31fe1Smrg ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 395c3d31fe1Smrg 396c3d31fe1Smrg /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 397c3d31fe1Smrg On Alpha, the integer registers can hold any mode. The floating-point 398c3d31fe1Smrg registers can hold 64-bit integers as well, but not smaller values. */ 399c3d31fe1Smrg 400c3d31fe1Smrg #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 401c3d31fe1Smrg (IN_RANGE ((REGNO), 32, 62) \ 402c3d31fe1Smrg ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \ 403c3d31fe1Smrg || (MODE) == SCmode || (MODE) == DCmode \ 404c3d31fe1Smrg : 1) 405c3d31fe1Smrg 406c3d31fe1Smrg /* A C expression that is nonzero if a value of mode 407c3d31fe1Smrg MODE1 is accessible in mode MODE2 without copying. 408c3d31fe1Smrg 409c3d31fe1Smrg This asymmetric test is true when MODE1 could be put 410c3d31fe1Smrg in an FP register but MODE2 could not. */ 411c3d31fe1Smrg 412c3d31fe1Smrg #define MODES_TIEABLE_P(MODE1, MODE2) \ 413c3d31fe1Smrg (HARD_REGNO_MODE_OK (32, (MODE1)) \ 414c3d31fe1Smrg ? HARD_REGNO_MODE_OK (32, (MODE2)) \ 415c3d31fe1Smrg : 1) 416c3d31fe1Smrg 417c3d31fe1Smrg /* Specify the registers used for certain standard purposes. 418c3d31fe1Smrg The values of these macros are register numbers. */ 419c3d31fe1Smrg 420c3d31fe1Smrg /* Alpha pc isn't overloaded on a register that the compiler knows about. */ 421c3d31fe1Smrg /* #define PC_REGNUM */ 422c3d31fe1Smrg 423c3d31fe1Smrg /* Register to use for pushing function arguments. */ 424c3d31fe1Smrg #define STACK_POINTER_REGNUM 30 425c3d31fe1Smrg 426c3d31fe1Smrg /* Base register for access to local variables of the function. */ 427c3d31fe1Smrg #define HARD_FRAME_POINTER_REGNUM 15 428c3d31fe1Smrg 429c3d31fe1Smrg /* Base register for access to arguments of the function. */ 430c3d31fe1Smrg #define ARG_POINTER_REGNUM 31 431c3d31fe1Smrg 432c3d31fe1Smrg /* Base register for access to local variables of function. */ 433c3d31fe1Smrg #define FRAME_POINTER_REGNUM 63 434c3d31fe1Smrg 435c3d31fe1Smrg /* Register in which static-chain is passed to a function. 436c3d31fe1Smrg 437c3d31fe1Smrg For the Alpha, this is based on an example; the calling sequence 438c3d31fe1Smrg doesn't seem to specify this. */ 439c3d31fe1Smrg #define STATIC_CHAIN_REGNUM 1 440c3d31fe1Smrg 441c3d31fe1Smrg /* The register number of the register used to address a table of 442c3d31fe1Smrg static data addresses in memory. */ 443c3d31fe1Smrg #define PIC_OFFSET_TABLE_REGNUM 29 444c3d31fe1Smrg 445c3d31fe1Smrg /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' 446c3d31fe1Smrg is clobbered by calls. */ 447c3d31fe1Smrg /* ??? It is and it isn't. It's required to be valid for a given 448c3d31fe1Smrg function when the function returns. It isn't clobbered by 449c3d31fe1Smrg current_file functions. Moreover, we do not expose the ldgp 450c3d31fe1Smrg until after reload, so we're probably safe. */ 451c3d31fe1Smrg /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 452c3d31fe1Smrg 453c3d31fe1Smrg /* Define the classes of registers for register constraints in the 454c3d31fe1Smrg machine description. Also define ranges of constants. 455c3d31fe1Smrg 456c3d31fe1Smrg One of the classes must always be named ALL_REGS and include all hard regs. 457c3d31fe1Smrg If there is more than one class, another class must be named NO_REGS 458c3d31fe1Smrg and contain no registers. 459c3d31fe1Smrg 460c3d31fe1Smrg The name GENERAL_REGS must be the name of a class (or an alias for 461c3d31fe1Smrg another name such as ALL_REGS). This is the class of registers 462c3d31fe1Smrg that is allowed by "g" or "r" in a register constraint. 463c3d31fe1Smrg Also, registers outside this class are allocated only when 464c3d31fe1Smrg instructions express preferences for them. 465c3d31fe1Smrg 466c3d31fe1Smrg The classes must be numbered in nondecreasing order; that is, 467c3d31fe1Smrg a larger-numbered class must never be contained completely 468c3d31fe1Smrg in a smaller-numbered class. 469c3d31fe1Smrg 470c3d31fe1Smrg For any two classes, it is very desirable that there be another 471c3d31fe1Smrg class that represents their union. */ 472c3d31fe1Smrg 473c3d31fe1Smrg enum reg_class { 474c3d31fe1Smrg NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, 475c3d31fe1Smrg GENERAL_REGS, FLOAT_REGS, ALL_REGS, 476c3d31fe1Smrg LIM_REG_CLASSES 477c3d31fe1Smrg }; 478c3d31fe1Smrg 479c3d31fe1Smrg #define N_REG_CLASSES (int) LIM_REG_CLASSES 480c3d31fe1Smrg 481c3d31fe1Smrg /* Give names of register classes as strings for dump file. */ 482c3d31fe1Smrg 483c3d31fe1Smrg #define REG_CLASS_NAMES \ 484c3d31fe1Smrg {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ 485c3d31fe1Smrg "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } 486c3d31fe1Smrg 487c3d31fe1Smrg /* Define which registers fit in which classes. 488c3d31fe1Smrg This is an initializer for a vector of HARD_REG_SET 489c3d31fe1Smrg of length N_REG_CLASSES. */ 490c3d31fe1Smrg 491c3d31fe1Smrg #define REG_CLASS_CONTENTS \ 492c3d31fe1Smrg { {0x00000000, 0x00000000}, /* NO_REGS */ \ 493c3d31fe1Smrg {0x00000001, 0x00000000}, /* R0_REG */ \ 494c3d31fe1Smrg {0x01000000, 0x00000000}, /* R24_REG */ \ 495c3d31fe1Smrg {0x02000000, 0x00000000}, /* R25_REG */ \ 496c3d31fe1Smrg {0x08000000, 0x00000000}, /* R27_REG */ \ 497c3d31fe1Smrg {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \ 498c3d31fe1Smrg {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ 499c3d31fe1Smrg {0xffffffff, 0xffffffff} } 500c3d31fe1Smrg 501c3d31fe1Smrg /* The same information, inverted: 502c3d31fe1Smrg Return the class number of the smallest class containing 503c3d31fe1Smrg reg number REGNO. This could be a conditional expression 504c3d31fe1Smrg or could index an array. */ 505c3d31fe1Smrg 506c3d31fe1Smrg #define REGNO_REG_CLASS(REGNO) \ 507c3d31fe1Smrg ((REGNO) == 0 ? R0_REG \ 508c3d31fe1Smrg : (REGNO) == 24 ? R24_REG \ 509c3d31fe1Smrg : (REGNO) == 25 ? R25_REG \ 510c3d31fe1Smrg : (REGNO) == 27 ? R27_REG \ 511c3d31fe1Smrg : IN_RANGE ((REGNO), 32, 62) ? FLOAT_REGS \ 512c3d31fe1Smrg : GENERAL_REGS) 513c3d31fe1Smrg 514c3d31fe1Smrg /* The class value for index registers, and the one for base regs. */ 515c3d31fe1Smrg #define INDEX_REG_CLASS NO_REGS 516c3d31fe1Smrg #define BASE_REG_CLASS GENERAL_REGS 517c3d31fe1Smrg 518c3d31fe1Smrg /* Given an rtx X being reloaded into a reg required to be 519c3d31fe1Smrg in class CLASS, return the class of reg to actually use. 520c3d31fe1Smrg In general this is just CLASS; but on some machines 521c3d31fe1Smrg in some cases it is preferable to use a more restrictive class. */ 522c3d31fe1Smrg 523c3d31fe1Smrg #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class 524c3d31fe1Smrg 525c3d31fe1Smrg /* If we are copying between general and FP registers, we need a memory 526c3d31fe1Smrg location unless the FIX extension is available. */ 527c3d31fe1Smrg 528c3d31fe1Smrg #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 529c3d31fe1Smrg (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \ 530c3d31fe1Smrg || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS))) 531c3d31fe1Smrg 532c3d31fe1Smrg /* Specify the mode to be used for memory when a secondary memory 533c3d31fe1Smrg location is needed. If MODE is floating-point, use it. Otherwise, 534c3d31fe1Smrg widen to a word like the default. This is needed because we always 535c3d31fe1Smrg store integers in FP registers in quadword format. This whole 536c3d31fe1Smrg area is very tricky! */ 537c3d31fe1Smrg #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 538c3d31fe1Smrg (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ 539c3d31fe1Smrg : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ 540c3d31fe1Smrg : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) 541c3d31fe1Smrg 542c3d31fe1Smrg /* Return the class of registers that cannot change mode from FROM to TO. */ 543c3d31fe1Smrg 544c3d31fe1Smrg #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 545c3d31fe1Smrg (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 546c3d31fe1Smrg ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) 547c3d31fe1Smrg 548c3d31fe1Smrg /* Define the cost of moving between registers of various classes. Moving 549c3d31fe1Smrg between FLOAT_REGS and anything else except float regs is expensive. 550c3d31fe1Smrg In fact, we make it quite expensive because we really don't want to 551c3d31fe1Smrg do these moves unless it is clearly worth it. Optimizations may 552c3d31fe1Smrg reduce the impact of not being able to allocate a pseudo to a 553c3d31fe1Smrg hard register. */ 554c3d31fe1Smrg 555c3d31fe1Smrg #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 556c3d31fe1Smrg (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 \ 557c3d31fe1Smrg : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8) \ 558c3d31fe1Smrg : 4+2*alpha_memory_latency) 559c3d31fe1Smrg 560c3d31fe1Smrg /* A C expressions returning the cost of moving data of MODE from a register to 561c3d31fe1Smrg or from memory. 562c3d31fe1Smrg 563c3d31fe1Smrg On the Alpha, bump this up a bit. */ 564c3d31fe1Smrg 565c3d31fe1Smrg extern int alpha_memory_latency; 566c3d31fe1Smrg #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) 567c3d31fe1Smrg 568c3d31fe1Smrg /* Provide the cost of a branch. Exact meaning under development. */ 569c3d31fe1Smrg #define BRANCH_COST(speed_p, predictable_p) 5 570c3d31fe1Smrg 571c3d31fe1Smrg /* Stack layout; function entry, exit and calling. */ 572c3d31fe1Smrg 573c3d31fe1Smrg /* Define this if pushing a word on the stack 574c3d31fe1Smrg makes the stack pointer a smaller address. */ 575c3d31fe1Smrg #define STACK_GROWS_DOWNWARD 576c3d31fe1Smrg 577c3d31fe1Smrg /* Define this to nonzero if the nominal address of the stack frame 578c3d31fe1Smrg is at the high-address end of the local variables; 579c3d31fe1Smrg that is, each additional local variable allocated 580c3d31fe1Smrg goes at a more negative offset in the frame. */ 581c3d31fe1Smrg /* #define FRAME_GROWS_DOWNWARD 0 */ 582c3d31fe1Smrg 583c3d31fe1Smrg /* Offset within stack frame to start allocating local variables at. 584c3d31fe1Smrg If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 585c3d31fe1Smrg first local allocated. Otherwise, it is the offset to the BEGINNING 586c3d31fe1Smrg of the first local allocated. */ 587c3d31fe1Smrg 588c3d31fe1Smrg #define STARTING_FRAME_OFFSET 0 589c3d31fe1Smrg 590c3d31fe1Smrg /* If we generate an insn to push BYTES bytes, 591c3d31fe1Smrg this says how many the stack pointer really advances by. 592c3d31fe1Smrg On Alpha, don't define this because there are no push insns. */ 593c3d31fe1Smrg /* #define PUSH_ROUNDING(BYTES) */ 594c3d31fe1Smrg 595c3d31fe1Smrg /* Define this to be nonzero if stack checking is built into the ABI. */ 596c3d31fe1Smrg #define STACK_CHECK_BUILTIN 1 597c3d31fe1Smrg 598c3d31fe1Smrg /* Define this if the maximum size of all the outgoing args is to be 599c3d31fe1Smrg accumulated and pushed during the prologue. The amount can be 600c3d31fe1Smrg found in the variable crtl->outgoing_args_size. */ 601c3d31fe1Smrg #define ACCUMULATE_OUTGOING_ARGS 1 602c3d31fe1Smrg 603c3d31fe1Smrg /* Offset of first parameter from the argument pointer register value. */ 604c3d31fe1Smrg 605c3d31fe1Smrg #define FIRST_PARM_OFFSET(FNDECL) 0 606c3d31fe1Smrg 607c3d31fe1Smrg /* Definitions for register eliminations. 608c3d31fe1Smrg 609c3d31fe1Smrg We have two registers that can be eliminated on the Alpha. First, the 610c3d31fe1Smrg frame pointer register can often be eliminated in favor of the stack 611c3d31fe1Smrg pointer register. Secondly, the argument pointer register can always be 612c3d31fe1Smrg eliminated; it is replaced with either the stack or frame pointer. */ 613c3d31fe1Smrg 614c3d31fe1Smrg /* This is an array of structures. Each structure initializes one pair 615c3d31fe1Smrg of eliminable registers. The "from" register number is given first, 616c3d31fe1Smrg followed by "to". Eliminations of the same "from" register are listed 617c3d31fe1Smrg in order of preference. */ 618c3d31fe1Smrg 619c3d31fe1Smrg #define ELIMINABLE_REGS \ 620c3d31fe1Smrg {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 621c3d31fe1Smrg { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 622c3d31fe1Smrg { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 623c3d31fe1Smrg { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 624c3d31fe1Smrg 625c3d31fe1Smrg /* Round up to a multiple of 16 bytes. */ 626c3d31fe1Smrg #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) 627c3d31fe1Smrg 628c3d31fe1Smrg /* Define the offset between two registers, one to be eliminated, and the other 629c3d31fe1Smrg its replacement, at the start of a routine. */ 630c3d31fe1Smrg #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 631c3d31fe1Smrg ((OFFSET) = alpha_initial_elimination_offset(FROM, TO)) 632c3d31fe1Smrg 633c3d31fe1Smrg /* Define this if stack space is still allocated for a parameter passed 634c3d31fe1Smrg in a register. */ 635c3d31fe1Smrg /* #define REG_PARM_STACK_SPACE */ 636c3d31fe1Smrg 637c3d31fe1Smrg /* Define how to find the value returned by a function. 638c3d31fe1Smrg VALTYPE is the data type of the value (as a tree). 639c3d31fe1Smrg If the precise function being called is known, FUNC is its FUNCTION_DECL; 640c3d31fe1Smrg otherwise, FUNC is 0. 641c3d31fe1Smrg 642c3d31fe1Smrg On Alpha the value is found in $0 for integer functions and 643c3d31fe1Smrg $f0 for floating-point functions. */ 644c3d31fe1Smrg 645c3d31fe1Smrg #define FUNCTION_VALUE(VALTYPE, FUNC) \ 646c3d31fe1Smrg function_value (VALTYPE, FUNC, VOIDmode) 647c3d31fe1Smrg 648c3d31fe1Smrg /* Define how to find the value returned by a library function 649c3d31fe1Smrg assuming the value has mode MODE. */ 650c3d31fe1Smrg 651c3d31fe1Smrg #define LIBCALL_VALUE(MODE) \ 652c3d31fe1Smrg function_value (NULL, NULL, MODE) 653c3d31fe1Smrg 654c3d31fe1Smrg /* 1 if N is a possible register number for a function value 655c3d31fe1Smrg as seen by the caller. */ 656c3d31fe1Smrg 657c3d31fe1Smrg #define FUNCTION_VALUE_REGNO_P(N) \ 658c3d31fe1Smrg ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) 659c3d31fe1Smrg 660c3d31fe1Smrg /* 1 if N is a possible register number for function argument passing. 661c3d31fe1Smrg On Alpha, these are $16-$21 and $f16-$f21. */ 662c3d31fe1Smrg 663c3d31fe1Smrg #define FUNCTION_ARG_REGNO_P(N) \ 664c3d31fe1Smrg (IN_RANGE ((N), 16, 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) 665c3d31fe1Smrg 666c3d31fe1Smrg /* Define a data type for recording info about an argument list 667c3d31fe1Smrg during the scan of that argument list. This data type should 668c3d31fe1Smrg hold all necessary information about the function itself 669c3d31fe1Smrg and about the args processed so far, enough to enable macros 670c3d31fe1Smrg such as FUNCTION_ARG to determine where the next arg should go. 671c3d31fe1Smrg 672c3d31fe1Smrg On Alpha, this is a single integer, which is a number of words 673c3d31fe1Smrg of arguments scanned so far. 674c3d31fe1Smrg Thus 6 or more means all following args should go on the stack. */ 675c3d31fe1Smrg 676c3d31fe1Smrg #define CUMULATIVE_ARGS int 677c3d31fe1Smrg 678c3d31fe1Smrg /* Initialize a variable CUM of type CUMULATIVE_ARGS 679c3d31fe1Smrg for a call to a function whose data type is FNTYPE. 680c3d31fe1Smrg For a library call, FNTYPE is 0. */ 681c3d31fe1Smrg 682c3d31fe1Smrg #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 683c3d31fe1Smrg (CUM) = 0 684c3d31fe1Smrg 685c3d31fe1Smrg /* Define intermediate macro to compute the size (in registers) of an argument 686c3d31fe1Smrg for the Alpha. */ 687c3d31fe1Smrg 688c3d31fe1Smrg #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ 689c3d31fe1Smrg ((MODE) == TFmode || (MODE) == TCmode ? 1 \ 690c3d31fe1Smrg : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ 691c3d31fe1Smrg + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 692c3d31fe1Smrg 693c3d31fe1Smrg /* Make (or fake) .linkage entry for function call. 694c3d31fe1Smrg IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ 695c3d31fe1Smrg 696c3d31fe1Smrg /* This macro defines the start of an assembly comment. */ 697c3d31fe1Smrg 698c3d31fe1Smrg #define ASM_COMMENT_START " #" 699c3d31fe1Smrg 700c3d31fe1Smrg /* This macro produces the initial definition of a function. */ 701c3d31fe1Smrg 702*af526226Smrg #undef ASM_DECLARE_FUNCTION_NAME 703c3d31fe1Smrg #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 704c3d31fe1Smrg alpha_start_function(FILE,NAME,DECL); 705c3d31fe1Smrg 706c3d31fe1Smrg /* This macro closes up a function definition for the assembler. */ 707c3d31fe1Smrg 708*af526226Smrg #undef ASM_DECLARE_FUNCTION_SIZE 709c3d31fe1Smrg #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ 710c3d31fe1Smrg alpha_end_function(FILE,NAME,DECL) 711c3d31fe1Smrg 712c3d31fe1Smrg /* Output any profiling code before the prologue. */ 713c3d31fe1Smrg 714c3d31fe1Smrg #define PROFILE_BEFORE_PROLOGUE 1 715c3d31fe1Smrg 716c3d31fe1Smrg /* Never use profile counters. */ 717c3d31fe1Smrg 718c3d31fe1Smrg #define NO_PROFILE_COUNTERS 1 719c3d31fe1Smrg 720c3d31fe1Smrg /* Output assembler code to FILE to increment profiler label # LABELNO 721c3d31fe1Smrg for profiling a function entry. Under OSF/1, profiling is enabled 722c3d31fe1Smrg by simply passing -pg to the assembler and linker. */ 723c3d31fe1Smrg 724c3d31fe1Smrg #define FUNCTION_PROFILER(FILE, LABELNO) 725c3d31fe1Smrg 726c3d31fe1Smrg /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 727c3d31fe1Smrg the stack pointer does not matter. The value is tested only in 728c3d31fe1Smrg functions that have frame pointers. 729c3d31fe1Smrg No definition is equivalent to always zero. */ 730c3d31fe1Smrg 731c3d31fe1Smrg #define EXIT_IGNORE_STACK 1 732c3d31fe1Smrg 733c3d31fe1Smrg /* Define registers used by the epilogue and return instruction. */ 734c3d31fe1Smrg 735c3d31fe1Smrg #define EPILOGUE_USES(REGNO) ((REGNO) == 26) 736c3d31fe1Smrg 737c3d31fe1Smrg /* Length in units of the trampoline for entering a nested function. */ 738c3d31fe1Smrg 739c3d31fe1Smrg #define TRAMPOLINE_SIZE 32 740c3d31fe1Smrg 741c3d31fe1Smrg /* The alignment of a trampoline, in bits. */ 742c3d31fe1Smrg 743c3d31fe1Smrg #define TRAMPOLINE_ALIGNMENT 64 744c3d31fe1Smrg 745c3d31fe1Smrg /* A C expression whose value is RTL representing the value of the return 746c3d31fe1Smrg address for the frame COUNT steps up from the current frame. 747c3d31fe1Smrg FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of 748c3d31fe1Smrg the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ 749c3d31fe1Smrg 750c3d31fe1Smrg #define RETURN_ADDR_RTX alpha_return_addr 751c3d31fe1Smrg 752c3d31fe1Smrg /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 753c3d31fe1Smrg can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 754c3d31fe1Smrg as the default definition in dwarf2out.c. */ 755c3d31fe1Smrg #undef DWARF_FRAME_REGNUM 756c3d31fe1Smrg #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG) 757c3d31fe1Smrg 758c3d31fe1Smrg /* Before the prologue, RA lives in $26. */ 759c3d31fe1Smrg #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) 760c3d31fe1Smrg #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) 761c3d31fe1Smrg #define DWARF_ALT_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (64) 762c3d31fe1Smrg #define DWARF_ZERO_REG 31 763c3d31fe1Smrg 764c3d31fe1Smrg /* Describe how we implement __builtin_eh_return. */ 765c3d31fe1Smrg #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) 766c3d31fe1Smrg #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) 767c3d31fe1Smrg #define EH_RETURN_HANDLER_RTX \ 768*af526226Smrg gen_rtx_MEM (Pmode, plus_constant (Pmode, stack_pointer_rtx, \ 769c3d31fe1Smrg crtl->outgoing_args_size)) 770c3d31fe1Smrg 771c3d31fe1Smrg /* Addressing modes, and classification of registers for them. */ 772c3d31fe1Smrg 773c3d31fe1Smrg /* Macros to check register numbers against specific register classes. */ 774c3d31fe1Smrg 775c3d31fe1Smrg /* These assume that REGNO is a hard or pseudo reg number. 776c3d31fe1Smrg They give nonzero only if REGNO is a hard reg of the suitable class 777c3d31fe1Smrg or a pseudo reg currently allocated to a suitable hard reg. 778c3d31fe1Smrg Since they use reg_renumber, they are safe only once reg_renumber 779*af526226Smrg has been allocated, which happens in reginfo.c during register 780*af526226Smrg allocation. */ 781c3d31fe1Smrg 782c3d31fe1Smrg #define REGNO_OK_FOR_INDEX_P(REGNO) 0 783c3d31fe1Smrg #define REGNO_OK_FOR_BASE_P(REGNO) \ 784c3d31fe1Smrg ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ 785c3d31fe1Smrg || (REGNO) == 63 || reg_renumber[REGNO] == 63) 786c3d31fe1Smrg 787c3d31fe1Smrg /* Maximum number of registers that can appear in a valid memory address. */ 788c3d31fe1Smrg #define MAX_REGS_PER_ADDRESS 1 789c3d31fe1Smrg 790c3d31fe1Smrg /* Recognize any constant value that is a valid address. For the Alpha, 791c3d31fe1Smrg there are only constants none since we want to use LDA to load any 792c3d31fe1Smrg symbolic addresses into registers. */ 793c3d31fe1Smrg 794c3d31fe1Smrg #define CONSTANT_ADDRESS_P(X) \ 795c3d31fe1Smrg (CONST_INT_P (X) \ 796c3d31fe1Smrg && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) 797c3d31fe1Smrg 798c3d31fe1Smrg /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 799c3d31fe1Smrg and check its validity for a certain class. 800c3d31fe1Smrg We have two alternate definitions for each of them. 801c3d31fe1Smrg The usual definition accepts all pseudo regs; the other rejects 802c3d31fe1Smrg them unless they have been allocated suitable hard regs. 803c3d31fe1Smrg The symbol REG_OK_STRICT causes the latter definition to be used. 804c3d31fe1Smrg 805c3d31fe1Smrg Most source files want to accept pseudo regs in the hope that 806c3d31fe1Smrg they will get allocated to the class that the insn wants them to be in. 807c3d31fe1Smrg Source files for reload pass need to be strict. 808c3d31fe1Smrg After reload, it makes no difference, since pseudo regs have 809c3d31fe1Smrg been eliminated by then. */ 810c3d31fe1Smrg 811c3d31fe1Smrg /* Nonzero if X is a hard reg that can be used as an index 812c3d31fe1Smrg or if it is a pseudo reg. */ 813c3d31fe1Smrg #define REG_OK_FOR_INDEX_P(X) 0 814c3d31fe1Smrg 815c3d31fe1Smrg /* Nonzero if X is a hard reg that can be used as a base reg 816c3d31fe1Smrg or if it is a pseudo reg. */ 817c3d31fe1Smrg #define NONSTRICT_REG_OK_FOR_BASE_P(X) \ 818c3d31fe1Smrg (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 819c3d31fe1Smrg 820c3d31fe1Smrg /* ??? Nonzero if X is the frame pointer, or some virtual register 821c3d31fe1Smrg that may eliminate to the frame pointer. These will be allowed to 822c3d31fe1Smrg have offsets greater than 32K. This is done because register 823c3d31fe1Smrg elimination offsets will change the hi/lo split, and if we split 824c3d31fe1Smrg before reload, we will require additional instructions. */ 825c3d31fe1Smrg #define NONSTRICT_REG_OK_FP_BASE_P(X) \ 826c3d31fe1Smrg (REGNO (X) == 31 || REGNO (X) == 63 \ 827c3d31fe1Smrg || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 828*af526226Smrg && REGNO (X) < LAST_VIRTUAL_POINTER_REGISTER)) 829c3d31fe1Smrg 830c3d31fe1Smrg /* Nonzero if X is a hard reg that can be used as a base reg. */ 831c3d31fe1Smrg #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 832c3d31fe1Smrg 833c3d31fe1Smrg #ifdef REG_OK_STRICT 834c3d31fe1Smrg #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X) 835c3d31fe1Smrg #else 836c3d31fe1Smrg #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X) 837c3d31fe1Smrg #endif 838c3d31fe1Smrg 839c3d31fe1Smrg /* Try a machine-dependent way of reloading an illegitimate address 840c3d31fe1Smrg operand. If we find one, push the reload and jump to WIN. This 841c3d31fe1Smrg macro is used in only one place: `find_reloads_address' in reload.c. */ 842c3d31fe1Smrg 843c3d31fe1Smrg #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ 844c3d31fe1Smrg do { \ 845c3d31fe1Smrg rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ 846c3d31fe1Smrg if (new_x) \ 847c3d31fe1Smrg { \ 848c3d31fe1Smrg X = new_x; \ 849c3d31fe1Smrg goto WIN; \ 850c3d31fe1Smrg } \ 851c3d31fe1Smrg } while (0) 852c3d31fe1Smrg 853c3d31fe1Smrg 854c3d31fe1Smrg /* Specify the machine mode that this machine uses 855c3d31fe1Smrg for the index in the tablejump instruction. */ 856c3d31fe1Smrg #define CASE_VECTOR_MODE SImode 857c3d31fe1Smrg 858c3d31fe1Smrg /* Define as C expression which evaluates to nonzero if the tablejump 859c3d31fe1Smrg instruction expects the table to contain offsets from the address of the 860c3d31fe1Smrg table. 861c3d31fe1Smrg 862c3d31fe1Smrg Do not define this if the table should contain absolute addresses. 863c3d31fe1Smrg On the Alpha, the table is really GP-relative, not relative to the PC 864c3d31fe1Smrg of the table, but we pretend that it is PC-relative; this should be OK, 865c3d31fe1Smrg but we should try to find some better way sometime. */ 866c3d31fe1Smrg #define CASE_VECTOR_PC_RELATIVE 1 867c3d31fe1Smrg 868c3d31fe1Smrg /* Define this as 1 if `char' should by default be signed; else as 0. */ 869c3d31fe1Smrg #define DEFAULT_SIGNED_CHAR 1 870c3d31fe1Smrg 871c3d31fe1Smrg /* Max number of bytes we can move to or from memory 872c3d31fe1Smrg in one reasonably fast instruction. */ 873c3d31fe1Smrg 874c3d31fe1Smrg #define MOVE_MAX 8 875c3d31fe1Smrg 876c3d31fe1Smrg /* If a memory-to-memory move would take MOVE_RATIO or more simple 877c3d31fe1Smrg move-instruction pairs, we will do a movmem or libcall instead. 878c3d31fe1Smrg 879c3d31fe1Smrg Without byte/word accesses, we want no more than four instructions; 880c3d31fe1Smrg with, several single byte accesses are better. */ 881c3d31fe1Smrg 882c3d31fe1Smrg #define MOVE_RATIO(speed) (TARGET_BWX ? 7 : 2) 883c3d31fe1Smrg 884c3d31fe1Smrg /* Largest number of bytes of an object that can be placed in a register. 885c3d31fe1Smrg On the Alpha we have plenty of registers, so use TImode. */ 886c3d31fe1Smrg #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 887c3d31fe1Smrg 888c3d31fe1Smrg /* Nonzero if access to memory by bytes is no faster than for words. 889c3d31fe1Smrg Also nonzero if doing byte operations (specifically shifts) in registers 890c3d31fe1Smrg is undesirable. 891c3d31fe1Smrg 892c3d31fe1Smrg On the Alpha, we want to not use the byte operation and instead use 893c3d31fe1Smrg masking operations to access fields; these will save instructions. */ 894c3d31fe1Smrg 895c3d31fe1Smrg #define SLOW_BYTE_ACCESS 1 896c3d31fe1Smrg 897c3d31fe1Smrg /* Define if operations between registers always perform the operation 898c3d31fe1Smrg on the full register even if a narrower mode is specified. */ 899c3d31fe1Smrg #define WORD_REGISTER_OPERATIONS 900c3d31fe1Smrg 901c3d31fe1Smrg /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 902c3d31fe1Smrg will either zero-extend or sign-extend. The value of this macro should 903c3d31fe1Smrg be the code that says which one of the two operations is implicitly 904c3d31fe1Smrg done, UNKNOWN if none. */ 905c3d31fe1Smrg #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 906c3d31fe1Smrg 907c3d31fe1Smrg /* Define if loading short immediate values into registers sign extends. */ 908c3d31fe1Smrg #define SHORT_IMMEDIATES_SIGN_EXTEND 909c3d31fe1Smrg 910c3d31fe1Smrg /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 911c3d31fe1Smrg is done just by pretending it is already truncated. */ 912c3d31fe1Smrg #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 913c3d31fe1Smrg 914c3d31fe1Smrg /* The CIX ctlz and cttz instructions return 64 for zero. */ 915c3d31fe1Smrg #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) 916c3d31fe1Smrg #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) 917c3d31fe1Smrg 918c3d31fe1Smrg /* Define the value returned by a floating-point comparison instruction. */ 919c3d31fe1Smrg 920c3d31fe1Smrg #define FLOAT_STORE_FLAG_VALUE(MODE) \ 921c3d31fe1Smrg REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) 922c3d31fe1Smrg 923c3d31fe1Smrg /* Specify the machine mode that pointers have. 924c3d31fe1Smrg After generation of rtl, the compiler makes no further distinction 925c3d31fe1Smrg between pointers and any other objects of this machine mode. */ 926c3d31fe1Smrg #define Pmode DImode 927c3d31fe1Smrg 928c3d31fe1Smrg /* Mode of a function address in a call instruction (for indexing purposes). */ 929c3d31fe1Smrg 930c3d31fe1Smrg #define FUNCTION_MODE Pmode 931c3d31fe1Smrg 932c3d31fe1Smrg /* Define this if addresses of constant functions 933c3d31fe1Smrg shouldn't be put through pseudo regs where they can be cse'd. 934c3d31fe1Smrg Desirable on machines where ordinary constants are expensive 935c3d31fe1Smrg but a CALL with constant address is cheap. 936c3d31fe1Smrg 937c3d31fe1Smrg We define this on the Alpha so that gen_call and gen_call_value 938c3d31fe1Smrg get to see the SYMBOL_REF (for the hint field of the jsr). It will 939c3d31fe1Smrg then copy it into a register, thus actually letting the address be 940c3d31fe1Smrg cse'ed. */ 941c3d31fe1Smrg 942c3d31fe1Smrg #define NO_FUNCTION_CSE 943c3d31fe1Smrg 944c3d31fe1Smrg /* Define this to be nonzero if shift instructions ignore all but the low-order 945c3d31fe1Smrg few bits. */ 946c3d31fe1Smrg #define SHIFT_COUNT_TRUNCATED 1 947c3d31fe1Smrg 948c3d31fe1Smrg /* Control the assembler format that we output. */ 949c3d31fe1Smrg 950c3d31fe1Smrg /* Output to assembler file text saying following lines 951c3d31fe1Smrg may contain character constants, extra white space, comments, etc. */ 952c3d31fe1Smrg #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "") 953c3d31fe1Smrg 954c3d31fe1Smrg /* Output to assembler file text saying following lines 955c3d31fe1Smrg no longer contain unusual constructs. */ 956c3d31fe1Smrg #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "") 957c3d31fe1Smrg 958c3d31fe1Smrg #define TEXT_SECTION_ASM_OP "\t.text" 959c3d31fe1Smrg 960c3d31fe1Smrg /* Output before writable data. */ 961c3d31fe1Smrg 962c3d31fe1Smrg #define DATA_SECTION_ASM_OP "\t.data" 963c3d31fe1Smrg 964c3d31fe1Smrg /* How to refer to registers in assembler output. 965c3d31fe1Smrg This sequence is indexed by compiler's hard-register-number (see above). */ 966c3d31fe1Smrg 967c3d31fe1Smrg #define REGISTER_NAMES \ 968c3d31fe1Smrg {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ 969c3d31fe1Smrg "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 970c3d31fe1Smrg "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 971c3d31fe1Smrg "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ 972c3d31fe1Smrg "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ 973c3d31fe1Smrg "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 974c3d31fe1Smrg "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ 975c3d31fe1Smrg "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} 976c3d31fe1Smrg 977c3d31fe1Smrg /* Strip name encoding when emitting labels. */ 978c3d31fe1Smrg 979c3d31fe1Smrg #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 980c3d31fe1Smrg do { \ 981c3d31fe1Smrg const char *name_ = NAME; \ 982c3d31fe1Smrg if (*name_ == '@' || *name_ == '%') \ 983c3d31fe1Smrg name_ += 2; \ 984c3d31fe1Smrg if (*name_ == '*') \ 985c3d31fe1Smrg name_++; \ 986c3d31fe1Smrg else \ 987c3d31fe1Smrg fputs (user_label_prefix, STREAM); \ 988c3d31fe1Smrg fputs (name_, STREAM); \ 989c3d31fe1Smrg } while (0) 990c3d31fe1Smrg 991c3d31fe1Smrg /* Globalizing directive for a label. */ 992c3d31fe1Smrg #define GLOBAL_ASM_OP "\t.globl " 993c3d31fe1Smrg 994*af526226Smrg /* Use dollar signs rather than periods in special g++ assembler names. */ 995c3d31fe1Smrg 996*af526226Smrg #undef NO_DOLLAR_IN_LABEL 997c3d31fe1Smrg 998c3d31fe1Smrg /* This is how to store into the string LABEL 999c3d31fe1Smrg the symbol_ref name of an internal numbered label where 1000c3d31fe1Smrg PREFIX is the class of label and NUM is the number within the class. 1001c3d31fe1Smrg This is suitable for output with `assemble_name'. */ 1002c3d31fe1Smrg 1003*af526226Smrg #undef ASM_GENERATE_INTERNAL_LABEL 1004c3d31fe1Smrg #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1005c3d31fe1Smrg sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) 1006c3d31fe1Smrg 1007c3d31fe1Smrg /* This is how to output an element of a case-vector that is relative. */ 1008c3d31fe1Smrg 1009c3d31fe1Smrg #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1010*af526226Smrg fprintf (FILE, "\t.gprel32 $L%d\n", (VALUE)) 1011c3d31fe1Smrg 1012c3d31fe1Smrg 1013c3d31fe1Smrg /* Print operand X (an rtx) in assembler syntax to file FILE. 1014c3d31fe1Smrg CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1015c3d31fe1Smrg For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1016c3d31fe1Smrg 1017c3d31fe1Smrg #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1018c3d31fe1Smrg 1019c3d31fe1Smrg /* Determine which codes are valid without a following integer. These must 1020c3d31fe1Smrg not be alphabetic. 1021c3d31fe1Smrg 1022c3d31fe1Smrg ~ Generates the name of the current function. 1023c3d31fe1Smrg 1024c3d31fe1Smrg / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX 1025c3d31fe1Smrg attributes are examined to determine what is appropriate. 1026c3d31fe1Smrg 1027c3d31fe1Smrg , Generates single precision suffix for floating point 1028c3d31fe1Smrg instructions (s for IEEE, f for VAX) 1029c3d31fe1Smrg 1030c3d31fe1Smrg - Generates double precision suffix for floating point 1031c3d31fe1Smrg instructions (t for IEEE, g for VAX) 1032c3d31fe1Smrg */ 1033c3d31fe1Smrg 1034c3d31fe1Smrg #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1035c3d31fe1Smrg ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ 1036c3d31fe1Smrg || (CODE) == '#' || (CODE) == '*' || (CODE) == '&') 1037c3d31fe1Smrg 1038c3d31fe1Smrg /* Print a memory address as an operand to reference that memory location. */ 1039c3d31fe1Smrg 1040c3d31fe1Smrg #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1041c3d31fe1Smrg print_operand_address((FILE), (ADDR)) 1042c3d31fe1Smrg 1043c3d31fe1Smrg /* If we use NM, pass -g to it so it only lists globals. */ 1044c3d31fe1Smrg #define NM_FLAGS "-pg" 1045c3d31fe1Smrg 1046c3d31fe1Smrg /* Definitions for debugging. */ 1047c3d31fe1Smrg 1048c3d31fe1Smrg /* Correct the offset of automatic variables and arguments. Note that 1049c3d31fe1Smrg the Alpha debug format wants all automatic variables and arguments 1050c3d31fe1Smrg to be in terms of two different offsets from the virtual frame pointer, 1051c3d31fe1Smrg which is the stack pointer before any adjustment in the function. 1052c3d31fe1Smrg The offset for the argument pointer is fixed for the native compiler, 1053c3d31fe1Smrg it is either zero (for the no arguments case) or large enough to hold 1054c3d31fe1Smrg all argument registers. 1055c3d31fe1Smrg The offset for the auto pointer is the fourth argument to the .frame 1056c3d31fe1Smrg directive (local_offset). 1057c3d31fe1Smrg To stay compatible with the native tools we use the same offsets 1058c3d31fe1Smrg from the virtual frame pointer and adjust the debugger arg/auto offsets 1059c3d31fe1Smrg accordingly. These debugger offsets are set up in output_prolog. */ 1060c3d31fe1Smrg 1061c3d31fe1Smrg extern long alpha_arg_offset; 1062c3d31fe1Smrg extern long alpha_auto_offset; 1063c3d31fe1Smrg #define DEBUGGER_AUTO_OFFSET(X) \ 1064c3d31fe1Smrg ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) 1065c3d31fe1Smrg #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) 1066c3d31fe1Smrg 1067c3d31fe1Smrg #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 1068c3d31fe1Smrg alpha_output_filename (STREAM, NAME) 1069c3d31fe1Smrg 1070c3d31fe1Smrg /* By default, turn on GDB extensions. */ 1071c3d31fe1Smrg #define DEFAULT_GDB_EXTENSIONS 1 1072c3d31fe1Smrg 1073c3d31fe1Smrg /* The system headers under Alpha systems are generally C++-aware. */ 1074c3d31fe1Smrg #define NO_IMPLICIT_EXTERN_C 1075