1*dd083157Smrg /* Copyright (C) 2009-2020 Free Software Foundation, Inc.
2c3d31fe1Smrg    Contributed by Anatoly Sokolov (aesok@post.ru)
3c3d31fe1Smrg 
4c3d31fe1Smrg    This file is part of GCC.
5c3d31fe1Smrg 
6c3d31fe1Smrg    GCC is free software; you can redistribute it and/or modify
7c3d31fe1Smrg    it under the terms of the GNU General Public License as published by
8c3d31fe1Smrg    the Free Software Foundation; either version 3, or (at your option)
9c3d31fe1Smrg    any later version.
10c3d31fe1Smrg 
11c3d31fe1Smrg    GCC is distributed in the hope that it will be useful,
12c3d31fe1Smrg    but WITHOUT ANY WARRANTY; without even the implied warranty of
13c3d31fe1Smrg    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14c3d31fe1Smrg    GNU General Public License for more details.
15c3d31fe1Smrg 
16c3d31fe1Smrg    You should have received a copy of the GNU General Public License
17c3d31fe1Smrg    along with GCC; see the file COPYING3.  If not see
18c3d31fe1Smrg    <http://www.gnu.org/licenses/>.  */
19c3d31fe1Smrg 
20af526226Smrg #ifndef IN_GEN_AVR_MMCU_TEXI
213903d7f3Smrg #define IN_TARGET_CODE 1
223903d7f3Smrg 
23c3d31fe1Smrg #include "config.h"
24c3d31fe1Smrg #include "system.h"
25c3d31fe1Smrg #include "coretypes.h"
26c3d31fe1Smrg #include "tm.h"
2763aace61Smrg #include "diagnostic.h"
28af526226Smrg #endif /* IN_GEN_AVR_MMCU_TEXI */
29c3d31fe1Smrg 
305ef59e75Smrg #include "avr-arch.h"
315ef59e75Smrg 
32af526226Smrg /* List of all known AVR MCU architectures.
33af526226Smrg    Order as of enum avr_arch from avr.h.  */
34c3d31fe1Smrg 
35af526226Smrg const avr_arch_t
36af526226Smrg avr_arch_types[] =
37af526226Smrg {
38af526226Smrg   /* unknown device specified */
393903d7f3Smrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, NULL, AVR_MMCU_DEFAULT },
40af526226Smrg   /*
413903d7f3Smrg     A  M  J  LM E  E  E  X  R  T  d S     FPO     S O   A
423903d7f3Smrg     S  U  M  PO L  L  I  M  A  I  a t     lMff    F ff  r
433903d7f3Smrg     M  L  P  MV P  P  J  E  M  N  t a     a s     R s   c
443903d7f3Smrg              XW M  M  M  G  P  Y  a r     s e       e   h
453903d7f3Smrg                    X  P  A  D       t     h t       t   ID   */
463903d7f3Smrg   { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "1",   "avr1"  },
473903d7f3Smrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "2",   "avr2"  },
483903d7f3Smrg   { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "25",  "avr25" },
493903d7f3Smrg   { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "3",   "avr3"  },
503903d7f3Smrg   { 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0x0060, 0,      32, "31",  "avr31" },
513903d7f3Smrg   { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "35",  "avr35" },
523903d7f3Smrg   { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "4",   "avr4"  },
533903d7f3Smrg   { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "5",   "avr5"  },
543903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0x0060, 0,      32, "51",  "avr51" },
553903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0x0060, 0,      32, "6",   "avr6"  },
56af526226Smrg 
573903d7f3Smrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0x0040, 0x4000, 0, "100", "avrtiny" },
583903d7f3Smrg   { 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0x2000, 0,      0, "102", "avrxmega2" },
593903d7f3Smrg   { 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0x2000, 0x8000, 0, "103", "avrxmega3" },
603903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0x2000, 0,      0, "104", "avrxmega4" },
613903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0x2000, 0,      0, "105", "avrxmega5" },
623903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0x2000, 0,      0, "106", "avrxmega6" },
633903d7f3Smrg   { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0x2000, 0,      0, "107", "avrxmega7" }
64c3d31fe1Smrg };
65c3d31fe1Smrg 
66af526226Smrg const avr_arch_info_t
67af526226Smrg avr_texinfo[] =
68af526226Smrg {
69af526226Smrg   { ARCH_AVR1,
70af526226Smrg     "This ISA is implemented by the minimal AVR core and supported "
71af526226Smrg     "for assembler only." },
72af526226Smrg   { ARCH_AVR2,
73af526226Smrg     "``Classic'' devices with up to 8@tie{}KiB of program memory." },
74af526226Smrg   { ARCH_AVR25,
75af526226Smrg     "``Classic'' devices with up to 8@tie{}KiB of program memory and with "
76af526226Smrg     "the @code{MOVW} instruction." },
77af526226Smrg   { ARCH_AVR3,
78af526226Smrg     "``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
79af526226Smrg     "program memory." },
80af526226Smrg   { ARCH_AVR31,
81af526226Smrg     "``Classic'' devices with 128@tie{}KiB of program memory." },
82af526226Smrg   { ARCH_AVR35,
83af526226Smrg     "``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
84af526226Smrg     "program memory and with the @code{MOVW} instruction." },
85af526226Smrg   { ARCH_AVR4,
86af526226Smrg     "``Enhanced'' devices with up to 8@tie{}KiB of program memory." },
87af526226Smrg   { ARCH_AVR5,
88af526226Smrg     "``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
89af526226Smrg     "program memory." },
90af526226Smrg   { ARCH_AVR51,
91af526226Smrg     "``Enhanced'' devices with 128@tie{}KiB of program memory." },
92af526226Smrg   { ARCH_AVR6,
93af526226Smrg     "``Enhanced'' devices with 3-byte PC, i.e.@: with more than 128@tie{}KiB "
94af526226Smrg     "of program memory." },
955ef59e75Smrg   { ARCH_AVRTINY,
965ef59e75Smrg     "``TINY'' Tiny core devices with 512@tie{}B up to 4@tie{}KiB of "
975ef59e75Smrg     "program memory." },
98af526226Smrg   { ARCH_AVRXMEGA2,
99af526226Smrg     "``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB "
100af526226Smrg     "of program memory." },
1013903d7f3Smrg   { ARCH_AVRXMEGA3,
1023903d7f3Smrg     "``XMEGA'' devices with up to 64@tie{}KiB of combined program memory "
1033903d7f3Smrg     "and RAM, and with program memory visible in the RAM address space." },
104af526226Smrg   { ARCH_AVRXMEGA4,
105af526226Smrg     "``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB "
106af526226Smrg     "of program memory." },
107af526226Smrg   { ARCH_AVRXMEGA5,
108af526226Smrg     "``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB "
109af526226Smrg     "of program memory and more than 64@tie{}KiB of RAM." },
110af526226Smrg   { ARCH_AVRXMEGA6,
111af526226Smrg     "``XMEGA'' devices with more than 128@tie{}KiB of program memory." },
112af526226Smrg   { ARCH_AVRXMEGA7,
113af526226Smrg     "``XMEGA'' devices with more than 128@tie{}KiB of program memory "
114af526226Smrg     "and more than 64@tie{}KiB of RAM." }
115af526226Smrg };
116c3d31fe1Smrg 
117af526226Smrg const avr_mcu_t
118af526226Smrg avr_mcu_types[] =
119af526226Smrg {
1203903d7f3Smrg #define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, FLASH_SIZE, PMOFF) \
1213903d7f3Smrg   { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, FLASH_SIZE, PMOFF },
122af526226Smrg #include "avr-mcus.def"
123af526226Smrg #undef AVR_MCU
124c3d31fe1Smrg     /* End of list.  */
1253903d7f3Smrg   { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, 0, 0 }
126c3d31fe1Smrg };
127c3d31fe1Smrg 
1285ef59e75Smrg 
1295ef59e75Smrg 
1305ef59e75Smrg 
1315ef59e75Smrg #ifndef IN_GEN_AVR_MMCU_TEXI
1325ef59e75Smrg 
1335ef59e75Smrg static char*
avr_archs_str(void)1345ef59e75Smrg avr_archs_str (void)
1355ef59e75Smrg {
1365ef59e75Smrg   char *archs = concat ("", NULL);
1375ef59e75Smrg 
1385ef59e75Smrg   // Build of core architectures' names.
1395ef59e75Smrg 
1405ef59e75Smrg   for (const avr_mcu_t *mcu = avr_mcu_types; mcu->name; mcu++)
1415ef59e75Smrg     if (!mcu->macro)
1425ef59e75Smrg       archs = concat (archs, " ", avr_arch_types[mcu->arch_id].name, NULL);
1435ef59e75Smrg 
1445ef59e75Smrg   return archs;
1455ef59e75Smrg }
1465ef59e75Smrg 
1475ef59e75Smrg 
1485ef59e75Smrg void
avr_inform_core_architectures(void)1495ef59e75Smrg avr_inform_core_architectures (void)
1505ef59e75Smrg {
1515ef59e75Smrg   char *archs = avr_archs_str ();
1525ef59e75Smrg   inform (input_location, "supported core architectures:%s", archs);
1535ef59e75Smrg   free (archs);
1545ef59e75Smrg }
1555ef59e75Smrg 
1565ef59e75Smrg #endif // IN_GEN_AVR_MMCU_TEXI
157