1 /* Subroutines used for code generation for RISC-V. 2 Copyright (C) 2011-2014 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley. 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #include "config.h" 23 #include "system.h" 24 #include "coretypes.h" 25 #include "tm.h" 26 #include "rtl.h" 27 #include "regs.h" 28 #include "hard-reg-set.h" 29 #include "insn-config.h" 30 #include "conditions.h" 31 #include "insn-attr.h" 32 #include "recog.h" 33 #include "output.h" 34 #include "tree.h" 35 //#include "varasm.h" 36 //#include "stor-layout.h" 37 //#include "calls.h" 38 #include "function.h" 39 #include "expr.h" 40 #include "optabs.h" 41 #include "libfuncs.h" 42 #include "flags.h" 43 #include "reload.h" 44 #include "tm_p.h" 45 #include "ggc.h" 46 #include "gstab.h" 47 #include "hashtab.h" 48 #include "debug.h" 49 #include "target.h" 50 #include "target-def.h" 51 #include "langhooks.h" 52 #include "sched-int.h" 53 #include "bitmap.h" 54 #include "diagnostic.h" 55 #include "target-globals.h" 56 #include "symcat.h" 57 #include <stdint.h> 58 59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ 60 #define UNSPEC_ADDRESS_P(X) \ 61 (GET_CODE (X) == UNSPEC \ 62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 64 65 /* Extract the symbol or label from UNSPEC wrapper X. */ 66 #define UNSPEC_ADDRESS(X) \ 67 XVECEXP (X, 0, 0) 68 69 /* Extract the symbol type from UNSPEC wrapper X. */ 70 #define UNSPEC_ADDRESS_TYPE(X) \ 71 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 72 73 /* The maximum distance between the top of the stack frame and the 74 value sp has when we save and restore registers. This is set by the 75 range of load/store offsets and must also preserve stack alignment. */ 76 #define RISCV_MAX_FIRST_STACK_STEP (RISCV_IMM_REACH/2 - 16) 77 78 /* True if INSN is a riscv.md pattern or asm statement. */ 79 #define USEFUL_INSN_P(INSN) \ 80 (NONDEBUG_INSN_P (INSN) \ 81 && GET_CODE (PATTERN (INSN)) != USE \ 82 && GET_CODE (PATTERN (INSN)) != CLOBBER \ 83 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ 84 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) 85 86 /* True if bit BIT is set in VALUE. */ 87 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) 88 89 /* Classifies an address. 90 91 ADDRESS_REG 92 A natural register + offset address. The register satisfies 93 riscv_valid_base_register_p and the offset is a const_arith_operand. 94 95 ADDRESS_LO_SUM 96 A LO_SUM rtx. The first operand is a valid base register and 97 the second operand is a symbolic address. 98 99 ADDRESS_CONST_INT 100 A signed 16-bit constant address. 101 102 ADDRESS_SYMBOLIC: 103 A constant symbolic address. */ 104 enum riscv_address_type { 105 ADDRESS_REG, 106 ADDRESS_LO_SUM, 107 ADDRESS_CONST_INT, 108 ADDRESS_SYMBOLIC 109 }; 110 111 /* Macros to create an enumeration identifier for a function prototype. */ 112 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B 113 #define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C 114 #define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D 115 #define RISCV_FTYPE_NAME4(A, B, C, D, E) RISCV_##A##_FTYPE_##B##_##C##_##D##_##E 116 117 /* Classifies the prototype of a built-in function. */ 118 enum riscv_function_type { 119 #define DEF_RISCV_FTYPE(NARGS, LIST) RISCV_FTYPE_NAME##NARGS LIST, 120 #include "config/riscv/riscv-ftypes.def" 121 #undef DEF_RISCV_FTYPE 122 RISCV_MAX_FTYPE_MAX 123 }; 124 125 /* Specifies how a built-in function should be converted into rtl. */ 126 enum riscv_builtin_type { 127 /* The function corresponds directly to an .md pattern. The return 128 value is mapped to operand 0 and the arguments are mapped to 129 operands 1 and above. */ 130 RISCV_BUILTIN_DIRECT, 131 132 /* The function corresponds directly to an .md pattern. There is no return 133 value and the arguments are mapped to operands 0 and above. */ 134 RISCV_BUILTIN_DIRECT_NO_TARGET 135 }; 136 137 /* Information about a function's frame layout. */ 138 struct GTY(()) riscv_frame_info { 139 /* The size of the frame in bytes. */ 140 HOST_WIDE_INT total_size; 141 142 /* Bit X is set if the function saves or restores GPR X. */ 143 unsigned int mask; 144 145 /* Likewise FPR X. */ 146 unsigned int fmask; 147 148 /* Offsets of fixed-point and floating-point save areas from frame bottom */ 149 HOST_WIDE_INT gp_sp_offset; 150 HOST_WIDE_INT fp_sp_offset; 151 152 /* Offset of virtual frame pointer from stack pointer/frame bottom */ 153 HOST_WIDE_INT frame_pointer_offset; 154 155 /* Offset of hard frame pointer from stack pointer/frame bottom */ 156 HOST_WIDE_INT hard_frame_pointer_offset; 157 158 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 159 HOST_WIDE_INT arg_pointer_offset; 160 }; 161 162 struct GTY(()) machine_function { 163 /* The number of extra stack bytes taken up by register varargs. 164 This area is allocated by the callee at the very top of the frame. */ 165 int varargs_size; 166 167 /* The current frame information, calculated by riscv_compute_frame_info. */ 168 struct riscv_frame_info frame; 169 }; 170 171 /* Information about a single argument. */ 172 struct riscv_arg_info { 173 /* True if the argument is passed in a floating-point register, or 174 would have been if we hadn't run out of registers. */ 175 bool fpr_p; 176 177 /* The number of words passed in registers, rounded up. */ 178 unsigned int reg_words; 179 180 /* For EABI, the offset of the first register from GP_ARG_FIRST or 181 FP_ARG_FIRST. For other ABIs, the offset of the first register from 182 the start of the ABI's argument structure (see the CUMULATIVE_ARGS 183 comment for details). 184 185 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely 186 on the stack. */ 187 unsigned int reg_offset; 188 189 /* The number of words that must be passed on the stack, rounded up. */ 190 unsigned int stack_words; 191 192 /* The offset from the start of the stack overflow area of the argument's 193 first stack word. Only meaningful when STACK_WORDS is nonzero. */ 194 unsigned int stack_offset; 195 }; 196 197 /* Information about an address described by riscv_address_type. 198 199 ADDRESS_CONST_INT 200 No fields are used. 201 202 ADDRESS_REG 203 REG is the base register and OFFSET is the constant offset. 204 205 ADDRESS_LO_SUM 206 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE 207 is the type of symbol it references. 208 209 ADDRESS_SYMBOLIC 210 SYMBOL_TYPE is the type of symbol that the address references. */ 211 struct riscv_address_info { 212 enum riscv_address_type type; 213 rtx reg; 214 rtx offset; 215 enum riscv_symbol_type symbol_type; 216 }; 217 218 /* One stage in a constant building sequence. These sequences have 219 the form: 220 221 A = VALUE[0] 222 A = A CODE[1] VALUE[1] 223 A = A CODE[2] VALUE[2] 224 ... 225 226 where A is an accumulator, each CODE[i] is a binary rtl operation 227 and each VALUE[i] is a constant integer. CODE[0] is undefined. */ 228 struct riscv_integer_op { 229 enum rtx_code code; 230 unsigned HOST_WIDE_INT value; 231 }; 232 233 /* The largest number of operations needed to load an integer constant. 234 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. 235 When the lowest bit is clear, we can try, but reject a sequence with 236 an extra SLL at the end. */ 237 #define RISCV_MAX_INTEGER_OPS 32 238 239 /* Costs of various operations on the different architectures. */ 240 241 struct riscv_rtx_cost_data 242 { 243 unsigned short fp_add; 244 unsigned short fp_mult_sf; 245 unsigned short fp_mult_df; 246 unsigned short fp_div_sf; 247 unsigned short fp_div_df; 248 unsigned short int_mult_si; 249 unsigned short int_mult_di; 250 unsigned short int_div_si; 251 unsigned short int_div_di; 252 unsigned short branch_cost; 253 unsigned short memory_latency; 254 }; 255 256 /* Global variables for machine-dependent things. */ 257 258 /* The processor that we should tune the code for. */ 259 enum processor riscv_tune; 260 261 /* Which cost information to use. */ 262 static const struct riscv_rtx_cost_data *riscv_cost; 263 264 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ 265 bool riscv_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; 266 267 /* riscv_lo_relocs[X] is the relocation to use when a symbol of type X 268 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or 269 if they are matched by a special .md file pattern. */ 270 const char *riscv_lo_relocs[NUM_SYMBOL_TYPES]; 271 272 /* Likewise for HIGHs. */ 273 const char *riscv_hi_relocs[NUM_SYMBOL_TYPES]; 274 275 /* Index R is the smallest register class that contains register R. */ 276 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { 277 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 278 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 279 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 280 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 281 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 282 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 283 GR_REGS, GR_REGS, T_REGS, T_REGS, 284 T_REGS, T_REGS, T_REGS, GR_REGS, 285 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 286 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 287 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 288 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 289 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 290 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 291 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 292 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 293 FRAME_REGS, FRAME_REGS, 294 }; 295 296 /* A table describing all the processors GCC knows about. Names are 297 matched in the order listed. The first mention of an ISA level is 298 taken as the canonical name for that ISA. 299 300 To ease comparison, please keep this table in the same order 301 as GAS's riscv_cpu_info_table. Please also make sure that 302 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march 303 options correctly. */ 304 static const struct riscv_cpu_info riscv_cpu_info_table[] = { 305 /* Entries for generic ISAs. */ 306 { "rocket", PROCESSOR_ROCKET, 0 }, 307 }; 308 309 /* Default costs. If these are used for a processor we should look 310 up the actual costs. */ 311 #define DEFAULT_COSTS COSTS_N_INSNS (8), /* fp_add */ \ 312 COSTS_N_INSNS (8), /* fp_mult_sf */ \ 313 COSTS_N_INSNS (8), /* fp_mult_df */ \ 314 COSTS_N_INSNS (20), /* fp_div_sf */ \ 315 COSTS_N_INSNS (20), /* fp_div_df */ \ 316 COSTS_N_INSNS (4), /* int_mult_si */ \ 317 COSTS_N_INSNS (4), /* int_mult_di */ \ 318 COSTS_N_INSNS (6), /* int_div_si */ \ 319 COSTS_N_INSNS (6), /* int_div_di */ \ 320 2, /* branch_cost */ \ 321 7 /* memory_latency */ 322 323 /* Floating-point costs for processors without an FPU. Just assume that 324 all floating-point libcalls are very expensive. */ 325 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ 326 COSTS_N_INSNS (256), /* fp_mult_sf */ \ 327 COSTS_N_INSNS (256), /* fp_mult_df */ \ 328 COSTS_N_INSNS (256), /* fp_div_sf */ \ 329 COSTS_N_INSNS (256) /* fp_div_df */ 330 331 /* Costs to use when optimizing for size. */ 332 static const struct riscv_rtx_cost_data riscv_rtx_cost_optimize_size = { 333 COSTS_N_INSNS (1), /* fp_add */ 334 COSTS_N_INSNS (1), /* fp_mult_sf */ 335 COSTS_N_INSNS (1), /* fp_mult_df */ 336 COSTS_N_INSNS (1), /* fp_div_sf */ 337 COSTS_N_INSNS (1), /* fp_div_df */ 338 COSTS_N_INSNS (1), /* int_mult_si */ 339 COSTS_N_INSNS (1), /* int_mult_di */ 340 COSTS_N_INSNS (1), /* int_div_si */ 341 COSTS_N_INSNS (1), /* int_div_di */ 342 1, /* branch_cost */ 343 1 /* memory_latency */ 344 }; 345 346 /* Costs to use when optimizing for speed, indexed by processor. */ 347 static const struct riscv_rtx_cost_data 348 riscv_rtx_cost_data[NUM_PROCESSOR_VALUES] = { 349 { /* Rocket */ DEFAULT_COSTS}, 350 }; 351 352 /* Predicates to test for presence of "near" and "far"/"long_call" 353 attributes on the given TYPE. */ 354 355 static bool 356 riscv_near_type_p (const_tree type) 357 { 358 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; 359 } 360 361 static bool 362 riscv_far_type_p (const_tree type) 363 { 364 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL 365 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); 366 } 367 368 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ 369 370 static int 371 riscv_comp_type_attributes (const_tree type1, const_tree type2) 372 { 373 /* Disallow mixed near/far attributes. */ 374 if (riscv_far_type_p (type1) && riscv_near_type_p (type2)) 375 return 0; 376 if (riscv_near_type_p (type1) && riscv_far_type_p (type2)) 377 return 0; 378 return 1; 379 } 380 381 /* Fill CODES with a sequence of rtl operations to load VALUE. 382 Return the number of operations needed. */ 383 384 static int 385 riscv_build_integer_1 (struct riscv_integer_op *codes, HOST_WIDE_INT value, 386 enum machine_mode mode) 387 { 388 HOST_WIDE_INT low_part = RISCV_CONST_LOW_PART (value); 389 int cost = INT_MAX, alt_cost; 390 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 391 392 if (SMALL_OPERAND (value) || LUI_OPERAND (value)) 393 { 394 /* Simply ADDI or LUI */ 395 codes[0].code = UNKNOWN; 396 codes[0].value = value; 397 return 1; 398 } 399 400 /* End with ADDI */ 401 if (low_part != 0 402 && !(mode == HImode && (int16_t)(value - low_part) != (value - low_part))) 403 { 404 cost = 1 + riscv_build_integer_1 (codes, value - low_part, mode); 405 codes[cost-1].code = PLUS; 406 codes[cost-1].value = low_part; 407 } 408 409 /* End with XORI */ 410 if (cost > 2 && (low_part < 0 || mode == HImode)) 411 { 412 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode); 413 alt_codes[alt_cost-1].code = XOR; 414 alt_codes[alt_cost-1].value = low_part; 415 if (alt_cost < cost) 416 cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes)); 417 } 418 419 /* Eliminate trailing zeros and end with SLLI */ 420 if (cost > 2 && (value & 1) == 0) 421 { 422 int shift = __builtin_ctzl(value); 423 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value >> shift, mode); 424 alt_codes[alt_cost-1].code = ASHIFT; 425 alt_codes[alt_cost-1].value = shift; 426 if (alt_cost < cost) 427 cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes)); 428 } 429 430 gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); 431 return cost; 432 } 433 434 static int 435 riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, 436 enum machine_mode mode) 437 { 438 int cost = riscv_build_integer_1 (codes, value, mode); 439 440 /* Eliminate leading zeros and end with SRLI */ 441 if (value > 0 && cost > 2) 442 { 443 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 444 int alt_cost, shift; 445 HOST_WIDE_INT shifted_val; 446 447 /* Try filling trailing bits with 1s */ 448 shift = __builtin_clzl(value); 449 shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1); 450 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 451 alt_codes[alt_cost-1].code = LSHIFTRT; 452 alt_codes[alt_cost-1].value = shift; 453 if (alt_cost < cost) 454 cost = alt_cost, memcpy (codes, alt_codes, sizeof (alt_codes)); 455 456 /* Try filling trailing bits with 0s */ 457 shifted_val = value << shift; 458 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 459 alt_codes[alt_cost-1].code = LSHIFTRT; 460 alt_codes[alt_cost-1].value = shift; 461 if (alt_cost < cost) 462 cost = alt_cost, memcpy (codes, alt_codes, sizeof (alt_codes)); 463 } 464 465 return cost; 466 } 467 468 static int 469 riscv_split_integer_cost (HOST_WIDE_INT val) 470 { 471 int cost; 472 int32_t loval = val, hival = (val - (int32_t)val) >> 32; 473 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 474 475 cost = 2 + riscv_build_integer (codes, loval, VOIDmode); 476 if (loval != hival) 477 cost += riscv_build_integer (codes, hival, VOIDmode); 478 479 return cost; 480 } 481 482 static int 483 riscv_integer_cost (HOST_WIDE_INT val) 484 { 485 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 486 return MIN (riscv_build_integer (codes, val, VOIDmode), 487 riscv_split_integer_cost (val)); 488 } 489 490 /* Try to split a 64b integer into 32b parts, then reassemble. */ 491 492 static rtx 493 riscv_split_integer (HOST_WIDE_INT val, enum machine_mode mode) 494 { 495 int32_t loval = val, hival = (val - (int32_t)val) >> 32; 496 rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); 497 498 riscv_move_integer (hi, hi, hival); 499 riscv_move_integer (lo, lo, loval); 500 501 hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); 502 hi = force_reg (mode, hi); 503 504 return gen_rtx_fmt_ee (PLUS, mode, hi, lo); 505 } 506 507 /* Return true if X is a thread-local symbol. */ 508 509 static bool 510 riscv_tls_symbol_p (const_rtx x) 511 { 512 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; 513 } 514 515 static bool 516 riscv_symbol_binds_local_p (const_rtx x) 517 { 518 return (SYMBOL_REF_DECL (x) 519 ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) 520 : SYMBOL_REF_LOCAL_P (x)); 521 } 522 523 /* Return the method that should be used to access SYMBOL_REF or 524 LABEL_REF X in context CONTEXT. */ 525 526 static enum riscv_symbol_type 527 riscv_classify_symbol (const_rtx x) 528 { 529 if (riscv_tls_symbol_p (x)) 530 return SYMBOL_TLS; 531 532 if (GET_CODE (x) == LABEL_REF) 533 { 534 if (LABEL_REF_NONLOCAL_P (x)) 535 return SYMBOL_GOT_DISP; 536 return SYMBOL_ABSOLUTE; 537 } 538 539 gcc_assert (GET_CODE (x) == SYMBOL_REF); 540 541 if (flag_pic && !riscv_symbol_binds_local_p (x)) 542 return SYMBOL_GOT_DISP; 543 544 return SYMBOL_ABSOLUTE; 545 } 546 547 /* Classify the base of symbolic expression X, given that X appears in 548 context CONTEXT. */ 549 550 static enum riscv_symbol_type 551 riscv_classify_symbolic_expression (rtx x) 552 { 553 rtx offset; 554 555 split_const (x, &x, &offset); 556 if (UNSPEC_ADDRESS_P (x)) 557 return UNSPEC_ADDRESS_TYPE (x); 558 559 return riscv_classify_symbol (x); 560 } 561 562 /* Return true if X is a symbolic constant that can be used in context 563 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ 564 565 bool 566 riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type) 567 { 568 rtx offset; 569 570 split_const (x, &x, &offset); 571 if (UNSPEC_ADDRESS_P (x)) 572 { 573 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 574 x = UNSPEC_ADDRESS (x); 575 } 576 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 577 *symbol_type = riscv_classify_symbol (x); 578 else 579 return false; 580 581 if (offset == const0_rtx) 582 return true; 583 584 /* Check whether a nonzero offset is valid for the underlying 585 relocations. */ 586 switch (*symbol_type) 587 { 588 case SYMBOL_ABSOLUTE: 589 return (int32_t) INTVAL (offset) == INTVAL (offset); 590 591 case SYMBOL_TLS: 592 case SYMBOL_TLS_LE: 593 case SYMBOL_TLS_IE: 594 case SYMBOL_GOT_DISP: 595 return false; 596 } 597 gcc_unreachable (); 598 } 599 600 /* Returns the number of instructions necessary to reference a symbol. */ 601 602 static int riscv_symbol_insns (enum riscv_symbol_type type) 603 { 604 switch (type) 605 { 606 case SYMBOL_TLS: return 0; /* Depends on the TLS model. */ 607 case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference itself */ 608 case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference itself */ 609 case SYMBOL_TLS_IE: return 4; /* LUI + LD + ADD TP + the reference itself */ 610 case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference itself */ 611 default: gcc_unreachable(); 612 } 613 } 614 615 /* A for_each_rtx callback. Stop the search if *X references a 616 thread-local symbol. */ 617 618 static int 619 riscv_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 620 { 621 return riscv_tls_symbol_p (*x); 622 } 623 624 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 625 626 static bool 627 riscv_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) 628 { 629 return riscv_const_insns (x) > 0; 630 } 631 632 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 633 634 static bool 635 riscv_cannot_force_const_mem (enum machine_mode mode, rtx x) 636 { 637 enum riscv_symbol_type type; 638 rtx base, offset; 639 640 /* There is no assembler syntax for expressing an address-sized 641 high part. */ 642 if (GET_CODE (x) == HIGH) 643 return true; 644 645 /* As an optimization, reject constants that riscv_legitimize_move 646 can expand inline. 647 648 Suppose we have a multi-instruction sequence that loads constant C 649 into register R. If R does not get allocated a hard register, and 650 R is used in an operand that allows both registers and memory 651 references, reload will consider forcing C into memory and using 652 one of the instruction's memory alternatives. Returning false 653 here will force it to use an input reload instead. */ 654 if (CONST_INT_P (x) && riscv_legitimate_constant_p (mode, x)) 655 return true; 656 657 split_const (x, &base, &offset); 658 if (riscv_symbolic_constant_p (base, &type)) 659 { 660 /* The same optimization as for CONST_INT. */ 661 if (SMALL_INT (offset) && riscv_symbol_insns (type) > 0) 662 return true; 663 } 664 665 /* TLS symbols must be computed by riscv_legitimize_move. */ 666 if (for_each_rtx (&x, &riscv_tls_symbol_ref_1, NULL)) 667 return true; 668 669 return false; 670 } 671 672 /* Return true if register REGNO is a valid base register for mode MODE. 673 STRICT_P is true if REG_OK_STRICT is in effect. */ 674 675 int 676 riscv_regno_mode_ok_for_base_p (int regno, enum machine_mode mode ATTRIBUTE_UNUSED, 677 bool strict_p) 678 { 679 if (!HARD_REGISTER_NUM_P (regno)) 680 { 681 if (!strict_p) 682 return true; 683 regno = reg_renumber[regno]; 684 } 685 686 /* These fake registers will be eliminated to either the stack or 687 hard frame pointer, both of which are usually valid base registers. 688 Reload deals with the cases where the eliminated form isn't valid. */ 689 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 690 return true; 691 692 return GP_REG_P (regno); 693 } 694 695 /* Return true if X is a valid base register for mode MODE. 696 STRICT_P is true if REG_OK_STRICT is in effect. */ 697 698 static bool 699 riscv_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p) 700 { 701 if (!strict_p && GET_CODE (x) == SUBREG) 702 x = SUBREG_REG (x); 703 704 return (REG_P (x) 705 && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); 706 } 707 708 /* Return true if, for every base register BASE_REG, (plus BASE_REG X) 709 can address a value of mode MODE. */ 710 711 static bool 712 riscv_valid_offset_p (rtx x, enum machine_mode mode) 713 { 714 /* Check that X is a signed 12-bit number. */ 715 if (!const_arith_operand (x, Pmode)) 716 return false; 717 718 /* We may need to split multiword moves, so make sure that every word 719 is accessible. */ 720 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 721 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) 722 return false; 723 724 return true; 725 } 726 727 /* Return true if a LO_SUM can address a value of mode MODE when the 728 LO_SUM symbol has type SYMBOL_TYPE. */ 729 730 static bool 731 riscv_valid_lo_sum_p (enum riscv_symbol_type symbol_type, enum machine_mode mode) 732 { 733 /* Check that symbols of type SYMBOL_TYPE can be used to access values 734 of mode MODE. */ 735 if (riscv_symbol_insns (symbol_type) == 0) 736 return false; 737 738 /* Check that there is a known low-part relocation. */ 739 if (riscv_lo_relocs[symbol_type] == NULL) 740 return false; 741 742 /* We may need to split multiword moves, so make sure that each word 743 can be accessed without inducing a carry. This is mainly needed 744 for o64, which has historically only guaranteed 64-bit alignment 745 for 128-bit types. */ 746 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 747 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) 748 return false; 749 750 return true; 751 } 752 753 /* Return true if X is a valid address for machine mode MODE. If it is, 754 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in 755 effect. */ 756 757 static bool 758 riscv_classify_address (struct riscv_address_info *info, rtx x, 759 enum machine_mode mode, bool strict_p) 760 { 761 switch (GET_CODE (x)) 762 { 763 case REG: 764 case SUBREG: 765 info->type = ADDRESS_REG; 766 info->reg = x; 767 info->offset = const0_rtx; 768 return riscv_valid_base_register_p (info->reg, mode, strict_p); 769 770 case PLUS: 771 info->type = ADDRESS_REG; 772 info->reg = XEXP (x, 0); 773 info->offset = XEXP (x, 1); 774 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 775 && riscv_valid_offset_p (info->offset, mode)); 776 777 case LO_SUM: 778 info->type = ADDRESS_LO_SUM; 779 info->reg = XEXP (x, 0); 780 info->offset = XEXP (x, 1); 781 /* We have to trust the creator of the LO_SUM to do something vaguely 782 sane. Target-independent code that creates a LO_SUM should also 783 create and verify the matching HIGH. Target-independent code that 784 adds an offset to a LO_SUM must prove that the offset will not 785 induce a carry. Failure to do either of these things would be 786 a bug, and we are not required to check for it here. The RISCV 787 backend itself should only create LO_SUMs for valid symbolic 788 constants, with the high part being either a HIGH or a copy 789 of _gp. */ 790 info->symbol_type 791 = riscv_classify_symbolic_expression (info->offset); 792 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 793 && riscv_valid_lo_sum_p (info->symbol_type, mode)); 794 795 case CONST_INT: 796 /* Small-integer addresses don't occur very often, but they 797 are legitimate if $0 is a valid base register. */ 798 info->type = ADDRESS_CONST_INT; 799 return SMALL_INT (x); 800 801 case CONST: 802 case LABEL_REF: 803 case SYMBOL_REF: 804 if (riscv_symbolic_constant_p (x, &info->symbol_type) 805 && riscv_symbol_insns (info->symbol_type) > 0 806 && !riscv_hi_relocs[info->symbol_type] 807 && riscv_lo_relocs[info->symbol_type]) 808 { 809 info->type = ADDRESS_LO_SUM; 810 info->reg = gen_rtx_REG (Pmode, GP_REGNUM); 811 info->offset = x; 812 return true; 813 } 814 815 default: 816 return false; 817 } 818 } 819 820 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 821 822 static bool 823 riscv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) 824 { 825 struct riscv_address_info addr; 826 827 return riscv_classify_address (&addr, x, mode, strict_p); 828 } 829 830 /* Return the number of instructions needed to load or store a value 831 of mode MODE at address X. Return 0 if X isn't valid for MODE. 832 Assume that multiword moves may need to be split into word moves 833 if MIGHT_SPLIT_P, otherwise assume that a single load or store is 834 enough. */ 835 836 int 837 riscv_address_insns (rtx x, enum machine_mode mode, bool might_split_p) 838 { 839 struct riscv_address_info addr; 840 int n = 1; 841 842 if (!riscv_classify_address (&addr, x, mode, false)) 843 return 0; 844 845 /* BLKmode is used for single unaligned loads and stores and should 846 not count as a multiword mode. */ 847 if (mode != BLKmode && might_split_p) 848 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 849 850 if (addr.type == ADDRESS_SYMBOLIC) 851 n *= riscv_symbol_insns (addr.symbol_type); 852 853 return n; 854 } 855 856 /* Return the number of instructions needed to load constant X. 857 Return 0 if X isn't a valid constant. */ 858 859 int 860 riscv_const_insns (rtx x) 861 { 862 enum riscv_symbol_type symbol_type; 863 rtx offset; 864 865 switch (GET_CODE (x)) 866 { 867 case HIGH: 868 if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type) 869 || !riscv_hi_relocs[symbol_type]) 870 return 0; 871 872 /* This is simply an LUI. */ 873 return 1; 874 875 case CONST_INT: 876 { 877 int cost = riscv_integer_cost (INTVAL (x)); 878 /* Force complicated constants to memory. */ 879 return cost < 4 ? cost : 0; 880 } 881 882 case CONST_DOUBLE: 883 case CONST_VECTOR: 884 /* Allow zeros for normal mode, where we can use x0. */ 885 return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; 886 887 case CONST: 888 /* See if we can refer to X directly. */ 889 if (riscv_symbolic_constant_p (x, &symbol_type)) 890 return riscv_symbol_insns (symbol_type); 891 892 /* Otherwise try splitting the constant into a base and offset. 893 If the offset is a 16-bit value, we can load the base address 894 into a register and then use (D)ADDIU to add in the offset. 895 If the offset is larger, we can load the base and offset 896 into separate registers and add them together with (D)ADDU. 897 However, the latter is only possible before reload; during 898 and after reload, we must have the option of forcing the 899 constant into the pool instead. */ 900 split_const (x, &x, &offset); 901 if (offset != 0) 902 { 903 int n = riscv_const_insns (x); 904 if (n != 0) 905 { 906 if (SMALL_INT (offset)) 907 return n + 1; 908 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x)) 909 return n + 1 + riscv_integer_cost (INTVAL (offset)); 910 } 911 } 912 return 0; 913 914 case SYMBOL_REF: 915 case LABEL_REF: 916 return riscv_symbol_insns (riscv_classify_symbol (x)); 917 918 default: 919 return 0; 920 } 921 } 922 923 /* X is a doubleword constant that can be handled by splitting it into 924 two words and loading each word separately. Return the number of 925 instructions required to do this. */ 926 927 int 928 riscv_split_const_insns (rtx x) 929 { 930 unsigned int low, high; 931 932 low = riscv_const_insns (riscv_subword (x, false)); 933 high = riscv_const_insns (riscv_subword (x, true)); 934 gcc_assert (low > 0 && high > 0); 935 return low + high; 936 } 937 938 /* Return the number of instructions needed to implement INSN, 939 given that it loads from or stores to MEM. */ 940 941 int 942 riscv_load_store_insns (rtx mem, rtx insn) 943 { 944 enum machine_mode mode; 945 bool might_split_p; 946 rtx set; 947 948 gcc_assert (MEM_P (mem)); 949 mode = GET_MODE (mem); 950 951 /* Try to prove that INSN does not need to be split. */ 952 might_split_p = true; 953 if (GET_MODE_BITSIZE (mode) == 64) 954 { 955 set = single_set (insn); 956 if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) 957 might_split_p = false; 958 } 959 960 return riscv_address_insns (XEXP (mem, 0), mode, might_split_p); 961 } 962 963 /* Emit a move from SRC to DEST. Assume that the move expanders can 964 handle all moves if !can_create_pseudo_p (). The distinction is 965 important because, unlike emit_move_insn, the move expanders know 966 how to force Pmode objects into the constant pool even when the 967 constant pool address is not itself legitimate. */ 968 969 rtx 970 riscv_emit_move (rtx dest, rtx src) 971 { 972 return (can_create_pseudo_p () 973 ? emit_move_insn (dest, src) 974 : emit_move_insn_1 (dest, src)); 975 } 976 977 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ 978 979 static void 980 riscv_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) 981 { 982 emit_insn (gen_rtx_SET (VOIDmode, target, 983 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); 984 } 985 986 /* Compute (CODE OP0 OP1) and store the result in a new register 987 of mode MODE. Return that new register. */ 988 989 static rtx 990 riscv_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1) 991 { 992 rtx reg; 993 994 reg = gen_reg_rtx (mode); 995 riscv_emit_binary (code, reg, op0, op1); 996 return reg; 997 } 998 999 /* Copy VALUE to a register and return that register. If new pseudos 1000 are allowed, copy it into a new register, otherwise use DEST. */ 1001 1002 static rtx 1003 riscv_force_temporary (rtx dest, rtx value) 1004 { 1005 if (can_create_pseudo_p ()) 1006 return force_reg (Pmode, value); 1007 else 1008 { 1009 riscv_emit_move (dest, value); 1010 return dest; 1011 } 1012 } 1013 1014 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, 1015 then add CONST_INT OFFSET to the result. */ 1016 1017 static rtx 1018 riscv_unspec_address_offset (rtx base, rtx offset, 1019 enum riscv_symbol_type symbol_type) 1020 { 1021 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 1022 UNSPEC_ADDRESS_FIRST + symbol_type); 1023 if (offset != const0_rtx) 1024 base = gen_rtx_PLUS (Pmode, base, offset); 1025 return gen_rtx_CONST (Pmode, base); 1026 } 1027 1028 /* Return an UNSPEC address with underlying address ADDRESS and symbol 1029 type SYMBOL_TYPE. */ 1030 1031 rtx 1032 riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type) 1033 { 1034 rtx base, offset; 1035 1036 split_const (address, &base, &offset); 1037 return riscv_unspec_address_offset (base, offset, symbol_type); 1038 } 1039 1040 /* If OP is an UNSPEC address, return the address to which it refers, 1041 otherwise return OP itself. */ 1042 1043 static rtx 1044 riscv_strip_unspec_address (rtx op) 1045 { 1046 rtx base, offset; 1047 1048 split_const (op, &base, &offset); 1049 if (UNSPEC_ADDRESS_P (base)) 1050 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); 1051 return op; 1052 } 1053 1054 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 1055 high part to BASE and return the result. Just return BASE otherwise. 1056 TEMP is as for riscv_force_temporary. 1057 1058 The returned expression can be used as the first operand to a LO_SUM. */ 1059 1060 static rtx 1061 riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) 1062 { 1063 addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); 1064 return riscv_force_temporary (temp, addr); 1065 } 1066 1067 /* Load an entry from the GOT. */ 1068 static rtx riscv_got_load_tls_gd(rtx dest, rtx sym) 1069 { 1070 return (Pmode == DImode ? gen_got_load_tls_gddi(dest, sym) : gen_got_load_tls_gdsi(dest, sym)); 1071 } 1072 1073 static rtx riscv_got_load_tls_ie(rtx dest, rtx sym) 1074 { 1075 return (Pmode == DImode ? gen_got_load_tls_iedi(dest, sym) : gen_got_load_tls_iesi(dest, sym)); 1076 } 1077 1078 static rtx riscv_got_load_tls_ie_hi(rtx dest, rtx sym) 1079 { 1080 return (Pmode == DImode ? gen_got_load_tls_ie_hidi(dest, sym) : gen_got_load_tls_ie_hisi(dest, sym)); 1081 } 1082 1083 static rtx riscv_got_load_tls_ie_lo(rtx dest, rtx base, rtx sym) 1084 { 1085 return (Pmode == DImode ? gen_got_load_tls_ie_lodi(dest, base, sym) : gen_got_load_tls_ie_losi(dest, base, sym)); 1086 } 1087 1088 static rtx riscv_tls_add_tp_ie(rtx dest, rtx base, rtx sym) 1089 { 1090 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1091 return (Pmode == DImode ? gen_tls_add_tp_iedi(dest, base, tp, sym) : gen_tls_add_tp_iesi(dest, base, tp, sym)); 1092 } 1093 1094 static rtx riscv_tls_add_tp_le(rtx dest, rtx base, rtx sym) 1095 { 1096 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1097 return (Pmode == DImode ? gen_tls_add_tp_ledi(dest, base, tp, sym) : gen_tls_add_tp_lesi(dest, base, tp, sym)); 1098 } 1099 1100 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise 1101 it appears in a MEM of that mode. Return true if ADDR is a legitimate 1102 constant in that context and can be split into high and low parts. 1103 If so, and if LOW_OUT is nonnull, emit the high part and store the 1104 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. 1105 1106 TEMP is as for riscv_force_temporary and is used to load the high 1107 part into a register. 1108 1109 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be 1110 a legitimize SET_SRC for an .md pattern, otherwise the low part 1111 is guaranteed to be a legitimate address for mode MODE. */ 1112 1113 bool 1114 riscv_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out) 1115 { 1116 enum riscv_symbol_type symbol_type; 1117 rtx high; 1118 1119 if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE) 1120 || !riscv_symbolic_constant_p (addr, &symbol_type) 1121 || riscv_symbol_insns (symbol_type) == 0 1122 || !riscv_hi_relocs[symbol_type]) 1123 return false; 1124 1125 if (low_out) 1126 { 1127 switch (symbol_type) 1128 { 1129 case SYMBOL_ABSOLUTE: 1130 high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); 1131 high = riscv_force_temporary (temp, high); 1132 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 1133 break; 1134 1135 default: 1136 gcc_unreachable (); 1137 } 1138 } 1139 1140 return true; 1141 } 1142 1143 /* Return a legitimate address for REG + OFFSET. TEMP is as for 1144 riscv_force_temporary; it is only needed when OFFSET is not a 1145 SMALL_OPERAND. */ 1146 1147 static rtx 1148 riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 1149 { 1150 if (!SMALL_OPERAND (offset)) 1151 { 1152 rtx high; 1153 1154 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. 1155 The addition inside the macro CONST_HIGH_PART may cause an 1156 overflow, so we need to force a sign-extension check. */ 1157 high = gen_int_mode (RISCV_CONST_HIGH_PART (offset), Pmode); 1158 offset = RISCV_CONST_LOW_PART (offset); 1159 high = riscv_force_temporary (temp, high); 1160 reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); 1161 } 1162 return plus_constant (Pmode, reg, offset); 1163 } 1164 1165 /* The __tls_get_attr symbol. */ 1166 static GTY(()) rtx riscv_tls_symbol; 1167 1168 /* Return an instruction sequence that calls __tls_get_addr. SYM is 1169 the TLS symbol we are referencing and TYPE is the symbol type to use 1170 (either global dynamic or local dynamic). V0 is an RTX for the 1171 return value location. */ 1172 1173 static rtx 1174 riscv_call_tls_get_addr (rtx sym, rtx v0) 1175 { 1176 rtx insn, a0; 1177 1178 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); 1179 1180 if (!riscv_tls_symbol) 1181 riscv_tls_symbol = init_one_libfunc ("__tls_get_addr"); 1182 1183 start_sequence (); 1184 1185 emit_insn (riscv_got_load_tls_gd(a0, sym)); 1186 insn = riscv_expand_call (false, v0, riscv_tls_symbol, const0_rtx); 1187 RTL_CONST_CALL_P (insn) = 1; 1188 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 1189 insn = get_insns (); 1190 1191 end_sequence (); 1192 1193 return insn; 1194 } 1195 1196 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return 1197 its address. The return value will be both a valid address and a valid 1198 SET_SRC (either a REG or a LO_SUM). */ 1199 1200 static rtx 1201 riscv_legitimize_tls_address (rtx loc) 1202 { 1203 rtx dest, insn, v0, tp, tmp1; 1204 1205 switch (SYMBOL_REF_TLS_MODEL (loc)) 1206 { 1207 case TLS_MODEL_LOCAL_DYNAMIC: 1208 /* Rely on section anchors for the optimization that LDM TLS 1209 provides. The anchor's address is loaded with GD TLS. */ 1210 case TLS_MODEL_GLOBAL_DYNAMIC: 1211 v0 = gen_rtx_REG (Pmode, GP_RETURN); 1212 insn = riscv_call_tls_get_addr (loc, v0); 1213 dest = gen_reg_rtx (Pmode); 1214 emit_libcall_block (insn, dest, v0, loc); 1215 break; 1216 1217 case TLS_MODEL_INITIAL_EXEC: 1218 if (flag_pic) 1219 { 1220 /* la.tls.ie; tp-relative add */ 1221 tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1222 tmp1 = gen_reg_rtx (Pmode); 1223 emit_insn (riscv_got_load_tls_ie (tmp1, loc)); 1224 dest = gen_reg_rtx (Pmode); 1225 emit_insn (gen_add3_insn (dest, tmp1, tp)); 1226 } 1227 else 1228 { 1229 /* lui %tls_ie_hi; ld %tls_le_lo; tp-relative add */ 1230 tmp1 = gen_reg_rtx (Pmode); 1231 emit_insn (riscv_got_load_tls_ie_hi (tmp1, loc)); 1232 dest = gen_reg_rtx (Pmode); 1233 emit_insn (riscv_got_load_tls_ie_lo (dest, tmp1, loc)); 1234 tmp1 = gen_reg_rtx (Pmode); 1235 emit_insn (riscv_tls_add_tp_ie (tmp1, dest, loc)); 1236 dest = gen_rtx_LO_SUM (Pmode, tmp1, 1237 riscv_unspec_address (loc, SYMBOL_TLS_IE)); 1238 } 1239 break; 1240 1241 case TLS_MODEL_LOCAL_EXEC: 1242 tmp1 = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE); 1243 dest = gen_reg_rtx (Pmode); 1244 emit_insn (riscv_tls_add_tp_le (dest, tmp1, loc)); 1245 dest = gen_rtx_LO_SUM (Pmode, dest, 1246 riscv_unspec_address (loc, SYMBOL_TLS_LE)); 1247 break; 1248 1249 default: 1250 gcc_unreachable (); 1251 } 1252 return dest; 1253 } 1254 1255 /* If X is not a valid address for mode MODE, force it into a register. */ 1256 1257 static rtx 1258 riscv_force_address (rtx x, enum machine_mode mode) 1259 { 1260 if (!riscv_legitimate_address_p (mode, x, false)) 1261 x = force_reg (Pmode, x); 1262 return x; 1263 } 1264 1265 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can 1266 be legitimized in a way that the generic machinery might not expect, 1267 return a new address, otherwise return NULL. MODE is the mode of 1268 the memory being accessed. */ 1269 1270 static rtx 1271 riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 1272 enum machine_mode mode) 1273 { 1274 rtx addr; 1275 1276 if (riscv_tls_symbol_p (x)) 1277 return riscv_legitimize_tls_address (x); 1278 1279 /* See if the address can split into a high part and a LO_SUM. */ 1280 if (riscv_split_symbol (NULL, x, mode, &addr)) 1281 return riscv_force_address (addr, mode); 1282 1283 /* Handle BASE + OFFSET using riscv_add_offset. */ 1284 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) 1285 && INTVAL (XEXP (x, 1)) != 0) 1286 { 1287 rtx base = XEXP (x, 0); 1288 HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); 1289 1290 if (!riscv_valid_base_register_p (base, mode, false)) 1291 base = copy_to_mode_reg (Pmode, base); 1292 addr = riscv_add_offset (NULL, base, offset); 1293 return riscv_force_address (addr, mode); 1294 } 1295 1296 return x; 1297 } 1298 1299 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */ 1300 1301 void 1302 riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) 1303 { 1304 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 1305 enum machine_mode mode; 1306 int i, num_ops; 1307 rtx x; 1308 1309 mode = GET_MODE (dest); 1310 num_ops = riscv_build_integer (codes, value, mode); 1311 1312 if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ 1313 && num_ops >= riscv_split_integer_cost (value)) 1314 x = riscv_split_integer (value, mode); 1315 else 1316 { 1317 /* Apply each binary operation to X. */ 1318 x = GEN_INT (codes[0].value); 1319 1320 for (i = 1; i < num_ops; i++) 1321 { 1322 if (!can_create_pseudo_p ()) 1323 { 1324 emit_insn (gen_rtx_SET (VOIDmode, temp, x)); 1325 x = temp; 1326 } 1327 else 1328 x = force_reg (mode, x); 1329 1330 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 1331 } 1332 } 1333 1334 emit_insn (gen_rtx_SET (VOIDmode, dest, x)); 1335 } 1336 1337 /* Subroutine of riscv_legitimize_move. Move constant SRC into register 1338 DEST given that SRC satisfies immediate_operand but doesn't satisfy 1339 move_operand. */ 1340 1341 static void 1342 riscv_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) 1343 { 1344 rtx base, offset; 1345 1346 /* Split moves of big integers into smaller pieces. */ 1347 if (splittable_const_int_operand (src, mode)) 1348 { 1349 riscv_move_integer (dest, dest, INTVAL (src)); 1350 return; 1351 } 1352 1353 /* Split moves of symbolic constants into high/low pairs. */ 1354 if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) 1355 { 1356 emit_insn (gen_rtx_SET (VOIDmode, dest, src)); 1357 return; 1358 } 1359 1360 /* Generate the appropriate access sequences for TLS symbols. */ 1361 if (riscv_tls_symbol_p (src)) 1362 { 1363 riscv_emit_move (dest, riscv_legitimize_tls_address (src)); 1364 return; 1365 } 1366 1367 /* If we have (const (plus symbol offset)), and that expression cannot 1368 be forced into memory, load the symbol first and add in the offset. Also 1369 prefer to do this even if the constant _can_ be forced into memory, as it 1370 usually produces better code. */ 1371 split_const (src, &base, &offset); 1372 if (offset != const0_rtx 1373 && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) 1374 { 1375 base = riscv_force_temporary (dest, base); 1376 riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); 1377 return; 1378 } 1379 1380 src = force_const_mem (mode, src); 1381 1382 /* When using explicit relocs, constant pool references are sometimes 1383 not legitimate addresses. */ 1384 riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); 1385 riscv_emit_move (dest, src); 1386 } 1387 1388 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent 1389 sequence that is valid. */ 1390 1391 bool 1392 riscv_legitimize_move (enum machine_mode mode, rtx dest, rtx src) 1393 { 1394 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 1395 { 1396 riscv_emit_move (dest, force_reg (mode, src)); 1397 return true; 1398 } 1399 1400 /* We need to deal with constants that would be legitimate 1401 immediate_operands but aren't legitimate move_operands. */ 1402 if (CONSTANT_P (src) && !move_operand (src, mode)) 1403 { 1404 riscv_legitimize_const_move (mode, dest, src); 1405 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 1406 return true; 1407 } 1408 return false; 1409 } 1410 1411 /* The cost of loading values from the constant pool. It should be 1412 larger than the cost of any constant we want to synthesize inline. */ 1413 #define CONSTANT_POOL_COST COSTS_N_INSNS (8) 1414 1415 /* Return true if there is an instruction that implements CODE and accepts 1416 X as an immediate operand. */ 1417 1418 static int 1419 riscv_immediate_operand_p (int code, HOST_WIDE_INT x) 1420 { 1421 switch (code) 1422 { 1423 case ASHIFT: 1424 case ASHIFTRT: 1425 case LSHIFTRT: 1426 /* All shift counts are truncated to a valid constant. */ 1427 return true; 1428 1429 case AND: 1430 case IOR: 1431 case XOR: 1432 case PLUS: 1433 case LT: 1434 case LTU: 1435 /* These instructions take 12-bit signed immediates. */ 1436 return SMALL_OPERAND (x); 1437 1438 case LE: 1439 /* We add 1 to the immediate and use SLT. */ 1440 return SMALL_OPERAND (x + 1); 1441 1442 case LEU: 1443 /* Likewise SLTU, but reject the always-true case. */ 1444 return SMALL_OPERAND (x + 1) && x + 1 != 0; 1445 1446 case GE: 1447 case GEU: 1448 /* We can emulate an immediate of 1 by using GT/GTU against x0. */ 1449 return x == 1; 1450 1451 default: 1452 /* By default assume that x0 can be used for 0. */ 1453 return x == 0; 1454 } 1455 } 1456 1457 /* Return the cost of binary operation X, given that the instruction 1458 sequence for a word-sized or smaller operation has cost SINGLE_COST 1459 and that the sequence of a double-word operation has cost DOUBLE_COST. 1460 If SPEED is true, optimize for speed otherwise optimize for size. */ 1461 1462 static int 1463 riscv_binary_cost (rtx x, int single_cost, int double_cost, bool speed) 1464 { 1465 int cost = single_cost; 1466 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) 1467 cost = double_cost; 1468 1469 return (cost 1470 + set_src_cost (XEXP (x, 0), speed) 1471 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed)); 1472 } 1473 1474 /* Return the cost of floating-point multiplications of mode MODE. */ 1475 1476 static int 1477 riscv_fp_mult_cost (enum machine_mode mode) 1478 { 1479 return mode == DFmode ? riscv_cost->fp_mult_df : riscv_cost->fp_mult_sf; 1480 } 1481 1482 /* Return the cost of floating-point divisions of mode MODE. */ 1483 1484 static int 1485 riscv_fp_div_cost (enum machine_mode mode) 1486 { 1487 return mode == DFmode ? riscv_cost->fp_div_df : riscv_cost->fp_div_sf; 1488 } 1489 1490 /* Return the cost of sign-extending OP to mode MODE, not including the 1491 cost of OP itself. */ 1492 1493 static int 1494 riscv_sign_extend_cost (enum machine_mode mode, rtx op) 1495 { 1496 if (MEM_P (op)) 1497 /* Extended loads are as cheap as unextended ones. */ 1498 return 0; 1499 1500 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) 1501 /* A sign extension from SImode to DImode in 64-bit mode is free. */ 1502 return 0; 1503 1504 /* We need to use a shift left and a shift right. */ 1505 return COSTS_N_INSNS (2); 1506 } 1507 1508 /* Return the cost of zero-extending OP to mode MODE, not including the 1509 cost of OP itself. */ 1510 1511 static int 1512 riscv_zero_extend_cost (enum machine_mode mode, rtx op) 1513 { 1514 if (MEM_P (op)) 1515 /* Extended loads are as cheap as unextended ones. */ 1516 return 0; 1517 1518 if ((TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) || 1519 ((mode == DImode || mode == SImode) && GET_MODE (op) == HImode)) 1520 /* We need a shift left by 32 bits and a shift right by 32 bits. */ 1521 return COSTS_N_INSNS (2); 1522 1523 /* We can use ANDI. */ 1524 return COSTS_N_INSNS (1); 1525 } 1526 1527 /* Implement TARGET_RTX_COSTS. */ 1528 1529 static bool 1530 riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, 1531 int *total, bool speed) 1532 { 1533 enum machine_mode mode = GET_MODE (x); 1534 bool float_mode_p = FLOAT_MODE_P (mode); 1535 int cost; 1536 rtx addr; 1537 1538 /* The cost of a COMPARE is hard to define for RISCV. COMPAREs don't 1539 appear in the instruction stream, and the cost of a comparison is 1540 really the cost of the branch or scc condition. At the time of 1541 writing, GCC only uses an explicit outer COMPARE code when optabs 1542 is testing whether a constant is expensive enough to force into a 1543 register. We want optabs to pass such constants through the RISCV 1544 expanders instead, so make all constants very cheap here. */ 1545 if (outer_code == COMPARE) 1546 { 1547 gcc_assert (CONSTANT_P (x)); 1548 *total = 0; 1549 return true; 1550 } 1551 1552 switch (code) 1553 { 1554 case CONST_INT: 1555 /* When not optimizing for size, we care more about the cost 1556 of hot code, and hot code is often in a loop. If a constant 1557 operand needs to be forced into a register, we will often be 1558 able to hoist the constant load out of the loop, so the load 1559 should not contribute to the cost. */ 1560 if (!optimize_size || riscv_immediate_operand_p (outer_code, INTVAL (x))) 1561 { 1562 *total = 0; 1563 return true; 1564 } 1565 /* Fall through. */ 1566 1567 case CONST: 1568 case SYMBOL_REF: 1569 case LABEL_REF: 1570 case CONST_DOUBLE: 1571 cost = riscv_const_insns (x); 1572 if (cost > 0) 1573 { 1574 /* If the constant is likely to be stored in a GPR, SETs of 1575 single-insn constants are as cheap as register sets; we 1576 never want to CSE them. */ 1577 if (cost == 1 && outer_code == SET && code == CONST_INT) 1578 cost = 0; 1579 *total = COSTS_N_INSNS (cost); 1580 return true; 1581 } 1582 /* The value will need to be fetched from the constant pool. */ 1583 *total = CONSTANT_POOL_COST; 1584 return true; 1585 1586 case MEM: 1587 /* If the address is legitimate, return the number of 1588 instructions it needs. */ 1589 addr = XEXP (x, 0); 1590 cost = riscv_address_insns (addr, mode, true); 1591 if (cost > 0) 1592 { 1593 *total = COSTS_N_INSNS (cost + riscv_cost->memory_latency); 1594 return true; 1595 } 1596 /* Otherwise use the default handling. */ 1597 return false; 1598 1599 case FFS: 1600 *total = COSTS_N_INSNS (6); 1601 return false; 1602 1603 case NOT: 1604 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); 1605 return false; 1606 1607 case AND: 1608 case IOR: 1609 case XOR: 1610 /* Double-word operations use two single-word operations. */ 1611 *total = riscv_binary_cost (x, 1, 2, speed); 1612 return true; 1613 1614 case ASHIFT: 1615 case ASHIFTRT: 1616 case LSHIFTRT: 1617 case ROTATE: 1618 case ROTATERT: 1619 if (CONSTANT_P (XEXP (x, 1))) 1620 *total = riscv_binary_cost (x, 1, 4, speed); 1621 else 1622 *total = riscv_binary_cost (x, 1, 12, speed); 1623 return true; 1624 1625 case ABS: 1626 if (float_mode_p) 1627 *total = riscv_cost->fp_add; 1628 else 1629 *total = COSTS_N_INSNS (4); 1630 return false; 1631 1632 case LO_SUM: 1633 *total = (COSTS_N_INSNS (1) 1634 + set_src_cost (XEXP (x, 0), speed)); 1635 return true; 1636 1637 case LT: 1638 case LTU: 1639 case LE: 1640 case LEU: 1641 case GT: 1642 case GTU: 1643 case GE: 1644 case GEU: 1645 case EQ: 1646 case NE: 1647 case UNORDERED: 1648 case LTGT: 1649 /* Branch comparisons have VOIDmode, so use the first operand's 1650 mode instead. */ 1651 mode = GET_MODE (XEXP (x, 0)); 1652 if (FLOAT_MODE_P (mode)) 1653 { 1654 *total = riscv_cost->fp_add; 1655 return false; 1656 } 1657 *total = riscv_binary_cost (x, 1, 4, speed); 1658 return true; 1659 1660 case MINUS: 1661 if (float_mode_p 1662 && !HONOR_NANS (mode) 1663 && !HONOR_SIGNED_ZEROS (mode)) 1664 { 1665 /* See if we can use NMADD or NMSUB. See riscv.md for the 1666 associated patterns. */ 1667 rtx op0 = XEXP (x, 0); 1668 rtx op1 = XEXP (x, 1); 1669 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) 1670 { 1671 *total = (riscv_fp_mult_cost (mode) 1672 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed) 1673 + set_src_cost (XEXP (op0, 1), speed) 1674 + set_src_cost (op1, speed)); 1675 return true; 1676 } 1677 if (GET_CODE (op1) == MULT) 1678 { 1679 *total = (riscv_fp_mult_cost (mode) 1680 + set_src_cost (op0, speed) 1681 + set_src_cost (XEXP (op1, 0), speed) 1682 + set_src_cost (XEXP (op1, 1), speed)); 1683 return true; 1684 } 1685 } 1686 /* Fall through. */ 1687 1688 case PLUS: 1689 if (float_mode_p) 1690 { 1691 /* If this is part of a MADD or MSUB, treat the PLUS as 1692 being free. */ 1693 if (GET_CODE (XEXP (x, 0)) == MULT) 1694 *total = 0; 1695 else 1696 *total = riscv_cost->fp_add; 1697 return false; 1698 } 1699 1700 /* Double-word operations require three ADDs and an SLTU. */ 1701 *total = riscv_binary_cost (x, 1, 4, speed); 1702 return true; 1703 1704 case NEG: 1705 if (float_mode_p 1706 && !HONOR_NANS (mode) 1707 && HONOR_SIGNED_ZEROS (mode)) 1708 { 1709 /* See if we can use NMADD or NMSUB. See riscv.md for the 1710 associated patterns. */ 1711 rtx op = XEXP (x, 0); 1712 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) 1713 && GET_CODE (XEXP (op, 0)) == MULT) 1714 { 1715 *total = (riscv_fp_mult_cost (mode) 1716 + set_src_cost (XEXP (XEXP (op, 0), 0), speed) 1717 + set_src_cost (XEXP (XEXP (op, 0), 1), speed) 1718 + set_src_cost (XEXP (op, 1), speed)); 1719 return true; 1720 } 1721 } 1722 1723 if (float_mode_p) 1724 *total = riscv_cost->fp_add; 1725 else 1726 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); 1727 return false; 1728 1729 case MULT: 1730 if (float_mode_p) 1731 *total = riscv_fp_mult_cost (mode); 1732 else if (mode == DImode && !TARGET_64BIT) 1733 /* We use a MUL and a MULH[[S]U]. */ 1734 *total = riscv_cost->int_mult_si * 2; 1735 else if (!speed) 1736 *total = 1; 1737 else if (mode == DImode) 1738 *total = riscv_cost->int_mult_di; 1739 else 1740 *total = riscv_cost->int_mult_si; 1741 return false; 1742 1743 case DIV: 1744 /* Check for a reciprocal. */ 1745 if (float_mode_p 1746 && flag_unsafe_math_optimizations 1747 && XEXP (x, 0) == CONST1_RTX (mode)) 1748 { 1749 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) 1750 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the 1751 division as being free. */ 1752 *total = set_src_cost (XEXP (x, 1), speed); 1753 else 1754 *total = (riscv_fp_div_cost (mode) 1755 + set_src_cost (XEXP (x, 1), speed)); 1756 return true; 1757 } 1758 /* Fall through. */ 1759 1760 case SQRT: 1761 case MOD: 1762 if (float_mode_p) 1763 { 1764 *total = riscv_fp_div_cost (mode); 1765 return false; 1766 } 1767 /* Fall through. */ 1768 1769 case UDIV: 1770 case UMOD: 1771 if (!speed) 1772 *total = 1; 1773 else if (mode == DImode) 1774 *total = riscv_cost->int_div_di; 1775 else 1776 *total = riscv_cost->int_div_si; 1777 return false; 1778 1779 case SIGN_EXTEND: 1780 *total = riscv_sign_extend_cost (mode, XEXP (x, 0)); 1781 return false; 1782 1783 case ZERO_EXTEND: 1784 *total = riscv_zero_extend_cost (mode, XEXP (x, 0)); 1785 return false; 1786 1787 case FLOAT: 1788 case UNSIGNED_FLOAT: 1789 case FIX: 1790 case FLOAT_EXTEND: 1791 case FLOAT_TRUNCATE: 1792 *total = riscv_cost->fp_add; 1793 return false; 1794 1795 default: 1796 return false; 1797 } 1798 } 1799 1800 /* Implement TARGET_ADDRESS_COST. */ 1801 1802 static int 1803 riscv_address_cost (rtx addr, enum machine_mode mode, 1804 addr_space_t as ATTRIBUTE_UNUSED, 1805 bool speed ATTRIBUTE_UNUSED) 1806 { 1807 return riscv_address_insns (addr, mode, false); 1808 } 1809 1810 /* Return one word of double-word value OP. HIGH_P is true to select the 1811 high part or false to select the low part. */ 1812 1813 rtx 1814 riscv_subword (rtx op, bool high_p) 1815 { 1816 unsigned int byte; 1817 enum machine_mode mode; 1818 1819 mode = GET_MODE (op); 1820 if (mode == VOIDmode) 1821 mode = TARGET_64BIT ? TImode : DImode; 1822 1823 byte = high_p ? UNITS_PER_WORD : 0; 1824 1825 if (FP_REG_RTX_P (op)) 1826 return gen_rtx_REG (word_mode, REGNO (op) + high_p); 1827 1828 if (MEM_P (op)) 1829 return adjust_address (op, word_mode, byte); 1830 1831 return simplify_gen_subreg (word_mode, op, mode, byte); 1832 } 1833 1834 /* Return true if a 64-bit move from SRC to DEST should be split into two. */ 1835 1836 bool 1837 riscv_split_64bit_move_p (rtx dest, rtx src) 1838 { 1839 /* All 64b moves are legal in 64b mode. All 64b FPR <-> FPR and 1840 FPR <-> MEM moves are legal in 32b mode, too. Although 1841 FPR <-> GPR moves are not available in general in 32b mode, 1842 we can at least load 0 into an FPR with fcvt.d.w fpr, x0. */ 1843 return !(TARGET_64BIT 1844 || (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 1845 || (FP_REG_RTX_P (dest) && MEM_P (src)) 1846 || (FP_REG_RTX_P (src) && MEM_P (dest)) 1847 || (FP_REG_RTX_P(dest) && src == CONST0_RTX(GET_MODE(src)))); 1848 } 1849 1850 /* Split a doubleword move from SRC to DEST. On 32-bit targets, 1851 this function handles 64-bit moves for which riscv_split_64bit_move_p 1852 holds. For 64-bit targets, this function handles 128-bit moves. */ 1853 1854 void 1855 riscv_split_doubleword_move (rtx dest, rtx src) 1856 { 1857 rtx low_dest; 1858 1859 /* The operation can be split into two normal moves. Decide in 1860 which order to do them. */ 1861 low_dest = riscv_subword (dest, false); 1862 if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) 1863 { 1864 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1865 riscv_emit_move (low_dest, riscv_subword (src, false)); 1866 } 1867 else 1868 { 1869 riscv_emit_move (low_dest, riscv_subword (src, false)); 1870 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1871 } 1872 } 1873 1874 /* Return the appropriate instructions to move SRC into DEST. Assume 1875 that SRC is operand 1 and DEST is operand 0. */ 1876 1877 const char * 1878 riscv_output_move (rtx dest, rtx src) 1879 { 1880 enum rtx_code dest_code, src_code; 1881 enum machine_mode mode; 1882 bool dbl_p; 1883 1884 dest_code = GET_CODE (dest); 1885 src_code = GET_CODE (src); 1886 mode = GET_MODE (dest); 1887 dbl_p = (GET_MODE_SIZE (mode) == 8); 1888 1889 if (dbl_p && riscv_split_64bit_move_p (dest, src)) 1890 return "#"; 1891 1892 if ((src_code == REG && GP_REG_P (REGNO (src))) 1893 || (src == CONST0_RTX (mode))) 1894 { 1895 if (dest_code == REG) 1896 { 1897 if (GP_REG_P (REGNO (dest))) 1898 return "move\t%0,%z1"; 1899 1900 if (FP_REG_P (REGNO (dest))) 1901 { 1902 if (!dbl_p) 1903 return "fmv.s.x\t%0,%z1"; 1904 if (TARGET_64BIT) 1905 return "fmv.d.x\t%0,%z1"; 1906 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ 1907 gcc_assert (src == CONST0_RTX (mode)); 1908 return "fcvt.d.w\t%0,x0"; 1909 } 1910 } 1911 if (dest_code == MEM) 1912 switch (GET_MODE_SIZE (mode)) 1913 { 1914 case 1: return "sb\t%z1,%0"; 1915 case 2: return "sh\t%z1,%0"; 1916 case 4: return "sw\t%z1,%0"; 1917 case 8: return "sd\t%z1,%0"; 1918 } 1919 } 1920 if (dest_code == REG && GP_REG_P (REGNO (dest))) 1921 { 1922 if (src_code == REG) 1923 { 1924 if (FP_REG_P (REGNO (src))) 1925 return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1"; 1926 } 1927 1928 if (src_code == MEM) 1929 switch (GET_MODE_SIZE (mode)) 1930 { 1931 case 1: return "lbu\t%0,%1"; 1932 case 2: return "lhu\t%0,%1"; 1933 case 4: return "lw\t%0,%1"; 1934 case 8: return "ld\t%0,%1"; 1935 } 1936 1937 if (src_code == CONST_INT) 1938 return "li\t%0,%1"; 1939 1940 if (src_code == HIGH) 1941 return "lui\t%0,%h1"; 1942 1943 if (symbolic_operand (src, VOIDmode)) 1944 { 1945 if (SYMBOL_REF_LOCAL_P (src) 1946 || (src_code == LABEL_REF && !LABEL_REF_NONLOCAL_P (src))) 1947 return "lla\t%0,%1"; 1948 return "la\t%0,%1"; 1949 } 1950 } 1951 if (src_code == REG && FP_REG_P (REGNO (src))) 1952 { 1953 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1954 return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1"; 1955 1956 if (dest_code == MEM) 1957 return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0"; 1958 } 1959 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1960 { 1961 if (src_code == MEM) 1962 return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1"; 1963 } 1964 gcc_unreachable (); 1965 } 1966 1967 /* Return true if CMP1 is a suitable second operand for integer ordering 1968 test CODE. See also the *sCC patterns in riscv.md. */ 1969 1970 static bool 1971 riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) 1972 { 1973 switch (code) 1974 { 1975 case GT: 1976 case GTU: 1977 return reg_or_0_operand (cmp1, VOIDmode); 1978 1979 case GE: 1980 case GEU: 1981 return cmp1 == const1_rtx; 1982 1983 case LT: 1984 case LTU: 1985 return arith_operand (cmp1, VOIDmode); 1986 1987 case LE: 1988 return sle_operand (cmp1, VOIDmode); 1989 1990 case LEU: 1991 return sleu_operand (cmp1, VOIDmode); 1992 1993 default: 1994 gcc_unreachable (); 1995 } 1996 } 1997 1998 /* Return true if *CMP1 (of mode MODE) is a valid second operand for 1999 integer ordering test *CODE, or if an equivalent combination can 2000 be formed by adjusting *CODE and *CMP1. When returning true, update 2001 *CODE and *CMP1 with the chosen code and operand, otherwise leave 2002 them alone. */ 2003 2004 static bool 2005 riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, 2006 enum machine_mode mode) 2007 { 2008 HOST_WIDE_INT plus_one; 2009 2010 if (riscv_int_order_operand_ok_p (*code, *cmp1)) 2011 return true; 2012 2013 if (CONST_INT_P (*cmp1)) 2014 switch (*code) 2015 { 2016 case LE: 2017 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2018 if (INTVAL (*cmp1) < plus_one) 2019 { 2020 *code = LT; 2021 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2022 return true; 2023 } 2024 break; 2025 2026 case LEU: 2027 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2028 if (plus_one != 0) 2029 { 2030 *code = LTU; 2031 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2032 return true; 2033 } 2034 break; 2035 2036 default: 2037 break; 2038 } 2039 return false; 2040 } 2041 2042 /* Compare CMP0 and CMP1 using ordering test CODE and store the result 2043 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR 2044 is nonnull, it's OK to set TARGET to the inverse of the result and 2045 flip *INVERT_PTR instead. */ 2046 2047 static void 2048 riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr, 2049 rtx target, rtx cmp0, rtx cmp1) 2050 { 2051 enum machine_mode mode; 2052 2053 /* First see if there is a RISCV instruction that can do this operation. 2054 If not, try doing the same for the inverse operation. If that also 2055 fails, force CMP1 into a register and try again. */ 2056 mode = GET_MODE (cmp0); 2057 if (riscv_canonicalize_int_order_test (&code, &cmp1, mode)) 2058 riscv_emit_binary (code, target, cmp0, cmp1); 2059 else 2060 { 2061 enum rtx_code inv_code = reverse_condition (code); 2062 if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode)) 2063 { 2064 cmp1 = force_reg (mode, cmp1); 2065 riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); 2066 } 2067 else if (invert_ptr == 0) 2068 { 2069 rtx inv_target; 2070 2071 inv_target = riscv_force_binary (GET_MODE (target), 2072 inv_code, cmp0, cmp1); 2073 riscv_emit_binary (XOR, target, inv_target, const1_rtx); 2074 } 2075 else 2076 { 2077 *invert_ptr = !*invert_ptr; 2078 riscv_emit_binary (inv_code, target, cmp0, cmp1); 2079 } 2080 } 2081 } 2082 2083 /* Return a register that is zero iff CMP0 and CMP1 are equal. 2084 The register will have the same mode as CMP0. */ 2085 2086 static rtx 2087 riscv_zero_if_equal (rtx cmp0, rtx cmp1) 2088 { 2089 if (cmp1 == const0_rtx) 2090 return cmp0; 2091 2092 return expand_binop (GET_MODE (cmp0), sub_optab, 2093 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 2094 } 2095 2096 /* Return false if we can easily emit code for the FP comparison specified 2097 by *CODE. If not, set *CODE to its inverse and return true. */ 2098 2099 static bool 2100 riscv_reversed_fp_cond (enum rtx_code *code) 2101 { 2102 switch (*code) 2103 { 2104 case EQ: 2105 case LT: 2106 case LE: 2107 case GT: 2108 case GE: 2109 case LTGT: 2110 case ORDERED: 2111 /* We know how to emit code for these cases... */ 2112 return false; 2113 2114 default: 2115 /* ...but we must invert these and rely on the others. */ 2116 *code = reverse_condition_maybe_unordered (*code); 2117 return true; 2118 } 2119 } 2120 2121 /* Convert a comparison into something that can be used in a branch or 2122 conditional move. On entry, *OP0 and *OP1 are the values being 2123 compared and *CODE is the code used to compare them. 2124 2125 Update *CODE, *OP0 and *OP1 so that they describe the final comparison. */ 2126 2127 static void 2128 riscv_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2129 { 2130 rtx cmp_op0 = *op0; 2131 rtx cmp_op1 = *op1; 2132 2133 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) 2134 { 2135 if (*op1 == const0_rtx) 2136 ; 2137 else if ((*code == EQ || *code == NE) && CONST_INT_P (cmp_op1) 2138 && SMALL_OPERAND (-INTVAL (cmp_op1))) 2139 { 2140 *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); 2141 riscv_emit_binary (PLUS, *op0, cmp_op0, GEN_INT (-INTVAL (cmp_op1))); 2142 *op1 = const0_rtx; 2143 } 2144 else if (*op1 != const0_rtx) 2145 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); 2146 } 2147 else 2148 { 2149 /* For FP comparisons, set an integer register with the result of the 2150 comparison, then branch on it. */ 2151 rtx tmp0, tmp1, final_op; 2152 enum rtx_code fp_code = *code; 2153 *code = riscv_reversed_fp_cond (&fp_code) ? EQ : NE; 2154 2155 switch (fp_code) 2156 { 2157 case ORDERED: 2158 /* a == a && b == b */ 2159 tmp0 = gen_reg_rtx (SImode); 2160 riscv_emit_binary (EQ, tmp0, cmp_op0, cmp_op0); 2161 tmp1 = gen_reg_rtx (SImode); 2162 riscv_emit_binary (EQ, tmp1, cmp_op1, cmp_op1); 2163 final_op = gen_reg_rtx (SImode); 2164 riscv_emit_binary (AND, final_op, tmp0, tmp1); 2165 break; 2166 2167 case LTGT: 2168 /* a < b || a > b */ 2169 tmp0 = gen_reg_rtx (SImode); 2170 riscv_emit_binary (LT, tmp0, cmp_op0, cmp_op1); 2171 tmp1 = gen_reg_rtx (SImode); 2172 riscv_emit_binary (GT, tmp1, cmp_op0, cmp_op1); 2173 final_op = gen_reg_rtx (SImode); 2174 riscv_emit_binary (IOR, final_op, tmp0, tmp1); 2175 break; 2176 2177 case EQ: 2178 case LE: 2179 case LT: 2180 case GE: 2181 case GT: 2182 /* We have instructions for these cases. */ 2183 final_op = gen_reg_rtx (SImode); 2184 riscv_emit_binary (fp_code, final_op, cmp_op0, cmp_op1); 2185 break; 2186 2187 default: 2188 gcc_unreachable (); 2189 } 2190 2191 /* Compare the binary result against 0. */ 2192 *op0 = final_op; 2193 *op1 = const0_rtx; 2194 } 2195 } 2196 2197 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] 2198 and OPERAND[3]. Store the result in OPERANDS[0]. 2199 2200 On 64-bit targets, the mode of the comparison and target will always be 2201 SImode, thus possibly narrower than that of the comparison's operands. */ 2202 2203 void 2204 riscv_expand_scc (rtx operands[]) 2205 { 2206 rtx target = operands[0]; 2207 enum rtx_code code = GET_CODE (operands[1]); 2208 rtx op0 = operands[2]; 2209 rtx op1 = operands[3]; 2210 2211 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); 2212 2213 if (code == EQ || code == NE) 2214 { 2215 rtx zie = riscv_zero_if_equal (op0, op1); 2216 riscv_emit_binary (code, target, zie, const0_rtx); 2217 } 2218 else 2219 riscv_emit_int_order_test (code, 0, target, op0, op1); 2220 } 2221 2222 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code 2223 CODE and jump to OPERANDS[3] if the condition holds. */ 2224 2225 void 2226 riscv_expand_conditional_branch (rtx *operands) 2227 { 2228 enum rtx_code code = GET_CODE (operands[0]); 2229 rtx op0 = operands[1]; 2230 rtx op1 = operands[2]; 2231 rtx condition; 2232 2233 riscv_emit_compare (&code, &op0, &op1); 2234 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 2235 emit_jump_insn (gen_condjump (condition, operands[3])); 2236 } 2237 2238 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 2239 least PARM_BOUNDARY bits of alignment, but will be given anything up 2240 to STACK_BOUNDARY bits if the type requires it. */ 2241 2242 static unsigned int 2243 riscv_function_arg_boundary (enum machine_mode mode, const_tree type) 2244 { 2245 unsigned int alignment; 2246 2247 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 2248 if (alignment < PARM_BOUNDARY) 2249 alignment = PARM_BOUNDARY; 2250 if (alignment > STACK_BOUNDARY) 2251 alignment = STACK_BOUNDARY; 2252 return alignment; 2253 } 2254 2255 /* Fill INFO with information about a single argument. CUM is the 2256 cumulative state for earlier arguments. MODE is the mode of this 2257 argument and TYPE is its type (if known). NAMED is true if this 2258 is a named (fixed) argument rather than a variable one. */ 2259 2260 static void 2261 riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, 2262 enum machine_mode mode, const_tree type, bool named) 2263 { 2264 bool doubleword_aligned_p; 2265 unsigned int num_bytes, num_words, max_regs; 2266 2267 /* Work out the size of the argument. */ 2268 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 2269 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2270 2271 /* Scalar, complex and vector floating-point types are passed in 2272 floating-point registers, as long as this is a named rather 2273 than a variable argument. */ 2274 info->fpr_p = (named 2275 && (type == 0 || FLOAT_TYPE_P (type)) 2276 && (GET_MODE_CLASS (mode) == MODE_FLOAT 2277 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 2278 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) 2279 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); 2280 2281 /* Complex floats should only go into FPRs if there are two FPRs free, 2282 otherwise they should be passed in the same way as a struct 2283 containing two floats. */ 2284 if (info->fpr_p 2285 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 2286 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) 2287 { 2288 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) 2289 info->fpr_p = false; 2290 else 2291 num_words = 2; 2292 } 2293 2294 /* See whether the argument has doubleword alignment. */ 2295 doubleword_aligned_p = (riscv_function_arg_boundary (mode, type) 2296 > BITS_PER_WORD); 2297 2298 /* Set REG_OFFSET to the register count we're interested in. 2299 The EABI allocates the floating-point registers separately, 2300 but the other ABIs allocate them like integer registers. */ 2301 info->reg_offset = cum->num_gprs; 2302 2303 /* Advance to an even register if the argument is doubleword-aligned. */ 2304 if (doubleword_aligned_p) 2305 info->reg_offset += info->reg_offset & 1; 2306 2307 /* Work out the offset of a stack argument. */ 2308 info->stack_offset = cum->stack_words; 2309 if (doubleword_aligned_p) 2310 info->stack_offset += info->stack_offset & 1; 2311 2312 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; 2313 2314 /* Partition the argument between registers and stack. */ 2315 info->reg_words = MIN (num_words, max_regs); 2316 info->stack_words = num_words - info->reg_words; 2317 } 2318 2319 /* INFO describes a register argument that has the normal format for the 2320 argument's mode. Return the register it uses, assuming that FPRs are 2321 available if HARD_FLOAT_P. */ 2322 2323 static unsigned int 2324 riscv_arg_regno (const struct riscv_arg_info *info, bool hard_float_p) 2325 { 2326 if (!info->fpr_p || !hard_float_p) 2327 return GP_ARG_FIRST + info->reg_offset; 2328 else 2329 return FP_ARG_FIRST + info->reg_offset; 2330 } 2331 2332 /* Implement TARGET_FUNCTION_ARG. */ 2333 2334 static rtx 2335 riscv_function_arg (cumulative_args_t cum_v, enum machine_mode mode, 2336 const_tree type, bool named) 2337 { 2338 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2339 struct riscv_arg_info info; 2340 2341 if (mode == VOIDmode) 2342 return NULL; 2343 2344 riscv_get_arg_info (&info, cum, mode, type, named); 2345 2346 /* Return straight away if the whole argument is passed on the stack. */ 2347 if (info.reg_offset == MAX_ARGS_IN_REGISTERS) 2348 return NULL; 2349 2350 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure 2351 contains a double in its entirety, then that 64-bit chunk is passed 2352 in a floating-point register. */ 2353 if (TARGET_HARD_FLOAT 2354 && named 2355 && type != 0 2356 && TREE_CODE (type) == RECORD_TYPE 2357 && TYPE_SIZE_UNIT (type) 2358 && host_integerp (TYPE_SIZE_UNIT (type), 1)) 2359 //&& tree_fits_uhwi_p (TYPE_SIZE_UNIT (type))) 2360 { 2361 tree field; 2362 2363 /* First check to see if there is any such field. */ 2364 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) 2365 if (TREE_CODE (field) == FIELD_DECL 2366 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) 2367 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD 2368 && host_integerp (bit_position (field), 0) 2369 //&& tree_fits_shwi_p (bit_position (field)) 2370 && int_bit_position (field) % BITS_PER_WORD == 0) 2371 break; 2372 2373 if (field != 0) 2374 { 2375 /* Now handle the special case by returning a PARALLEL 2376 indicating where each 64-bit chunk goes. INFO.REG_WORDS 2377 chunks are passed in registers. */ 2378 unsigned int i; 2379 HOST_WIDE_INT bitpos; 2380 rtx ret; 2381 2382 /* assign_parms checks the mode of ENTRY_PARM, so we must 2383 use the actual mode here. */ 2384 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); 2385 2386 bitpos = 0; 2387 field = TYPE_FIELDS (type); 2388 for (i = 0; i < info.reg_words; i++) 2389 { 2390 rtx reg; 2391 2392 for (; field; field = DECL_CHAIN (field)) 2393 if (TREE_CODE (field) == FIELD_DECL 2394 && int_bit_position (field) >= bitpos) 2395 break; 2396 2397 if (field 2398 && int_bit_position (field) == bitpos 2399 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) 2400 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) 2401 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); 2402 else 2403 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); 2404 2405 XVECEXP (ret, 0, i) 2406 = gen_rtx_EXPR_LIST (VOIDmode, reg, 2407 GEN_INT (bitpos / BITS_PER_UNIT)); 2408 2409 bitpos += BITS_PER_WORD; 2410 } 2411 return ret; 2412 } 2413 } 2414 2415 /* Handle the n32/n64 conventions for passing complex floating-point 2416 arguments in FPR pairs. The real part goes in the lower register 2417 and the imaginary part goes in the upper register. */ 2418 if (info.fpr_p 2419 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2420 { 2421 rtx real, imag; 2422 enum machine_mode inner; 2423 unsigned int regno; 2424 2425 inner = GET_MODE_INNER (mode); 2426 regno = FP_ARG_FIRST + info.reg_offset; 2427 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) 2428 { 2429 /* Real part in registers, imaginary part on stack. */ 2430 gcc_assert (info.stack_words == info.reg_words); 2431 return gen_rtx_REG (inner, regno); 2432 } 2433 else 2434 { 2435 gcc_assert (info.stack_words == 0); 2436 real = gen_rtx_EXPR_LIST (VOIDmode, 2437 gen_rtx_REG (inner, regno), 2438 const0_rtx); 2439 imag = gen_rtx_EXPR_LIST (VOIDmode, 2440 gen_rtx_REG (inner, 2441 regno + info.reg_words / 2), 2442 GEN_INT (GET_MODE_SIZE (inner))); 2443 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); 2444 } 2445 } 2446 2447 return gen_rtx_REG (mode, riscv_arg_regno (&info, TARGET_HARD_FLOAT)); 2448 } 2449 2450 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 2451 2452 static void 2453 riscv_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, 2454 const_tree type, bool named) 2455 { 2456 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2457 struct riscv_arg_info info; 2458 2459 riscv_get_arg_info (&info, cum, mode, type, named); 2460 2461 /* Advance the register count. This has the effect of setting 2462 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 2463 argument required us to skip the final GPR and pass the whole 2464 argument on the stack. */ 2465 cum->num_gprs = info.reg_offset + info.reg_words; 2466 2467 /* Advance the stack word count. */ 2468 if (info.stack_words > 0) 2469 cum->stack_words = info.stack_offset + info.stack_words; 2470 } 2471 2472 /* Implement TARGET_ARG_PARTIAL_BYTES. */ 2473 2474 static int 2475 riscv_arg_partial_bytes (cumulative_args_t cum, 2476 enum machine_mode mode, tree type, bool named) 2477 { 2478 struct riscv_arg_info info; 2479 2480 riscv_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); 2481 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; 2482 } 2483 2484 /* See whether VALTYPE is a record whose fields should be returned in 2485 floating-point registers. If so, return the number of fields and 2486 list them in FIELDS (which should have two elements). Return 0 2487 otherwise. 2488 2489 For n32 & n64, a structure with one or two fields is returned in 2490 floating-point registers as long as every field has a floating-point 2491 type. */ 2492 2493 static int 2494 riscv_fpr_return_fields (const_tree valtype, tree *fields) 2495 { 2496 tree field; 2497 int i; 2498 2499 if (TREE_CODE (valtype) != RECORD_TYPE) 2500 return 0; 2501 2502 i = 0; 2503 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) 2504 { 2505 if (TREE_CODE (field) != FIELD_DECL) 2506 continue; 2507 2508 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) 2509 return 0; 2510 2511 if (i == 2) 2512 return 0; 2513 2514 fields[i++] = field; 2515 } 2516 return i; 2517 } 2518 2519 /* Return true if the function return value MODE will get returned in a 2520 floating-point register. */ 2521 2522 static bool 2523 riscv_return_mode_in_fpr_p (enum machine_mode mode) 2524 { 2525 return ((GET_MODE_CLASS (mode) == MODE_FLOAT 2526 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT 2527 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2528 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); 2529 } 2530 2531 /* Return the representation of an FPR return register when the 2532 value being returned in FP_RETURN has mode VALUE_MODE and the 2533 return type itself has mode TYPE_MODE. On NewABI targets, 2534 the two modes may be different for structures like: 2535 2536 struct __attribute__((packed)) foo { float f; } 2537 2538 where we return the SFmode value of "f" in FP_RETURN, but where 2539 the structure itself has mode BLKmode. */ 2540 2541 static rtx 2542 riscv_return_fpr_single (enum machine_mode type_mode, 2543 enum machine_mode value_mode) 2544 { 2545 rtx x; 2546 2547 x = gen_rtx_REG (value_mode, FP_RETURN); 2548 if (type_mode != value_mode) 2549 { 2550 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); 2551 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); 2552 } 2553 return x; 2554 } 2555 2556 /* Return a composite value in a pair of floating-point registers. 2557 MODE1 and OFFSET1 are the mode and byte offset for the first value, 2558 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the 2559 complete value. 2560 2561 For n32 & n64, $f0 always holds the first value and $f2 the second. 2562 Otherwise the values are packed together as closely as possible. */ 2563 2564 static rtx 2565 riscv_return_fpr_pair (enum machine_mode mode, 2566 enum machine_mode mode1, HOST_WIDE_INT offset1, 2567 enum machine_mode mode2, HOST_WIDE_INT offset2) 2568 { 2569 return gen_rtx_PARALLEL 2570 (mode, 2571 gen_rtvec (2, 2572 gen_rtx_EXPR_LIST (VOIDmode, 2573 gen_rtx_REG (mode1, FP_RETURN), 2574 GEN_INT (offset1)), 2575 gen_rtx_EXPR_LIST (VOIDmode, 2576 gen_rtx_REG (mode2, FP_RETURN + 1), 2577 GEN_INT (offset2)))); 2578 2579 } 2580 2581 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 2582 VALTYPE is the return type and MODE is VOIDmode. For libcalls, 2583 VALTYPE is null and MODE is the mode of the return value. */ 2584 2585 rtx 2586 riscv_function_value (const_tree valtype, const_tree func, enum machine_mode mode) 2587 { 2588 if (valtype) 2589 { 2590 tree fields[2]; 2591 int unsigned_p; 2592 2593 mode = TYPE_MODE (valtype); 2594 unsigned_p = TYPE_UNSIGNED (valtype); 2595 2596 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, 2597 return values, promote the mode here too. */ 2598 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); 2599 2600 /* Handle structures whose fields are returned in $f0/$f2. */ 2601 switch (riscv_fpr_return_fields (valtype, fields)) 2602 { 2603 case 1: 2604 return riscv_return_fpr_single (mode, 2605 TYPE_MODE (TREE_TYPE (fields[0]))); 2606 2607 case 2: 2608 return riscv_return_fpr_pair (mode, 2609 TYPE_MODE (TREE_TYPE (fields[0])), 2610 int_byte_position (fields[0]), 2611 TYPE_MODE (TREE_TYPE (fields[1])), 2612 int_byte_position (fields[1])); 2613 } 2614 2615 /* Only use FPRs for scalar, complex or vector types. */ 2616 if (!FLOAT_TYPE_P (valtype)) 2617 return gen_rtx_REG (mode, GP_RETURN); 2618 } 2619 2620 /* Handle long doubles for n32 & n64. */ 2621 if (mode == TFmode) 2622 return riscv_return_fpr_pair (mode, 2623 DImode, 0, 2624 DImode, GET_MODE_SIZE (mode) / 2); 2625 2626 if (riscv_return_mode_in_fpr_p (mode)) 2627 { 2628 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2629 return riscv_return_fpr_pair (mode, 2630 GET_MODE_INNER (mode), 0, 2631 GET_MODE_INNER (mode), 2632 GET_MODE_SIZE (mode) / 2); 2633 else 2634 return gen_rtx_REG (mode, FP_RETURN); 2635 } 2636 2637 return gen_rtx_REG (mode, GP_RETURN); 2638 } 2639 2640 /* Implement TARGET_RETURN_IN_MEMORY. Scalars and small structures 2641 that fit in two registers are returned in v0/v1. */ 2642 2643 static bool 2644 riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) 2645 { 2646 return !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD); 2647 } 2648 2649 /* Implement TARGET_PASS_BY_REFERENCE. */ 2650 2651 static bool 2652 riscv_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, 2653 enum machine_mode mode, const_tree type, 2654 bool named ATTRIBUTE_UNUSED) 2655 { 2656 if (type && riscv_return_in_memory (type, NULL_TREE)) 2657 return true; 2658 return targetm.calls.must_pass_in_stack (mode, type); 2659 } 2660 2661 /* Implement TARGET_SETUP_INCOMING_VARARGS. */ 2662 2663 static void 2664 riscv_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, 2665 tree type, int *pretend_size ATTRIBUTE_UNUSED, 2666 int no_rtl) 2667 { 2668 CUMULATIVE_ARGS local_cum; 2669 int gp_saved; 2670 2671 /* The caller has advanced CUM up to, but not beyond, the last named 2672 argument. Advance a local copy of CUM past the last "real" named 2673 argument, to find out how many registers are left over. */ 2674 local_cum = *get_cumulative_args (cum); 2675 riscv_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, 1); 2676 2677 /* Found out how many registers we need to save. */ 2678 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 2679 2680 if (!no_rtl && gp_saved > 0) 2681 { 2682 rtx ptr, mem; 2683 2684 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, 2685 REG_PARM_STACK_SPACE (cfun->decl) 2686 - gp_saved * UNITS_PER_WORD); 2687 mem = gen_frame_mem (BLKmode, ptr); 2688 set_mem_alias_set (mem, get_varargs_alias_set ()); 2689 2690 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 2691 mem, gp_saved); 2692 } 2693 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 2694 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD; 2695 } 2696 2697 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ 2698 2699 static void 2700 riscv_va_start (tree valist, rtx nextarg) 2701 { 2702 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); 2703 std_expand_builtin_va_start (valist, nextarg); 2704 } 2705 2706 /* Expand a call of type TYPE. RESULT is where the result will go (null 2707 for "call"s and "sibcall"s), ADDR is the address of the function, 2708 ARGS_SIZE is the size of the arguments and AUX is the value passed 2709 to us by riscv_function_arg. Return the call itself. */ 2710 2711 rtx 2712 riscv_expand_call (bool sibcall_p, rtx result, rtx addr, rtx args_size) 2713 { 2714 rtx pattern; 2715 2716 if (!call_insn_operand (addr, VOIDmode)) 2717 { 2718 rtx reg = RISCV_EPILOGUE_TEMP (Pmode); 2719 riscv_emit_move (reg, addr); 2720 addr = reg; 2721 } 2722 2723 if (result == 0) 2724 { 2725 rtx (*fn) (rtx, rtx); 2726 2727 if (sibcall_p) 2728 fn = gen_sibcall_internal; 2729 else 2730 fn = gen_call_internal; 2731 2732 pattern = fn (addr, args_size); 2733 } 2734 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) 2735 { 2736 /* Handle return values created by riscv_return_fpr_pair. */ 2737 rtx (*fn) (rtx, rtx, rtx, rtx); 2738 rtx reg1, reg2; 2739 2740 if (sibcall_p) 2741 fn = gen_sibcall_value_multiple_internal; 2742 else 2743 fn = gen_call_value_multiple_internal; 2744 2745 reg1 = XEXP (XVECEXP (result, 0, 0), 0); 2746 reg2 = XEXP (XVECEXP (result, 0, 1), 0); 2747 pattern = fn (reg1, addr, args_size, reg2); 2748 } 2749 else 2750 { 2751 rtx (*fn) (rtx, rtx, rtx); 2752 2753 if (sibcall_p) 2754 fn = gen_sibcall_value_internal; 2755 else 2756 fn = gen_call_value_internal; 2757 2758 /* Handle return values created by riscv_return_fpr_single. */ 2759 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) 2760 result = XEXP (XVECEXP (result, 0, 0), 0); 2761 pattern = fn (result, addr, args_size); 2762 } 2763 2764 return emit_call_insn (pattern); 2765 } 2766 2767 /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 2768 Assume that the areas do not overlap. */ 2769 2770 static void 2771 riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) 2772 { 2773 HOST_WIDE_INT offset, delta; 2774 unsigned HOST_WIDE_INT bits; 2775 int i; 2776 enum machine_mode mode; 2777 rtx *regs; 2778 2779 bits = MAX( BITS_PER_UNIT, 2780 MIN( BITS_PER_WORD, MIN( MEM_ALIGN(src),MEM_ALIGN(dest) ) ) ); 2781 2782 mode = mode_for_size (bits, MODE_INT, 0); 2783 delta = bits / BITS_PER_UNIT; 2784 2785 /* Allocate a buffer for the temporary registers. */ 2786 regs = XALLOCAVEC (rtx, length / delta); 2787 2788 /* Load as many BITS-sized chunks as possible. Use a normal load if 2789 the source has enough alignment, otherwise use left/right pairs. */ 2790 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 2791 { 2792 regs[i] = gen_reg_rtx (mode); 2793 riscv_emit_move (regs[i], adjust_address (src, mode, offset)); 2794 } 2795 2796 /* Copy the chunks to the destination. */ 2797 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 2798 riscv_emit_move (adjust_address (dest, mode, offset), regs[i]); 2799 2800 /* Mop up any left-over bytes. */ 2801 if (offset < length) 2802 { 2803 src = adjust_address (src, BLKmode, offset); 2804 dest = adjust_address (dest, BLKmode, offset); 2805 move_by_pieces (dest, src, length - offset, 2806 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); 2807 } 2808 } 2809 2810 /* Helper function for doing a loop-based block operation on memory 2811 reference MEM. Each iteration of the loop will operate on LENGTH 2812 bytes of MEM. 2813 2814 Create a new base register for use within the loop and point it to 2815 the start of MEM. Create a new memory reference that uses this 2816 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 2817 2818 static void 2819 riscv_adjust_block_mem (rtx mem, HOST_WIDE_INT length, 2820 rtx *loop_reg, rtx *loop_mem) 2821 { 2822 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 2823 2824 /* Although the new mem does not refer to a known location, 2825 it does keep up to LENGTH bytes of alignment. */ 2826 *loop_mem = change_address (mem, BLKmode, *loop_reg); 2827 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 2828 } 2829 2830 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER 2831 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that 2832 the memory regions do not overlap. */ 2833 2834 static void 2835 riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, 2836 HOST_WIDE_INT bytes_per_iter) 2837 { 2838 rtx label, src_reg, dest_reg, final_src, test; 2839 HOST_WIDE_INT leftover; 2840 2841 leftover = length % bytes_per_iter; 2842 length -= leftover; 2843 2844 /* Create registers and memory references for use within the loop. */ 2845 riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); 2846 riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); 2847 2848 /* Calculate the value that SRC_REG should have after the last iteration 2849 of the loop. */ 2850 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 2851 0, 0, OPTAB_WIDEN); 2852 2853 /* Emit the start of the loop. */ 2854 label = gen_label_rtx (); 2855 emit_label (label); 2856 2857 /* Emit the loop body. */ 2858 riscv_block_move_straight (dest, src, bytes_per_iter); 2859 2860 /* Move on to the next block. */ 2861 riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); 2862 riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); 2863 2864 /* Emit the loop condition. */ 2865 test = gen_rtx_NE (VOIDmode, src_reg, final_src); 2866 if (Pmode == DImode) 2867 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); 2868 else 2869 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); 2870 2871 /* Mop up any left-over bytes. */ 2872 if (leftover) 2873 riscv_block_move_straight (dest, src, leftover); 2874 } 2875 2876 /* Expand a movmemsi instruction, which copies LENGTH bytes from 2877 memory reference SRC to memory reference DEST. */ 2878 2879 bool 2880 riscv_expand_block_move (rtx dest, rtx src, rtx length) 2881 { 2882 if (CONST_INT_P (length)) 2883 { 2884 HOST_WIDE_INT factor, align; 2885 2886 align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); 2887 factor = BITS_PER_WORD / align; 2888 2889 if (INTVAL (length) <= RISCV_MAX_MOVE_BYTES_STRAIGHT / factor) 2890 { 2891 riscv_block_move_straight (dest, src, INTVAL (length)); 2892 return true; 2893 } 2894 else if (optimize && align >= BITS_PER_WORD) 2895 { 2896 riscv_block_move_loop (dest, src, INTVAL (length), 2897 RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / factor); 2898 return true; 2899 } 2900 } 2901 return false; 2902 } 2903 2904 /* (Re-)Initialize riscv_lo_relocs and riscv_hi_relocs. */ 2905 2906 static void 2907 riscv_init_relocs (void) 2908 { 2909 memset (riscv_hi_relocs, '\0', sizeof (riscv_hi_relocs)); 2910 memset (riscv_lo_relocs, '\0', sizeof (riscv_lo_relocs)); 2911 2912 if (!flag_pic) 2913 { 2914 riscv_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; 2915 riscv_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; 2916 2917 riscv_hi_relocs[SYMBOL_TLS_LE] = "%tprel_hi("; 2918 riscv_lo_relocs[SYMBOL_TLS_LE] = "%tprel_lo("; 2919 2920 riscv_lo_relocs[SYMBOL_TLS_IE] = "%tls_ie_off("; 2921 } 2922 } 2923 2924 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM 2925 in context CONTEXT. RELOCS is the array of relocations to use. */ 2926 2927 static void 2928 riscv_print_operand_reloc (FILE *file, rtx op, const char **relocs) 2929 { 2930 enum riscv_symbol_type symbol_type; 2931 const char *p; 2932 2933 symbol_type = riscv_classify_symbolic_expression (op); 2934 gcc_assert (relocs[symbol_type]); 2935 2936 fputs (relocs[symbol_type], file); 2937 output_addr_const (file, riscv_strip_unspec_address (op)); 2938 for (p = relocs[symbol_type]; *p != 0; p++) 2939 if (*p == '(') 2940 fputc (')', file); 2941 } 2942 2943 static const char * 2944 riscv_memory_model_suffix (enum memmodel model) 2945 { 2946 switch (model) 2947 { 2948 case MEMMODEL_ACQ_REL: 2949 case MEMMODEL_SEQ_CST: 2950 return ".sc"; 2951 case MEMMODEL_ACQUIRE: 2952 case MEMMODEL_CONSUME: 2953 return ".aq"; 2954 case MEMMODEL_RELEASE: 2955 return ".rl"; 2956 case MEMMODEL_RELAXED: 2957 return ""; 2958 default: gcc_unreachable(); 2959 } 2960 } 2961 2962 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 2963 2964 'h' Print the high-part relocation associated with OP, after stripping 2965 any outermost HIGH. 2966 'R' Print the low-part relocation associated with OP. 2967 'C' Print the integer branch condition for comparison OP. 2968 'A' Print the atomic operation suffix for memory model OP. 2969 'z' Print $0 if OP is zero, otherwise print OP normally. */ 2970 2971 static void 2972 riscv_print_operand (FILE *file, rtx op, int letter) 2973 { 2974 enum rtx_code code; 2975 2976 gcc_assert (op); 2977 code = GET_CODE (op); 2978 2979 switch (letter) 2980 { 2981 case 'h': 2982 if (code == HIGH) 2983 op = XEXP (op, 0); 2984 riscv_print_operand_reloc (file, op, riscv_hi_relocs); 2985 break; 2986 2987 case 'R': 2988 riscv_print_operand_reloc (file, op, riscv_lo_relocs); 2989 break; 2990 2991 case 'C': 2992 /* The RTL names match the instruction names. */ 2993 fputs (GET_RTX_NAME (code), file); 2994 break; 2995 2996 case 'A': 2997 fputs (riscv_memory_model_suffix ((enum memmodel)INTVAL (op)), file); 2998 break; 2999 3000 default: 3001 switch (code) 3002 { 3003 case REG: 3004 if (letter && letter != 'z') 3005 output_operand_lossage ("invalid use of '%%%c'", letter); 3006 fprintf (file, "%s", reg_names[REGNO (op)]); 3007 break; 3008 3009 case MEM: 3010 if (letter == 'y') 3011 fprintf (file, "%s", reg_names[REGNO(XEXP(op, 0))]); 3012 else if (letter && letter != 'z') 3013 output_operand_lossage ("invalid use of '%%%c'", letter); 3014 else 3015 output_address (XEXP (op, 0)); 3016 break; 3017 3018 default: 3019 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 3020 fputs (reg_names[GP_REG_FIRST], file); 3021 else if (letter && letter != 'z') 3022 output_operand_lossage ("invalid use of '%%%c'", letter); 3023 else 3024 output_addr_const (file, riscv_strip_unspec_address (op)); 3025 break; 3026 } 3027 } 3028 } 3029 3030 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 3031 3032 static void 3033 riscv_print_operand_address (FILE *file, rtx x) 3034 { 3035 struct riscv_address_info addr; 3036 3037 if (riscv_classify_address (&addr, x, word_mode, true)) 3038 switch (addr.type) 3039 { 3040 case ADDRESS_REG: 3041 riscv_print_operand (file, addr.offset, 0); 3042 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3043 return; 3044 3045 case ADDRESS_LO_SUM: 3046 riscv_print_operand_reloc (file, addr.offset, riscv_lo_relocs); 3047 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3048 return; 3049 3050 case ADDRESS_CONST_INT: 3051 output_addr_const (file, x); 3052 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); 3053 return; 3054 3055 case ADDRESS_SYMBOLIC: 3056 output_addr_const (file, riscv_strip_unspec_address (x)); 3057 return; 3058 } 3059 gcc_unreachable (); 3060 } 3061 3062 bool 3063 riscv_size_ok_for_small_data_p (int size) 3064 { 3065 return g_switch_value && IN_RANGE (size, 1, g_switch_value); 3066 } 3067 3068 /* Return true if EXP should be placed in the small data section. */ 3069 3070 static bool 3071 riscv_in_small_data_p (const_tree x) 3072 { 3073 if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL) 3074 return false; 3075 3076 if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x)) 3077 { 3078 const char *sec = TREE_STRING_POINTER (DECL_SECTION_NAME (x)); 3079 return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0; 3080 } 3081 3082 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x))); 3083 } 3084 3085 /* Return a section for X, handling small data. */ 3086 3087 static section * 3088 riscv_elf_select_rtx_section (enum machine_mode mode, rtx x, 3089 unsigned HOST_WIDE_INT align) 3090 { 3091 section *s = default_elf_select_rtx_section (mode, x, align); 3092 3093 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode))) 3094 { 3095 if (strncmp (s->named.name, ".rodata.cst", strlen (".rodata.cst")) == 0) 3096 { 3097 /* Rename .rodata.cst* to .srodata.cst*. */ 3098 char name[32]; 3099 sprintf (name, ".s%s", s->named.name + 1); 3100 return get_section (name, s->named.common.flags, NULL); 3101 } 3102 3103 if (s == data_section) 3104 return sdata_section; 3105 } 3106 3107 return s; 3108 } 3109 3110 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ 3111 3112 static void ATTRIBUTE_UNUSED 3113 riscv_output_dwarf_dtprel (FILE *file, int size, rtx x) 3114 { 3115 switch (size) 3116 { 3117 case 4: 3118 fputs ("\t.dtprelword\t", file); 3119 break; 3120 3121 case 8: 3122 fputs ("\t.dtpreldword\t", file); 3123 break; 3124 3125 default: 3126 gcc_unreachable (); 3127 } 3128 output_addr_const (file, x); 3129 fputs ("+0x8000", file); 3130 } 3131 3132 /* Make the last instruction frame-related and note that it performs 3133 the operation described by FRAME_PATTERN. */ 3134 3135 static void 3136 riscv_set_frame_expr (rtx frame_pattern) 3137 { 3138 rtx insn; 3139 3140 insn = get_last_insn (); 3141 RTX_FRAME_RELATED_P (insn) = 1; 3142 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3143 frame_pattern, 3144 REG_NOTES (insn)); 3145 } 3146 3147 /* Return a frame-related rtx that stores REG at MEM. 3148 REG must be a single register. */ 3149 3150 static rtx 3151 riscv_frame_set (rtx mem, rtx reg) 3152 { 3153 rtx set; 3154 3155 set = gen_rtx_SET (VOIDmode, mem, reg); 3156 RTX_FRAME_RELATED_P (set) = 1; 3157 3158 return set; 3159 } 3160 3161 /* Return true if the current function must save register REGNO. */ 3162 3163 static bool 3164 riscv_save_reg_p (unsigned int regno) 3165 { 3166 bool call_saved = !global_regs[regno] && !call_really_used_regs[regno]; 3167 bool might_clobber = crtl->saves_all_registers 3168 || df_regs_ever_live_p (regno) 3169 || (regno == HARD_FRAME_POINTER_REGNUM 3170 && frame_pointer_needed); 3171 3172 return (call_saved && might_clobber) 3173 || (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return); 3174 } 3175 3176 /* Populate the current function's riscv_frame_info structure. 3177 3178 RISC-V stack frames grown downward. High addresses are at the top. 3179 3180 +-------------------------------+ 3181 | | 3182 | incoming stack arguments | 3183 | | 3184 +-------------------------------+ 3185 | | 3186 | caller-allocated save area | 3187 A | for register arguments | 3188 | | 3189 +-------------------------------+ <-- incoming stack pointer 3190 | | 3191 | callee-allocated save area | 3192 B | for arguments that are | 3193 | split between registers and | 3194 | the stack | 3195 | | 3196 +-------------------------------+ <-- arg_pointer_rtx 3197 | | 3198 C | callee-allocated save area | 3199 | for register varargs | 3200 | | 3201 +-------------------------------+ <-- hard_frame_pointer_rtx; 3202 | | stack_pointer_rtx + gp_sp_offset 3203 | GPR save area | + UNITS_PER_WORD 3204 | | 3205 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset 3206 | | + UNITS_PER_HWVALUE 3207 | FPR save area | 3208 | | 3209 +-------------------------------+ <-- frame_pointer_rtx (virtual) 3210 | | 3211 | local variables | 3212 | | 3213 P +-------------------------------+ 3214 | | 3215 | outgoing stack arguments | 3216 | | 3217 +-------------------------------+ 3218 | | 3219 | caller-allocated save area | 3220 | for register arguments | 3221 | | 3222 +-------------------------------+ <-- stack_pointer_rtx 3223 3224 At least two of A, B and C will be empty. 3225 3226 Dynamic stack allocations such as alloca insert data at point P. 3227 They decrease stack_pointer_rtx but leave frame_pointer_rtx and 3228 hard_frame_pointer_rtx unchanged. */ 3229 3230 static void 3231 riscv_compute_frame_info (void) 3232 { 3233 struct riscv_frame_info *frame; 3234 HOST_WIDE_INT offset; 3235 unsigned int regno, i; 3236 3237 frame = &cfun->machine->frame; 3238 memset (frame, 0, sizeof (*frame)); 3239 3240 /* Find out which GPRs we need to save. */ 3241 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3242 if (riscv_save_reg_p (regno)) 3243 frame->mask |= 1 << (regno - GP_REG_FIRST); 3244 3245 /* If this function calls eh_return, we must also save and restore the 3246 EH data registers. */ 3247 if (crtl->calls_eh_return) 3248 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) 3249 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); 3250 3251 /* Find out which FPRs we need to save. This loop must iterate over 3252 the same space as its companion in riscv_for_each_saved_gpr_and_fpr. */ 3253 if (TARGET_HARD_FLOAT) 3254 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3255 if (riscv_save_reg_p (regno)) 3256 frame->fmask |= 1 << (regno - FP_REG_FIRST); 3257 3258 /* At the bottom of the frame are any outgoing stack arguments. */ 3259 offset = crtl->outgoing_args_size; 3260 /* Next are local stack variables. */ 3261 offset += RISCV_STACK_ALIGN (get_frame_size ()); 3262 /* The virtual frame pointer points above the local variables. */ 3263 frame->frame_pointer_offset = offset; 3264 /* Next are the callee-saved FPRs. */ 3265 if (frame->fmask) 3266 { 3267 unsigned num_saved = __builtin_popcount(frame->fmask); 3268 offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_FPREG); 3269 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; 3270 } 3271 /* Next are the callee-saved GPRs. */ 3272 if (frame->mask) 3273 { 3274 unsigned num_saved = __builtin_popcount(frame->mask); 3275 offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_WORD); 3276 frame->gp_sp_offset = offset - UNITS_PER_WORD; 3277 } 3278 /* The hard frame pointer points above the callee-saved GPRs. */ 3279 frame->hard_frame_pointer_offset = offset; 3280 /* Above the hard frame pointer is the callee-allocated varags save area. */ 3281 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size); 3282 frame->arg_pointer_offset = offset; 3283 /* Next is the callee-allocated area for pretend stack arguments. */ 3284 offset += crtl->args.pretend_args_size; 3285 frame->total_size = offset; 3286 /* Next points the incoming stack pointer and any incoming arguments. */ 3287 } 3288 3289 /* Make sure that we're not trying to eliminate to the wrong hard frame 3290 pointer. */ 3291 3292 static bool 3293 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 3294 { 3295 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); 3296 } 3297 3298 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer 3299 or argument pointer. TO is either the stack pointer or hard frame 3300 pointer. */ 3301 3302 HOST_WIDE_INT 3303 riscv_initial_elimination_offset (int from, int to) 3304 { 3305 HOST_WIDE_INT src, dest; 3306 3307 riscv_compute_frame_info (); 3308 3309 if (to == HARD_FRAME_POINTER_REGNUM) 3310 dest = cfun->machine->frame.hard_frame_pointer_offset; 3311 else if (to == STACK_POINTER_REGNUM) 3312 dest = 0; /* this is the base of all offsets */ 3313 else 3314 gcc_unreachable (); 3315 3316 if (from == FRAME_POINTER_REGNUM) 3317 src = cfun->machine->frame.frame_pointer_offset; 3318 else if (from == ARG_POINTER_REGNUM) 3319 src = cfun->machine->frame.arg_pointer_offset; 3320 else 3321 gcc_unreachable (); 3322 3323 return src - dest; 3324 } 3325 3326 /* Implement RETURN_ADDR_RTX. We do not support moving back to a 3327 previous frame. */ 3328 3329 rtx 3330 riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 3331 { 3332 if (count != 0) 3333 return const0_rtx; 3334 3335 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 3336 } 3337 3338 /* Emit code to change the current function's return address to 3339 ADDRESS. SCRATCH is available as a scratch register, if needed. 3340 ADDRESS and SCRATCH are both word-mode GPRs. */ 3341 3342 void 3343 riscv_set_return_address (rtx address, rtx scratch) 3344 { 3345 rtx slot_address; 3346 3347 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); 3348 slot_address = riscv_add_offset (scratch, stack_pointer_rtx, 3349 cfun->machine->frame.gp_sp_offset); 3350 riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); 3351 } 3352 3353 /* A function to save or store a register. The first argument is the 3354 register and the second is the stack slot. */ 3355 typedef void (*riscv_save_restore_fn) (rtx, rtx); 3356 3357 /* Use FN to save or restore register REGNO. MODE is the register's 3358 mode and OFFSET is the offset of its save slot from the current 3359 stack pointer. */ 3360 3361 static void 3362 riscv_save_restore_reg (enum machine_mode mode, int regno, 3363 HOST_WIDE_INT offset, riscv_save_restore_fn fn) 3364 { 3365 rtx mem; 3366 3367 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset)); 3368 fn (gen_rtx_REG (mode, regno), mem); 3369 } 3370 3371 /* Call FN for each register that is saved by the current function. 3372 SP_OFFSET is the offset of the current stack pointer from the start 3373 of the frame. */ 3374 3375 static void 3376 riscv_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, 3377 riscv_save_restore_fn fn) 3378 { 3379 HOST_WIDE_INT offset; 3380 int regno; 3381 3382 /* Save the link register and s-registers. */ 3383 offset = cfun->machine->frame.gp_sp_offset - sp_offset; 3384 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++) 3385 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3386 { 3387 riscv_save_restore_reg (word_mode, regno, offset, fn); 3388 offset -= UNITS_PER_WORD; 3389 } 3390 3391 /* This loop must iterate over the same space as its companion in 3392 riscv_compute_frame_info. */ 3393 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 3394 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3395 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 3396 { 3397 riscv_save_restore_reg (DFmode, regno, offset, fn); 3398 offset -= GET_MODE_SIZE (DFmode); 3399 } 3400 } 3401 3402 /* Emit a move from SRC to DEST, given that one of them is a register 3403 save slot and that the other is a register. TEMP is a temporary 3404 GPR of the same mode that is available if need be. */ 3405 3406 static void 3407 riscv_emit_save_slot_move (rtx dest, rtx src, rtx temp) 3408 { 3409 unsigned int regno; 3410 rtx mem; 3411 enum reg_class rclass; 3412 3413 if (REG_P (src)) 3414 { 3415 regno = REGNO (src); 3416 mem = dest; 3417 } 3418 else 3419 { 3420 regno = REGNO (dest); 3421 mem = src; 3422 } 3423 3424 rclass = riscv_secondary_reload_class (REGNO_REG_CLASS (regno), 3425 GET_MODE (mem), mem, mem == src); 3426 3427 if (rclass == NO_REGS) 3428 riscv_emit_move (dest, src); 3429 else 3430 { 3431 gcc_assert (!reg_overlap_mentioned_p (dest, temp)); 3432 riscv_emit_move (temp, src); 3433 riscv_emit_move (dest, temp); 3434 } 3435 if (MEM_P (dest)) 3436 riscv_set_frame_expr (riscv_frame_set (dest, src)); 3437 } 3438 3439 /* Save register REG to MEM. Make the instruction frame-related. */ 3440 3441 static void 3442 riscv_save_reg (rtx reg, rtx mem) 3443 { 3444 riscv_emit_save_slot_move (mem, reg, RISCV_PROLOGUE_TEMP (GET_MODE (reg))); 3445 } 3446 3447 3448 /* Expand the "prologue" pattern. */ 3449 3450 void 3451 riscv_expand_prologue (void) 3452 { 3453 const struct riscv_frame_info *frame; 3454 HOST_WIDE_INT size; 3455 rtx insn; 3456 3457 frame = &cfun->machine->frame; 3458 size = frame->total_size; 3459 3460 if (flag_stack_usage) 3461 current_function_static_stack_size = size; 3462 3463 /* Save the registers. Allocate up to RISCV_MAX_FIRST_STACK_STEP 3464 bytes beforehand; this is enough to cover the register save area 3465 without going out of range. */ 3466 if ((frame->mask | frame->fmask) != 0) 3467 { 3468 HOST_WIDE_INT step1; 3469 3470 step1 = MIN (size, RISCV_MAX_FIRST_STACK_STEP); 3471 insn = gen_add3_insn (stack_pointer_rtx, 3472 stack_pointer_rtx, 3473 GEN_INT (-step1)); 3474 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 3475 size -= step1; 3476 riscv_for_each_saved_gpr_and_fpr (size, riscv_save_reg); 3477 } 3478 3479 /* Set up the frame pointer, if we're using one. */ 3480 if (frame_pointer_needed) 3481 { 3482 insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, 3483 GEN_INT (frame->hard_frame_pointer_offset - size)); 3484 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 3485 } 3486 3487 /* Allocate the rest of the frame. */ 3488 if (size > 0) 3489 { 3490 if (SMALL_OPERAND (-size)) 3491 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, 3492 stack_pointer_rtx, 3493 GEN_INT (-size)))) = 1; 3494 else 3495 { 3496 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (size)); 3497 emit_insn (gen_sub3_insn (stack_pointer_rtx, 3498 stack_pointer_rtx, 3499 RISCV_PROLOGUE_TEMP (Pmode))); 3500 3501 /* Describe the combined effect of the previous instructions. */ 3502 riscv_set_frame_expr 3503 (gen_rtx_SET (VOIDmode, stack_pointer_rtx, 3504 plus_constant (Pmode, stack_pointer_rtx, -size))); 3505 } 3506 } 3507 } 3508 3509 /* Emit instructions to restore register REG from slot MEM. */ 3510 3511 static void 3512 riscv_restore_reg (rtx reg, rtx mem) 3513 { 3514 riscv_emit_save_slot_move (reg, mem, RISCV_EPILOGUE_TEMP (GET_MODE (reg))); 3515 } 3516 3517 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P 3518 says which. */ 3519 3520 void 3521 riscv_expand_epilogue (bool sibcall_p) 3522 { 3523 const struct riscv_frame_info *frame; 3524 HOST_WIDE_INT step1, step2; 3525 3526 if (!sibcall_p && riscv_can_use_return_insn ()) 3527 { 3528 emit_jump_insn (gen_return ()); 3529 return; 3530 } 3531 3532 /* Split the frame into two. STEP1 is the amount of stack we should 3533 deallocate before restoring the registers. STEP2 is the amount we 3534 should deallocate afterwards. 3535 3536 Start off by assuming that no registers need to be restored. */ 3537 frame = &cfun->machine->frame; 3538 step1 = frame->total_size; 3539 step2 = 0; 3540 3541 /* Move past any dynamic stack allocations. */ 3542 if (cfun->calls_alloca) 3543 { 3544 rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset); 3545 if (!SMALL_INT (adjust)) 3546 { 3547 riscv_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust); 3548 adjust = RISCV_EPILOGUE_TEMP (Pmode); 3549 } 3550 3551 emit_insn (gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, adjust)); 3552 } 3553 3554 /* If we need to restore registers, deallocate as much stack as 3555 possible in the second step without going out of range. */ 3556 if ((frame->mask | frame->fmask) != 0) 3557 { 3558 step2 = MIN (step1, RISCV_MAX_FIRST_STACK_STEP); 3559 step1 -= step2; 3560 } 3561 3562 /* Set TARGET to BASE + STEP1. */ 3563 if (step1 > 0) 3564 { 3565 /* Get an rtx for STEP1 that we can add to BASE. */ 3566 rtx adjust = GEN_INT (step1); 3567 if (!SMALL_OPERAND (step1)) 3568 { 3569 riscv_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust); 3570 adjust = RISCV_EPILOGUE_TEMP (Pmode); 3571 } 3572 3573 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); 3574 } 3575 3576 /* Restore the registers. */ 3577 riscv_for_each_saved_gpr_and_fpr (frame->total_size - step2, 3578 riscv_restore_reg); 3579 3580 /* Deallocate the final bit of the frame. */ 3581 if (step2 > 0) 3582 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 3583 GEN_INT (step2))); 3584 3585 /* Add in the __builtin_eh_return stack adjustment. */ 3586 if (crtl->calls_eh_return) 3587 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 3588 EH_RETURN_STACKADJ_RTX)); 3589 3590 if (!sibcall_p) 3591 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); 3592 } 3593 3594 /* Return nonzero if this function is known to have a null epilogue. 3595 This allows the optimizer to omit jumps to jumps if no stack 3596 was created. */ 3597 3598 bool 3599 riscv_can_use_return_insn (void) 3600 { 3601 return reload_completed && cfun->machine->frame.total_size == 0; 3602 } 3603 3604 /* Return true if register REGNO can store a value of mode MODE. 3605 The result of this function is cached in riscv_hard_regno_mode_ok. */ 3606 3607 static bool 3608 riscv_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode) 3609 { 3610 unsigned int size; 3611 enum mode_class mclass; 3612 3613 /* This is hella bogus but ira_build segfaults on RV32 without it. */ 3614 if (VECTOR_MODE_P (mode)) 3615 return true; 3616 3617 if (mode == CCmode) 3618 return GP_REG_P (regno); 3619 3620 size = GET_MODE_SIZE (mode); 3621 mclass = GET_MODE_CLASS (mode); 3622 3623 if (GP_REG_P (regno)) 3624 /* Double-word values must be even-register-aligned. */ 3625 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; 3626 3627 if (FP_REG_P (regno)) 3628 { 3629 /* Allow TFmode for CCmode reloads. */ 3630 if (mode == TFmode) 3631 return true; 3632 3633 if (mclass == MODE_FLOAT 3634 || mclass == MODE_COMPLEX_FLOAT 3635 || mclass == MODE_VECTOR_FLOAT) 3636 return size <= UNITS_PER_FPVALUE; 3637 } 3638 3639 return false; 3640 } 3641 3642 /* Implement HARD_REGNO_NREGS. */ 3643 3644 unsigned int 3645 riscv_hard_regno_nregs (int regno, enum machine_mode mode) 3646 { 3647 if (FP_REG_P (regno)) 3648 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; 3649 3650 /* All other registers are word-sized. */ 3651 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3652 } 3653 3654 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases 3655 in riscv_hard_regno_nregs. */ 3656 3657 int 3658 riscv_class_max_nregs (enum reg_class rclass, enum machine_mode mode) 3659 { 3660 int size; 3661 HARD_REG_SET left; 3662 3663 size = 0x8000; 3664 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); 3665 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) 3666 { 3667 size = MIN (size, UNITS_PER_FPREG); 3668 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); 3669 } 3670 if (!hard_reg_set_empty_p (left)) 3671 size = MIN (size, UNITS_PER_WORD); 3672 return (GET_MODE_SIZE (mode) + size - 1) / size; 3673 } 3674 3675 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ 3676 3677 static reg_class_t 3678 riscv_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) 3679 { 3680 return reg_class_subset_p (FP_REGS, rclass) ? FP_REGS : 3681 reg_class_subset_p (GR_REGS, rclass) ? GR_REGS : 3682 rclass; 3683 } 3684 3685 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. 3686 Return a "canonical" class to represent it in later calculations. */ 3687 3688 static reg_class_t 3689 riscv_canonicalize_move_class (reg_class_t rclass) 3690 { 3691 if (reg_class_subset_p (rclass, GENERAL_REGS)) 3692 rclass = GENERAL_REGS; 3693 3694 return rclass; 3695 } 3696 3697 /* Return the cost of moving a value of mode MODE from a register of 3698 class FROM to a GPR. Return 0 for classes that are unions of other 3699 classes handled by this function. */ 3700 3701 static int 3702 riscv_move_to_gpr_cost (reg_class_t from) 3703 { 3704 switch (from) 3705 { 3706 case GENERAL_REGS: 3707 return 1; 3708 3709 case FP_REGS: 3710 /* FP->int moves can cause recoupling on decoupled implementations */ 3711 return 4; 3712 3713 default: 3714 return 0; 3715 } 3716 } 3717 3718 /* Return the cost of moving a value of mode MODE from a GPR to a 3719 register of class TO. Return 0 for classes that are unions of 3720 other classes handled by this function. */ 3721 3722 static int 3723 riscv_move_from_gpr_cost (reg_class_t to) 3724 { 3725 switch (to) 3726 { 3727 case GENERAL_REGS: 3728 case FP_REGS: 3729 return 1; 3730 3731 default: 3732 return 0; 3733 } 3734 } 3735 3736 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the 3737 maximum of the move costs for subclasses; regclass will work out 3738 the maximum for us. */ 3739 3740 static int 3741 riscv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, 3742 reg_class_t from, reg_class_t to) 3743 { 3744 int cost1, cost2; 3745 3746 from = riscv_canonicalize_move_class (from); 3747 to = riscv_canonicalize_move_class (to); 3748 3749 /* Handle moves that can be done without using general-purpose registers. */ 3750 if (from == FP_REGS && to == FP_REGS) 3751 /* fmv.fmt. */ 3752 return 1; 3753 3754 /* Handle cases in which only one class deviates from the ideal. */ 3755 if (from == GENERAL_REGS) 3756 return riscv_move_from_gpr_cost (to); 3757 if (to == GENERAL_REGS) 3758 return riscv_move_to_gpr_cost (from); 3759 3760 /* Handles cases that require a GPR temporary. */ 3761 cost1 = riscv_move_to_gpr_cost (from); 3762 if (cost1 != 0) 3763 { 3764 cost2 = riscv_move_from_gpr_cost (to); 3765 if (cost2 != 0) 3766 return cost1 + cost2; 3767 } 3768 3769 return 0; 3770 } 3771 3772 /* Implement TARGET_MEMORY_MOVE_COST. */ 3773 3774 static int 3775 riscv_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) 3776 { 3777 return (riscv_cost->memory_latency 3778 + memory_move_secondary_cost (mode, rclass, in)); 3779 } 3780 3781 /* Return the register class required for a secondary register when 3782 copying between one of the registers in RCLASS and value X, which 3783 has mode MODE. X is the source of the move if IN_P, otherwise it 3784 is the destination. Return NO_REGS if no secondary register is 3785 needed. */ 3786 3787 enum reg_class 3788 riscv_secondary_reload_class (enum reg_class rclass, 3789 enum machine_mode mode, rtx x, 3790 bool in_p ATTRIBUTE_UNUSED) 3791 { 3792 int regno; 3793 3794 regno = true_regnum (x); 3795 3796 if (reg_class_subset_p (rclass, FP_REGS)) 3797 { 3798 if (MEM_P (x) && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)) 3799 /* We can use flw/fld/fsw/fsd. */ 3800 return NO_REGS; 3801 3802 if (GP_REG_P (regno) || x == CONST0_RTX (mode)) 3803 /* We can use fmv or go through memory when mode > Pmode. */ 3804 return NO_REGS; 3805 3806 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x)) 3807 /* We can force the constant to memory and use flw/fld. */ 3808 return NO_REGS; 3809 3810 if (FP_REG_P (regno)) 3811 /* We can use fmv.fmt. */ 3812 return NO_REGS; 3813 3814 /* Otherwise, we need to reload through an integer register. */ 3815 return GR_REGS; 3816 } 3817 if (FP_REG_P (regno)) 3818 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; 3819 3820 return NO_REGS; 3821 } 3822 3823 /* Implement TARGET_MODE_REP_EXTENDED. */ 3824 3825 static int 3826 riscv_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) 3827 { 3828 /* On 64-bit targets, SImode register values are sign-extended to DImode. */ 3829 if (TARGET_64BIT && mode == SImode && mode_rep == DImode) 3830 return SIGN_EXTEND; 3831 3832 return UNKNOWN; 3833 } 3834 3835 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ 3836 3837 static bool 3838 riscv_scalar_mode_supported_p (enum machine_mode mode) 3839 { 3840 if (ALL_FIXED_POINT_MODE_P (mode) 3841 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) 3842 return true; 3843 3844 return default_scalar_mode_supported_p (mode); 3845 } 3846 3847 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output 3848 dependencies have no cost. */ 3849 3850 static int 3851 riscv_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, 3852 rtx dep ATTRIBUTE_UNUSED, int cost) 3853 { 3854 if (REG_NOTE_KIND (link) != 0) 3855 return 0; 3856 return cost; 3857 } 3858 3859 /* Return the number of instructions that can be issued per cycle. */ 3860 3861 static int 3862 riscv_issue_rate (void) 3863 { 3864 switch (riscv_tune) 3865 { 3866 case PROCESSOR_ROCKET: 3867 return 1; 3868 3869 default: 3870 return 1; 3871 } 3872 } 3873 3874 /* This structure describes a single built-in function. */ 3875 struct riscv_builtin_description { 3876 /* The code of the main .md file instruction. See riscv_builtin_type 3877 for more information. */ 3878 enum insn_code icode; 3879 3880 /* The name of the built-in function. */ 3881 const char *name; 3882 3883 /* Specifies how the function should be expanded. */ 3884 enum riscv_builtin_type builtin_type; 3885 3886 /* The function's prototype. */ 3887 enum riscv_function_type function_type; 3888 3889 /* Whether the function is available. */ 3890 unsigned int (*avail) (void); 3891 }; 3892 3893 static unsigned int 3894 riscv_builtin_avail_riscv (void) 3895 { 3896 return 1; 3897 } 3898 3899 /* Construct a riscv_builtin_description from the given arguments. 3900 3901 INSN is the name of the associated instruction pattern, without the 3902 leading CODE_FOR_riscv_. 3903 3904 CODE is the floating-point condition code associated with the 3905 function. It can be 'f' if the field is not applicable. 3906 3907 NAME is the name of the function itself, without the leading 3908 "__builtin_riscv_". 3909 3910 BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields. 3911 3912 AVAIL is the name of the availability predicate, without the leading 3913 riscv_builtin_avail_. */ 3914 #define RISCV_BUILTIN(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL) \ 3915 { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME, \ 3916 BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL } 3917 3918 /* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function 3919 mapped to instruction CODE_FOR_<INSN>, FUNCTION_TYPE and AVAIL 3920 are as for RISCV_BUILTIN. */ 3921 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 3922 RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) 3923 3924 /* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT_NO_TARGET 3925 function mapped to instruction CODE_FOR_<INSN>, FUNCTION_TYPE 3926 and AVAIL are as for RISCV_BUILTIN. */ 3927 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 3928 RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT_NO_TARGET, \ 3929 FUNCTION_TYPE, AVAIL) 3930 3931 static const struct riscv_builtin_description riscv_builtins[] = { 3932 DIRECT_NO_TARGET_BUILTIN (nop, RISCV_VOID_FTYPE_VOID, riscv), 3933 }; 3934 3935 /* Index I is the function declaration for riscv_builtins[I], or null if the 3936 function isn't defined on this target. */ 3937 static GTY(()) tree riscv_builtin_decls[ARRAY_SIZE (riscv_builtins)]; 3938 3939 3940 /* Source-level argument types. */ 3941 #define RISCV_ATYPE_VOID void_type_node 3942 #define RISCV_ATYPE_INT integer_type_node 3943 #define RISCV_ATYPE_POINTER ptr_type_node 3944 #define RISCV_ATYPE_CPOINTER const_ptr_type_node 3945 3946 /* Standard mode-based argument types. */ 3947 #define RISCV_ATYPE_UQI unsigned_intQI_type_node 3948 #define RISCV_ATYPE_SI intSI_type_node 3949 #define RISCV_ATYPE_USI unsigned_intSI_type_node 3950 #define RISCV_ATYPE_DI intDI_type_node 3951 #define RISCV_ATYPE_UDI unsigned_intDI_type_node 3952 #define RISCV_ATYPE_SF float_type_node 3953 #define RISCV_ATYPE_DF double_type_node 3954 3955 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists 3956 their associated RISCV_ATYPEs. */ 3957 #define RISCV_FTYPE_ATYPES1(A, B) \ 3958 RISCV_ATYPE_##A, RISCV_ATYPE_##B 3959 3960 #define RISCV_FTYPE_ATYPES2(A, B, C) \ 3961 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C 3962 3963 #define RISCV_FTYPE_ATYPES3(A, B, C, D) \ 3964 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D 3965 3966 #define RISCV_FTYPE_ATYPES4(A, B, C, D, E) \ 3967 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \ 3968 RISCV_ATYPE_##E 3969 3970 /* Return the function type associated with function prototype TYPE. */ 3971 3972 static tree 3973 riscv_build_function_type (enum riscv_function_type type) 3974 { 3975 static tree types[(int) RISCV_MAX_FTYPE_MAX]; 3976 3977 if (types[(int) type] == NULL_TREE) 3978 switch (type) 3979 { 3980 #define DEF_RISCV_FTYPE(NUM, ARGS) \ 3981 case RISCV_FTYPE_NAME##NUM ARGS: \ 3982 types[(int) type] \ 3983 = build_function_type_list (RISCV_FTYPE_ATYPES##NUM ARGS, \ 3984 NULL_TREE); \ 3985 break; 3986 #include "config/riscv/riscv-ftypes.def" 3987 #undef DEF_RISCV_FTYPE 3988 default: 3989 gcc_unreachable (); 3990 } 3991 3992 return types[(int) type]; 3993 } 3994 3995 /* Implement TARGET_INIT_BUILTINS. */ 3996 3997 static void 3998 riscv_init_builtins (void) 3999 { 4000 const struct riscv_builtin_description *d; 4001 unsigned int i; 4002 4003 /* Iterate through all of the bdesc arrays, initializing all of the 4004 builtin functions. */ 4005 for (i = 0; i < ARRAY_SIZE (riscv_builtins); i++) 4006 { 4007 d = &riscv_builtins[i]; 4008 if (d->avail ()) 4009 riscv_builtin_decls[i] 4010 = add_builtin_function (d->name, 4011 riscv_build_function_type (d->function_type), 4012 i, BUILT_IN_MD, NULL, NULL); 4013 } 4014 } 4015 4016 /* Implement TARGET_BUILTIN_DECL. */ 4017 4018 static tree 4019 riscv_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) 4020 { 4021 if (code >= ARRAY_SIZE (riscv_builtins)) 4022 return error_mark_node; 4023 return riscv_builtin_decls[code]; 4024 } 4025 4026 /* Take argument ARGNO from EXP's argument list and convert it into a 4027 form suitable for input operand OPNO of instruction ICODE. Return the 4028 value. */ 4029 4030 static rtx 4031 riscv_prepare_builtin_arg (enum insn_code icode, 4032 unsigned int opno, tree exp, unsigned int argno) 4033 { 4034 tree arg; 4035 rtx value; 4036 enum machine_mode mode; 4037 4038 arg = CALL_EXPR_ARG (exp, argno); 4039 value = expand_normal (arg); 4040 mode = insn_data[icode].operand[opno].mode; 4041 if (!insn_data[icode].operand[opno].predicate (value, mode)) 4042 { 4043 /* We need to get the mode from ARG for two reasons: 4044 4045 - to cope with address operands, where MODE is the mode of the 4046 memory, rather than of VALUE itself. 4047 4048 - to cope with special predicates like pmode_register_operand, 4049 where MODE is VOIDmode. */ 4050 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value); 4051 4052 /* Check the predicate again. */ 4053 if (!insn_data[icode].operand[opno].predicate (value, mode)) 4054 { 4055 error ("invalid argument to built-in function"); 4056 return const0_rtx; 4057 } 4058 } 4059 4060 return value; 4061 } 4062 4063 /* Return an rtx suitable for output operand OP of instruction ICODE. 4064 If TARGET is non-null, try to use it where possible. */ 4065 4066 static rtx 4067 riscv_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target) 4068 { 4069 enum machine_mode mode; 4070 4071 mode = insn_data[icode].operand[op].mode; 4072 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode)) 4073 target = gen_reg_rtx (mode); 4074 4075 return target; 4076 } 4077 4078 /* Expand a RISCV_BUILTIN_DIRECT or RISCV_BUILTIN_DIRECT_NO_TARGET function; 4079 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function 4080 and ICODE is the code of the associated .md pattern. TARGET, if nonnull, 4081 suggests a good place to put the result. */ 4082 4083 static rtx 4084 riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, 4085 bool has_target_p) 4086 { 4087 rtx ops[MAX_RECOG_OPERANDS]; 4088 int opno, argno; 4089 4090 /* Map any target to operand 0. */ 4091 opno = 0; 4092 if (has_target_p) 4093 { 4094 target = riscv_prepare_builtin_target (icode, opno, target); 4095 ops[opno] = target; 4096 opno++; 4097 } 4098 4099 /* Map the arguments to the other operands. The n_operands value 4100 for an expander includes match_dups and match_scratches as well as 4101 match_operands, so n_operands is only an upper bound on the number 4102 of arguments to the expander function. */ 4103 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands); 4104 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++) 4105 ops[opno] = riscv_prepare_builtin_arg (icode, opno, exp, argno); 4106 4107 switch (opno) 4108 { 4109 case 2: 4110 emit_insn (GEN_FCN (icode) (ops[0], ops[1])); 4111 break; 4112 4113 case 3: 4114 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); 4115 break; 4116 4117 case 4: 4118 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); 4119 break; 4120 4121 default: 4122 gcc_unreachable (); 4123 } 4124 return target; 4125 } 4126 4127 /* Implement TARGET_EXPAND_BUILTIN. */ 4128 4129 static rtx 4130 riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 4131 enum machine_mode mode ATTRIBUTE_UNUSED, 4132 int ignore ATTRIBUTE_UNUSED) 4133 { 4134 tree fndecl; 4135 unsigned int fcode, avail; 4136 const struct riscv_builtin_description *d; 4137 4138 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 4139 fcode = DECL_FUNCTION_CODE (fndecl); 4140 gcc_assert (fcode < ARRAY_SIZE (riscv_builtins)); 4141 d = &riscv_builtins[fcode]; 4142 avail = d->avail (); 4143 gcc_assert (avail != 0); 4144 switch (d->builtin_type) 4145 { 4146 case RISCV_BUILTIN_DIRECT: 4147 return riscv_expand_builtin_direct (d->icode, target, exp, true); 4148 4149 case RISCV_BUILTIN_DIRECT_NO_TARGET: 4150 return riscv_expand_builtin_direct (d->icode, target, exp, false); 4151 } 4152 gcc_unreachable (); 4153 } 4154 4155 /* This structure records that the current function has a LO_SUM 4156 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is 4157 the largest offset applied to BASE by all such LO_SUMs. */ 4158 struct riscv_lo_sum_offset { 4159 rtx base; 4160 HOST_WIDE_INT offset; 4161 }; 4162 4163 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ 4164 4165 static hashval_t 4166 riscv_hash_base (rtx base) 4167 { 4168 int do_not_record_p; 4169 4170 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); 4171 } 4172 4173 /* Hash-table callbacks for riscv_lo_sum_offsets. */ 4174 4175 static hashval_t 4176 riscv_lo_sum_offset_hash (const void *entry) 4177 { 4178 return riscv_hash_base (((const struct riscv_lo_sum_offset *) entry)->base); 4179 } 4180 4181 static int 4182 riscv_lo_sum_offset_eq (const void *entry, const void *value) 4183 { 4184 return rtx_equal_p (((const struct riscv_lo_sum_offset *) entry)->base, 4185 (const_rtx) value); 4186 } 4187 4188 /* Look up symbolic constant X in HTAB, which is a hash table of 4189 riscv_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be 4190 paired with a recorded LO_SUM, otherwise record X in the table. */ 4191 4192 static bool 4193 riscv_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option) 4194 { 4195 rtx base, offset; 4196 void **slot; 4197 struct riscv_lo_sum_offset *entry; 4198 4199 /* Split X into a base and offset. */ 4200 split_const (x, &base, &offset); 4201 if (UNSPEC_ADDRESS_P (base)) 4202 base = UNSPEC_ADDRESS (base); 4203 4204 /* Look up the base in the hash table. */ 4205 slot = htab_find_slot_with_hash (htab, base, riscv_hash_base (base), option); 4206 if (slot == NULL) 4207 return false; 4208 4209 entry = (struct riscv_lo_sum_offset *) *slot; 4210 if (option == INSERT) 4211 { 4212 if (entry == NULL) 4213 { 4214 entry = XNEW (struct riscv_lo_sum_offset); 4215 entry->base = base; 4216 entry->offset = INTVAL (offset); 4217 *slot = entry; 4218 } 4219 else 4220 { 4221 if (INTVAL (offset) > entry->offset) 4222 entry->offset = INTVAL (offset); 4223 } 4224 } 4225 return INTVAL (offset) <= entry->offset; 4226 } 4227 4228 /* A for_each_rtx callback for which DATA is a riscv_lo_sum_offset hash table. 4229 Record every LO_SUM in *LOC. */ 4230 4231 static int 4232 riscv_record_lo_sum (rtx *loc, void *data) 4233 { 4234 if (GET_CODE (*loc) == LO_SUM) 4235 riscv_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT); 4236 return 0; 4237 } 4238 4239 /* Return true if INSN is a SET of an orphaned high-part relocation. 4240 HTAB is a hash table of riscv_lo_sum_offsets that describes all the 4241 LO_SUMs in the current function. */ 4242 4243 static bool 4244 riscv_orphaned_high_part_p (htab_t htab, rtx insn) 4245 { 4246 rtx x, set; 4247 4248 set = single_set (insn); 4249 if (set) 4250 { 4251 /* Check for %his. */ 4252 x = SET_SRC (set); 4253 if (GET_CODE (x) == HIGH 4254 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) 4255 return !riscv_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); 4256 } 4257 return false; 4258 } 4259 4260 /* Delete any high-part relocations whose partnering low parts are dead. */ 4261 4262 static void 4263 riscv_reorg_process_insns (void) 4264 { 4265 rtx insn, next_insn; 4266 htab_t htab; 4267 4268 /* Force all instructions to be split into their final form. */ 4269 split_all_insns_noflow (); 4270 4271 /* Recalculate instruction lengths without taking nops into account. */ 4272 shorten_branches (get_insns ()); 4273 4274 htab = htab_create (37, riscv_lo_sum_offset_hash, 4275 riscv_lo_sum_offset_eq, free); 4276 4277 /* Make a first pass over the instructions, recording all the LO_SUMs. */ 4278 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) 4279 if (USEFUL_INSN_P (insn)) 4280 for_each_rtx (&PATTERN (insn), riscv_record_lo_sum, htab); 4281 4282 /* Make a second pass over the instructions. Delete orphaned 4283 high-part relocations or turn them into NOPs. Avoid hazards 4284 by inserting NOPs. */ 4285 for (insn = get_insns (); insn != 0; insn = next_insn) 4286 { 4287 next_insn = NEXT_INSN (insn); 4288 if (USEFUL_INSN_P (insn)) 4289 { 4290 /* INSN is a single instruction. Delete it if it's an 4291 orphaned high-part relocation. */ 4292 if (riscv_orphaned_high_part_p (htab, insn)) 4293 delete_insn (insn); 4294 } 4295 } 4296 4297 htab_delete (htab); 4298 } 4299 4300 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ 4301 4302 static void 4303 riscv_reorg (void) 4304 { 4305 riscv_reorg_process_insns (); 4306 } 4307 4308 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 4309 in order to avoid duplicating too much logic from elsewhere. */ 4310 4311 static void 4312 riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4313 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4314 tree function) 4315 { 4316 rtx this_rtx, temp1, temp2, insn, fnaddr; 4317 bool use_sibcall_p; 4318 4319 /* Pretend to be a post-reload pass while generating rtl. */ 4320 reload_completed = 1; 4321 4322 /* Mark the end of the (empty) prologue. */ 4323 emit_note (NOTE_INSN_PROLOGUE_END); 4324 4325 /* Determine if we can use a sibcall to call FUNCTION directly. */ 4326 fnaddr = XEXP (DECL_RTL (function), 0); 4327 use_sibcall_p = absolute_symbolic_operand (fnaddr, Pmode); 4328 4329 /* We need two temporary registers in some cases. */ 4330 temp1 = gen_rtx_REG (Pmode, GP_RETURN); 4331 temp2 = gen_rtx_REG (Pmode, GP_RETURN + 1); 4332 4333 /* Find out which register contains the "this" pointer. */ 4334 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 4335 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 4336 else 4337 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); 4338 4339 /* Add DELTA to THIS_RTX. */ 4340 if (delta != 0) 4341 { 4342 rtx offset = GEN_INT (delta); 4343 if (!SMALL_OPERAND (delta)) 4344 { 4345 riscv_emit_move (temp1, offset); 4346 offset = temp1; 4347 } 4348 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); 4349 } 4350 4351 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ 4352 if (vcall_offset != 0) 4353 { 4354 rtx addr; 4355 4356 /* Set TEMP1 to *THIS_RTX. */ 4357 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); 4358 4359 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ 4360 addr = riscv_add_offset (temp2, temp1, vcall_offset); 4361 4362 /* Load the offset and add it to THIS_RTX. */ 4363 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); 4364 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); 4365 } 4366 4367 /* Jump to the target function. Use a sibcall if direct jumps are 4368 allowed, otherwise load the address into a register first. */ 4369 if (use_sibcall_p) 4370 { 4371 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); 4372 SIBLING_CALL_P (insn) = 1; 4373 } 4374 else 4375 { 4376 riscv_emit_move(temp1, fnaddr); 4377 emit_jump_insn (gen_indirect_jump (temp1)); 4378 } 4379 4380 /* Run just enough of rest_of_compilation. This sequence was 4381 "borrowed" from alpha.c. */ 4382 insn = get_insns (); 4383 split_all_insns_noflow (); 4384 shorten_branches (insn); 4385 final_start_function (insn, file, 1); 4386 final (insn, file, 1); 4387 final_end_function (); 4388 4389 /* Clean up the vars set above. Note that final_end_function resets 4390 the global pointer for us. */ 4391 reload_completed = 0; 4392 } 4393 4394 /* Allocate a chunk of memory for per-function machine-dependent data. */ 4395 4396 static struct machine_function * 4397 riscv_init_machine_status (void) 4398 { 4399 return ggc_alloc_cleared_machine_function (); 4400 } 4401 4402 /* Return the riscv_cpu_info entry for the processor or ISA given 4403 by CPU_STRING. Return null if the string isn't recognized. 4404 4405 A similar function exists in GAS. */ 4406 4407 static const struct riscv_cpu_info * 4408 riscv_parse_cpu (const char *cpu_string) 4409 { 4410 unsigned int i; 4411 4412 for (i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) 4413 if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) 4414 return riscv_cpu_info_table + i; 4415 4416 return NULL; 4417 } 4418 4419 /* Implement TARGET_OPTION_OVERRIDE. */ 4420 4421 static void 4422 riscv_option_override (void) 4423 { 4424 int regno, mode; 4425 const struct riscv_cpu_info *info; 4426 4427 #ifdef SUBTARGET_OVERRIDE_OPTIONS 4428 SUBTARGET_OVERRIDE_OPTIONS; 4429 #endif 4430 4431 info = riscv_parse_cpu (RISCV_CPU_STRING_DEFAULT); 4432 gcc_assert (info); 4433 riscv_tune = info->cpu; 4434 4435 if (riscv_tune_string != 0) 4436 { 4437 const struct riscv_cpu_info *tune = riscv_parse_cpu (riscv_tune_string); 4438 if (tune) 4439 riscv_tune = tune->cpu; 4440 } 4441 4442 flag_pcc_struct_return = 0; 4443 4444 /* Decide which rtx_costs structure to use. */ 4445 if (optimize_size) 4446 riscv_cost = &riscv_rtx_cost_optimize_size; 4447 else 4448 riscv_cost = &riscv_rtx_cost_data[riscv_tune]; 4449 4450 /* If the user hasn't specified a branch cost, use the processor's 4451 default. */ 4452 if (riscv_branch_cost == 0) 4453 riscv_branch_cost = riscv_cost->branch_cost; 4454 4455 if (!TARGET_USE_GP) 4456 g_switch_value = 0; 4457 4458 /* Prefer a call to memcpy over inline code when optimizing for size, 4459 though see MOVE_RATIO in riscv.h. */ 4460 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) 4461 target_flags |= MASK_MEMCPY; 4462 4463 /* Use atomic instructions, if user did not specify a preference */ 4464 if ((target_flags_explicit & MASK_ATOMIC) == 0) 4465 target_flags |= MASK_ATOMIC; 4466 4467 /* Set up riscv_hard_regno_mode_ok. */ 4468 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 4469 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 4470 riscv_hard_regno_mode_ok[mode][regno] 4471 = riscv_hard_regno_mode_ok_p (regno, (enum machine_mode) mode); 4472 4473 /* Function to allocate machine-dependent function status. */ 4474 init_machine_status = &riscv_init_machine_status; 4475 4476 riscv_init_relocs (); 4477 } 4478 4479 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 4480 4481 static void 4482 riscv_conditional_register_usage (void) 4483 { 4484 int regno; 4485 4486 if (!TARGET_HARD_FLOAT) 4487 { 4488 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4489 fixed_regs[regno] = call_used_regs[regno] = 1; 4490 } 4491 } 4492 4493 /* Implement TARGET_TRAMPOLINE_INIT. */ 4494 4495 static void 4496 riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4497 { 4498 rtx addr, end_addr, mem; 4499 rtx trampoline[4]; 4500 unsigned int i; 4501 HOST_WIDE_INT static_chain_offset, target_function_offset; 4502 4503 /* Work out the offsets of the pointers from the start of the 4504 trampoline code. */ 4505 gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); 4506 static_chain_offset = TRAMPOLINE_CODE_SIZE; 4507 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); 4508 4509 /* Get pointers to the beginning and end of the code block. */ 4510 addr = force_reg (Pmode, XEXP (m_tramp, 0)); 4511 end_addr = riscv_force_binary (Pmode, PLUS, addr, GEN_INT (TRAMPOLINE_CODE_SIZE)); 4512 4513 #define OP(X) gen_int_mode (X, SImode) 4514 #define MATCH_LREG ((Pmode) == DImode ? MATCH_LD : MATCH_LW) 4515 4516 /* auipc v0, 0 4517 l[wd] v1, target_function_offset(v0) 4518 l[wd] $static_chain, static_chain_offset(v0) 4519 jr v1 4520 */ 4521 4522 trampoline[0] = OP (RISCV_UTYPE (AUIPC, STATIC_CHAIN_REGNUM, 0)); 4523 trampoline[1] = OP (RISCV_ITYPE (LREG, RISCV_PROLOGUE_TEMP_REGNUM, 4524 STATIC_CHAIN_REGNUM, target_function_offset)); 4525 trampoline[2] = OP (RISCV_ITYPE (LREG, STATIC_CHAIN_REGNUM, 4526 STATIC_CHAIN_REGNUM, static_chain_offset)); 4527 trampoline[3] = OP (RISCV_ITYPE (JALR, 0, RISCV_PROLOGUE_TEMP_REGNUM, 0)); 4528 4529 #undef MATCH_LREG 4530 #undef OP 4531 4532 /* Copy the trampoline code. Leave any padding uninitialized. */ 4533 for (i = 0; i < ARRAY_SIZE (trampoline); i++) 4534 { 4535 mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); 4536 riscv_emit_move (mem, trampoline[i]); 4537 } 4538 4539 /* Set up the static chain pointer field. */ 4540 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); 4541 riscv_emit_move (mem, chain_value); 4542 4543 /* Set up the target function field. */ 4544 mem = adjust_address (m_tramp, ptr_mode, target_function_offset); 4545 riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); 4546 4547 /* Flush the code part of the trampoline. */ 4548 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); 4549 emit_insn (gen_clear_cache (addr, end_addr)); 4550 } 4551 4552 /* Initialize the GCC target structure. */ 4553 #undef TARGET_ASM_ALIGNED_HI_OP 4554 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 4555 #undef TARGET_ASM_ALIGNED_SI_OP 4556 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 4557 #undef TARGET_ASM_ALIGNED_DI_OP 4558 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 4559 4560 #undef TARGET_OPTION_OVERRIDE 4561 #define TARGET_OPTION_OVERRIDE riscv_option_override 4562 4563 #undef TARGET_LEGITIMIZE_ADDRESS 4564 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address 4565 4566 #undef TARGET_SCHED_ADJUST_COST 4567 #define TARGET_SCHED_ADJUST_COST riscv_adjust_cost 4568 #undef TARGET_SCHED_ISSUE_RATE 4569 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate 4570 4571 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 4572 #define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true 4573 4574 #undef TARGET_REGISTER_MOVE_COST 4575 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost 4576 #undef TARGET_MEMORY_MOVE_COST 4577 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost 4578 #undef TARGET_RTX_COSTS 4579 #define TARGET_RTX_COSTS riscv_rtx_costs 4580 #undef TARGET_ADDRESS_COST 4581 #define TARGET_ADDRESS_COST riscv_address_cost 4582 4583 #undef TARGET_MACHINE_DEPENDENT_REORG 4584 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg 4585 4586 #undef TARGET_PREFERRED_RELOAD_CLASS 4587 #define TARGET_PREFERRED_RELOAD_CLASS riscv_preferred_reload_class 4588 4589 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 4590 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 4591 4592 #undef TARGET_EXPAND_BUILTIN_VA_START 4593 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start 4594 4595 #undef TARGET_PROMOTE_FUNCTION_MODE 4596 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote 4597 4598 #undef TARGET_RETURN_IN_MEMORY 4599 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory 4600 4601 #undef TARGET_ASM_OUTPUT_MI_THUNK 4602 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk 4603 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 4604 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 4605 4606 #undef TARGET_PRINT_OPERAND 4607 #define TARGET_PRINT_OPERAND riscv_print_operand 4608 #undef TARGET_PRINT_OPERAND_ADDRESS 4609 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address 4610 4611 #undef TARGET_SETUP_INCOMING_VARARGS 4612 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs 4613 #undef TARGET_STRICT_ARGUMENT_NAMING 4614 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 4615 #undef TARGET_MUST_PASS_IN_STACK 4616 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 4617 #undef TARGET_PASS_BY_REFERENCE 4618 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference 4619 #undef TARGET_ARG_PARTIAL_BYTES 4620 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes 4621 #undef TARGET_FUNCTION_ARG 4622 #define TARGET_FUNCTION_ARG riscv_function_arg 4623 #undef TARGET_FUNCTION_ARG_ADVANCE 4624 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance 4625 #undef TARGET_FUNCTION_ARG_BOUNDARY 4626 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary 4627 4628 #undef TARGET_MODE_REP_EXTENDED 4629 #define TARGET_MODE_REP_EXTENDED riscv_mode_rep_extended 4630 4631 #undef TARGET_SCALAR_MODE_SUPPORTED_P 4632 #define TARGET_SCALAR_MODE_SUPPORTED_P riscv_scalar_mode_supported_p 4633 4634 #undef TARGET_INIT_BUILTINS 4635 #define TARGET_INIT_BUILTINS riscv_init_builtins 4636 #undef TARGET_BUILTIN_DECL 4637 #define TARGET_BUILTIN_DECL riscv_builtin_decl 4638 #undef TARGET_EXPAND_BUILTIN 4639 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin 4640 4641 #undef TARGET_HAVE_TLS 4642 #define TARGET_HAVE_TLS HAVE_AS_TLS 4643 4644 #undef TARGET_CANNOT_FORCE_CONST_MEM 4645 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem 4646 4647 #undef TARGET_LEGITIMATE_CONSTANT_P 4648 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p 4649 4650 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 4651 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true 4652 4653 #undef TARGET_COMP_TYPE_ATTRIBUTES 4654 #define TARGET_COMP_TYPE_ATTRIBUTES riscv_comp_type_attributes 4655 4656 #ifdef HAVE_AS_DTPRELWORD 4657 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL 4658 #define TARGET_ASM_OUTPUT_DWARF_DTPREL riscv_output_dwarf_dtprel 4659 #endif 4660 4661 #undef TARGET_LEGITIMATE_ADDRESS_P 4662 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p 4663 4664 #undef TARGET_CAN_ELIMINATE 4665 #define TARGET_CAN_ELIMINATE riscv_can_eliminate 4666 4667 #undef TARGET_CONDITIONAL_REGISTER_USAGE 4668 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage 4669 4670 #undef TARGET_TRAMPOLINE_INIT 4671 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init 4672 4673 #undef TARGET_IN_SMALL_DATA_P 4674 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p 4675 4676 #undef TARGET_ASM_SELECT_RTX_SECTION 4677 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section 4678 4679 #undef TARGET_MIN_ANCHOR_OFFSET 4680 #define TARGET_MIN_ANCHOR_OFFSET (-RISCV_IMM_REACH/2) 4681 4682 #undef TARGET_MAX_ANCHOR_OFFSET 4683 #define TARGET_MAX_ANCHOR_OFFSET (RISCV_IMM_REACH/2-1) 4684 4685 struct gcc_target targetm = TARGET_INITIALIZER; 4686 4687 #include "gt-riscv.h" 4688