1*56bb7041Schristos@ Test file for ARM/GAS -- vldr reg, =... expressions. 2*56bb7041Schristos.fpu neon 3*56bb7041Schristos.text 4*56bb7041Schristos.align 5*56bb7041Schristosfoo: 6*56bb7041Schristos # test both low and high index of the 7*56bb7041Schristos # Advanced SIMD and Floating-point reg. 8*56bb7041Schristos .macro vlxr regtype const 9*56bb7041Schristos .irp regindex, 0, 14, 28, 31 10*56bb7041Schristos vldr \regtype\regindex, \const 11*56bb7041Schristos .endr 12*56bb7041Schristos .endm 13*56bb7041Schristos 14*56bb7041Schristos .macro vlxreq regtype const 15*56bb7041Schristos .irp regindex, 0, 14, 28, 31 16*56bb7041Schristos vldreq \regtype\regindex, \const 17*56bb7041Schristos .endr 18*56bb7041Schristos .endm 19*56bb7041Schristos 20*56bb7041Schristos .macro vlxrmi regtype const 21*56bb7041Schristos .irp regindex, 0, 14, 28, 31 22*56bb7041Schristos vldrmi \regtype\regindex, \const 23*56bb7041Schristos .endr 24*56bb7041Schristos .endm 25*56bb7041Schristos 26*56bb7041Schristos vlxr s "=0" 27*56bb7041Schristos vlxr s "=0xff000000" 28*56bb7041Schristos vlxr s "=-1" 29*56bb7041Schristos vlxr s "=0x0fff0000" 30*56bb7041Schristos .pool 31*56bb7041Schristos 32*56bb7041Schristos vlxr s "=0" 33*56bb7041Schristos vlxr s "=0x00ff0000" 34*56bb7041Schristos vlxr s "=0xff00ffff" 35*56bb7041Schristos vlxr s "=0x00fff000" 36*56bb7041Schristos .pool 37*56bb7041Schristos 38*56bb7041Schristos vlxreq s "=0" 39*56bb7041Schristos vlxreq s "=0x0000ff00" 40*56bb7041Schristos vlxreq s "=0xffff00ff" 41*56bb7041Schristos vlxreq s "=0x000fff00" 42*56bb7041Schristos .pool 43*56bb7041Schristos 44*56bb7041Schristos vlxrmi s "=0" 45*56bb7041Schristos vlxrmi s "=0x000000ff" 46*56bb7041Schristos vlxrmi s "=0xffffff00" 47*56bb7041Schristos vlxrmi s "=0x0000fff0" 48*56bb7041Schristos .pool 49*56bb7041Schristos 50*56bb7041Schristos vlxr d "=0" 51*56bb7041Schristos vlxr d "=0xca000000" 52*56bb7041Schristos vlxr d "=-1" 53*56bb7041Schristos vlxr d "=0x0fff0000" 54*56bb7041Schristos .pool 55*56bb7041Schristos 56*56bb7041Schristos vlxr d "=0" 57*56bb7041Schristos vlxr d "=0x00ff0000" 58*56bb7041Schristos vlxr d "=0xff0000ff" 59*56bb7041Schristos vlxr d "=0x00fff000" 60*56bb7041Schristos .pool 61*56bb7041Schristos 62*56bb7041Schristos vlxreq d "=0" 63*56bb7041Schristos vlxreq d "=0x0000ff00" 64*56bb7041Schristos vlxreq d "=0xffff00ff" 65*56bb7041Schristos vlxreq d "=0x000fff00" 66*56bb7041Schristos .pool 67*56bb7041Schristos 68*56bb7041Schristos vlxrmi d "=0" 69*56bb7041Schristos vlxrmi d "=0x000000ff" 70*56bb7041Schristos vlxrmi d "=0xffffff00" 71*56bb7041Schristos vlxrmi d "=0x0000ffff" 72*56bb7041Schristos .pool 73*56bb7041Schristos 74*56bb7041Schristos vlxr d "=0" 75*56bb7041Schristos vlxr d "=0xff00000000000000" 76*56bb7041Schristos vlxr d "=-1" 77*56bb7041Schristos vlxr d "=0x0fff000000000000" 78*56bb7041Schristos .pool 79*56bb7041Schristos 80*56bb7041Schristos vlxr d "=0" 81*56bb7041Schristos vlxr d "=0x00ff00000000000" 82*56bb7041Schristos vlxr d "=0xff00ffff0000000" 83*56bb7041Schristos vlxr d "=0x00fff0000000000" 84*56bb7041Schristos .pool 85*56bb7041Schristos 86*56bb7041Schristos vlxreq d "=0" 87*56bb7041Schristos vlxreq d "=0x0000ff0000000000" 88*56bb7041Schristos vlxreq d "=0xffff00ff00000000" 89*56bb7041Schristos vlxreq d "=0x000fff0000000000" 90*56bb7041Schristos .pool 91*56bb7041Schristos 92*56bb7041Schristos vlxrmi d "=0" 93*56bb7041Schristos vlxrmi d "=0x000000ff00000000" 94*56bb7041Schristos vlxrmi d "=0xffffff0000000000" 95*56bb7041Schristos vlxrmi d "=0x0000fff000000000" 96*56bb7041Schristos .pool 97*56bb7041Schristos 98*56bb7041Schristos # pool should be aligned to 8-byte. 99*56bb7041Schristos .p2align 3 100*56bb7041Schristos vldr d1, =0x0000fff000000000 101*56bb7041Schristos .pool 102*56bb7041Schristos 103*56bb7041Schristos # no error when code is align already. 104*56bb7041Schristos .p2align 3 105*56bb7041Schristos add r0, r1, #0 106*56bb7041Schristos vldr d1, =0x0000fff000000000 107*56bb7041Schristos .pool 108*56bb7041Schristos 109*56bb7041Schristos .p2align 3 110*56bb7041Schristos vldr d1, =0x0000fff000000000 111*56bb7041Schristos vldr s2, =0xff000000 112*56bb7041Schristos # padding A 113*56bb7041Schristos vldr d3, =0x0000fff000000001 114*56bb7041Schristos # reuse padding slot A 115*56bb7041Schristos vldr s4, =0xff000001 116*56bb7041Schristos # reuse d3 117*56bb7041Schristos vldr d5, =0x0000fff000000001 118*56bb7041Schristos # new 8-byte entry 119*56bb7041Schristos vldr d6, =0x0000fff000000002 120*56bb7041Schristos # new 8-byte entry 121*56bb7041Schristos vldr d7, =0x0000fff000000003 122*56bb7041Schristos # new 4-byte entry 123*56bb7041Schristos vldr s8, =0xff000002 124*56bb7041Schristos # padding B 125*56bb7041Schristos vldr d9, =0x0000fff000000004 126*56bb7041Schristos # reuse padding slot B 127*56bb7041Schristos vldr s10, =0xff000003 128*56bb7041Schristos # new 8-byte entry 129*56bb7041Schristos vldr d11, =0x0000fff000000005 130*56bb7041Schristos # new 4 entry 131*56bb7041Schristos vldr s12, =0xff000004 132*56bb7041Schristos # new 4 entry 133*56bb7041Schristos vldr s13, =0xff000005 134*56bb7041Schristos # reuse value of s4 in pool 135*56bb7041Schristos vldr s14, =0xff000001 136*56bb7041Schristos # reuse high part of d1 in pool 137*56bb7041Schristos vldr s15, =0x0000fff0 138*56bb7041Schristos # 8-byte entry reuse two 4-byte entries. 139*56bb7041Schristos # this reuse should only happen for 140*56bb7041Schristos # little-endian 141*56bb7041Schristos # d16 reuse s12, s13 142*56bb7041Schristos vldr d16, =0xff000005ff000004 143*56bb7041Schristos # d17 should not reuse high part of d11 and s12. 144*56bb7041Schristos # because the it's align 8-byte aligned. 145*56bb7041Schristos vldr d17, =0xff0000040000fff0 146*56bb7041Schristos .pool 147