1 /* Xtensa ELF support for BFD. 2 Copyright (C) 2003-2020 Free Software Foundation, Inc. 3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, 20 USA. */ 21 22 /* This file holds definitions specific to the Xtensa ELF ABI. */ 23 24 #ifndef _ELF_XTENSA_H 25 #define _ELF_XTENSA_H 26 27 #include "elf/reloc-macros.h" 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* Relocations. */ 34 START_RELOC_NUMBERS (elf_xtensa_reloc_type) 35 RELOC_NUMBER (R_XTENSA_NONE, 0) 36 RELOC_NUMBER (R_XTENSA_32, 1) 37 RELOC_NUMBER (R_XTENSA_RTLD, 2) 38 RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3) 39 RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4) 40 RELOC_NUMBER (R_XTENSA_RELATIVE, 5) 41 RELOC_NUMBER (R_XTENSA_PLT, 6) 42 RELOC_NUMBER (R_XTENSA_OP0, 8) 43 RELOC_NUMBER (R_XTENSA_OP1, 9) 44 RELOC_NUMBER (R_XTENSA_OP2, 10) 45 RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11) 46 RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12) 47 RELOC_NUMBER (R_XTENSA_32_PCREL, 14) 48 RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15) 49 RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16) 50 RELOC_NUMBER (R_XTENSA_DIFF8, 17) 51 RELOC_NUMBER (R_XTENSA_DIFF16, 18) 52 RELOC_NUMBER (R_XTENSA_DIFF32, 19) 53 RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20) 54 RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21) 55 RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22) 56 RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23) 57 RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24) 58 RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25) 59 RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26) 60 RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27) 61 RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28) 62 RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29) 63 RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30) 64 RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31) 65 RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32) 66 RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33) 67 RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34) 68 RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35) 69 RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36) 70 RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37) 71 RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38) 72 RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39) 73 RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40) 74 RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41) 75 RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42) 76 RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43) 77 RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44) 78 RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45) 79 RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46) 80 RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47) 81 RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48) 82 RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49) 83 RELOC_NUMBER (R_XTENSA_TLSDESC_FN, 50) 84 RELOC_NUMBER (R_XTENSA_TLSDESC_ARG, 51) 85 RELOC_NUMBER (R_XTENSA_TLS_DTPOFF, 52) 86 RELOC_NUMBER (R_XTENSA_TLS_TPOFF, 53) 87 RELOC_NUMBER (R_XTENSA_TLS_FUNC, 54) 88 RELOC_NUMBER (R_XTENSA_TLS_ARG, 55) 89 RELOC_NUMBER (R_XTENSA_TLS_CALL, 56) 90 RELOC_NUMBER (R_XTENSA_PDIFF8, 57) 91 RELOC_NUMBER (R_XTENSA_PDIFF16, 58) 92 RELOC_NUMBER (R_XTENSA_PDIFF32, 59) 93 RELOC_NUMBER (R_XTENSA_NDIFF8, 60) 94 RELOC_NUMBER (R_XTENSA_NDIFF16, 61) 95 RELOC_NUMBER (R_XTENSA_NDIFF32, 62) 96 END_RELOC_NUMBERS (R_XTENSA_max) 97 98 /* Processor-specific flags for the ELF header e_flags field. */ 99 100 /* Four-bit Xtensa machine type field. */ 101 #define EF_XTENSA_MACH 0x0000000f 102 103 /* Various CPU types. */ 104 #define E_XTENSA_MACH 0x00000000 105 106 /* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. 107 Highly unlikely, but what the heck. */ 108 109 #define EF_XTENSA_XT_INSN 0x00000100 110 #define EF_XTENSA_XT_LIT 0x00000200 111 112 113 /* Processor-specific dynamic array tags. */ 114 115 /* Offset of the table that records the GOT location(s). */ 116 #define DT_XTENSA_GOT_LOC_OFF 0x70000000 117 118 /* Number of entries in the GOT location table. */ 119 #define DT_XTENSA_GOT_LOC_SZ 0x70000001 120 121 122 /* Definitions for instruction and literal property tables. The 123 tables for ".gnu.linkonce.*" sections are placed in the following 124 sections: 125 126 instruction tables: .gnu.linkonce.x.* 127 literal tables: .gnu.linkonce.p.* 128 */ 129 130 #define XTENSA_INSN_SEC_NAME ".xt.insn" 131 #define XTENSA_LIT_SEC_NAME ".xt.lit" 132 #define XTENSA_PROP_SEC_NAME ".xt.prop" 133 134 typedef struct property_table_entry_t 135 { 136 bfd_vma address; 137 bfd_vma size; 138 flagword flags; 139 } property_table_entry; 140 141 /* Flags in the property tables to specify whether blocks of memory are 142 literals, instructions, data, or unreachable. For instructions, 143 blocks that begin loop targets and branch targets are designated. 144 Blocks that do not allow density instructions, instruction reordering 145 or transformation are also specified. Finally, for branch targets, 146 branch target alignment priority is included. Alignment of the next 147 block is specified in the current block and the size of the current 148 block does not include any fill required to align to the next 149 block. */ 150 151 #define XTENSA_PROP_LITERAL 0x00000001 152 #define XTENSA_PROP_INSN 0x00000002 153 #define XTENSA_PROP_DATA 0x00000004 154 #define XTENSA_PROP_UNREACHABLE 0x00000008 155 /* Instruction-only properties at beginning of code. */ 156 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 157 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 158 /* Instruction-only properties about code. */ 159 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 160 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 161 /* Historically, NO_TRANSFORM was a property of instructions, 162 but it should apply to literals under certain circumstances. */ 163 #define XTENSA_PROP_NO_TRANSFORM 0x00000100 164 165 /* Branch target alignment information. This transmits information 166 to the linker optimization about the priority of aligning a 167 particular block for branch target alignment: None, low priority, 168 high priority, or required. These only need to be checked in 169 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 170 Common usage is: 171 172 switch (GET_XTENSA_PROP_BT_ALIGN(flags)) 173 case XTENSA_PROP_BT_ALIGN_NONE: 174 case XTENSA_PROP_BT_ALIGN_LOW: 175 case XTENSA_PROP_BT_ALIGN_HIGH: 176 case XTENSA_PROP_BT_ALIGN_REQUIRE: 177 */ 178 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 179 180 /* No branch target alignment. */ 181 #define XTENSA_PROP_BT_ALIGN_NONE 0x0 182 /* Low priority branch target alignment. */ 183 #define XTENSA_PROP_BT_ALIGN_LOW 0x1 184 /* High priority branch target alignment. */ 185 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 186 /* Required branch target alignment. */ 187 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 188 189 #define GET_XTENSA_PROP_BT_ALIGN(flag) \ 190 (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) 191 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 192 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 193 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 194 195 /* Alignment is specified in the block BEFORE the one that needs 196 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 197 get the required alignment specified as a power of 2. Use 198 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 199 alignment. Be careful of side effects since the SET will evaluate 200 flags twice. Also, note that the SIZE of a block in the property 201 table does not include the alignment size, so the alignment fill 202 must be calculated to determine if two blocks are contiguous. 203 TEXT_ALIGN is not currently implemented but is a placeholder for a 204 possible future implementation. */ 205 206 #define XTENSA_PROP_ALIGN 0x00000800 207 208 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 209 210 #define GET_XTENSA_PROP_ALIGNMENT(flag) \ 211 (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) 212 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 213 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 214 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 215 216 #define XTENSA_PROP_INSN_ABSLIT 0x00020000 217 218 extern asection *xtensa_make_property_section (asection *, const char *); 219 extern int 220 xtensa_read_table_entries (bfd *abfd, 221 asection *section, 222 property_table_entry **table_p, 223 const char *sec_name, 224 bfd_boolean output_addr); 225 extern int 226 xtensa_compute_fill_extra_space (property_table_entry *entry); 227 228 extern int 229 xtensa_abi_choice (void); 230 231 #ifdef __cplusplus 232 } 233 #endif 234 235 #endif /* _ELF_XTENSA_H */ 236