1*a1ba9ba4Schristos2013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com> 2*a1ba9ba4Schristos 3*a1ba9ba4Schristos * nds32-dis.c (sr_map): Add system register table for disassembling. 4*a1ba9ba4Schristos (usr_map): Fix typo. 5*a1ba9ba4Schristos * nds32-asm.c (keyword_sr): Add embedded debug registers. 6*a1ba9ba4Schristos 7*a1ba9ba4Schristos2013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com> 8*a1ba9ba4Schristos 9*a1ba9ba4Schristos * i386-dis.c (MOD_FF_REG_3): New. 10*a1ba9ba4Schristos (MOD_FF_REG_5): Likewise. 11*a1ba9ba4Schristos (mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5. 12*a1ba9ba4Schristos (reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5. 13*a1ba9ba4Schristos 14*a1ba9ba4Schristos2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> 15*a1ba9ba4Schristos 16*a1ba9ba4Schristos * mips-dis.c: Add mips_cp1_names pointer. 17*a1ba9ba4Schristos (mips_cp1_names_numeric): New array. 18*a1ba9ba4Schristos (mips_cp1_names_mips3264): New array. 19*a1ba9ba4Schristos (mips_arch_choice): Add cp1_names. 20*a1ba9ba4Schristos (mips_arch_choices): Add relevant cp1 register name array to each of 21*a1ba9ba4Schristos the elements. 22*a1ba9ba4Schristos (set_default_mips_dis_options): Add support for setting up the 23*a1ba9ba4Schristos mips_cp1_names pointer. 24*a1ba9ba4Schristos (parse_mips_dis_option): Add support for the cp1-names command line 25*a1ba9ba4Schristos variable. Also setup the mips_cp1_names pointer. 26*a1ba9ba4Schristos (print_reg): Print out name of the cp1 register. 27*a1ba9ba4Schristos 28*a1ba9ba4Schristos2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> 29*a1ba9ba4Schristos 30*a1ba9ba4Schristos * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, 31*a1ba9ba4Schristos +v and +w. 32*a1ba9ba4Schristos (micromips_opcodes): Reduced element index range for sldi, splati, 33*a1ba9ba4Schristos copy_s, copy_u, insert and insve instructions. 34*a1ba9ba4Schristos * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, 35*a1ba9ba4Schristos +v and +w. 36*a1ba9ba4Schristos (mips_builtin_opcodes): Reduced element index range for sldi, splati, 37*a1ba9ba4Schristos copy_s, copy_u, insert and insve instructions. 38*a1ba9ba4Schristos 39*a1ba9ba4Schristos2013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de> 40*a1ba9ba4Schristos 41*a1ba9ba4Schristos * nds32-dis.c (mnemonic_96): Fix typo. 42*a1ba9ba4Schristos 43*a1ba9ba4Schristos2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com> 44*a1ba9ba4Schristos Wei-Cheng Wang <cole945@gmail.com> 45*a1ba9ba4Schristos 46*a1ba9ba4Schristos * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c 47*a1ba9ba4Schristos and nds32-dis.c. 48*a1ba9ba4Schristos * Makefile.in: Regenerate. 49*a1ba9ba4Schristos * configure.in: Add case for bfd_nds32_arch. 50*a1ba9ba4Schristos * configure: Regenerate. 51*a1ba9ba4Schristos * disassemble.c (ARCH_nds32): Define. 52*a1ba9ba4Schristos * nds32-asm.c: New file for nds32. 53*a1ba9ba4Schristos * nds32-asm.h: New file for nds32. 54*a1ba9ba4Schristos * nds32-dis.c: New file for nds32. 55*a1ba9ba4Schristos * nds32-opc.h: New file for nds32. 56*a1ba9ba4Schristos 57*a1ba9ba4Schristos2013-12-05 Nick Clifton <nickc@redhat.com> 58*a1ba9ba4Schristos 59*a1ba9ba4Schristos * s390-mkopc.c (dumpTable): Provide a format string to printf so 60*a1ba9ba4Schristos that compiling with -Werror=format-security does not produce an 61*a1ba9ba4Schristos error. 62*a1ba9ba4Schristos 63*a1ba9ba4Schristos2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> 64*a1ba9ba4Schristos 65*a1ba9ba4Schristos * aarch64-opc.c (aarch64_pstatefields): Update. 66*a1ba9ba4Schristos 67*a1ba9ba4Schristos2013-11-19 Catherine Moore <clm@codesourcery.com> 68*a1ba9ba4Schristos 69*a1ba9ba4Schristos * micromips-opc.c (LM): Define. 70*a1ba9ba4Schristos (micromips_opcodes): Add LM to load instructions. 71*a1ba9ba4Schristos * mips-opc.c (prefe): Add LM attribute. 72*a1ba9ba4Schristos 73*a1ba9ba4Schristos2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> 74*a1ba9ba4Schristos 75*a1ba9ba4Schristos Revert 76*a1ba9ba4Schristos 77*a1ba9ba4Schristos 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> 78*a1ba9ba4Schristos 79*a1ba9ba4Schristos * aarch64-opc.c (CPENT): New define. 80*a1ba9ba4Schristos (F_READONLY, F_WRITEONLY): Likewise. 81*a1ba9ba4Schristos (aarch64_sys_regs): Add trace unit registers. 82*a1ba9ba4Schristos (aarch64_sys_reg_readonly_p): New function. 83*a1ba9ba4Schristos (aarch64_sys_reg_writeonly_p): Ditto. 84*a1ba9ba4Schristos 85*a1ba9ba4Schristos2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> 86*a1ba9ba4Schristos 87*a1ba9ba4Schristos * aarch64-opc.c (CPENT): New define. 88*a1ba9ba4Schristos (F_READONLY, F_WRITEONLY): Likewise. 89*a1ba9ba4Schristos (aarch64_sys_regs): Add trace unit registers. 90*a1ba9ba4Schristos (aarch64_sys_reg_readonly_p): New function. 91*a1ba9ba4Schristos (aarch64_sys_reg_writeonly_p): Ditto. 92*a1ba9ba4Schristos 93*a1ba9ba4Schristos2013-11-15 Maciej W. Rozycki <macro@codesourcery.com> 94*a1ba9ba4Schristos 95*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and 96*a1ba9ba4Schristos "mtcr". 97*a1ba9ba4Schristos 98*a1ba9ba4Schristos2013-11-11 Catherine Moore <clm@codesourcery.com> 99*a1ba9ba4Schristos 100*a1ba9ba4Schristos * mips-dis.c (print_insn_mips): Use 101*a1ba9ba4Schristos INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. 102*a1ba9ba4Schristos (print_insn_micromips): Likewise. 103*a1ba9ba4Schristos * mips-opc.c (LDD): Remove. 104*a1ba9ba4Schristos (CLD): Include INSN_LOAD_MEMORY. 105*a1ba9ba4Schristos (LM): New. 106*a1ba9ba4Schristos (mips_builtin_opcodes): Use LM instead of LDD. 107*a1ba9ba4Schristos Add LM to load instructions. 108*a1ba9ba4Schristos 109*a1ba9ba4Schristos2013-11-08 H.J. Lu <hongjiu.lu@intel.com> 110*a1ba9ba4Schristos 111*a1ba9ba4Schristos PR gas/16140 112*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS. 113*a1ba9ba4Schristos * i386-init.h: Regenerated. 114*a1ba9ba4Schristos 115*a1ba9ba4Schristos2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> 116*a1ba9ba4Schristos 117*a1ba9ba4Schristos * aarch64-opc.c (F_DEPRECATED): New macro. 118*a1ba9ba4Schristos (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with 119*a1ba9ba4Schristos F_DEPRECATED. 120*a1ba9ba4Schristos (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on 121*a1ba9ba4Schristos AARCH64_OPND_SYSREG. 122*a1ba9ba4Schristos 123*a1ba9ba4Schristos2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> 124*a1ba9ba4Schristos 125*a1ba9ba4Schristos * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. 126*a1ba9ba4Schristos (convert_from_csel): Likewise. 127*a1ba9ba4Schristos * aarch64-opc.c (operand_general_constraint_met_p): Handle 128*a1ba9ba4Schristos AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. 129*a1ba9ba4Schristos (aarch64_print_operand): Handle AARCH64_OPND_COND1. 130*a1ba9ba4Schristos * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of 131*a1ba9ba4Schristos COND for cinc, cset, cinv, csetm and cneg. 132*a1ba9ba4Schristos (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. 133*a1ba9ba4Schristos * aarch64-asm-2.c: Re-generated. 134*a1ba9ba4Schristos * aarch64-dis-2.c: Ditto. 135*a1ba9ba4Schristos * aarch64-opc-2.c: Ditto. 136*a1ba9ba4Schristos 137*a1ba9ba4Schristos2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> 138*a1ba9ba4Schristos 139*a1ba9ba4Schristos * aarch64-opc.c (set_syntax_error): New function. 140*a1ba9ba4Schristos (operand_general_constraint_met_p): Replace set_other_error 141*a1ba9ba4Schristos with set_syntax_error. 142*a1ba9ba4Schristos 143*a1ba9ba4Schristos2013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com> 144*a1ba9ba4Schristos 145*a1ba9ba4Schristos * s390-dis.c (init_disasm): Default to full 'zarch' opcode 146*a1ba9ba4Schristos availability even for 31-bit programs. 147*a1ba9ba4Schristos 148*a1ba9ba4Schristos2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 149*a1ba9ba4Schristos 150*a1ba9ba4Schristos * arm-dis.c (neon_opcodes): Adjust print string for vshll. 151*a1ba9ba4Schristos 152*a1ba9ba4Schristos2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> 153*a1ba9ba4Schristos 154*a1ba9ba4Schristos * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W, 155*a1ba9ba4Schristos +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, 156*a1ba9ba4Schristos +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. 157*a1ba9ba4Schristos (MSA): New define. 158*a1ba9ba4Schristos (MSA64): New define. 159*a1ba9ba4Schristos (micromips_opcodes): Add MSA instructions. 160*a1ba9ba4Schristos * mips-dis.c (msa_control_names): New array. 161*a1ba9ba4Schristos (mips_abi_choice): Add ASE_MSA to mips32r2. 162*a1ba9ba4Schristos Remove ASE_MDMX from mips64r2. 163*a1ba9ba4Schristos Add ASE_MSA and ASE_MSA64 to mips64r2. 164*a1ba9ba4Schristos (parse_mips_dis_option): Handle -Mmsa. 165*a1ba9ba4Schristos (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. 166*a1ba9ba4Schristos (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. 167*a1ba9ba4Schristos (print_mips_disassembler_options): Print -Mmsa. 168*a1ba9ba4Schristos * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, 169*a1ba9ba4Schristos +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. 170*a1ba9ba4Schristos (MSA): New define. 171*a1ba9ba4Schristos (MSA64): New define. 172*a1ba9ba4Schristos (mips_builtin_op): Add MSA instructions. 173*a1ba9ba4Schristos 174*a1ba9ba4Schristos2013-10-13 Sandra Loosemore <sandra@codesourcery.com> 175*a1ba9ba4Schristos 176*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba" 177*a1ba9ba4Schristos as the primary name of r30. 178*a1ba9ba4Schristos 179*a1ba9ba4Schristos2013-10-12 Jan Beulich <jbeulich@suse.com> 180*a1ba9ba4Schristos 181*a1ba9ba4Schristos * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the 182*a1ba9ba4Schristos default case. 183*a1ba9ba4Schristos (OP_E_register): Move v_bnd_mode alongside m_mode. 184*a1ba9ba4Schristos * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants. 185*a1ba9ba4Schristos Drop Reg16 and Disp16. Add NoRex64. 186*a1ba9ba4Schristos (bndmk, bndmov, bndldx, bndstx): Drop Disp16. 187*a1ba9ba4Schristos * i386-tbl.h: Re-generate. 188*a1ba9ba4Schristos 189*a1ba9ba4Schristos2013-10-10 Sean Keys <skeys@ipdatasys.com> 190*a1ba9ba4Schristos 191*a1ba9ba4Schristos * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode 192*a1ba9ba4Schristos table. 193*a1ba9ba4Schristos * xgate-dis.c (print_insn): Refactor to work with table change. 194*a1ba9ba4Schristos 195*a1ba9ba4Schristos2013-10-10 Roland McGrath <mcgrathr@google.com> 196*a1ba9ba4Schristos 197*a1ba9ba4Schristos * i386-dis.c (oappend_maybe_intel): New function. 198*a1ba9ba4Schristos (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it. 199*a1ba9ba4Schristos (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise. 200*a1ba9ba4Schristos (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise. 201*a1ba9ba4Schristos 202*a1ba9ba4Schristos * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress 203*a1ba9ba4Schristos possible compiler warnings when the union's initializer is 204*a1ba9ba4Schristos actually meant for the 'preg' enum typed member. 205*a1ba9ba4Schristos * crx-opc.c (REG): Likewise. 206*a1ba9ba4Schristos 207*a1ba9ba4Schristos * v850-dis.c (v850_cacheop_codes, v850_prefop_codes): 208*a1ba9ba4Schristos Remove duplicate const qualifier. 209*a1ba9ba4Schristos 210*a1ba9ba4Schristos2013-10-08 Jan Beulich <jbeulich@suse.com> 211*a1ba9ba4Schristos 212*a1ba9ba4Schristos * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified. 213*a1ba9ba4Schristos (clflush): Use Anysize instead of Byte|Unspecified. 214*a1ba9ba4Schristos (prefetch*): Likewise. 215*a1ba9ba4Schristos * i386-tbl.h: Re-generate. 216*a1ba9ba4Schristos 217*a1ba9ba4Schristos2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com> 218*a1ba9ba4Schristos 219*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0. 220*a1ba9ba4Schristos 221*a1ba9ba4Schristos2013-09-30 H.J. Lu <hongjiu.lu@intel.com> 222*a1ba9ba4Schristos 223*a1ba9ba4Schristos * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand. 224*a1ba9ba4Schristos * i386-init.h: Regenerated. 225*a1ba9ba4Schristos 226*a1ba9ba4Schristos2013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com> 227*a1ba9ba4Schristos 228*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS. 229*a1ba9ba4Schristos * i386-init.h: Regenerated. 230*a1ba9ba4Schristos 231*a1ba9ba4Schristos2013-09-20 Alan Modra <amodra@gmail.com> 232*a1ba9ba4Schristos 233*a1ba9ba4Schristos * configure: Regenerate. 234*a1ba9ba4Schristos 235*a1ba9ba4Schristos2013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com> 236*a1ba9ba4Schristos 237*a1ba9ba4Schristos * s390-opc.txt (clih): Make the immediate unsigned. 238*a1ba9ba4Schristos 239*a1ba9ba4Schristos2013-09-04 Roland McGrath <mcgrathr@google.com> 240*a1ba9ba4Schristos 241*a1ba9ba4Schristos PR gas/15914 242*a1ba9ba4Schristos * arm-dis.c (arm_opcodes): Add udf. 243*a1ba9ba4Schristos (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. 244*a1ba9ba4Schristos (thumb32_opcodes): Add udf.w. 245*a1ba9ba4Schristos (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says. 246*a1ba9ba4Schristos 247*a1ba9ba4Schristos2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 248*a1ba9ba4Schristos 249*a1ba9ba4Schristos * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra. 250*a1ba9ba4Schristos For the load fp integer instructions only the suppression flag was 251*a1ba9ba4Schristos new with z196 version. 252*a1ba9ba4Schristos 253*a1ba9ba4Schristos2013-08-28 Nick Clifton <nickc@redhat.com> 254*a1ba9ba4Schristos 255*a1ba9ba4Schristos * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the 256*a1ba9ba4Schristos immediate is not suitable for the 32-bit ABI. 257*a1ba9ba4Schristos 258*a1ba9ba4Schristos2013-08-23 Maciej W. Rozycki <macro@codesourcery.com> 259*a1ba9ba4Schristos 260*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", 261*a1ba9ba4Schristos replacing NODS. 262*a1ba9ba4Schristos 263*a1ba9ba4Schristos2013-08-23 Yuri Chornoivan <yurchor@ukr.net> 264*a1ba9ba4Schristos 265*a1ba9ba4Schristos PR binutils/15834 266*a1ba9ba4Schristos * aarch64-asm.c: Fix typos. 267*a1ba9ba4Schristos * aarch64-dis.c: Likewise. 268*a1ba9ba4Schristos * msp430-dis.c: Likewise. 269*a1ba9ba4Schristos 270*a1ba9ba4Schristos2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> 271*a1ba9ba4Schristos 272*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" 273*a1ba9ba4Schristos macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. 274*a1ba9ba4Schristos Use +H rather than +C for the real "dext". 275*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Likewise. 276*a1ba9ba4Schristos 277*a1ba9ba4Schristos2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> 278*a1ba9ba4Schristos 279*a1ba9ba4Schristos * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. 280*a1ba9ba4Schristos * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG 281*a1ba9ba4Schristos and OPTIONAL_MAPPED_REG. 282*a1ba9ba4Schristos * mips-opc.c (decode_mips_operand): Likewise. 283*a1ba9ba4Schristos * mips16-opc.c (decode_mips16_operand): Likewise. 284*a1ba9ba4Schristos * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. 285*a1ba9ba4Schristos 286*a1ba9ba4Schristos2013-08-19 H.J. Lu <hongjiu.lu@intel.com> 287*a1ba9ba4Schristos 288*a1ba9ba4Schristos * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed. 289*a1ba9ba4Schristos (PREFIX_EVEX_0F3A3F): Likewise. 290*a1ba9ba4Schristos * i386-dis-evex.h (evex_table): Updated. 291*a1ba9ba4Schristos 292*a1ba9ba4Schristos2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> 293*a1ba9ba4Schristos 294*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of 295*a1ba9ba4Schristos VCLIPW. 296*a1ba9ba4Schristos 297*a1ba9ba4Schristos2013-08-05 Eric Botcazou <ebotcazou@adacore.com> 298*a1ba9ba4Schristos Konrad Eisele <konrad@gaisler.com> 299*a1ba9ba4Schristos 300*a1ba9ba4Schristos * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for 301*a1ba9ba4Schristos bfd_mach_sparc. 302*a1ba9ba4Schristos * sparc-opc.c (MASK_LEON): Define. 303*a1ba9ba4Schristos (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. 304*a1ba9ba4Schristos (letandleon): New macro. 305*a1ba9ba4Schristos (v9andleon): Likewise. 306*a1ba9ba4Schristos (sparc_opc): Add leon. 307*a1ba9ba4Schristos (umac): Enable for letandleon. 308*a1ba9ba4Schristos (smac): Likewise. 309*a1ba9ba4Schristos (casa): Enable for v9andleon. 310*a1ba9ba4Schristos (cas): Likewise. 311*a1ba9ba4Schristos (casl): Likewise. 312*a1ba9ba4Schristos 313*a1ba9ba4Schristos2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> 314*a1ba9ba4Schristos Richard Sandiford <rdsandiford@googlemail.com> 315*a1ba9ba4Schristos 316*a1ba9ba4Schristos * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, 317*a1ba9ba4Schristos OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. 318*a1ba9ba4Schristos (print_vu0_channel): New function. 319*a1ba9ba4Schristos (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. 320*a1ba9ba4Schristos (print_insn_args): Handle '#'. 321*a1ba9ba4Schristos (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. 322*a1ba9ba4Schristos * mips-opc.c (mips_vu0_channel_mask): New constant. 323*a1ba9ba4Schristos (decode_mips_operand): Handle new VU0 operand types. 324*a1ba9ba4Schristos (VU0, VU0CH): New macros. 325*a1ba9ba4Schristos (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" 326*a1ba9ba4Schristos for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. 327*a1ba9ba4Schristos Use "+6" rather than "G" for QMFC2 and QMTC2. 328*a1ba9ba4Schristos 329*a1ba9ba4Schristos2013-08-03 Richard Sandiford <rdsandiford@googlemail.com> 330*a1ba9ba4Schristos 331*a1ba9ba4Schristos * mips-formats.h (PCREL): Reorder parameters and update the definition 332*a1ba9ba4Schristos to match new mips_pcrel_operand layout. 333*a1ba9ba4Schristos (JUMP, JALX, BRANCH): Update accordingly. 334*a1ba9ba4Schristos * mips16-opc.c (decode_mips16_operand): Likewise. 335*a1ba9ba4Schristos 336*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 337*a1ba9ba4Schristos 338*a1ba9ba4Schristos * micromips-opc.c (WR_s): Delete. 339*a1ba9ba4Schristos 340*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 341*a1ba9ba4Schristos 342*a1ba9ba4Schristos * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 343*a1ba9ba4Schristos New macros. 344*a1ba9ba4Schristos (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 345*a1ba9ba4Schristos (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. 346*a1ba9ba4Schristos (mips_builtin_opcodes): Use the new position-based read-write flags 347*a1ba9ba4Schristos instead of field-based ones. Use UDI for "udi..." instructions. 348*a1ba9ba4Schristos * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 349*a1ba9ba4Schristos New macros. 350*a1ba9ba4Schristos (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. 351*a1ba9ba4Schristos (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. 352*a1ba9ba4Schristos (WR_SP, RD_16): New macros. 353*a1ba9ba4Schristos (RD_SP): Redefine as an INSN2_* flag. 354*a1ba9ba4Schristos (MOD_SP): Redefine in terms of RD_SP and WR_SP. 355*a1ba9ba4Schristos (mips16_opcodes): Use the new position-based read-write flags 356*a1ba9ba4Schristos instead of field-based ones. Use RD_16 for "nop". Move RD_SP to 357*a1ba9ba4Schristos pinfo2 field. 358*a1ba9ba4Schristos * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 359*a1ba9ba4Schristos New macros. 360*a1ba9ba4Schristos (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) 361*a1ba9ba4Schristos (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) 362*a1ba9ba4Schristos (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. 363*a1ba9ba4Schristos (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. 364*a1ba9ba4Schristos (micromips_opcodes): Use the new position-based read-write flags 365*a1ba9ba4Schristos instead of field-based ones. 366*a1ba9ba4Schristos * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. 367*a1ba9ba4Schristos (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead 368*a1ba9ba4Schristos of field-based flags. 369*a1ba9ba4Schristos 370*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 371*a1ba9ba4Schristos 372*a1ba9ba4Schristos * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. 373*a1ba9ba4Schristos (WR_SP): Replace with... 374*a1ba9ba4Schristos (MOD_SP): ...this. 375*a1ba9ba4Schristos (mips16_opcodes): Update accordingly. 376*a1ba9ba4Schristos * mips-dis.c (print_insn_mips16): Likewise. 377*a1ba9ba4Schristos 378*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 379*a1ba9ba4Schristos 380*a1ba9ba4Schristos * mips16-opc.c (mips16_opcodes): Reformat. 381*a1ba9ba4Schristos 382*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 383*a1ba9ba4Schristos 384*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags 385*a1ba9ba4Schristos for operands that are hard-coded to $0. 386*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Likewise. 387*a1ba9ba4Schristos 388*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 389*a1ba9ba4Schristos 390*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d 391*a1ba9ba4Schristos for the single-operand forms of JALR and JALR.HB. 392*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB 393*a1ba9ba4Schristos and JALRS.HB. 394*a1ba9ba4Schristos 395*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 396*a1ba9ba4Schristos 397*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector 398*a1ba9ba4Schristos instructions. Fix them to use WR_MACC instead of WR_CC and 399*a1ba9ba4Schristos add missing RD_MACCs. 400*a1ba9ba4Schristos 401*a1ba9ba4Schristos2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 402*a1ba9ba4Schristos 403*a1ba9ba4Schristos * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address. 404*a1ba9ba4Schristos 405*a1ba9ba4Schristos2013-07-29 Peter Bergner <bergner@vnet.ibm.com> 406*a1ba9ba4Schristos 407*a1ba9ba4Schristos * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect. 408*a1ba9ba4Schristos 409*a1ba9ba4Schristos2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> 410*a1ba9ba4Schristos Alexander Ivchenko <alexander.ivchenko@intel.com> 411*a1ba9ba4Schristos Maxim Kuznetsov <maxim.kuznetsov@intel.com> 412*a1ba9ba4Schristos Sergey Lega <sergey.s.lega@intel.com> 413*a1ba9ba4Schristos Anna Tikhonova <anna.tikhonova@intel.com> 414*a1ba9ba4Schristos Ilya Tocar <ilya.tocar@intel.com> 415*a1ba9ba4Schristos Andrey Turetskiy <andrey.turetskiy@intel.com> 416*a1ba9ba4Schristos Ilya Verbin <ilya.verbin@intel.com> 417*a1ba9ba4Schristos Kirill Yukhin <kirill.yukhin@intel.com> 418*a1ba9ba4Schristos Michael Zolotukhin <michael.v.zolotukhin@intel.com> 419*a1ba9ba4Schristos 420*a1ba9ba4Schristos * i386-dis-evex.h: New. 421*a1ba9ba4Schristos * i386-dis.c (OP_Rounding): New. 422*a1ba9ba4Schristos (VPCMP_Fixup): New. 423*a1ba9ba4Schristos (OP_Mask): New. 424*a1ba9ba4Schristos (Rdq): New. 425*a1ba9ba4Schristos (XMxmmq): New. 426*a1ba9ba4Schristos (EXdScalarS): New. 427*a1ba9ba4Schristos (EXymm): New. 428*a1ba9ba4Schristos (EXEvexHalfBcstXmmq): New. 429*a1ba9ba4Schristos (EXxmm_mdq): New. 430*a1ba9ba4Schristos (EXEvexXGscat): New. 431*a1ba9ba4Schristos (EXEvexXNoBcst): New. 432*a1ba9ba4Schristos (VPCMP): New. 433*a1ba9ba4Schristos (EXxEVexR): New. 434*a1ba9ba4Schristos (EXxEVexS): New. 435*a1ba9ba4Schristos (XMask): New. 436*a1ba9ba4Schristos (MaskG): New. 437*a1ba9ba4Schristos (MaskE): New. 438*a1ba9ba4Schristos (MaskR): New. 439*a1ba9ba4Schristos (MaskVex): New. 440*a1ba9ba4Schristos (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, 441*a1ba9ba4Schristos evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, 442*a1ba9ba4Schristos evex_rounding_mode, evex_sae_mode, mask_mode. 443*a1ba9ba4Schristos (USE_EVEX_TABLE): New. 444*a1ba9ba4Schristos (EVEX_TABLE): New. 445*a1ba9ba4Schristos (EVEX enum): New. 446*a1ba9ba4Schristos (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, 447*a1ba9ba4Schristos REG_EVEX_0F38C7. 448*a1ba9ba4Schristos (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, 449*a1ba9ba4Schristos MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, 450*a1ba9ba4Schristos MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, 451*a1ba9ba4Schristos MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, 452*a1ba9ba4Schristos MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, 453*a1ba9ba4Schristos MOD_EVEX_0F38C7_REG_6. 454*a1ba9ba4Schristos (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, 455*a1ba9ba4Schristos PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, 456*a1ba9ba4Schristos PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, 457*a1ba9ba4Schristos PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, 458*a1ba9ba4Schristos PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, 459*a1ba9ba4Schristos PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, 460*a1ba9ba4Schristos PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, 461*a1ba9ba4Schristos PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, 462*a1ba9ba4Schristos PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, 463*a1ba9ba4Schristos PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, 464*a1ba9ba4Schristos PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, 465*a1ba9ba4Schristos PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, 466*a1ba9ba4Schristos PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, 467*a1ba9ba4Schristos PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, 468*a1ba9ba4Schristos PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, 469*a1ba9ba4Schristos PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, 470*a1ba9ba4Schristos PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, 471*a1ba9ba4Schristos PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, 472*a1ba9ba4Schristos PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, 473*a1ba9ba4Schristos PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, 474*a1ba9ba4Schristos PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, 475*a1ba9ba4Schristos PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, 476*a1ba9ba4Schristos PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, 477*a1ba9ba4Schristos PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, 478*a1ba9ba4Schristos PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, 479*a1ba9ba4Schristos PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, 480*a1ba9ba4Schristos PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, 481*a1ba9ba4Schristos PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, 482*a1ba9ba4Schristos PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, 483*a1ba9ba4Schristos PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, 484*a1ba9ba4Schristos PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, 485*a1ba9ba4Schristos PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, 486*a1ba9ba4Schristos PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, 487*a1ba9ba4Schristos PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, 488*a1ba9ba4Schristos PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, 489*a1ba9ba4Schristos PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, 490*a1ba9ba4Schristos PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, 491*a1ba9ba4Schristos PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, 492*a1ba9ba4Schristos PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, 493*a1ba9ba4Schristos PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, 494*a1ba9ba4Schristos PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, 495*a1ba9ba4Schristos PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, 496*a1ba9ba4Schristos PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, 497*a1ba9ba4Schristos PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, 498*a1ba9ba4Schristos PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, 499*a1ba9ba4Schristos PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, 500*a1ba9ba4Schristos PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, 501*a1ba9ba4Schristos PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, 502*a1ba9ba4Schristos PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, 503*a1ba9ba4Schristos PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, 504*a1ba9ba4Schristos PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, 505*a1ba9ba4Schristos PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, 506*a1ba9ba4Schristos PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, 507*a1ba9ba4Schristos PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, 508*a1ba9ba4Schristos PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, 509*a1ba9ba4Schristos PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, 510*a1ba9ba4Schristos PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, 511*a1ba9ba4Schristos PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, 512*a1ba9ba4Schristos PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, 513*a1ba9ba4Schristos PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, 514*a1ba9ba4Schristos PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, 515*a1ba9ba4Schristos PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, 516*a1ba9ba4Schristos PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, 517*a1ba9ba4Schristos PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, 518*a1ba9ba4Schristos PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, 519*a1ba9ba4Schristos PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, 520*a1ba9ba4Schristos PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, 521*a1ba9ba4Schristos PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, 522*a1ba9ba4Schristos PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, 523*a1ba9ba4Schristos PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, 524*a1ba9ba4Schristos PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, 525*a1ba9ba4Schristos PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, 526*a1ba9ba4Schristos PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, 527*a1ba9ba4Schristos PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, 528*a1ba9ba4Schristos PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, 529*a1ba9ba4Schristos PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, 530*a1ba9ba4Schristos PREFIX_EVEX_0F3A55. 531*a1ba9ba4Schristos (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, 532*a1ba9ba4Schristos VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, 533*a1ba9ba4Schristos VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, 534*a1ba9ba4Schristos VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, 535*a1ba9ba4Schristos VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, 536*a1ba9ba4Schristos VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, 537*a1ba9ba4Schristos VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, 538*a1ba9ba4Schristos VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, 539*a1ba9ba4Schristos VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, 540*a1ba9ba4Schristos VEX_W_0F3A32_P_2_LEN_0. 541*a1ba9ba4Schristos (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, 542*a1ba9ba4Schristos EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, 543*a1ba9ba4Schristos EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, 544*a1ba9ba4Schristos EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, 545*a1ba9ba4Schristos EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, 546*a1ba9ba4Schristos EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, 547*a1ba9ba4Schristos EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, 548*a1ba9ba4Schristos EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, 549*a1ba9ba4Schristos EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, 550*a1ba9ba4Schristos EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, 551*a1ba9ba4Schristos EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, 552*a1ba9ba4Schristos EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, 553*a1ba9ba4Schristos EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, 554*a1ba9ba4Schristos EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, 555*a1ba9ba4Schristos EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, 556*a1ba9ba4Schristos EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, 557*a1ba9ba4Schristos EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, 558*a1ba9ba4Schristos EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, 559*a1ba9ba4Schristos EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, 560*a1ba9ba4Schristos EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, 561*a1ba9ba4Schristos EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, 562*a1ba9ba4Schristos EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, 563*a1ba9ba4Schristos EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, 564*a1ba9ba4Schristos EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, 565*a1ba9ba4Schristos EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, 566*a1ba9ba4Schristos EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, 567*a1ba9ba4Schristos EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, 568*a1ba9ba4Schristos EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, 569*a1ba9ba4Schristos EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, 570*a1ba9ba4Schristos EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, 571*a1ba9ba4Schristos EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, 572*a1ba9ba4Schristos EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, 573*a1ba9ba4Schristos EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, 574*a1ba9ba4Schristos EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, 575*a1ba9ba4Schristos EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, 576*a1ba9ba4Schristos EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, 577*a1ba9ba4Schristos EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, 578*a1ba9ba4Schristos EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, 579*a1ba9ba4Schristos EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, 580*a1ba9ba4Schristos EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, 581*a1ba9ba4Schristos EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, 582*a1ba9ba4Schristos EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, 583*a1ba9ba4Schristos EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, 584*a1ba9ba4Schristos EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, 585*a1ba9ba4Schristos EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, 586*a1ba9ba4Schristos EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, 587*a1ba9ba4Schristos EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, 588*a1ba9ba4Schristos EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, 589*a1ba9ba4Schristos EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, 590*a1ba9ba4Schristos EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, 591*a1ba9ba4Schristos EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, 592*a1ba9ba4Schristos EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, 593*a1ba9ba4Schristos EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, 594*a1ba9ba4Schristos EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. 595*a1ba9ba4Schristos (struct vex): Add fields evex, r, v, mask_register_specifier, 596*a1ba9ba4Schristos zeroing, ll, b. 597*a1ba9ba4Schristos (intel_names_xmm): Add upper 16 registers. 598*a1ba9ba4Schristos (att_names_xmm): Ditto. 599*a1ba9ba4Schristos (intel_names_ymm): Ditto. 600*a1ba9ba4Schristos (att_names_ymm): Ditto. 601*a1ba9ba4Schristos (names_zmm): New. 602*a1ba9ba4Schristos (intel_names_zmm): Ditto. 603*a1ba9ba4Schristos (att_names_zmm): Ditto. 604*a1ba9ba4Schristos (names_mask): Ditto. 605*a1ba9ba4Schristos (intel_names_mask): Ditto. 606*a1ba9ba4Schristos (att_names_mask): Ditto. 607*a1ba9ba4Schristos (names_rounding): Ditto. 608*a1ba9ba4Schristos (names_broadcast): Ditto. 609*a1ba9ba4Schristos (x86_64_table): Add escape to evex-table. 610*a1ba9ba4Schristos (reg_table): Include reg_table evex-entries from 611*a1ba9ba4Schristos i386-dis-evex.h. Fix prefetchwt1 instruction. 612*a1ba9ba4Schristos (prefix_table): Add entries for new instructions. 613*a1ba9ba4Schristos (vex_table): Ditto. 614*a1ba9ba4Schristos (vex_len_table): Ditto. 615*a1ba9ba4Schristos (vex_w_table): Ditto. 616*a1ba9ba4Schristos (mod_table): Ditto. 617*a1ba9ba4Schristos (get_valid_dis386): Properly handle new instructions. 618*a1ba9ba4Schristos (print_insn): Handle zmm and mask registers, print mask operand. 619*a1ba9ba4Schristos (intel_operand_size): Support EVEX, new modes and sizes. 620*a1ba9ba4Schristos (OP_E_register): Handle new modes. 621*a1ba9ba4Schristos (OP_E_memory): Ditto. 622*a1ba9ba4Schristos (OP_G): Ditto. 623*a1ba9ba4Schristos (OP_XMM): Ditto. 624*a1ba9ba4Schristos (OP_EX): Ditto. 625*a1ba9ba4Schristos (OP_VEX): Ditto. 626*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and 627*a1ba9ba4Schristos CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, 628*a1ba9ba4Schristos CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. 629*a1ba9ba4Schristos (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, 630*a1ba9ba4Schristos CpuAVX512PF and CpuVREX. 631*a1ba9ba4Schristos (operand_type_init): Add OPERAND_TYPE_REGZMM, 632*a1ba9ba4Schristos OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. 633*a1ba9ba4Schristos (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, 634*a1ba9ba4Schristos StaticRounding, SAE, Disp8MemShift, NoDefMask. 635*a1ba9ba4Schristos (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. 636*a1ba9ba4Schristos * i386-init.h: Regenerate. 637*a1ba9ba4Schristos * i386-opc.h (CpuAVX512F): New. 638*a1ba9ba4Schristos (CpuAVX512CD): New. 639*a1ba9ba4Schristos (CpuAVX512ER): New. 640*a1ba9ba4Schristos (CpuAVX512PF): New. 641*a1ba9ba4Schristos (CpuVREX): New. 642*a1ba9ba4Schristos (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, 643*a1ba9ba4Schristos cpuavx512pf and cpuvrex fields. 644*a1ba9ba4Schristos (VecSIB): Add VecSIB512. 645*a1ba9ba4Schristos (EVex): New. 646*a1ba9ba4Schristos (Masking): New. 647*a1ba9ba4Schristos (VecESize): New. 648*a1ba9ba4Schristos (Broadcast): New. 649*a1ba9ba4Schristos (StaticRounding): New. 650*a1ba9ba4Schristos (SAE): New. 651*a1ba9ba4Schristos (Disp8MemShift): New. 652*a1ba9ba4Schristos (NoDefMask): New. 653*a1ba9ba4Schristos (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, 654*a1ba9ba4Schristos staticrounding, sae, disp8memshift and nodefmask. 655*a1ba9ba4Schristos (RegZMM): New. 656*a1ba9ba4Schristos (Zmmword): Ditto. 657*a1ba9ba4Schristos (Vec_Disp8): Ditto. 658*a1ba9ba4Schristos (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 659*a1ba9ba4Schristos fields. 660*a1ba9ba4Schristos (RegVRex): New. 661*a1ba9ba4Schristos * i386-opc.tbl: Add AVX512 instructions. 662*a1ba9ba4Schristos * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM 663*a1ba9ba4Schristos registers, mask registers. 664*a1ba9ba4Schristos * i386-tbl.h: Regenerate. 665*a1ba9ba4Schristos 666*a1ba9ba4Schristos2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> 667*a1ba9ba4Schristos 668*a1ba9ba4Schristos PR gas/15220 669*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for 670*a1ba9ba4Schristos Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. 671*a1ba9ba4Schristos 672*a1ba9ba4Schristos2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> 673*a1ba9ba4Schristos 674*a1ba9ba4Schristos * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9, 675*a1ba9ba4Schristos PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, 676*a1ba9ba4Schristos PREFIX_0F3ACC. 677*a1ba9ba4Schristos (prefix_table): Updated. 678*a1ba9ba4Schristos (three_byte_table): Likewise. 679*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS. 680*a1ba9ba4Schristos (cpu_flags): Add CpuSHA. 681*a1ba9ba4Schristos (i386_cpu_flags): Add cpusha. 682*a1ba9ba4Schristos * i386-init.h: Regenerate. 683*a1ba9ba4Schristos * i386-opc.h (CpuSHA): New. 684*a1ba9ba4Schristos (CpuUnused): Restored. 685*a1ba9ba4Schristos (i386_cpu_flags): Add cpusha. 686*a1ba9ba4Schristos * i386-opc.tbl: Add SHA instructions. 687*a1ba9ba4Schristos * i386-tbl.h: Regenerate. 688*a1ba9ba4Schristos 689*a1ba9ba4Schristos2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> 690*a1ba9ba4Schristos Kirill Yukhin <kirill.yukhin@intel.com> 691*a1ba9ba4Schristos Michael Zolotukhin <michael.v.zolotukhin@intel.com> 692*a1ba9ba4Schristos 693*a1ba9ba4Schristos * i386-dis.c (BND_Fixup): New. 694*a1ba9ba4Schristos (Ebnd): New. 695*a1ba9ba4Schristos (Ev_bnd): New. 696*a1ba9ba4Schristos (Gbnd): New. 697*a1ba9ba4Schristos (BND): New. 698*a1ba9ba4Schristos (v_bnd_mode): New. 699*a1ba9ba4Schristos (bnd_mode): New. 700*a1ba9ba4Schristos (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, 701*a1ba9ba4Schristos MOD_0F1B_PREFIX_1. 702*a1ba9ba4Schristos (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B. 703*a1ba9ba4Schristos (dis tables): Replace XX with BND for near branch and call 704*a1ba9ba4Schristos instructions. 705*a1ba9ba4Schristos (prefix_table): Add new entries. 706*a1ba9ba4Schristos (mod_table): Likewise. 707*a1ba9ba4Schristos (names_bnd): New. 708*a1ba9ba4Schristos (intel_names_bnd): New. 709*a1ba9ba4Schristos (att_names_bnd): New. 710*a1ba9ba4Schristos (BND_PREFIX): New. 711*a1ba9ba4Schristos (prefix_name): Handle BND_PREFIX. 712*a1ba9ba4Schristos (print_insn): Initialize names_bnd. 713*a1ba9ba4Schristos (intel_operand_size): Handle new modes. 714*a1ba9ba4Schristos (OP_E_register): Likewise. 715*a1ba9ba4Schristos (OP_E_memory): Likewise. 716*a1ba9ba4Schristos (OP_G): Likewise. 717*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Add CpuMPX. 718*a1ba9ba4Schristos (cpu_flags): Add CpuMPX. 719*a1ba9ba4Schristos (operand_type_init): Add RegBND. 720*a1ba9ba4Schristos (opcode_modifiers): Add BNDPrefixOk. 721*a1ba9ba4Schristos (operand_types): Add RegBND. 722*a1ba9ba4Schristos * i386-init.h: Regenerate. 723*a1ba9ba4Schristos * i386-opc.h (CpuMPX): New. 724*a1ba9ba4Schristos (CpuUnused): Comment out. 725*a1ba9ba4Schristos (i386_cpu_flags): Add cpumpx. 726*a1ba9ba4Schristos (BNDPrefixOk): New. 727*a1ba9ba4Schristos (i386_opcode_modifier): Add bndprefixok. 728*a1ba9ba4Schristos (RegBND): New. 729*a1ba9ba4Schristos (i386_operand_type): Add regbnd. 730*a1ba9ba4Schristos * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. 731*a1ba9ba4Schristos Add MPX instructions and bnd prefix. 732*a1ba9ba4Schristos * i386-reg.tbl: Add bnd0-bnd3 registers. 733*a1ba9ba4Schristos * i386-tbl.h: Regenerate. 734*a1ba9ba4Schristos 735*a1ba9ba4Schristos2013-07-17 Richard Sandiford <rdsandiford@googlemail.com> 736*a1ba9ba4Schristos 737*a1ba9ba4Schristos * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add 738*a1ba9ba4Schristos ATTRIBUTE_UNUSED. 739*a1ba9ba4Schristos 740*a1ba9ba4Schristos2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 741*a1ba9ba4Schristos 742*a1ba9ba4Schristos * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove 743*a1ba9ba4Schristos special rules. 744*a1ba9ba4Schristos * Makefile.in: Regenerate. 745*a1ba9ba4Schristos * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize 746*a1ba9ba4Schristos all fields. Reformat. 747*a1ba9ba4Schristos 748*a1ba9ba4Schristos2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 749*a1ba9ba4Schristos 750*a1ba9ba4Schristos * mips16-opc.c: Include mips-formats.h. 751*a1ba9ba4Schristos (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New 752*a1ba9ba4Schristos static arrays. 753*a1ba9ba4Schristos (decode_mips16_operand): New function. 754*a1ba9ba4Schristos * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete. 755*a1ba9ba4Schristos (print_insn_arg): Handle OP_ENTRY_EXIT list. 756*a1ba9ba4Schristos Abort for OP_SAVE_RESTORE_LIST. 757*a1ba9ba4Schristos (print_mips16_insn_arg): Change interface. Use mips_operand 758*a1ba9ba4Schristos structures. Delete GET_OP_S. Move GET_OP definition to... 759*a1ba9ba4Schristos (print_insn_mips16): ...here. Call init_print_arg_state. 760*a1ba9ba4Schristos Update the call to print_mips16_insn_arg. 761*a1ba9ba4Schristos 762*a1ba9ba4Schristos2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 763*a1ba9ba4Schristos 764*a1ba9ba4Schristos * mips-formats.h: New file. 765*a1ba9ba4Schristos * mips-opc.c: Include mips-formats.h. 766*a1ba9ba4Schristos (reg_0_map): New static array. 767*a1ba9ba4Schristos (decode_mips_operand): New function. 768*a1ba9ba4Schristos * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. 769*a1ba9ba4Schristos (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) 770*a1ba9ba4Schristos (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) 771*a1ba9ba4Schristos (int_c_map): New static arrays. 772*a1ba9ba4Schristos (decode_micromips_operand): New function. 773*a1ba9ba4Schristos * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) 774*a1ba9ba4Schristos (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) 775*a1ba9ba4Schristos (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) 776*a1ba9ba4Schristos (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) 777*a1ba9ba4Schristos (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) 778*a1ba9ba4Schristos (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) 779*a1ba9ba4Schristos (micromips_imm_b_map, micromips_imm_c_map): Delete. 780*a1ba9ba4Schristos (print_reg): New function. 781*a1ba9ba4Schristos (mips_print_arg_state): New structure. 782*a1ba9ba4Schristos (init_print_arg_state, print_insn_arg): New functions. 783*a1ba9ba4Schristos (print_insn_args): Change interface and use mips_operand structures. 784*a1ba9ba4Schristos Delete GET_OP_S. Move GET_OP definition to... 785*a1ba9ba4Schristos (print_insn_mips): ...here. Update the call to print_insn_args. 786*a1ba9ba4Schristos (print_insn_micromips): Use print_insn_args. 787*a1ba9ba4Schristos 788*a1ba9ba4Schristos2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 789*a1ba9ba4Schristos 790*a1ba9ba4Schristos * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands 791*a1ba9ba4Schristos in macros. 792*a1ba9ba4Schristos 793*a1ba9ba4Schristos2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 794*a1ba9ba4Schristos 795*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for 796*a1ba9ba4Schristos ADDA.S, MULA.S and SUBA.S. 797*a1ba9ba4Schristos 798*a1ba9ba4Schristos2013-07-08 H.J. Lu <hongjiu.lu@intel.com> 799*a1ba9ba4Schristos 800*a1ba9ba4Schristos PR gas/13572 801*a1ba9ba4Schristos * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. 802*a1ba9ba4Schristos * i386-tbl.h: Regenerated. 803*a1ba9ba4Schristos 804*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 805*a1ba9ba4Schristos 806*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD 807*a1ba9ba4Schristos and SD A(B) macros up. 808*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Likewise. 809*a1ba9ba4Schristos 810*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 811*a1ba9ba4Schristos 812*a1ba9ba4Schristos * mips16-opc.c: Add entries for argumentless "entry" and "exit" 813*a1ba9ba4Schristos instructions. 814*a1ba9ba4Schristos 815*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 816*a1ba9ba4Schristos 817*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 818*a1ba9ba4Schristos MDMX-like instructions. 819*a1ba9ba4Schristos * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when 820*a1ba9ba4Schristos printing "Q" operands for INSN_5400 instructions. 821*a1ba9ba4Schristos 822*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 823*a1ba9ba4Schristos 824*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and 825*a1ba9ba4Schristos "+S" for "cins". 826*a1ba9ba4Schristos * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. 827*a1ba9ba4Schristos Combine cases. 828*a1ba9ba4Schristos 829*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 830*a1ba9ba4Schristos 831*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for 832*a1ba9ba4Schristos "jalx". 833*a1ba9ba4Schristos * mips16-opc.c (mips16_opcodes): Likewise. 834*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Likewise. 835*a1ba9ba4Schristos * mips-dis.c (print_insn_args, print_mips16_insn_arg) 836*a1ba9ba4Schristos (print_insn_mips16): Handle "+i". 837*a1ba9ba4Schristos (print_insn_micromips): Likewise. Conditionally preserve the 838*a1ba9ba4Schristos ISA bit for "a" but not for "+i". 839*a1ba9ba4Schristos 840*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 841*a1ba9ba4Schristos 842*a1ba9ba4Schristos * micromips-opc.c (WR_mhi): Rename to.. 843*a1ba9ba4Schristos (WR_mh): ...this. 844*a1ba9ba4Schristos (micromips_opcodes): Update "movep" entry accordingly. Replace 845*a1ba9ba4Schristos "mh,mi" with "mh". 846*a1ba9ba4Schristos * mips-dis.c (micromips_to_32_reg_h_map): Rename to... 847*a1ba9ba4Schristos (micromips_to_32_reg_h_map1): ...this. 848*a1ba9ba4Schristos (micromips_to_32_reg_i_map): Rename to... 849*a1ba9ba4Schristos (micromips_to_32_reg_h_map2): ...this. 850*a1ba9ba4Schristos (print_micromips_insn): Remove "mi" case. Print both registers 851*a1ba9ba4Schristos in the pair for "mh". 852*a1ba9ba4Schristos 853*a1ba9ba4Schristos2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 854*a1ba9ba4Schristos 855*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. 856*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Likewise. 857*a1ba9ba4Schristos * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" 858*a1ba9ba4Schristos and "+T" handling. Check for a "0" suffix when deciding whether to 859*a1ba9ba4Schristos use coprocessor 0 names. In that case, also check for ",H" selectors. 860*a1ba9ba4Schristos 861*a1ba9ba4Schristos2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 862*a1ba9ba4Schristos 863*a1ba9ba4Schristos * s390-opc.c (J12_12, J24_24): New macros. 864*a1ba9ba4Schristos (INSTR_MII_UPI): Rename to INSTR_MII_UPP. 865*a1ba9ba4Schristos (MASK_MII_UPI): Rename to MASK_MII_UPP. 866*a1ba9ba4Schristos * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. 867*a1ba9ba4Schristos 868*a1ba9ba4Schristos2013-07-04 Alan Modra <amodra@gmail.com> 869*a1ba9ba4Schristos 870*a1ba9ba4Schristos * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu. 871*a1ba9ba4Schristos 872*a1ba9ba4Schristos2013-06-26 Nick Clifton <nickc@redhat.com> 873*a1ba9ba4Schristos 874*a1ba9ba4Schristos * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss 875*a1ba9ba4Schristos field when checking for type 2 nop. 876*a1ba9ba4Schristos * rx-decode.c: Regenerate. 877*a1ba9ba4Schristos 878*a1ba9ba4Schristos2013-06-25 Maciej W. Rozycki <macro@codesourcery.com> 879*a1ba9ba4Schristos 880*a1ba9ba4Schristos * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" 881*a1ba9ba4Schristos and "movep" macros. 882*a1ba9ba4Schristos 883*a1ba9ba4Schristos2013-06-24 Maciej W. Rozycki <macro@codesourcery.com> 884*a1ba9ba4Schristos 885*a1ba9ba4Schristos * mips-dis.c (is_mips16_plt_tail): New function. 886*a1ba9ba4Schristos (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address 887*a1ba9ba4Schristos word. 888*a1ba9ba4Schristos (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries. 889*a1ba9ba4Schristos 890*a1ba9ba4Schristos2013-06-21 DJ Delorie <dj@redhat.com> 891*a1ba9ba4Schristos 892*a1ba9ba4Schristos * msp430-decode.opc: New. 893*a1ba9ba4Schristos * msp430-decode.c: New/generated. 894*a1ba9ba4Schristos * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. 895*a1ba9ba4Schristos (MAINTAINER_CLEANFILES): Likewise. 896*a1ba9ba4Schristos Add rule to build msp430-decode.c frommsp430decode.opc 897*a1ba9ba4Schristos using the opc2c program. 898*a1ba9ba4Schristos * Makefile.in: Regenerate. 899*a1ba9ba4Schristos * configure.in: Add msp430-decode.lo to msp430 architecture files. 900*a1ba9ba4Schristos * configure: Regenerate. 901*a1ba9ba4Schristos 902*a1ba9ba4Schristos2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com> 903*a1ba9ba4Schristos 904*a1ba9ba4Schristos * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it. 905*a1ba9ba4Schristos (SYMTAB_AVAILABLE): Removed. 906*a1ba9ba4Schristos (#include "elf/aarch64.h): Ditto. 907*a1ba9ba4Schristos 908*a1ba9ba4Schristos2013-06-17 Catherine Moore <clm@codesourcery.com> 909*a1ba9ba4Schristos Maciej W. Rozycki <macro@codesourcery.com> 910*a1ba9ba4Schristos Chao-Ying Fu <fu@mips.com> 911*a1ba9ba4Schristos 912*a1ba9ba4Schristos * micromips-opc.c (EVA): Define. 913*a1ba9ba4Schristos (TLBINV): Define. 914*a1ba9ba4Schristos (micromips_opcodes): Add EVA opcodes. 915*a1ba9ba4Schristos * mips-dis.c (mips_arch_choices): Update for ASE_EVA. 916*a1ba9ba4Schristos (print_insn_args): Handle EVA offsets. 917*a1ba9ba4Schristos (print_insn_micromips): Likewise. 918*a1ba9ba4Schristos * mips-opc.c (EVA): Define. 919*a1ba9ba4Schristos (TLBINV): Define. 920*a1ba9ba4Schristos (mips_builtin_opcodes): Add EVA opcodes. 921*a1ba9ba4Schristos 922*a1ba9ba4Schristos2013-06-17 Alan Modra <amodra@gmail.com> 923*a1ba9ba4Schristos 924*a1ba9ba4Schristos * Makefile.am (mips-opc.lo): Add rules to create automatic 925*a1ba9ba4Schristos dependency files. Pass archdefs. 926*a1ba9ba4Schristos (micromips-opc.lo, mips16-opc.lo): Likewise. 927*a1ba9ba4Schristos * Makefile.in: Regenerate. 928*a1ba9ba4Schristos 929*a1ba9ba4Schristos2013-06-14 DJ Delorie <dj@redhat.com> 930*a1ba9ba4Schristos 931*a1ba9ba4Schristos * rx-decode.opc (rx_decode_opcode): Bit operations on 932*a1ba9ba4Schristos registers are 32-bit operations, not 8-bit operations. 933*a1ba9ba4Schristos * rx-decode.c: Regenerate. 934*a1ba9ba4Schristos 935*a1ba9ba4Schristos2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com> 936*a1ba9ba4Schristos 937*a1ba9ba4Schristos * micromips-opc.c (IVIRT): New define. 938*a1ba9ba4Schristos (IVIRT64): New define. 939*a1ba9ba4Schristos (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, 940*a1ba9ba4Schristos tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions. 941*a1ba9ba4Schristos 942*a1ba9ba4Schristos * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, 943*a1ba9ba4Schristos dmtgc0 to print cp0 names. 944*a1ba9ba4Schristos 945*a1ba9ba4Schristos2013-06-09 Sandra Loosemore <sandra@codesourcery.com> 946*a1ba9ba4Schristos 947*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b" 948*a1ba9ba4Schristos argument. 949*a1ba9ba4Schristos 950*a1ba9ba4Schristos2013-06-08 Catherine Moore <clm@codesourcery.com> 951*a1ba9ba4Schristos Richard Sandiford <rdsandiford@googlemail.com> 952*a1ba9ba4Schristos 953*a1ba9ba4Schristos * micromips-opc.c (D32, D33, MC): Update definitions. 954*a1ba9ba4Schristos (micromips_opcodes): Initialize ase field. 955*a1ba9ba4Schristos * mips-dis.c (mips_arch_choice): Add ase field. 956*a1ba9ba4Schristos (mips_arch_choices): Initialize ase field. 957*a1ba9ba4Schristos (set_default_mips_dis_options): Declare and setup mips_ase. 958*a1ba9ba4Schristos * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 959*a1ba9ba4Schristos MT32, MC): Update definitions. 960*a1ba9ba4Schristos (mips_builtin_opcodes): Initialize ase field. 961*a1ba9ba4Schristos 962*a1ba9ba4Schristos2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com> 963*a1ba9ba4Schristos 964*a1ba9ba4Schristos * s390-opc.txt (flogr): Require a register pair destination. 965*a1ba9ba4Schristos 966*a1ba9ba4Schristos2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 967*a1ba9ba4Schristos 968*a1ba9ba4Schristos * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU 969*a1ba9ba4Schristos instruction format. 970*a1ba9ba4Schristos 971*a1ba9ba4Schristos2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> 972*a1ba9ba4Schristos 973*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. 974*a1ba9ba4Schristos 975*a1ba9ba4Schristos2013-05-20 Peter Bergner <bergner@vnet.ibm.com> 976*a1ba9ba4Schristos 977*a1ba9ba4Schristos * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8. 978*a1ba9ba4Schristos * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK, 979*a1ba9ba4Schristos XLS_MASK, PPCVSX2): New defines. 980*a1ba9ba4Schristos (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb, 981*a1ba9ba4Schristos fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, 982*a1ba9ba4Schristos mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp, 983*a1ba9ba4Schristos mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd, 984*a1ba9ba4Schristos mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx, 985*a1ba9ba4Schristos vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher, 986*a1ba9ba4Schristos vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd., 987*a1ba9ba4Schristos vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd, 988*a1ba9ba4Schristos vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw, 989*a1ba9ba4Schristos vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor, 990*a1ba9ba4Schristos vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh, 991*a1ba9ba4Schristos vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox, 992*a1ba9ba4Schristos vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, 993*a1ba9ba4Schristos vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, 994*a1ba9ba4Schristos xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, 995*a1ba9ba4Schristos xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, 996*a1ba9ba4Schristos xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp, 997*a1ba9ba4Schristos xssubsp, xxleqv, xxlnand, xxlorc>: New instructions. 998*a1ba9ba4Schristos <lxvx, stxvx>: New extended mnemonics. 999*a1ba9ba4Schristos 1000*a1ba9ba4Schristos2013-05-17 Alan Modra <amodra@gmail.com> 1001*a1ba9ba4Schristos 1002*a1ba9ba4Schristos * ia64-raw.tbl: Replace non-ASCII char. 1003*a1ba9ba4Schristos * ia64-waw.tbl: Likewise. 1004*a1ba9ba4Schristos * ia64-asmtab.c: Regenerate. 1005*a1ba9ba4Schristos 1006*a1ba9ba4Schristos2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com> 1007*a1ba9ba4Schristos 1008*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS. 1009*a1ba9ba4Schristos * i386-init.h: Regenerated. 1010*a1ba9ba4Schristos 1011*a1ba9ba4Schristos2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com> 1012*a1ba9ba4Schristos 1013*a1ba9ba4Schristos * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion. 1014*a1ba9ba4Schristos * aarch64-opc.c (operand_general_constraint_met_p): Relax the range 1015*a1ba9ba4Schristos check from [0, 255] to [-128, 255]. 1016*a1ba9ba4Schristos 1017*a1ba9ba4Schristos2013-05-09 Andrew Pinski <apinski@cavium.com> 1018*a1ba9ba4Schristos 1019*a1ba9ba4Schristos * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2. 1020*a1ba9ba4Schristos Add INSN_VIRT and INSN_VIRT64 to mips64r2. 1021*a1ba9ba4Schristos (parse_mips_dis_option): Handle the virt option. 1022*a1ba9ba4Schristos (print_insn_args): Handle "+J". 1023*a1ba9ba4Schristos (print_mips_disassembler_options): Print out message about virt64. 1024*a1ba9ba4Schristos * mips-opc.c (IVIRT): New define. 1025*a1ba9ba4Schristos (IVIRT64): New define. 1026*a1ba9ba4Schristos (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, 1027*a1ba9ba4Schristos tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. 1028*a1ba9ba4Schristos Move rfe to the bottom as it conflicts with tlbgp. 1029*a1ba9ba4Schristos 1030*a1ba9ba4Schristos2013-05-09 Alan Modra <amodra@gmail.com> 1031*a1ba9ba4Schristos 1032*a1ba9ba4Schristos * ppc-opc.c (extract_vlesi): Properly sign extend. 1033*a1ba9ba4Schristos (extract_vlensi): Likewise. Comment reason for setting invalid. 1034*a1ba9ba4Schristos 1035*a1ba9ba4Schristos2013-05-02 Nick Clifton <nickc@redhat.com> 1036*a1ba9ba4Schristos 1037*a1ba9ba4Schristos * msp430-dis.c: Add support for MSP430X instructions. 1038*a1ba9ba4Schristos 1039*a1ba9ba4Schristos2013-04-24 Sandra Loosemore <sandra@codesourcery.com> 1040*a1ba9ba4Schristos 1041*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register 1042*a1ba9ba4Schristos to "eccinj". 1043*a1ba9ba4Schristos 1044*a1ba9ba4Schristos2013-04-17 Wei-chen Wang <cole945@gmail.com> 1045*a1ba9ba4Schristos 1046*a1ba9ba4Schristos PR binutils/15369 1047*a1ba9ba4Schristos * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead 1048*a1ba9ba4Schristos of CGEN_CPU_ENDIAN. 1049*a1ba9ba4Schristos (hash_insns_list): Likewise. 1050*a1ba9ba4Schristos 1051*a1ba9ba4Schristos2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com> 1052*a1ba9ba4Schristos 1053*a1ba9ba4Schristos * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false 1054*a1ba9ba4Schristos warning workaround. 1055*a1ba9ba4Schristos 1056*a1ba9ba4Schristos2013-04-08 Jan Beulich <jbeulich@suse.com> 1057*a1ba9ba4Schristos 1058*a1ba9ba4Schristos * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries. 1059*a1ba9ba4Schristos * i386-tbl.h: Re-generate. 1060*a1ba9ba4Schristos 1061*a1ba9ba4Schristos2013-04-06 David S. Miller <davem@davemloft.net> 1062*a1ba9ba4Schristos 1063*a1ba9ba4Schristos * sparc-dis.c (compare_opcodes): When encountering multiple aliases 1064*a1ba9ba4Schristos of an opcode, prefer the one with F_PREFERRED set. 1065*a1ba9ba4Schristos * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, 1066*a1ba9ba4Schristos lzcnt, flush with '[address]' syntax, and missing cbcond pseudo 1067*a1ba9ba4Schristos ops. Make 64-bit VIS logical ops have "d" suffix in their names, 1068*a1ba9ba4Schristos mark existing mnenomics as aliases. Add "cc" suffix to edge 1069*a1ba9ba4Schristos instructions generating condition codes, mark existing mnenomics 1070*a1ba9ba4Schristos as aliases. Add "fp" prefix to VIS compare instructions, mark 1071*a1ba9ba4Schristos existing mnenomics as aliases. 1072*a1ba9ba4Schristos 1073*a1ba9ba4Schristos2013-04-03 Nick Clifton <nickc@redhat.com> 1074*a1ba9ba4Schristos 1075*a1ba9ba4Schristos * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the 1076*a1ba9ba4Schristos destination address by subtracting the operand from the current 1077*a1ba9ba4Schristos address. 1078*a1ba9ba4Schristos * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store 1079*a1ba9ba4Schristos a positive value in the insn. 1080*a1ba9ba4Schristos (extract_u16_loop): Do not negate the returned value. 1081*a1ba9ba4Schristos (D16_LOOP): Add V850_INVERSE_PCREL flag. 1082*a1ba9ba4Schristos 1083*a1ba9ba4Schristos (ceilf.sw): Remove duplicate entry. 1084*a1ba9ba4Schristos (cvtf.hs): New entry. 1085*a1ba9ba4Schristos (cvtf.sh): Likewise. 1086*a1ba9ba4Schristos (fmaf.s): Likewise. 1087*a1ba9ba4Schristos (fmsf.s): Likewise. 1088*a1ba9ba4Schristos (fnmaf.s): Likewise. 1089*a1ba9ba4Schristos (fnmsf.s): Likewise. 1090*a1ba9ba4Schristos (maddf.s): Restrict to E3V5 architectures. 1091*a1ba9ba4Schristos (msubf.s): Likewise. 1092*a1ba9ba4Schristos (nmaddf.s): Likewise. 1093*a1ba9ba4Schristos (nmsubf.s): Likewise. 1094*a1ba9ba4Schristos 1095*a1ba9ba4Schristos2013-03-27 H.J. Lu <hongjiu.lu@intel.com> 1096*a1ba9ba4Schristos 1097*a1ba9ba4Schristos * i386-dis.c (get_sib): Add the sizeflag argument. Properly 1098*a1ba9ba4Schristos check address mode. 1099*a1ba9ba4Schristos (print_insn): Pass sizeflag to get_sib. 1100*a1ba9ba4Schristos 1101*a1ba9ba4Schristos2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> 1102*a1ba9ba4Schristos 1103*a1ba9ba4Schristos PR binutils/15068 1104*a1ba9ba4Schristos * tic6x-dis.c: Add support for displaying 16-bit insns. 1105*a1ba9ba4Schristos 1106*a1ba9ba4Schristos2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> 1107*a1ba9ba4Schristos 1108*a1ba9ba4Schristos PR gas/15095 1109*a1ba9ba4Schristos * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have 1110*a1ba9ba4Schristos individual msb and lsb halves in src1 & src2 fields. Discard the 1111*a1ba9ba4Schristos src1 (lsb) value and only use src2 (msb), discarding bit 0, to 1112*a1ba9ba4Schristos follow what Ti SDK does in that case as any value in the src1 1113*a1ba9ba4Schristos field yields the same output with SDK disassembler. 1114*a1ba9ba4Schristos 1115*a1ba9ba4Schristos2013-03-12 Michael Eager <eager@eagercon.com> 1116*a1ba9ba4Schristos 1117*a1ba9ba4Schristos * opcodes/mips-dis.c (print_insn_args): Modify def of reg. 1118*a1ba9ba4Schristos 1119*a1ba9ba4Schristos2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 1120*a1ba9ba4Schristos 1121*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. 1122*a1ba9ba4Schristos 1123*a1ba9ba4Schristos2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 1124*a1ba9ba4Schristos 1125*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. 1126*a1ba9ba4Schristos 1127*a1ba9ba4Schristos2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 1128*a1ba9ba4Schristos 1129*a1ba9ba4Schristos * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register. 1130*a1ba9ba4Schristos 1131*a1ba9ba4Schristos2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1132*a1ba9ba4Schristos 1133*a1ba9ba4Schristos * arm-dis.c (arm_opcodes): Add entries for CRC instructions. 1134*a1ba9ba4Schristos (thumb32_opcodes): Likewise. 1135*a1ba9ba4Schristos (print_insn_thumb32): Handle 'S' control char. 1136*a1ba9ba4Schristos 1137*a1ba9ba4Schristos2013-03-08 Yann Sionneau <yann.sionneau@gmail.com> 1138*a1ba9ba4Schristos 1139*a1ba9ba4Schristos * lm32-desc.c: Regenerate. 1140*a1ba9ba4Schristos 1141*a1ba9ba4Schristos2013-03-01 H.J. Lu <hongjiu.lu@intel.com> 1142*a1ba9ba4Schristos 1143*a1ba9ba4Schristos * i386-reg.tbl (riz): Add RegRex64. 1144*a1ba9ba4Schristos * i386-tbl.h: Regenerated. 1145*a1ba9ba4Schristos 1146*a1ba9ba4Schristos2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> 1147*a1ba9ba4Schristos 1148*a1ba9ba4Schristos * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. 1149*a1ba9ba4Schristos (aarch64_feature_crc): New static. 1150*a1ba9ba4Schristos (CRC): New macro. 1151*a1ba9ba4Schristos (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, 1152*a1ba9ba4Schristos crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. 1153*a1ba9ba4Schristos * aarch64-asm-2.c: Re-generate. 1154*a1ba9ba4Schristos * aarch64-dis-2.c: Ditto. 1155*a1ba9ba4Schristos * aarch64-opc-2.c: Ditto. 1156*a1ba9ba4Schristos 1157*a1ba9ba4Schristos2013-02-27 Alan Modra <amodra@gmail.com> 1158*a1ba9ba4Schristos 1159*a1ba9ba4Schristos * rl78-decode.opc (rl78_decode_opcode): Fix typo. 1160*a1ba9ba4Schristos * rl78-decode.c: Regenerate. 1161*a1ba9ba4Schristos 1162*a1ba9ba4Schristos2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com> 1163*a1ba9ba4Schristos 1164*a1ba9ba4Schristos * rl78-decode.opc: Fix encoding of DIVWU insn. 1165*a1ba9ba4Schristos * rl78-decode.c: Regenerate. 1166*a1ba9ba4Schristos 1167*a1ba9ba4Schristos2013-02-19 H.J. Lu <hongjiu.lu@intel.com> 1168*a1ba9ba4Schristos 1169*a1ba9ba4Schristos PR gas/15159 1170*a1ba9ba4Schristos * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. 1171*a1ba9ba4Schristos 1172*a1ba9ba4Schristos * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. 1173*a1ba9ba4Schristos (cpu_flags): Add CpuSMAP. 1174*a1ba9ba4Schristos 1175*a1ba9ba4Schristos * i386-opc.h (CpuSMAP): New. 1176*a1ba9ba4Schristos (i386_cpu_flags): Add cpusmap. 1177*a1ba9ba4Schristos 1178*a1ba9ba4Schristos * i386-opc.tbl: Add clac and stac. 1179*a1ba9ba4Schristos 1180*a1ba9ba4Schristos * i386-init.h: Regenerated. 1181*a1ba9ba4Schristos * i386-tbl.h: Likewise. 1182*a1ba9ba4Schristos 1183*a1ba9ba4Schristos2013-02-15 Markos Chandras <markos.chandras@imgtec.com> 1184*a1ba9ba4Schristos 1185*a1ba9ba4Schristos * metag-dis.c: Initialize outf->bytes_per_chunk to 4 1186*a1ba9ba4Schristos which also makes the disassembler output be in little 1187*a1ba9ba4Schristos endian like it should be. 1188*a1ba9ba4Schristos 1189*a1ba9ba4Schristos2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com> 1190*a1ba9ba4Schristos 1191*a1ba9ba4Schristos * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' 1192*a1ba9ba4Schristos fields to NULL. 1193*a1ba9ba4Schristos (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. 1194*a1ba9ba4Schristos 1195*a1ba9ba4Schristos2013-02-13 Maciej W. Rozycki <macro@codesourcery.com> 1196*a1ba9ba4Schristos 1197*a1ba9ba4Schristos * mips-dis.c (is_compressed_mode_p): Only match symbols from the 1198*a1ba9ba4Schristos section disassembled. 1199*a1ba9ba4Schristos 1200*a1ba9ba4Schristos2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1201*a1ba9ba4Schristos 1202*a1ba9ba4Schristos * arm-dis.c: Update strht pattern. 1203*a1ba9ba4Schristos 1204*a1ba9ba4Schristos2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> 1205*a1ba9ba4Schristos 1206*a1ba9ba4Schristos * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for 1207*a1ba9ba4Schristos single-float. Disable ll, lld, sc and scd for EE. Disable the 1208*a1ba9ba4Schristos trunc.w.s macro for EE. 1209*a1ba9ba4Schristos 1210*a1ba9ba4Schristos2013-02-06 Sandra Loosemore <sandra@codesourcery.com> 1211*a1ba9ba4Schristos Andrew Jenner <andrew@codesourcery.com> 1212*a1ba9ba4Schristos 1213*a1ba9ba4Schristos Based on patches from Altera Corporation. 1214*a1ba9ba4Schristos 1215*a1ba9ba4Schristos * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and 1216*a1ba9ba4Schristos nios2-opc.c. 1217*a1ba9ba4Schristos * Makefile.in: Regenerated. 1218*a1ba9ba4Schristos * configure.in: Add case for bfd_nios2_arch. 1219*a1ba9ba4Schristos * configure: Regenerated. 1220*a1ba9ba4Schristos * disassemble.c (ARCH_nios2): Define. 1221*a1ba9ba4Schristos (disassembler): Add case for bfd_arch_nios2. 1222*a1ba9ba4Schristos * nios2-dis.c: New file. 1223*a1ba9ba4Schristos * nios2-opc.c: New file. 1224*a1ba9ba4Schristos 1225*a1ba9ba4Schristos2013-02-04 Alan Modra <amodra@gmail.com> 1226*a1ba9ba4Schristos 1227*a1ba9ba4Schristos * po/POTFILES.in: Regenerate. 1228*a1ba9ba4Schristos * rl78-decode.c: Regenerate. 1229*a1ba9ba4Schristos * rx-decode.c: Regenerate. 1230*a1ba9ba4Schristos 1231*a1ba9ba4Schristos2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> 1232*a1ba9ba4Schristos 1233*a1ba9ba4Schristos * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and 1234*a1ba9ba4Schristos ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. 1235*a1ba9ba4Schristos * aarch64-asm.c (convert_xtl_to_shll): New function. 1236*a1ba9ba4Schristos (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by 1237*a1ba9ba4Schristos calling convert_xtl_to_shll. 1238*a1ba9ba4Schristos * aarch64-dis.c (convert_shll_to_xtl): New function. 1239*a1ba9ba4Schristos (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by 1240*a1ba9ba4Schristos calling convert_shll_to_xtl. 1241*a1ba9ba4Schristos * aarch64-gen.c: Update copyright year. 1242*a1ba9ba4Schristos * aarch64-asm-2.c: Re-generate. 1243*a1ba9ba4Schristos * aarch64-dis-2.c: Re-generate. 1244*a1ba9ba4Schristos * aarch64-opc-2.c: Re-generate. 1245*a1ba9ba4Schristos 1246*a1ba9ba4Schristos2013-01-24 Nick Clifton <nickc@redhat.com> 1247*a1ba9ba4Schristos 1248*a1ba9ba4Schristos * v850-dis.c: Add support for e3v5 architecture. 1249*a1ba9ba4Schristos * v850-opc.c: Likewise. 1250*a1ba9ba4Schristos 1251*a1ba9ba4Schristos2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> 1252*a1ba9ba4Schristos 1253*a1ba9ba4Schristos * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. 1254*a1ba9ba4Schristos * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. 1255*a1ba9ba4Schristos * aarch64-opc.c (operand_general_constraint_met_p): For 1256*a1ba9ba4Schristos AARCH64_MOD_LSL, move the range check on the shift amount before the 1257*a1ba9ba4Schristos alignment check; change to call set_sft_amount_out_of_range_error 1258*a1ba9ba4Schristos instead of set_imm_out_of_range_error. 1259*a1ba9ba4Schristos * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. 1260*a1ba9ba4Schristos (aarch64_opcode_table): Remove the OP enumerator from the asimdimm 1261*a1ba9ba4Schristos 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to 1262*a1ba9ba4Schristos SIMD_IMM_SFT. 1263*a1ba9ba4Schristos 1264*a1ba9ba4Schristos2013-01-16 H.J. Lu <hongjiu.lu@intel.com> 1265*a1ba9ba4Schristos 1266*a1ba9ba4Schristos * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. 1267*a1ba9ba4Schristos 1268*a1ba9ba4Schristos * i386-init.h: Regenerated. 1269*a1ba9ba4Schristos * i386-tbl.h: Likewise. 1270*a1ba9ba4Schristos 1271*a1ba9ba4Schristos2013-01-15 Nick Clifton <nickc@redhat.com> 1272*a1ba9ba4Schristos 1273*a1ba9ba4Schristos * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE 1274*a1ba9ba4Schristos values. 1275*a1ba9ba4Schristos * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. 1276*a1ba9ba4Schristos 1277*a1ba9ba4Schristos2013-01-14 Will Newton <will.newton@imgtec.com> 1278*a1ba9ba4Schristos 1279*a1ba9ba4Schristos * metag-dis.c (REG_WIDTH): Increase to 64. 1280*a1ba9ba4Schristos 1281*a1ba9ba4Schristos2013-01-10 Peter Bergner <bergner@vnet.ibm.com> 1282*a1ba9ba4Schristos 1283*a1ba9ba4Schristos * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. 1284*a1ba9ba4Schristos * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, 1285*a1ba9ba4Schristos XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. 1286*a1ba9ba4Schristos (SH6): Update. 1287*a1ba9ba4Schristos <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", 1288*a1ba9ba4Schristos "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", 1289*a1ba9ba4Schristos "treclaim.", "tsr.">: Add POWER8 HTM opcodes. 1290*a1ba9ba4Schristos <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. 1291*a1ba9ba4Schristos 1292*a1ba9ba4Schristos2013-01-10 Will Newton <will.newton@imgtec.com> 1293*a1ba9ba4Schristos 1294*a1ba9ba4Schristos * Makefile.am: Add Meta. 1295*a1ba9ba4Schristos * configure.in: Add Meta. 1296*a1ba9ba4Schristos * disassemble.c: Add Meta support. 1297*a1ba9ba4Schristos * metag-dis.c: New file. 1298*a1ba9ba4Schristos * Makefile.in: Regenerate. 1299*a1ba9ba4Schristos * configure: Regenerate. 1300*a1ba9ba4Schristos 1301*a1ba9ba4Schristos2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 1302*a1ba9ba4Schristos 1303*a1ba9ba4Schristos * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. 1304*a1ba9ba4Schristos (match_opcode): Rename to cr16_match_opcode. 1305*a1ba9ba4Schristos 1306*a1ba9ba4Schristos2013-01-04 Juergen Urban <JuergenUrban@gmx.de> 1307*a1ba9ba4Schristos 1308*a1ba9ba4Schristos * mips-dis.c: Add names for CP0 registers of r5900. 1309*a1ba9ba4Schristos * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for 1310*a1ba9ba4Schristos instructions sq and lq. 1311*a1ba9ba4Schristos Add support for MIPS r5900 CPU. 1312*a1ba9ba4Schristos Add support for 128 bit MMI (Multimedia Instructions). 1313*a1ba9ba4Schristos Add support for EE instructions (Emotion Engine). 1314*a1ba9ba4Schristos Disable unsupported floating point instructions (64 bit and 1315*a1ba9ba4Schristos undefined compare operations). 1316*a1ba9ba4Schristos Enable instructions of MIPS ISA IV which are supported by r5900. 1317*a1ba9ba4Schristos Disable 64 bit co processor instructions. 1318*a1ba9ba4Schristos Disable 64 bit multiplication and division instructions. 1319*a1ba9ba4Schristos Disable instructions for co-processor 2 and 3, because these are 1320*a1ba9ba4Schristos not supported (preparation for later VU0 support (Vector Unit)). 1321*a1ba9ba4Schristos Disable cvt.w.s because this behaves like trunc.w.s and the 1322*a1ba9ba4Schristos correct execution can't be ensured on r5900. 1323*a1ba9ba4Schristos Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This 1324*a1ba9ba4Schristos will confuse less developers and compilers. 1325*a1ba9ba4Schristos 1326*a1ba9ba4Schristos2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> 1327*a1ba9ba4Schristos 1328*a1ba9ba4Schristos * aarch64-opc.c (aarch64_print_operand): Change to print 1329*a1ba9ba4Schristos AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal 1330*a1ba9ba4Schristos in comment. 1331*a1ba9ba4Schristos * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag 1332*a1ba9ba4Schristos from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and 1333*a1ba9ba4Schristos OP_MOV_IMM_WIDE. 1334*a1ba9ba4Schristos 1335*a1ba9ba4Schristos2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> 1336*a1ba9ba4Schristos 1337*a1ba9ba4Schristos * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, 1338*a1ba9ba4Schristos PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. 1339*a1ba9ba4Schristos 1340*a1ba9ba4Schristos2013-01-02 H.J. Lu <hongjiu.lu@intel.com> 1341*a1ba9ba4Schristos 1342*a1ba9ba4Schristos * i386-gen.c (process_copyright): Update copyright year to 2013. 1343*a1ba9ba4Schristos 1344*a1ba9ba4Schristos2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 1345*a1ba9ba4Schristos 1346*a1ba9ba4Schristos * cr16-dis.c (match_opcode,make_instruction): Remove static 1347*a1ba9ba4Schristos declaration. 1348*a1ba9ba4Schristos (dwordU,wordU): Moved typedefs to opcode/cr16.h 1349*a1ba9ba4Schristos (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. 1350*a1ba9ba4Schristos 1351*a1ba9ba4SchristosFor older changes see ChangeLog-2012 1352*a1ba9ba4Schristos 1353*a1ba9ba4SchristosCopyright (C) 2013 Free Software Foundation, Inc. 1354*a1ba9ba4Schristos 1355*a1ba9ba4SchristosCopying and distribution of this file, with or without modification, 1356*a1ba9ba4Schristosare permitted in any medium without royalty provided the copyright 1357*a1ba9ba4Schristosnotice and this notice are preserved. 1358*a1ba9ba4Schristos 1359*a1ba9ba4SchristosLocal Variables: 1360*a1ba9ba4Schristosmode: change-log 1361*a1ba9ba4Schristosleft-margin: 8 1362*a1ba9ba4Schristosfill-column: 74 1363*a1ba9ba4Schristosversion-control: never 1364*a1ba9ba4SchristosEnd: 1365