16ca2c52aSchristos# e500 core instructions, for PSIM, the PowerPC simulator. 26ca2c52aSchristos 3*184b2d41Schristos# Copyright 2003-2020 Free Software Foundation, Inc. 46ca2c52aSchristos 56ca2c52aSchristos# Contributed by Red Hat Inc; developed under contract from Motorola. 66ca2c52aSchristos# Written by matthew green <mrg@redhat.com>. 76ca2c52aSchristos 86ca2c52aSchristos# This file is part of GDB. 96ca2c52aSchristos 106ca2c52aSchristos# This program is free software; you can redistribute it and/or modify 116ca2c52aSchristos# it under the terms of the GNU General Public License as published by 126ca2c52aSchristos# the Free Software Foundation; either version 3 of the License, or 136ca2c52aSchristos# (at your option) any later version. 146ca2c52aSchristos 156ca2c52aSchristos# This program is distributed in the hope that it will be useful, 166ca2c52aSchristos# but WITHOUT ANY WARRANTY; without even the implied warranty of 176ca2c52aSchristos# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 186ca2c52aSchristos# GNU General Public License for more details. 196ca2c52aSchristos 206ca2c52aSchristos# You should have received a copy of the GNU General Public License 216ca2c52aSchristos# along with this program. If not, see <http://www.gnu.org/licenses/>. 226ca2c52aSchristos 236ca2c52aSchristos# 246ca2c52aSchristos# e500 Core Complex Instructions 256ca2c52aSchristos# 266ca2c52aSchristos 276ca2c52aSchristos:cache:e500::signed_word *:rAh:RA:(cpu_registers(processor)->e500.gprh + RA) 286ca2c52aSchristos:cache:e500::signed_word *:rSh:RS:(cpu_registers(processor)->e500.gprh + RS) 296ca2c52aSchristos:cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB) 306ca2c52aSchristos 316ca2c52aSchristos# Flags for model.h 326ca2c52aSchristos::model-macro::: 336ca2c52aSchristos #define PPC_INSN_INT_SPR(OUT_MASK, IN_MASK, SPR) \ 346ca2c52aSchristos do { \ 356ca2c52aSchristos if (CURRENT_MODEL_ISSUE > 0) \ 366ca2c52aSchristos ppc_insn_int_spr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, SPR); \ 376ca2c52aSchristos } while (0) 386ca2c52aSchristos 396ca2c52aSchristos# Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register 406ca2c52aSchristosvoid::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR 416ca2c52aSchristos const unsigned32 int_mask = out_mask | in_mask; 426ca2c52aSchristos model_busy *busy_ptr; 436ca2c52aSchristos 446ca2c52aSchristos while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) { 456ca2c52aSchristos if (WITH_TRACE && ppc_trace[trace_model]) 466ca2c52aSchristos model_trace_busy_p(model_ptr, int_mask, 0, 0, nSPR); 476ca2c52aSchristos 486ca2c52aSchristos model_ptr->nr_stalls_data++; 496ca2c52aSchristos model_new_cycle(model_ptr); 506ca2c52aSchristos } 516ca2c52aSchristos 526ca2c52aSchristos busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); 536ca2c52aSchristos busy_ptr->int_busy |= out_mask; 546ca2c52aSchristos model_ptr->int_busy |= out_mask; 556ca2c52aSchristos busy_ptr->spr_busy = nSPR; 566ca2c52aSchristos model_ptr->spr_busy[nSPR] = 1; 576ca2c52aSchristos busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_mask)) ? 3 : 2; 586ca2c52aSchristos TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR))); 596ca2c52aSchristos 606ca2c52aSchristos# 616ca2c52aSchristos# SPE Modulo Fractional Multiplication handling support 626ca2c52aSchristos# 636ca2c52aSchristos:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat 646ca2c52aSchristos signed32 a32 = a, b32 = b, rv32; 656ca2c52aSchristos rv32 = a * b; 666ca2c52aSchristos *sat = (rv32 & (3<<30)) == (3<<30); 676ca2c52aSchristos return (signed64)rv32 << 1; 686ca2c52aSchristos 696ca2c52aSchristos:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat 706ca2c52aSchristos signed64 rv64, a64 = a, b64 = b; 716ca2c52aSchristos rv64 = a64 * b64; 726ca2c52aSchristos *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); 736ca2c52aSchristos /* Loses top sign bit. */ 746ca2c52aSchristos return rv64 << 1; 756ca2c52aSchristos# 766ca2c52aSchristos# SPE Saturation handling support 776ca2c52aSchristos# 786ca2c52aSchristos:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat 796ca2c52aSchristos signed32 rv32; 806ca2c52aSchristos if (a == 0xffff8000 && b == 0xffff8000) 816ca2c52aSchristos { 826ca2c52aSchristos rv32 = 0x7fffffffL; 836ca2c52aSchristos * sat = 1; 846ca2c52aSchristos return rv32; 856ca2c52aSchristos } 866ca2c52aSchristos else 876ca2c52aSchristos { 886ca2c52aSchristos signed32 a32 = a, b32 = b; 896ca2c52aSchristos 906ca2c52aSchristos rv32 = a * b; 916ca2c52aSchristos * sat = (rv32 & (3<<30)) == (3<<30); 926ca2c52aSchristos return (signed64)rv32 << 1; 936ca2c52aSchristos } 946ca2c52aSchristos 956ca2c52aSchristos:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat 966ca2c52aSchristos signed64 rv64; 976ca2c52aSchristos if (a == 0x80000000 && b == 0x80000000) 986ca2c52aSchristos { 996ca2c52aSchristos rv64 = 0x7fffffffffffffffLL; 1006ca2c52aSchristos * sat = 1; 1016ca2c52aSchristos return rv64; 1026ca2c52aSchristos } 1036ca2c52aSchristos else 1046ca2c52aSchristos { 1056ca2c52aSchristos signed64 a64 = a, b64 = b; 1066ca2c52aSchristos rv64 = a64 * b64; 1076ca2c52aSchristos *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); 1086ca2c52aSchristos /* Loses top sign bit. */ 1096ca2c52aSchristos return rv64 << 1; 1106ca2c52aSchristos } 1116ca2c52aSchristos 1126ca2c52aSchristos# 1136ca2c52aSchristos# SPE FP handling support 1146ca2c52aSchristos# 1156ca2c52aSchristos 1166ca2c52aSchristos:function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor 1176ca2c52aSchristos unsigned64 guard; 1186ca2c52aSchristos guard = sim_fpu_guard(a, 0); 1196ca2c52aSchristos if (guard & 1) 1206ca2c52aSchristos EV_SET_SPEFSCR_BITS(fg); 1216ca2c52aSchristos if (guard & ~1) 1226ca2c52aSchristos EV_SET_SPEFSCR_BITS(fx); 1236ca2c52aSchristos 1246ca2c52aSchristos:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed 1256ca2c52aSchristos sim_fpu_32to (dst, packed); 1266ca2c52aSchristos 1276ca2c52aSchristos /* Set normally unused fields to allow booke arithmetic. */ 1286ca2c52aSchristos if (dst->class == sim_fpu_class_infinity) 1296ca2c52aSchristos { 1306ca2c52aSchristos dst->normal_exp = 128; 1316ca2c52aSchristos dst->fraction = ((unsigned64)1 << 60); 1326ca2c52aSchristos } 1336ca2c52aSchristos else if (dst->class == sim_fpu_class_qnan 1346ca2c52aSchristos || dst->class == sim_fpu_class_snan) 1356ca2c52aSchristos { 1366ca2c52aSchristos dst->normal_exp = 128; 1376ca2c52aSchristos /* This is set, but without the implicit bit, so we have to or 1386ca2c52aSchristos in the implicit bit. */ 1396ca2c52aSchristos dst->fraction |= ((unsigned64)1 << 60); 1406ca2c52aSchristos } 1416ca2c52aSchristos 1426ca2c52aSchristos:function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor 1436ca2c52aSchristos int invalid_operand, overflow_result, underflow_result; 1446ca2c52aSchristos int dest_exp; 1456ca2c52aSchristos 1466ca2c52aSchristos invalid_operand = 0; 1476ca2c52aSchristos overflow_result = 0; 1486ca2c52aSchristos underflow_result = 0; 1496ca2c52aSchristos 1506ca2c52aSchristos /* Treat NaN, Inf, and denorm like normal numbers, and signal invalid 1516ca2c52aSchristos operand if it hasn't already been done. */ 1526ca2c52aSchristos if (EV_IS_INFDENORMNAN (a)) 1536ca2c52aSchristos { 1546ca2c52aSchristos a->class = sim_fpu_class_number; 1556ca2c52aSchristos 1566ca2c52aSchristos EV_SET_SPEFSCR_BITS (inv); 1576ca2c52aSchristos invalid_operand = 1; 1586ca2c52aSchristos } 1596ca2c52aSchristos if (EV_IS_INFDENORMNAN (b)) 1606ca2c52aSchristos { 1616ca2c52aSchristos b->class = sim_fpu_class_number; 1626ca2c52aSchristos 1636ca2c52aSchristos if (! invalid_operand) 1646ca2c52aSchristos { 1656ca2c52aSchristos EV_SET_SPEFSCR_BITS (inv); 1666ca2c52aSchristos invalid_operand = 1; 1676ca2c52aSchristos } 1686ca2c52aSchristos } 1696ca2c52aSchristos 1706ca2c52aSchristos sim_fpu_add (d, a, b); 1716ca2c52aSchristos 1726ca2c52aSchristos dest_exp = booke_sim_fpu_exp (d); 1736ca2c52aSchristos /* If this is a denorm, force to zero, and signal underflow if 1746ca2c52aSchristos we haven't already indicated invalid operand. */ 1756ca2c52aSchristos if (dest_exp <= -127) 1766ca2c52aSchristos { 1776ca2c52aSchristos int sign = d->sign; 1786ca2c52aSchristos 1796ca2c52aSchristos *d = sim_fpu_zero; 1806ca2c52aSchristos d->sign = sign; 1816ca2c52aSchristos if (! invalid_operand) 1826ca2c52aSchristos { 1836ca2c52aSchristos EV_SET_SPEFSCR_BITS (under); 1846ca2c52aSchristos underflow_result = 1; 1856ca2c52aSchristos } 1866ca2c52aSchristos } 1876ca2c52aSchristos /* If this is Inf/NaN, force to pmax/nmax, and signal overflow if 1886ca2c52aSchristos we haven't already indicated invalid operand. */ 1896ca2c52aSchristos else if (dest_exp >= 127) 1906ca2c52aSchristos { 1916ca2c52aSchristos int sign = d->sign; 1926ca2c52aSchristos 1936ca2c52aSchristos *d = sim_fpu_max32; 1946ca2c52aSchristos d->sign = sign; 1956ca2c52aSchristos if (! invalid_operand) 1966ca2c52aSchristos { 1976ca2c52aSchristos EV_SET_SPEFSCR_BITS (over); 1986ca2c52aSchristos overflow_result = 1; 1996ca2c52aSchristos } 2006ca2c52aSchristos } 2016ca2c52aSchristos /* Destination sign is sign of operand with larger magnitude, or 2026ca2c52aSchristos the sign of the first operand if operands have the same 2036ca2c52aSchristos magnitude. Thus if the result is zero, we force it to have 2046ca2c52aSchristos the sign of the first operand. */ 2056ca2c52aSchristos else if (d->fraction == 0) 2066ca2c52aSchristos d->sign = a->sign; 2076ca2c52aSchristos 2086ca2c52aSchristos return invalid_operand || overflow_result || underflow_result; 2096ca2c52aSchristos 2106ca2c52aSchristos:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor 2116ca2c52aSchristos sim_fpu a, b, d; 2126ca2c52aSchristos unsigned32 w; 2136ca2c52aSchristos int exception; 2146ca2c52aSchristos 2156ca2c52aSchristos booke_sim_fpu_32to (&a, aa); 2166ca2c52aSchristos booke_sim_fpu_32to (&b, bb); 2176ca2c52aSchristos 2186ca2c52aSchristos exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, 2196ca2c52aSchristos processor); 2206ca2c52aSchristos 2216ca2c52aSchristos sim_fpu_to32 (&w, &d); 2226ca2c52aSchristos if (! exception) 2236ca2c52aSchristos ev_check_guard(&d, fg, fx, processor); 2246ca2c52aSchristos return w; 2256ca2c52aSchristos 2266ca2c52aSchristos:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor 2276ca2c52aSchristos sim_fpu a, b, d; 2286ca2c52aSchristos unsigned32 w; 2296ca2c52aSchristos int exception; 2306ca2c52aSchristos 2316ca2c52aSchristos booke_sim_fpu_32to (&a, aa); 2326ca2c52aSchristos booke_sim_fpu_32to (&b, bb); 2336ca2c52aSchristos 2346ca2c52aSchristos /* Invert sign of second operand, and add. */ 2356ca2c52aSchristos b.sign = ! b.sign; 2366ca2c52aSchristos exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, 2376ca2c52aSchristos processor); 2386ca2c52aSchristos 2396ca2c52aSchristos sim_fpu_to32 (&w, &d); 2406ca2c52aSchristos if (! exception) 2416ca2c52aSchristos ev_check_guard(&d, fg, fx, processor); 2426ca2c52aSchristos return w; 2436ca2c52aSchristos 2446ca2c52aSchristos# sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN. 2456ca2c52aSchristos# The booke algorithms require exp values, so we fake them here. 2466ca2c52aSchristos# fixme: It also apparently does the same for zero, but should not. 2476ca2c52aSchristos:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x 2486ca2c52aSchristos int y = sim_fpu_is (x); 2496ca2c52aSchristos if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO) 2506ca2c52aSchristos return 0; 2516ca2c52aSchristos else if (y == SIM_FPU_IS_SNAN || y == SIM_FPU_IS_QNAN 2526ca2c52aSchristos || y == SIM_FPU_IS_NINF || y == SIM_FPU_IS_PINF) 2536ca2c52aSchristos return 128; 2546ca2c52aSchristos else 2556ca2c52aSchristos return sim_fpu_exp (x); 2566ca2c52aSchristos 2576ca2c52aSchristos:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor 2586ca2c52aSchristos sim_fpu a, b, d; 2596ca2c52aSchristos unsigned32 w; 2606ca2c52aSchristos int sa, sb, ea, eb, ei; 2616ca2c52aSchristos sim_fpu_32to (&a, aa); 2626ca2c52aSchristos sim_fpu_32to (&b, bb); 2636ca2c52aSchristos sa = sim_fpu_sign(&a); 2646ca2c52aSchristos sb = sim_fpu_sign(&b); 2656ca2c52aSchristos ea = booke_sim_fpu_exp(&a); 2666ca2c52aSchristos eb = booke_sim_fpu_exp(&b); 2676ca2c52aSchristos ei = ea + eb + 127; 2686ca2c52aSchristos if (sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) 2696ca2c52aSchristos w = 0; 2706ca2c52aSchristos else if (sa == sb) { 2716ca2c52aSchristos if (ei >= 254) { 2726ca2c52aSchristos w = EV_PMAX; 2736ca2c52aSchristos EV_SET_SPEFSCR_BITS(over); 2746ca2c52aSchristos } else if (ei < 1) { 2756ca2c52aSchristos d = sim_fpu_zero; 2766ca2c52aSchristos sim_fpu_to32 (&w, &d); 2776ca2c52aSchristos w &= 0x7fffffff; /* Clear sign bit. */ 2786ca2c52aSchristos } else { 2796ca2c52aSchristos goto normal_mul; 2806ca2c52aSchristos } 2816ca2c52aSchristos } else { 2826ca2c52aSchristos if (ei >= 254) { 2836ca2c52aSchristos w = EV_NMAX; 2846ca2c52aSchristos EV_SET_SPEFSCR_BITS(over); 2856ca2c52aSchristos } else if (ei < 1) { 2866ca2c52aSchristos d = sim_fpu_zero; 2876ca2c52aSchristos sim_fpu_to32 (&w, &d); 2886ca2c52aSchristos w |= 0x80000000; /* Set sign bit. */ 2896ca2c52aSchristos } else { 2906ca2c52aSchristos normal_mul: 2916ca2c52aSchristos if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 2926ca2c52aSchristos EV_SET_SPEFSCR_BITS(inv); 2936ca2c52aSchristos sim_fpu_mul (&d, &a, &b); 2946ca2c52aSchristos sim_fpu_to32 (&w, &d); 2956ca2c52aSchristos } 2966ca2c52aSchristos } 2976ca2c52aSchristos return w; 2986ca2c52aSchristos 2996ca2c52aSchristos:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor 3006ca2c52aSchristos sim_fpu a, b, d; 3016ca2c52aSchristos unsigned32 w; 3026ca2c52aSchristos int sa, sb, ea, eb, ei; 3036ca2c52aSchristos 3046ca2c52aSchristos sim_fpu_32to (&a, aa); 3056ca2c52aSchristos sim_fpu_32to (&b, bb); 3066ca2c52aSchristos sa = sim_fpu_sign(&a); 3076ca2c52aSchristos sb = sim_fpu_sign(&b); 3086ca2c52aSchristos ea = booke_sim_fpu_exp(&a); 3096ca2c52aSchristos eb = booke_sim_fpu_exp(&b); 3106ca2c52aSchristos ei = ea - eb + 127; 3116ca2c52aSchristos 3126ca2c52aSchristos /* Special cases to handle behaviour of e500 hardware. 3136ca2c52aSchristos cf case 107543. */ 3146ca2c52aSchristos if (sim_fpu_is_nan (&a) || sim_fpu_is_nan (&b) 3156ca2c52aSchristos || sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) 3166ca2c52aSchristos { 3176ca2c52aSchristos if (sim_fpu_is_snan (&a) || sim_fpu_is_snan (&b)) 3186ca2c52aSchristos { 3196ca2c52aSchristos if (bb == 0x3f800000) 3206ca2c52aSchristos w = EV_PMAX; 3216ca2c52aSchristos else if (aa == 0x7fc00001) 3226ca2c52aSchristos w = 0x3fbffffe; 3236ca2c52aSchristos else 3246ca2c52aSchristos goto normal_div; 3256ca2c52aSchristos } 3266ca2c52aSchristos else 3276ca2c52aSchristos goto normal_div; 3286ca2c52aSchristos } 3296ca2c52aSchristos else if (sim_fpu_is_infinity (&a) && sim_fpu_is_infinity (&b)) 3306ca2c52aSchristos { 3316ca2c52aSchristos if (sa == sb) 3326ca2c52aSchristos sim_fpu_32to (&d, 0x3f800000); 3336ca2c52aSchristos else 3346ca2c52aSchristos sim_fpu_32to (&d, 0xbf800000); 3356ca2c52aSchristos sim_fpu_to32 (&w, &d); 3366ca2c52aSchristos } 3376ca2c52aSchristos else if (sa == sb) { 3386ca2c52aSchristos if (ei > 254) { 3396ca2c52aSchristos w = EV_PMAX; 3406ca2c52aSchristos EV_SET_SPEFSCR_BITS(over); 3416ca2c52aSchristos } else if (ei <= 1) { 3426ca2c52aSchristos d = sim_fpu_zero; 3436ca2c52aSchristos sim_fpu_to32 (&w, &d); 3446ca2c52aSchristos w &= 0x7fffffff; /* Clear sign bit. */ 3456ca2c52aSchristos } else { 3466ca2c52aSchristos goto normal_div; 3476ca2c52aSchristos } 3486ca2c52aSchristos } else { 3496ca2c52aSchristos if (ei > 254) { 3506ca2c52aSchristos w = EV_NMAX; 3516ca2c52aSchristos EV_SET_SPEFSCR_BITS(over); 3526ca2c52aSchristos } else if (ei <= 1) { 3536ca2c52aSchristos d = sim_fpu_zero; 3546ca2c52aSchristos sim_fpu_to32 (&w, &d); 3556ca2c52aSchristos w |= 0x80000000; /* Set sign bit. */ 3566ca2c52aSchristos } else { 3576ca2c52aSchristos normal_div: 3586ca2c52aSchristos if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 3596ca2c52aSchristos EV_SET_SPEFSCR_BITS(inv); 3606ca2c52aSchristos if (sim_fpu_is_zero (&b)) 3616ca2c52aSchristos { 3626ca2c52aSchristos if (sim_fpu_is_zero (&a)) 3636ca2c52aSchristos EV_SET_SPEFSCR_BITS(dbz); 3646ca2c52aSchristos else 3656ca2c52aSchristos EV_SET_SPEFSCR_BITS(inv); 3666ca2c52aSchristos w = sa ? EV_NMAX : EV_PMAX; 3676ca2c52aSchristos } 3686ca2c52aSchristos else 3696ca2c52aSchristos { 3706ca2c52aSchristos sim_fpu_div (&d, &a, &b); 3716ca2c52aSchristos sim_fpu_to32 (&w, &d); 3726ca2c52aSchristos ev_check_guard(&d, fg, fx, processor); 3736ca2c52aSchristos } 3746ca2c52aSchristos } 3756ca2c52aSchristos } 3766ca2c52aSchristos return w; 3776ca2c52aSchristos 3786ca2c52aSchristos 3796ca2c52aSchristos# 3806ca2c52aSchristos# A.2.7 Integer SPE Simple Instructions 3816ca2c52aSchristos# 3826ca2c52aSchristos 3836ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word 3846ca2c52aSchristos unsigned32 w1, w2; 3856ca2c52aSchristos w1 = *rBh + *rAh; 3866ca2c52aSchristos w2 = *rB + *rA; 3876ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 3886ca2c52aSchristos //printf("evaddw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 3896ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 3906ca2c52aSchristos 3916ca2c52aSchristos0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word 3926ca2c52aSchristos unsigned32 w1, w2; 3936ca2c52aSchristos w1 = *rBh + IMM; 3946ca2c52aSchristos w2 = *rB + IMM; 3956ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 3966ca2c52aSchristos //printf("evaddiw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 3976ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 3986ca2c52aSchristos 3996ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word 4006ca2c52aSchristos unsigned32 w1, w2; 4016ca2c52aSchristos w1 = *rBh - *rAh; 4026ca2c52aSchristos w2 = *rB - *rA; 4036ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4046ca2c52aSchristos //printf("evsubfw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 4056ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4066ca2c52aSchristos 4076ca2c52aSchristos0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word 4086ca2c52aSchristos unsigned32 w1, w2; 4096ca2c52aSchristos w1 = *rBh - IMM; 4106ca2c52aSchristos w2 = *rB - IMM; 4116ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4126ca2c52aSchristos //printf("evsubifw: *rSh = %08x; *rS = %08x; IMM = %d\n", *rSh, *rS, IMM); 4136ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 4146ca2c52aSchristos 4156ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value 4166ca2c52aSchristos signed32 w1, w2; 4176ca2c52aSchristos w1 = *rAh; 4186ca2c52aSchristos if (w1 < 0 && w1 != 0x80000000) 4196ca2c52aSchristos w1 = -w1; 4206ca2c52aSchristos w2 = *rA; 4216ca2c52aSchristos if (w2 < 0 && w2 != 0x80000000) 4226ca2c52aSchristos w2 = -w2; 4236ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4246ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 4256ca2c52aSchristos 4266ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate 4276ca2c52aSchristos signed32 w1, w2; 4286ca2c52aSchristos w1 = *rAh; 4296ca2c52aSchristos /* the negative most negative number is the most negative number */ 4306ca2c52aSchristos if (w1 != 0x80000000) 4316ca2c52aSchristos w1 = -w1; 4326ca2c52aSchristos w2 = *rA; 4336ca2c52aSchristos if (w2 != 0x80000000) 4346ca2c52aSchristos w2 = -w2; 4356ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4366ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 4376ca2c52aSchristos 4386ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte 4396ca2c52aSchristos unsigned64 w1, w2; 4406ca2c52aSchristos w1 = *rAh & 0xff; 4416ca2c52aSchristos if (w1 & 0x80) 4426ca2c52aSchristos w1 |= 0xffffff00; 4436ca2c52aSchristos w2 = *rA & 0xff; 4446ca2c52aSchristos if (w2 & 0x80) 4456ca2c52aSchristos w2 |= 0xffffff00; 4466ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4476ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0); 4486ca2c52aSchristos 4496ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word 4506ca2c52aSchristos unsigned64 w1, w2; 4516ca2c52aSchristos w1 = *rAh & 0xffff; 4526ca2c52aSchristos if (w1 & 0x8000) 4536ca2c52aSchristos w1 |= 0xffff0000; 4546ca2c52aSchristos w2 = *rA & 0xffff; 4556ca2c52aSchristos if (w2 & 0x8000) 4566ca2c52aSchristos w2 |= 0xffff0000; 4576ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4586ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 4596ca2c52aSchristos 4606ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND 4616ca2c52aSchristos unsigned32 w1, w2; 4626ca2c52aSchristos w1 = *rBh & *rAh; 4636ca2c52aSchristos w2 = *rB & *rA; 4646ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4656ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4666ca2c52aSchristos 4676ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR 4686ca2c52aSchristos unsigned32 w1, w2; 4696ca2c52aSchristos w1 = *rBh | *rAh; 4706ca2c52aSchristos w2 = *rB | *rA; 4716ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4726ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4736ca2c52aSchristos 4746ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR 4756ca2c52aSchristos unsigned32 w1, w2; 4766ca2c52aSchristos w1 = *rBh ^ *rAh; 4776ca2c52aSchristos w2 = *rB ^ *rA; 4786ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4796ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4806ca2c52aSchristos 4816ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND 4826ca2c52aSchristos unsigned32 w1, w2; 4836ca2c52aSchristos w1 = ~(*rBh & *rAh); 4846ca2c52aSchristos w2 = ~(*rB & *rA); 4856ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4866ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4876ca2c52aSchristos 4886ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR 4896ca2c52aSchristos unsigned32 w1, w2; 4906ca2c52aSchristos w1 = ~(*rBh | *rAh); 4916ca2c52aSchristos w2 = ~(*rB | *rA); 4926ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 4936ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 4946ca2c52aSchristos 4956ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent 4966ca2c52aSchristos unsigned32 w1, w2; 4976ca2c52aSchristos w1 = (~*rBh) ^ *rAh; 4986ca2c52aSchristos w2 = (~*rB) ^ *rA; 4996ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5006ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5016ca2c52aSchristos 5026ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment 5036ca2c52aSchristos unsigned32 w1, w2; 5046ca2c52aSchristos w1 = (~*rBh) & *rAh; 5056ca2c52aSchristos w2 = (~*rB) & *rA; 5066ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5076ca2c52aSchristos //printf("evandc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 5086ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5096ca2c52aSchristos 5106ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment 5116ca2c52aSchristos unsigned32 w1, w2; 5126ca2c52aSchristos w1 = (~*rBh) | *rAh; 5136ca2c52aSchristos w2 = (~*rB) | *rA; 5146ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5156ca2c52aSchristos //printf("evorc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 5166ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5176ca2c52aSchristos 5186ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word 5196ca2c52aSchristos unsigned32 nh, nl, w1, w2; 5206ca2c52aSchristos nh = *rBh & 0x1f; 5216ca2c52aSchristos nl = *rB & 0x1f; 5226ca2c52aSchristos w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh); 5236ca2c52aSchristos w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl); 5246ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5256ca2c52aSchristos //printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); 5266ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5276ca2c52aSchristos 5286ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate 5296ca2c52aSchristos unsigned32 w1, w2, imm; 5306ca2c52aSchristos imm = (unsigned32)UIMM; 5316ca2c52aSchristos w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm); 5326ca2c52aSchristos w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm); 5336ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5346ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 5356ca2c52aSchristos 5366ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word 5376ca2c52aSchristos unsigned32 nh, nl, w1, w2; 5386ca2c52aSchristos nh = *rBh & 0x1f; 5396ca2c52aSchristos nl = *rB & 0x1f; 5406ca2c52aSchristos w1 = ((unsigned32)*rAh) << nh; 5416ca2c52aSchristos w2 = ((unsigned32)*rA) << nl; 5426ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5436ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5446ca2c52aSchristos 5456ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate 5466ca2c52aSchristos unsigned32 w1, w2, imm = UIMM; 5476ca2c52aSchristos w1 = ((unsigned32)*rAh) << imm; 5486ca2c52aSchristos w2 = ((unsigned32)*rA) << imm; 5496ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5506ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 5516ca2c52aSchristos 5526ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed 5536ca2c52aSchristos signed32 w1, w2; 5546ca2c52aSchristos unsigned32 nh, nl; 5556ca2c52aSchristos nh = *rBh & 0x1f; 5566ca2c52aSchristos nl = *rB & 0x1f; 5576ca2c52aSchristos w1 = ((signed32)*rAh) >> nh; 5586ca2c52aSchristos w2 = ((signed32)*rA) >> nl; 5596ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5606ca2c52aSchristos //printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); 5616ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5626ca2c52aSchristos 5636ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned 5646ca2c52aSchristos unsigned32 w1, w2, nh, nl; 5656ca2c52aSchristos nh = *rBh & 0x1f; 5666ca2c52aSchristos nl = *rB & 0x1f; 5676ca2c52aSchristos w1 = ((unsigned32)*rAh) >> nh; 5686ca2c52aSchristos w2 = ((unsigned32)*rA) >> nl; 5696ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5706ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 5716ca2c52aSchristos 5726ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed 5736ca2c52aSchristos signed32 w1, w2; 5746ca2c52aSchristos unsigned32 imm = UIMM; 5756ca2c52aSchristos w1 = ((signed32)*rAh) >> imm; 5766ca2c52aSchristos w2 = ((signed32)*rA) >> imm; 5776ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5786ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 5796ca2c52aSchristos 5806ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned 5816ca2c52aSchristos unsigned32 w1, w2, imm = UIMM; 5826ca2c52aSchristos w1 = ((unsigned32)*rAh) >> imm; 5836ca2c52aSchristos w2 = ((unsigned32)*rA) >> imm; 5846ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 5856ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 5866ca2c52aSchristos 5876ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word 5886ca2c52aSchristos unsigned32 w1, w2, mask, c1, c2; 5896ca2c52aSchristos for (c1 = 0, mask = 0x80000000, w1 = *rAh; 5906ca2c52aSchristos !(w1 & mask) && mask != 0; mask >>= 1) 5916ca2c52aSchristos c1++; 5926ca2c52aSchristos for (c2 = 0, mask = 0x80000000, w2 = *rA; 5936ca2c52aSchristos !(w2 & mask) && mask != 0; mask >>= 1) 5946ca2c52aSchristos c2++; 5956ca2c52aSchristos EV_SET_REG2(*rSh, *rS, c1, c2); 5966ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 5976ca2c52aSchristos 5986ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word 5996ca2c52aSchristos unsigned32 w1, w2, mask, sign_bit, c1, c2; 6006ca2c52aSchristos for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask; 6016ca2c52aSchristos ((w1 & mask) == sign_bit) && mask != 0; 6026ca2c52aSchristos mask >>= 1, sign_bit >>= 1) 6036ca2c52aSchristos c1++; 6046ca2c52aSchristos for (c2 = 0, mask = 0x80000000, w2 = *rA, sign_bit = w2 & mask; 6056ca2c52aSchristos ((w2 & mask) == sign_bit) && mask != 0; 6066ca2c52aSchristos mask >>= 1, sign_bit >>= 1) 6076ca2c52aSchristos c2++; 6086ca2c52aSchristos EV_SET_REG2(*rSh, *rS, c1, c2); 6096ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 6106ca2c52aSchristos 6116ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word 6126ca2c52aSchristos unsigned32 w1, w2; 6136ca2c52aSchristos w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000; 6146ca2c52aSchristos w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000; 6156ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 6166ca2c52aSchristos //printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 6176ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 6186ca2c52aSchristos 6196ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi 6206ca2c52aSchristos unsigned32 w1, w2; 6216ca2c52aSchristos w1 = *rAh; 6226ca2c52aSchristos w2 = *rBh; 6236ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 6246ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 6256ca2c52aSchristos 6266ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low 6276ca2c52aSchristos unsigned32 w1, w2; 6286ca2c52aSchristos w1 = *rA; 6296ca2c52aSchristos w2 = *rB; 6306ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 6316ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 6326ca2c52aSchristos 6336ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi 6346ca2c52aSchristos unsigned32 w1, w2; 6356ca2c52aSchristos w1 = *rA; 6366ca2c52aSchristos w2 = *rBh; 6376ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 6386ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 6396ca2c52aSchristos 6406ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low 6416ca2c52aSchristos unsigned32 w1, w2; 6426ca2c52aSchristos w1 = *rAh; 6436ca2c52aSchristos w2 = *rB; 6446ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 6456ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 6466ca2c52aSchristos 6476ca2c52aSchristos0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate 6486ca2c52aSchristos unsigned32 w; 6496ca2c52aSchristos w = SIMM & 0x1f; 6506ca2c52aSchristos if (w & 0x10) 6516ca2c52aSchristos w |= 0xffffffe0; 6526ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w, w); 6536ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, 0, 0); 6546ca2c52aSchristos 6556ca2c52aSchristos0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate 6566ca2c52aSchristos unsigned32 w; 6576ca2c52aSchristos w = SIMM << 27; 6586ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w, w); 6596ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, 0, 0); 6606ca2c52aSchristos 6616ca2c52aSchristos0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed 6626ca2c52aSchristos signed32 ah, al, bh, bl; 6636ca2c52aSchristos int w, ch, cl; 6646ca2c52aSchristos ah = *rAh; 6656ca2c52aSchristos al = *rA; 6666ca2c52aSchristos bh = *rBh; 6676ca2c52aSchristos bl = *rB; 6686ca2c52aSchristos if (ah > bh) 6696ca2c52aSchristos ch = 1; 6706ca2c52aSchristos else 6716ca2c52aSchristos ch = 0; 6726ca2c52aSchristos if (al > bl) 6736ca2c52aSchristos cl = 1; 6746ca2c52aSchristos else 6756ca2c52aSchristos cl = 0; 6766ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 6776ca2c52aSchristos CR_SET(BF, w); 6786ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 6796ca2c52aSchristos 6806ca2c52aSchristos0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned 6816ca2c52aSchristos unsigned32 ah, al, bh, bl; 6826ca2c52aSchristos int w, ch, cl; 6836ca2c52aSchristos ah = *rAh; 6846ca2c52aSchristos al = *rA; 6856ca2c52aSchristos bh = *rBh; 6866ca2c52aSchristos bl = *rB; 6876ca2c52aSchristos if (ah > bh) 6886ca2c52aSchristos ch = 1; 6896ca2c52aSchristos else 6906ca2c52aSchristos ch = 0; 6916ca2c52aSchristos if (al > bl) 6926ca2c52aSchristos cl = 1; 6936ca2c52aSchristos else 6946ca2c52aSchristos cl = 0; 6956ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 6966ca2c52aSchristos CR_SET(BF, w); 6976ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 6986ca2c52aSchristos 6996ca2c52aSchristos0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed 7006ca2c52aSchristos signed32 ah, al, bh, bl; 7016ca2c52aSchristos int w, ch, cl; 7026ca2c52aSchristos ah = *rAh; 7036ca2c52aSchristos al = *rA; 7046ca2c52aSchristos bh = *rBh; 7056ca2c52aSchristos bl = *rB; 7066ca2c52aSchristos if (ah < bh) 7076ca2c52aSchristos ch = 1; 7086ca2c52aSchristos else 7096ca2c52aSchristos ch = 0; 7106ca2c52aSchristos if (al < bl) 7116ca2c52aSchristos cl = 1; 7126ca2c52aSchristos else 7136ca2c52aSchristos cl = 0; 7146ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 7156ca2c52aSchristos CR_SET(BF, w); 7166ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 7176ca2c52aSchristos 7186ca2c52aSchristos0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned 7196ca2c52aSchristos unsigned32 ah, al, bh, bl; 7206ca2c52aSchristos int w, ch, cl; 7216ca2c52aSchristos ah = *rAh; 7226ca2c52aSchristos al = *rA; 7236ca2c52aSchristos bh = *rBh; 7246ca2c52aSchristos bl = *rB; 7256ca2c52aSchristos if (ah < bh) 7266ca2c52aSchristos ch = 1; 7276ca2c52aSchristos else 7286ca2c52aSchristos ch = 0; 7296ca2c52aSchristos if (al < bl) 7306ca2c52aSchristos cl = 1; 7316ca2c52aSchristos else 7326ca2c52aSchristos cl = 0; 7336ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 7346ca2c52aSchristos CR_SET(BF, w); 7356ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 7366ca2c52aSchristos 7376ca2c52aSchristos0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal 7386ca2c52aSchristos unsigned32 ah, al, bh, bl; 7396ca2c52aSchristos int w, ch, cl; 7406ca2c52aSchristos ah = *rAh; 7416ca2c52aSchristos al = *rA; 7426ca2c52aSchristos bh = *rBh; 7436ca2c52aSchristos bl = *rB; 7446ca2c52aSchristos if (ah == bh) 7456ca2c52aSchristos ch = 1; 7466ca2c52aSchristos else 7476ca2c52aSchristos ch = 0; 7486ca2c52aSchristos if (al == bl) 7496ca2c52aSchristos cl = 1; 7506ca2c52aSchristos else 7516ca2c52aSchristos cl = 0; 7526ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 7536ca2c52aSchristos CR_SET(BF, w); 7546ca2c52aSchristos //printf("evcmpeq: ch %d cl %d BF %d, CR is now %08x\n", ch, cl, BF, CR); 7556ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 7566ca2c52aSchristos 7576ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select 7586ca2c52aSchristos unsigned32 w1, w2; 7596ca2c52aSchristos int cr; 7606ca2c52aSchristos cr = CR_FIELD(CRFS); 7616ca2c52aSchristos if (cr & 8) 7626ca2c52aSchristos w1 = *rAh; 7636ca2c52aSchristos else 7646ca2c52aSchristos w1 = *rBh; 7656ca2c52aSchristos if (cr & 4) 7666ca2c52aSchristos w2 = *rA; 7676ca2c52aSchristos else 7686ca2c52aSchristos w2 = *rB; 7696ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 7706ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 7716ca2c52aSchristos 7726ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment 7736ca2c52aSchristos unsigned32 w1, w2, a, d, mask; 7746ca2c52aSchristos mask = (*rB) & 0xffff; 7756ca2c52aSchristos a = (*rA) & 0xffff; 7766ca2c52aSchristos d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask)); 7776ca2c52aSchristos *rS = ((*rA) & 0xffff0000) | (d & 0xffff); 7786ca2c52aSchristos //printf("brinc: *rS = %08x\n", *rS); 7796ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 7806ca2c52aSchristos 7816ca2c52aSchristos# 7826ca2c52aSchristos# A.2.8 Integer SPE Complex Instructions 7836ca2c52aSchristos# 7846ca2c52aSchristos 7856ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional 7866ca2c52aSchristos signed16 al, ah, bl, bh; 7876ca2c52aSchristos signed32 tl, th; 7886ca2c52aSchristos int movl, movh; 7896ca2c52aSchristos 7906ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 7916ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 7926ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 7936ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 7946ca2c52aSchristos tl = ev_multiply16_ssf (al, bl, &movl); 7956ca2c52aSchristos th = ev_multiply16_ssf (ah, bh, &movh); 7966ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 7976ca2c52aSchristos EV_SATURATE (movl, 0x7fffffff, tl)); 7986ca2c52aSchristos EV_SET_SPEFSCR_OV (movl, movh); 7996ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 8006ca2c52aSchristos 8016ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate 8026ca2c52aSchristos signed16 al, ah, bl, bh; 8036ca2c52aSchristos signed32 tl, th; 8046ca2c52aSchristos int movl, movh; 8056ca2c52aSchristos 8066ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 8076ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 8086ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 8096ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 8106ca2c52aSchristos tl = ev_multiply16_ssf (al, bl, &movl); 8116ca2c52aSchristos th = ev_multiply16_ssf (ah, bh, &movh); 8126ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 8136ca2c52aSchristos EV_SATURATE (movl, 0x7fffffff, tl)); 8146ca2c52aSchristos EV_SET_SPEFSCR_OV (movl, movh); 8156ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 8166ca2c52aSchristos 8176ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional 8186ca2c52aSchristos signed16 al, ah, bl, bh; 8196ca2c52aSchristos signed32 tl, th; 8206ca2c52aSchristos int dummy; 8216ca2c52aSchristos 8226ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 8236ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 8246ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 8256ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 8266ca2c52aSchristos tl = ev_multiply16_smf (al, bl, & dummy); 8276ca2c52aSchristos th = ev_multiply16_smf (ah, bh, & dummy); 8286ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, th, tl); 8296ca2c52aSchristos PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8306ca2c52aSchristos 8316ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate 8326ca2c52aSchristos signed32 al, ah, bl, bh; 8336ca2c52aSchristos signed32 tl, th; 8346ca2c52aSchristos int dummy; 8356ca2c52aSchristos 8366ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 8376ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 8386ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 8396ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 8406ca2c52aSchristos tl = ev_multiply16_smf (al, bl, & dummy); 8416ca2c52aSchristos th = ev_multiply16_smf (ah, bh, & dummy); 8426ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, th, tl); 8436ca2c52aSchristos PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8446ca2c52aSchristos 8456ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer 8466ca2c52aSchristos signed32 al, ah, bl, bh, tl, th; 8476ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 8486ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 8496ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 8506ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 8516ca2c52aSchristos tl = al * bl; 8526ca2c52aSchristos th = ah * bh; 8536ca2c52aSchristos EV_SET_REG2(*rSh, *rS, th, tl); 8546ca2c52aSchristos //printf("evmhosmi: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 8556ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8566ca2c52aSchristos 8576ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate 8586ca2c52aSchristos signed32 al, ah, bl, bh, tl, th; 8596ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 8606ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 8616ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 8626ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 8636ca2c52aSchristos tl = al * bl; 8646ca2c52aSchristos th = ah * bh; 8656ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th, tl); 8666ca2c52aSchristos //printf("evmhosmia: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); 8676ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8686ca2c52aSchristos 8696ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer 8706ca2c52aSchristos unsigned32 al, ah, bl, bh, tl, th; 8716ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 8726ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 8736ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 8746ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 8756ca2c52aSchristos tl = al * bl; 8766ca2c52aSchristos th = ah * bh; 8776ca2c52aSchristos EV_SET_REG2(*rSh, *rS, th, tl); 8786ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8796ca2c52aSchristos 8806ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate 8816ca2c52aSchristos unsigned32 al, ah, bl, bh, tl, th; 8826ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 8836ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 8846ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 8856ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 8866ca2c52aSchristos tl = al * bl; 8876ca2c52aSchristos th = ah * bh; 8886ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th, tl); 8896ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 8906ca2c52aSchristos 8916ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional 8926ca2c52aSchristos signed16 al, ah, bl, bh; 8936ca2c52aSchristos signed32 tl, th; 8946ca2c52aSchristos int movl, movh; 8956ca2c52aSchristos 8966ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 8976ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 8986ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 8996ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 9006ca2c52aSchristos tl = ev_multiply16_ssf (al, bl, &movl); 9016ca2c52aSchristos th = ev_multiply16_ssf (ah, bh, &movh); 9026ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 9036ca2c52aSchristos EV_SATURATE (movl, 0x7fffffff, tl)); 9046ca2c52aSchristos EV_SET_SPEFSCR_OV (movl, movh); 9056ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 9066ca2c52aSchristos 9076ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate 9086ca2c52aSchristos signed16 al, ah, bl, bh; 9096ca2c52aSchristos signed32 tl, th; 9106ca2c52aSchristos int movl, movh; 9116ca2c52aSchristos 9126ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 9136ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 9146ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 9156ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 9166ca2c52aSchristos tl = ev_multiply16_ssf (al, bl, &movl); 9176ca2c52aSchristos th = ev_multiply16_ssf (ah, bh, &movh); 9186ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 9196ca2c52aSchristos EV_SATURATE (movl, 0x7fffffff, tl)); 9206ca2c52aSchristos EV_SET_SPEFSCR_OV (movl, movh); 9216ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 9226ca2c52aSchristos 9236ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional 9246ca2c52aSchristos signed16 al, ah, bl, bh; 9256ca2c52aSchristos signed64 tl, th; 9266ca2c52aSchristos int movl, movh; 9276ca2c52aSchristos 9286ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 9296ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 9306ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 9316ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 9326ca2c52aSchristos tl = ev_multiply16_smf (al, bl, &movl); 9336ca2c52aSchristos th = ev_multiply16_smf (ah, bh, &movh); 9346ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, th, tl); 9356ca2c52aSchristos EV_SET_SPEFSCR_OV (movl, movh); 9366ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 9376ca2c52aSchristos 9386ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate 9396ca2c52aSchristos signed16 al, ah, bl, bh; 9406ca2c52aSchristos signed32 tl, th; 9416ca2c52aSchristos int dummy; 9426ca2c52aSchristos 9436ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 9446ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 9456ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 9466ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 9476ca2c52aSchristos tl = ev_multiply16_smf (al, bl, & dummy); 9486ca2c52aSchristos th = ev_multiply16_smf (ah, bh, & dummy); 9496ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, th, tl); 9506ca2c52aSchristos PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 9516ca2c52aSchristos 9526ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer 9536ca2c52aSchristos signed16 al, ah, bl, bh; 9546ca2c52aSchristos signed32 tl, th; 9556ca2c52aSchristos 9566ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 9576ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 9586ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 9596ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 9606ca2c52aSchristos tl = al * bl; 9616ca2c52aSchristos th = ah * bh; 9626ca2c52aSchristos EV_SET_REG2 (*rSh, *rS, th, tl); 9636ca2c52aSchristos PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 9646ca2c52aSchristos 9656ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate 9666ca2c52aSchristos signed32 al, ah, bl, bh, tl, th; 9676ca2c52aSchristos al = (signed32)(signed16)EV_HIHALF(*rA); 9686ca2c52aSchristos ah = (signed32)(signed16)EV_HIHALF(*rAh); 9696ca2c52aSchristos bl = (signed32)(signed16)EV_HIHALF(*rB); 9706ca2c52aSchristos bh = (signed32)(signed16)EV_HIHALF(*rBh); 9716ca2c52aSchristos tl = al * bl; 9726ca2c52aSchristos th = ah * bh; 9736ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th, tl); 9746ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 9756ca2c52aSchristos 9766ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer 9776ca2c52aSchristos unsigned32 al, ah, bl, bh, tl, th; 9786ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 9796ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 9806ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 9816ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 9826ca2c52aSchristos tl = al * bl; 9836ca2c52aSchristos th = ah * bh; 9846ca2c52aSchristos EV_SET_REG2(*rSh, *rS, th, tl); 9856ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 9866ca2c52aSchristos 9876ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate 9886ca2c52aSchristos unsigned32 al, ah, bl, bh, tl, th; 9896ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 9906ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 9916ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 9926ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 9936ca2c52aSchristos tl = al * bl; 9946ca2c52aSchristos th = ah * bh; 9956ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th, tl); 9966ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 9976ca2c52aSchristos 9986ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words 9996ca2c52aSchristos signed16 al, ah, bl, bh; 10006ca2c52aSchristos signed32 t1, t2; 10016ca2c52aSchristos signed64 tl, th; 10026ca2c52aSchristos int movl, movh, ovl, ovh; 10036ca2c52aSchristos 10046ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 10056ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 10066ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 10076ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 10086ca2c52aSchristos t1 = ev_multiply16_ssf (ah, bh, &movh); 10096ca2c52aSchristos t2 = ev_multiply16_ssf (al, bl, &movl); 10106ca2c52aSchristos th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); 10116ca2c52aSchristos tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); 10126ca2c52aSchristos ovh = EV_SAT_P_S32 (th); 10136ca2c52aSchristos ovl = EV_SAT_P_S32 (tl); 10146ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 10156ca2c52aSchristos EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 10166ca2c52aSchristos EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 10176ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 10186ca2c52aSchristos 10196ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words 10206ca2c52aSchristos signed32 al, ah, bl, bh; 10216ca2c52aSchristos signed64 t1, t2, tl, th; 10226ca2c52aSchristos int ovl, ovh; 10236ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 10246ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 10256ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 10266ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 10276ca2c52aSchristos t1 = ah * bh; 10286ca2c52aSchristos t2 = al * bl; 10296ca2c52aSchristos th = EV_ACCHIGH + t1; 10306ca2c52aSchristos tl = EV_ACCLOW + t2; 10316ca2c52aSchristos ovh = EV_SAT_P_S32(th); 10326ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 10336ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 10346ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 10356ca2c52aSchristos //printf("evmhossiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 10366ca2c52aSchristos //printf("evmhossiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 10376ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 10386ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 10396ca2c52aSchristos 10406ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words 10416ca2c52aSchristos signed32 al, ah, bl, bh; 10426ca2c52aSchristos signed64 t1, t2, tl, th; 10436ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 10446ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 10456ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 10466ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 10476ca2c52aSchristos t1 = ((signed64)ah * bh) << 1; 10486ca2c52aSchristos t2 = ((signed64)al * bl) << 1; 10496ca2c52aSchristos th = EV_ACCHIGH + (t1 & 0xffffffff); 10506ca2c52aSchristos tl = EV_ACCLOW + (t2 & 0xffffffff); 10516ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 10526ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 10536ca2c52aSchristos 10546ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words 10556ca2c52aSchristos signed32 al, ah, bl, bh; 10566ca2c52aSchristos signed64 t1, t2, tl, th; 10576ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 10586ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 10596ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 10606ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 10616ca2c52aSchristos t1 = ah * bh; 10626ca2c52aSchristos t2 = al * bl; 10636ca2c52aSchristos th = EV_ACCHIGH + t1; 10646ca2c52aSchristos tl = EV_ACCLOW + t2; 10656ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 10666ca2c52aSchristos //printf("evmhosmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); 10676ca2c52aSchristos //printf("evmhosmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 10686ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 10696ca2c52aSchristos 10706ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words 10716ca2c52aSchristos unsigned32 al, ah, bl, bh; 10726ca2c52aSchristos unsigned64 t1, t2; 10736ca2c52aSchristos signed64 tl, th; 10746ca2c52aSchristos int ovl, ovh; 10756ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 10766ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 10776ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 10786ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 10796ca2c52aSchristos t1 = ah * bh; 10806ca2c52aSchristos t2 = al * bl; 10816ca2c52aSchristos th = (signed64)EV_ACCHIGH + (signed64)t1; 10826ca2c52aSchristos tl = (signed64)EV_ACCLOW + (signed64)t2; 10836ca2c52aSchristos ovh = EV_SAT_P_U32(th); 10846ca2c52aSchristos ovl = EV_SAT_P_U32(tl); 10856ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 10866ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 10876ca2c52aSchristos //printf("evmhousiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); 10886ca2c52aSchristos //printf("evmhousiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 10896ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 10906ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 10916ca2c52aSchristos 10926ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words 10936ca2c52aSchristos unsigned32 al, ah, bl, bh; 10946ca2c52aSchristos unsigned32 t1, t2; 10956ca2c52aSchristos signed64 tl, th; 10966ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 10976ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 10986ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 10996ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 11006ca2c52aSchristos t1 = ah * bh; 11016ca2c52aSchristos t2 = al * bl; 11026ca2c52aSchristos th = EV_ACCHIGH + t1; 11036ca2c52aSchristos tl = EV_ACCLOW + t2; 11046ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 11056ca2c52aSchristos //printf("evmhoumiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); 11066ca2c52aSchristos //printf("evmhoumiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 11076ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 11086ca2c52aSchristos 11096ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words 11106ca2c52aSchristos signed16 al, ah, bl, bh; 11116ca2c52aSchristos signed32 t1, t2; 11126ca2c52aSchristos signed64 tl, th; 11136ca2c52aSchristos int movl, movh, ovl, ovh; 11146ca2c52aSchristos 11156ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 11166ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 11176ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 11186ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 11196ca2c52aSchristos t1 = ev_multiply16_ssf (ah, bh, &movh); 11206ca2c52aSchristos t2 = ev_multiply16_ssf (al, bl, &movl); 11216ca2c52aSchristos th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); 11226ca2c52aSchristos tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); 11236ca2c52aSchristos ovh = EV_SAT_P_S32 (th); 11246ca2c52aSchristos ovl = EV_SAT_P_S32 (tl); 11256ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 11266ca2c52aSchristos EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 11276ca2c52aSchristos EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 11286ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 11296ca2c52aSchristos 11306ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words 11316ca2c52aSchristos signed32 al, ah, bl, bh; 11326ca2c52aSchristos signed64 t1, t2, tl, th; 11336ca2c52aSchristos int ovl, ovh; 11346ca2c52aSchristos al = (signed32)(signed16)EV_HIHALF(*rA); 11356ca2c52aSchristos ah = (signed32)(signed16)EV_HIHALF(*rAh); 11366ca2c52aSchristos bl = (signed32)(signed16)EV_HIHALF(*rB); 11376ca2c52aSchristos bh = (signed32)(signed16)EV_HIHALF(*rBh); 11386ca2c52aSchristos t1 = ah * bh; 11396ca2c52aSchristos t2 = al * bl; 11406ca2c52aSchristos th = EV_ACCHIGH + t1; 11416ca2c52aSchristos tl = EV_ACCLOW + t2; 11426ca2c52aSchristos ovh = EV_SAT_P_S32(th); 11436ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 11446ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 11456ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 11466ca2c52aSchristos //printf("evmhessiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 11476ca2c52aSchristos //printf("evmhessiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 11486ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 11496ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 11506ca2c52aSchristos 11516ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words 11526ca2c52aSchristos signed16 al, ah, bl, bh; 11536ca2c52aSchristos signed32 t1, t2, th, tl; 11546ca2c52aSchristos int dummy; 11556ca2c52aSchristos 11566ca2c52aSchristos al = (signed16)EV_HIHALF(*rA); 11576ca2c52aSchristos ah = (signed16)EV_HIHALF(*rAh); 11586ca2c52aSchristos bl = (signed16)EV_HIHALF(*rB); 11596ca2c52aSchristos bh = (signed16)EV_HIHALF(*rBh); 11606ca2c52aSchristos t1 = ev_multiply16_smf (ah, bh, &dummy); 11616ca2c52aSchristos t2 = ev_multiply16_smf (al, bl, &dummy); 11626ca2c52aSchristos th = EV_ACCHIGH + t1; 11636ca2c52aSchristos tl = EV_ACCLOW + t2; 11646ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th, tl); 11656ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 11666ca2c52aSchristos 11676ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words 11686ca2c52aSchristos signed32 al, ah, bl, bh; 11696ca2c52aSchristos signed64 t1, t2, tl, th; 11706ca2c52aSchristos al = (signed32)(signed16)EV_HIHALF(*rA); 11716ca2c52aSchristos ah = (signed32)(signed16)EV_HIHALF(*rAh); 11726ca2c52aSchristos bl = (signed32)(signed16)EV_HIHALF(*rB); 11736ca2c52aSchristos bh = (signed32)(signed16)EV_HIHALF(*rBh); 11746ca2c52aSchristos t1 = ah * bh; 11756ca2c52aSchristos t2 = al * bl; 11766ca2c52aSchristos th = EV_ACCHIGH + t1; 11776ca2c52aSchristos tl = EV_ACCLOW + t2; 11786ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 11796ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 11806ca2c52aSchristos 11816ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words 11826ca2c52aSchristos unsigned32 al, ah, bl, bh; 11836ca2c52aSchristos unsigned64 t1, t2; 11846ca2c52aSchristos signed64 tl, th; 11856ca2c52aSchristos int ovl, ovh; 11866ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 11876ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 11886ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 11896ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 11906ca2c52aSchristos t1 = ah * bh; 11916ca2c52aSchristos t2 = al * bl; 11926ca2c52aSchristos th = (signed64)EV_ACCHIGH + (signed64)t1; 11936ca2c52aSchristos tl = (signed64)EV_ACCLOW + (signed64)t2; 11946ca2c52aSchristos ovh = EV_SAT_P_U32(th); 11956ca2c52aSchristos ovl = EV_SAT_P_U32(tl); 11966ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 11976ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 11986ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 11996ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 12006ca2c52aSchristos 12016ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words 12026ca2c52aSchristos unsigned32 al, ah, bl, bh; 12036ca2c52aSchristos unsigned32 t1, t2; 12046ca2c52aSchristos unsigned64 tl, th; 12056ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 12066ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 12076ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 12086ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 12096ca2c52aSchristos t1 = ah * bh; 12106ca2c52aSchristos t2 = al * bl; 12116ca2c52aSchristos th = EV_ACCHIGH + t1; 12126ca2c52aSchristos tl = EV_ACCLOW + t2; 12136ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 12146ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 12156ca2c52aSchristos 12166ca2c52aSchristos 12176ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words 12186ca2c52aSchristos signed16 al, ah, bl, bh; 12196ca2c52aSchristos signed32 t1, t2; 12206ca2c52aSchristos signed64 tl, th; 12216ca2c52aSchristos int movl, movh, ovl, ovh; 12226ca2c52aSchristos 12236ca2c52aSchristos al = (signed16) EV_LOHALF (*rA); 12246ca2c52aSchristos ah = (signed16) EV_LOHALF (*rAh); 12256ca2c52aSchristos bl = (signed16) EV_LOHALF (*rB); 12266ca2c52aSchristos bh = (signed16) EV_LOHALF (*rBh); 12276ca2c52aSchristos t1 = ev_multiply16_ssf (ah, bh, &movh); 12286ca2c52aSchristos t2 = ev_multiply16_ssf (al, bl, &movl); 12296ca2c52aSchristos th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); 12306ca2c52aSchristos tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); 12316ca2c52aSchristos ovh = EV_SAT_P_S32 (th); 12326ca2c52aSchristos ovl = EV_SAT_P_S32 (tl); 12336ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 12346ca2c52aSchristos EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 12356ca2c52aSchristos EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 12366ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 12376ca2c52aSchristos 12386ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words 12396ca2c52aSchristos signed32 al, ah, bl, bh; 12406ca2c52aSchristos signed64 t1, t2, tl, th; 12416ca2c52aSchristos int ovl, ovh; 12426ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 12436ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 12446ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 12456ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 12466ca2c52aSchristos t1 = ah * bh; 12476ca2c52aSchristos t2 = al * bl; 12486ca2c52aSchristos th = EV_ACCHIGH - t1; 12496ca2c52aSchristos tl = EV_ACCLOW - t2; 12506ca2c52aSchristos ovh = EV_SAT_P_S32(th); 12516ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 12526ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 12536ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 12546ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 12556ca2c52aSchristos //printf("evmhossianw: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); 12566ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 12576ca2c52aSchristos 12586ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words 12596ca2c52aSchristos signed32 al, ah, bl, bh; 12606ca2c52aSchristos signed64 t1, t2, tl, th; 12616ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 12626ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 12636ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 12646ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 12656ca2c52aSchristos t1 = ((signed64)ah * bh) << 1; 12666ca2c52aSchristos t2 = ((signed64)al * bl) << 1; 12676ca2c52aSchristos th = EV_ACCHIGH - (t1 & 0xffffffff); 12686ca2c52aSchristos tl = EV_ACCLOW - (t2 & 0xffffffff); 12696ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 12706ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 12716ca2c52aSchristos 12726ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words 12736ca2c52aSchristos signed32 al, ah, bl, bh; 12746ca2c52aSchristos signed64 t1, t2, tl, th; 12756ca2c52aSchristos al = (signed32)(signed16)EV_LOHALF(*rA); 12766ca2c52aSchristos ah = (signed32)(signed16)EV_LOHALF(*rAh); 12776ca2c52aSchristos bl = (signed32)(signed16)EV_LOHALF(*rB); 12786ca2c52aSchristos bh = (signed32)(signed16)EV_LOHALF(*rBh); 12796ca2c52aSchristos t1 = ah * bh; 12806ca2c52aSchristos t2 = al * bl; 12816ca2c52aSchristos th = EV_ACCHIGH - t1; 12826ca2c52aSchristos tl = EV_ACCLOW - t2; 12836ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 12846ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 12856ca2c52aSchristos 12866ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words 12876ca2c52aSchristos unsigned32 al, ah, bl, bh; 12886ca2c52aSchristos unsigned64 t1, t2; 12896ca2c52aSchristos signed64 tl, th; 12906ca2c52aSchristos int ovl, ovh; 12916ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 12926ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 12936ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 12946ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 12956ca2c52aSchristos t1 = ah * bh; 12966ca2c52aSchristos t2 = al * bl; 12976ca2c52aSchristos th = (signed64)EV_ACCHIGH - (signed64)t1; 12986ca2c52aSchristos tl = (signed64)EV_ACCLOW - (signed64)t2; 12996ca2c52aSchristos ovl = EV_SAT_P_U32(tl); 13006ca2c52aSchristos ovh = EV_SAT_P_U32(th); 13016ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 13026ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 13036ca2c52aSchristos //printf("evmhousianw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 13046ca2c52aSchristos //printf("evmoussianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 13056ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 13066ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 13076ca2c52aSchristos 13086ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words 13096ca2c52aSchristos unsigned32 al, ah, bl, bh; 13106ca2c52aSchristos unsigned32 t1, t2; 13116ca2c52aSchristos unsigned64 tl, th; 13126ca2c52aSchristos al = (unsigned32)(unsigned16)EV_LOHALF(*rA); 13136ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); 13146ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); 13156ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); 13166ca2c52aSchristos t1 = ah * bh; 13176ca2c52aSchristos t2 = al * bl; 13186ca2c52aSchristos th = EV_ACCHIGH - t1; 13196ca2c52aSchristos tl = EV_ACCLOW - t2; 13206ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 13216ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 13226ca2c52aSchristos 13236ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words 13246ca2c52aSchristos signed16 al, ah, bl, bh; 13256ca2c52aSchristos signed32 t1, t2; 13266ca2c52aSchristos signed64 tl, th; 13276ca2c52aSchristos int movl, movh, ovl, ovh; 13286ca2c52aSchristos 13296ca2c52aSchristos al = (signed16) EV_HIHALF (*rA); 13306ca2c52aSchristos ah = (signed16) EV_HIHALF (*rAh); 13316ca2c52aSchristos bl = (signed16) EV_HIHALF (*rB); 13326ca2c52aSchristos bh = (signed16) EV_HIHALF (*rBh); 13336ca2c52aSchristos t1 = ev_multiply16_ssf (ah, bh, &movh); 13346ca2c52aSchristos t2 = ev_multiply16_ssf (al, bl, &movl); 13356ca2c52aSchristos th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); 13366ca2c52aSchristos tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); 13376ca2c52aSchristos ovh = EV_SAT_P_S32 (th); 13386ca2c52aSchristos ovl = EV_SAT_P_S32 (tl); 13396ca2c52aSchristos EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 13406ca2c52aSchristos EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 13416ca2c52aSchristos EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 13426ca2c52aSchristos PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 13436ca2c52aSchristos 13446ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words 13456ca2c52aSchristos signed32 al, ah, bl, bh; 13466ca2c52aSchristos signed64 t1, t2, tl, th; 13476ca2c52aSchristos int ovl, ovh; 13486ca2c52aSchristos al = (signed32)(signed16)EV_HIHALF(*rA); 13496ca2c52aSchristos ah = (signed32)(signed16)EV_HIHALF(*rAh); 13506ca2c52aSchristos bl = (signed32)(signed16)EV_HIHALF(*rB); 13516ca2c52aSchristos bh = (signed32)(signed16)EV_HIHALF(*rBh); 13526ca2c52aSchristos t1 = ah * bh; 13536ca2c52aSchristos t2 = al * bl; 13546ca2c52aSchristos th = EV_ACCHIGH - t1; 13556ca2c52aSchristos tl = EV_ACCLOW - t2; 13566ca2c52aSchristos ovh = EV_SAT_P_S32(th); 13576ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 13586ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 13596ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 13606ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 13616ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 13626ca2c52aSchristos 13636ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words 13646ca2c52aSchristos signed32 al, ah, bl, bh; 13656ca2c52aSchristos signed64 t1, t2, tl, th; 13666ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 13676ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 13686ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 13696ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 13706ca2c52aSchristos t1 = ((signed64)ah * bh) << 1; 13716ca2c52aSchristos t2 = ((signed64)al * bl) << 1; 13726ca2c52aSchristos th = EV_ACCHIGH - (t1 & 0xffffffff); 13736ca2c52aSchristos tl = EV_ACCLOW - (t2 & 0xffffffff); 13746ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 13756ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 13766ca2c52aSchristos 13776ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words 13786ca2c52aSchristos signed32 al, ah, bl, bh; 13796ca2c52aSchristos signed64 t1, t2, tl, th; 13806ca2c52aSchristos al = (signed32)(signed16)EV_HIHALF(*rA); 13816ca2c52aSchristos ah = (signed32)(signed16)EV_HIHALF(*rAh); 13826ca2c52aSchristos bl = (signed32)(signed16)EV_HIHALF(*rB); 13836ca2c52aSchristos bh = (signed32)(signed16)EV_HIHALF(*rBh); 13846ca2c52aSchristos t1 = ah * bh; 13856ca2c52aSchristos t2 = al * bl; 13866ca2c52aSchristos th = EV_ACCHIGH - t1; 13876ca2c52aSchristos tl = EV_ACCLOW - t2; 13886ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 13896ca2c52aSchristos //printf("evmhesmianw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); 13906ca2c52aSchristos //printf("evmhesmianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 13916ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 13926ca2c52aSchristos 13936ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words 13946ca2c52aSchristos unsigned32 al, ah, bl, bh; 13956ca2c52aSchristos unsigned64 t1, t2; 13966ca2c52aSchristos signed64 tl, th; 13976ca2c52aSchristos int ovl, ovh; 13986ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 13996ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 14006ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 14016ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 14026ca2c52aSchristos t1 = ah * bh; 14036ca2c52aSchristos t2 = al * bl; 14046ca2c52aSchristos th = (signed64)EV_ACCHIGH - (signed64)t1; 14056ca2c52aSchristos tl = (signed64)EV_ACCLOW - (signed64)t2; 14066ca2c52aSchristos ovl = EV_SAT_P_U32(tl); 14076ca2c52aSchristos ovh = EV_SAT_P_U32(th); 14086ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 14096ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 14106ca2c52aSchristos //printf("evmheusianw: ovh %d ovl %d al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 14116ca2c52aSchristos //printf("evmheusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 14126ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 14136ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 14146ca2c52aSchristos 14156ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words 14166ca2c52aSchristos unsigned32 al, ah, bl, bh; 14176ca2c52aSchristos unsigned32 t1, t2; 14186ca2c52aSchristos unsigned64 tl, th; 14196ca2c52aSchristos al = (unsigned32)(unsigned16)EV_HIHALF(*rA); 14206ca2c52aSchristos ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); 14216ca2c52aSchristos bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); 14226ca2c52aSchristos bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); 14236ca2c52aSchristos t1 = ah * bh; 14246ca2c52aSchristos t2 = al * bl; 14256ca2c52aSchristos th = EV_ACCHIGH - t1; 14266ca2c52aSchristos tl = EV_ACCLOW - t2; 14276ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 14286ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14296ca2c52aSchristos 14306ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate 14316ca2c52aSchristos signed32 a, b; 14326ca2c52aSchristos signed64 t1, t2; 14336ca2c52aSchristos a = (signed32)(signed16)EV_LOHALF(*rA); 14346ca2c52aSchristos b = (signed32)(signed16)EV_LOHALF(*rB); 14356ca2c52aSchristos t1 = EV_MUL16_SSF(a, b); 14366ca2c52aSchristos if (t1 & ((unsigned64)1 << 32)) 14376ca2c52aSchristos t1 |= 0xfffffffe00000000; 14386ca2c52aSchristos t2 = ACC + t1; 14396ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14406ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14416ca2c52aSchristos 14426ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate 14436ca2c52aSchristos signed32 a, b; 14446ca2c52aSchristos signed64 t1, t2; 14456ca2c52aSchristos a = (signed32)(signed16)EV_LOHALF(*rA); 14466ca2c52aSchristos b = (signed32)(signed16)EV_LOHALF(*rB); 14476ca2c52aSchristos t1 = (signed64)a * (signed64)b; 14486ca2c52aSchristos t2 = (signed64)ACC + t1; 14496ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14506ca2c52aSchristos //printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); 14516ca2c52aSchristos //printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 14526ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14536ca2c52aSchristos 14546ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate 14556ca2c52aSchristos unsigned32 a, b; 14566ca2c52aSchristos unsigned64 t1, t2; 14576ca2c52aSchristos a = (unsigned32)(unsigned16)EV_LOHALF(*rA); 14586ca2c52aSchristos b = (unsigned32)(unsigned16)EV_LOHALF(*rB); 14596ca2c52aSchristos t1 = a * b; 14606ca2c52aSchristos t2 = ACC + t1; 14616ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14626ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14636ca2c52aSchristos 14646ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate 14656ca2c52aSchristos signed32 a, b; 14666ca2c52aSchristos signed64 t1, t2; 14676ca2c52aSchristos a = (signed32)(signed16)EV_HIHALF(*rA); 14686ca2c52aSchristos b = (signed32)(signed16)EV_HIHALF(*rB); 14696ca2c52aSchristos t1 = EV_MUL16_SSF(a, b); 14706ca2c52aSchristos if (t1 & ((unsigned64)1 << 32)) 14716ca2c52aSchristos t1 |= 0xfffffffe00000000; 14726ca2c52aSchristos t2 = ACC + t1; 14736ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14746ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14756ca2c52aSchristos 14766ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate 14776ca2c52aSchristos signed32 a, b; 14786ca2c52aSchristos signed64 t1, t2; 14796ca2c52aSchristos a = (signed32)(signed16)EV_HIHALF(*rA); 14806ca2c52aSchristos b = (signed32)(signed16)EV_HIHALF(*rB); 14816ca2c52aSchristos t1 = (signed64)(a * b); 14826ca2c52aSchristos t2 = ACC + t1; 14836ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14846ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14856ca2c52aSchristos 14866ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate 14876ca2c52aSchristos unsigned32 a, b; 14886ca2c52aSchristos unsigned64 t1, t2; 14896ca2c52aSchristos a = (unsigned32)(unsigned16)EV_HIHALF(*rA); 14906ca2c52aSchristos b = (unsigned32)(unsigned16)EV_HIHALF(*rB); 14916ca2c52aSchristos t1 = a * b; 14926ca2c52aSchristos t2 = ACC + t1; 14936ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 14946ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 14956ca2c52aSchristos 14966ca2c52aSchristos 14976ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative 14986ca2c52aSchristos signed32 a, b; 14996ca2c52aSchristos signed64 t1, t2; 15006ca2c52aSchristos a = (signed32)(signed16)EV_LOHALF(*rA); 15016ca2c52aSchristos b = (signed32)(signed16)EV_LOHALF(*rB); 15026ca2c52aSchristos t1 = EV_MUL16_SSF(a, b); 15036ca2c52aSchristos if (t1 & ((unsigned64)1 << 32)) 15046ca2c52aSchristos t1 |= 0xfffffffe00000000; 15056ca2c52aSchristos t2 = ACC - t1; 15066ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15076ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15086ca2c52aSchristos 15096ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative 15106ca2c52aSchristos signed32 a, b; 15116ca2c52aSchristos signed64 t1, t2; 15126ca2c52aSchristos a = (signed32)(signed16)EV_LOHALF(*rA); 15136ca2c52aSchristos b = (signed32)(signed16)EV_LOHALF(*rB); 15146ca2c52aSchristos t1 = (signed64)a * (signed64)b; 15156ca2c52aSchristos t2 = ACC - t1; 15166ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15176ca2c52aSchristos //printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); 15186ca2c52aSchristos //printf("evmhogsmian: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 15196ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15206ca2c52aSchristos 15216ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative 15226ca2c52aSchristos unsigned32 a, b; 15236ca2c52aSchristos unsigned64 t1, t2; 15246ca2c52aSchristos a = (unsigned32)(unsigned16)EV_LOHALF(*rA); 15256ca2c52aSchristos b = (unsigned32)(unsigned16)EV_LOHALF(*rB); 15266ca2c52aSchristos t1 = (unsigned64)a * (unsigned64)b; 15276ca2c52aSchristos t2 = ACC - t1; 15286ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15296ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15306ca2c52aSchristos 15316ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative 15326ca2c52aSchristos signed32 a, b; 15336ca2c52aSchristos signed64 t1, t2; 15346ca2c52aSchristos a = (signed32)(signed16)EV_HIHALF(*rA); 15356ca2c52aSchristos b = (signed32)(signed16)EV_HIHALF(*rB); 15366ca2c52aSchristos t1 = EV_MUL16_SSF(a, b); 15376ca2c52aSchristos if (t1 & ((unsigned64)1 << 32)) 15386ca2c52aSchristos t1 |= 0xfffffffe00000000; 15396ca2c52aSchristos t2 = ACC - t1; 15406ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15416ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15426ca2c52aSchristos 15436ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative 15446ca2c52aSchristos signed32 a, b; 15456ca2c52aSchristos signed64 t1, t2; 15466ca2c52aSchristos a = (signed32)(signed16)EV_HIHALF(*rA); 15476ca2c52aSchristos b = (signed32)(signed16)EV_HIHALF(*rB); 15486ca2c52aSchristos t1 = (signed64)a * (signed64)b; 15496ca2c52aSchristos t2 = ACC - t1; 15506ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15516ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15526ca2c52aSchristos 15536ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative 15546ca2c52aSchristos unsigned32 a, b; 15556ca2c52aSchristos unsigned64 t1, t2; 15566ca2c52aSchristos a = (unsigned32)(unsigned16)EV_HIHALF(*rA); 15576ca2c52aSchristos b = (unsigned32)(unsigned16)EV_HIHALF(*rB); 15586ca2c52aSchristos t1 = (unsigned64)a * (unsigned64)b; 15596ca2c52aSchristos t2 = ACC - t1; 15606ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 15616ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 15626ca2c52aSchristos 15636ca2c52aSchristos 15646ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional 15656ca2c52aSchristos signed32 al, ah, bl, bh; 15666ca2c52aSchristos signed64 t1, t2; 15676ca2c52aSchristos int movl, movh; 15686ca2c52aSchristos al = *rA; 15696ca2c52aSchristos ah = *rAh; 15706ca2c52aSchristos bl = *rB; 15716ca2c52aSchristos bh = *rBh; 15726ca2c52aSchristos t1 = ev_multiply32_ssf(al, bl, &movl); 15736ca2c52aSchristos t2 = ev_multiply32_ssf(ah, bh, &movh); 15746ca2c52aSchristos EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), 15756ca2c52aSchristos EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); 15766ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, movh); 15776ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 15786ca2c52aSchristos 15796ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate 15806ca2c52aSchristos signed32 al, ah, bl, bh; 15816ca2c52aSchristos signed64 t1, t2; 15826ca2c52aSchristos int movl, movh; 15836ca2c52aSchristos al = *rA; 15846ca2c52aSchristos ah = *rAh; 15856ca2c52aSchristos bl = *rB; 15866ca2c52aSchristos bh = *rBh; 15876ca2c52aSchristos t1 = ev_multiply32_ssf(al, bl, &movl); 15886ca2c52aSchristos t2 = ev_multiply32_ssf(ah, bh, &movh); 15896ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), 15906ca2c52aSchristos EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); 15916ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, movh); 15926ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 15936ca2c52aSchristos 15946ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional 15956ca2c52aSchristos signed32 al, ah, bl, bh; 15966ca2c52aSchristos signed64 t1, t2; 15976ca2c52aSchristos al = *rA; 15986ca2c52aSchristos ah = *rAh; 15996ca2c52aSchristos bl = *rB; 16006ca2c52aSchristos bh = *rBh; 16016ca2c52aSchristos t1 = EV_MUL32_SSF(al, bl); 16026ca2c52aSchristos t2 = EV_MUL32_SSF(ah, bh); 16036ca2c52aSchristos EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 16046ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16056ca2c52aSchristos 16066ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate 16076ca2c52aSchristos signed32 al, ah, bl, bh; 16086ca2c52aSchristos signed64 t1, t2; 16096ca2c52aSchristos al = *rA; 16106ca2c52aSchristos ah = *rAh; 16116ca2c52aSchristos bl = *rB; 16126ca2c52aSchristos bh = *rBh; 16136ca2c52aSchristos t1 = EV_MUL32_SSF(al, bl); 16146ca2c52aSchristos t2 = EV_MUL32_SSF(ah, bh); 16156ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 16166ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16176ca2c52aSchristos 16186ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer 16196ca2c52aSchristos signed32 al, ah, bl, bh; 16206ca2c52aSchristos signed64 t1, t2; 16216ca2c52aSchristos al = *rA; 16226ca2c52aSchristos ah = *rAh; 16236ca2c52aSchristos bl = *rB; 16246ca2c52aSchristos bh = *rBh; 16256ca2c52aSchristos t1 = (signed64)al * (signed64)bl; 16266ca2c52aSchristos t2 = (signed64)ah * (signed64)bh; 16276ca2c52aSchristos EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 16286ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16296ca2c52aSchristos 16306ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate 16316ca2c52aSchristos signed32 al, ah, bl, bh; 16326ca2c52aSchristos signed64 t1, t2; 16336ca2c52aSchristos al = *rA; 16346ca2c52aSchristos ah = *rAh; 16356ca2c52aSchristos bl = *rB; 16366ca2c52aSchristos bh = *rBh; 16376ca2c52aSchristos t1 = (signed64)al * (signed64)bl; 16386ca2c52aSchristos t2 = (signed64)ah * (signed64)bh; 16396ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 16406ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16416ca2c52aSchristos 16426ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer 16436ca2c52aSchristos unsigned32 al, ah, bl, bh; 16446ca2c52aSchristos unsigned64 t1, t2; 16456ca2c52aSchristos al = *rA; 16466ca2c52aSchristos ah = *rAh; 16476ca2c52aSchristos bl = *rB; 16486ca2c52aSchristos bh = *rBh; 16496ca2c52aSchristos t1 = (unsigned64)al * (unsigned64)bl; 16506ca2c52aSchristos t2 = (unsigned64)ah * (unsigned64)bh; 16516ca2c52aSchristos EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 16526ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16536ca2c52aSchristos 16546ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate 16556ca2c52aSchristos unsigned32 al, ah, bl, bh; 16566ca2c52aSchristos unsigned64 t1, t2; 16576ca2c52aSchristos al = *rA; 16586ca2c52aSchristos ah = *rAh; 16596ca2c52aSchristos bl = *rB; 16606ca2c52aSchristos bh = *rBh; 16616ca2c52aSchristos t1 = (unsigned64)al * (unsigned64)bl; 16626ca2c52aSchristos t2 = (unsigned64)ah * (unsigned64)bh; 16636ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 16646ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 16656ca2c52aSchristos 16666ca2c52aSchristos 16676ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional 16686ca2c52aSchristos signed32 al, ah, bl, bh; 16696ca2c52aSchristos signed64 t1, t2; 16706ca2c52aSchristos int movl, movh; 16716ca2c52aSchristos al = *rA; 16726ca2c52aSchristos ah = *rAh; 16736ca2c52aSchristos bl = *rB; 16746ca2c52aSchristos bh = *rBh; 16756ca2c52aSchristos t1 = ev_multiply32_ssf(al, bl, &movl); 16766ca2c52aSchristos t2 = ev_multiply32_ssf(ah, bh, &movh); 16776ca2c52aSchristos EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), 16786ca2c52aSchristos EV_SATURATE(movl, 0xffffffff, t1)); 16796ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, movh); 16806ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 16816ca2c52aSchristos 16826ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate 16836ca2c52aSchristos signed32 al, ah, bl, bh; 16846ca2c52aSchristos signed64 t1, t2; 16856ca2c52aSchristos int movl, movh; 16866ca2c52aSchristos al = *rA; 16876ca2c52aSchristos ah = *rAh; 16886ca2c52aSchristos bl = *rB; 16896ca2c52aSchristos bh = *rBh; 16906ca2c52aSchristos t1 = ev_multiply32_ssf(al, bl, &movl); 16916ca2c52aSchristos t2 = ev_multiply32_ssf(ah, bh, &movh); 16926ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), 16936ca2c52aSchristos EV_SATURATE(movl, 0xffffffff, t1)); 16946ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, movh); 16956ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 16966ca2c52aSchristos 16976ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional 16986ca2c52aSchristos signed32 al, ah, bl, bh; 16996ca2c52aSchristos signed64 t1, t2; 17006ca2c52aSchristos al = *rA; 17016ca2c52aSchristos ah = *rAh; 17026ca2c52aSchristos bl = *rB; 17036ca2c52aSchristos bh = *rBh; 17046ca2c52aSchristos t1 = EV_MUL32_SSF(al, bl); 17056ca2c52aSchristos t2 = EV_MUL32_SSF(ah, bh); 17066ca2c52aSchristos EV_SET_REG2(*rSh, *rS, t2, t1); 17076ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 17086ca2c52aSchristos 17096ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate 17106ca2c52aSchristos signed32 al, ah, bl, bh; 17116ca2c52aSchristos signed64 t1, t2; 17126ca2c52aSchristos al = *rA; 17136ca2c52aSchristos ah = *rAh; 17146ca2c52aSchristos bl = *rB; 17156ca2c52aSchristos bh = *rBh; 17166ca2c52aSchristos t1 = EV_MUL32_SSF(al, bl); 17176ca2c52aSchristos t2 = EV_MUL32_SSF(ah, bh); 17186ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t2, t1); 17196ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 17206ca2c52aSchristos 17216ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer 17226ca2c52aSchristos unsigned32 al, ah, bl, bh; 17236ca2c52aSchristos unsigned64 t1, t2; 17246ca2c52aSchristos al = *rA; 17256ca2c52aSchristos ah = *rAh; 17266ca2c52aSchristos bl = *rB; 17276ca2c52aSchristos bh = *rBh; 17286ca2c52aSchristos t1 = (unsigned64)al * (unsigned64)bl; 17296ca2c52aSchristos t2 = (unsigned64)ah * (unsigned64)bh; 17306ca2c52aSchristos EV_SET_REG2(*rSh, *rS, t2, t1); 17316ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 17326ca2c52aSchristos 17336ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate 17346ca2c52aSchristos unsigned32 al, ah, bl, bh; 17356ca2c52aSchristos unsigned64 t1, t2; 17366ca2c52aSchristos al = *rA; 17376ca2c52aSchristos ah = *rAh; 17386ca2c52aSchristos bl = *rB; 17396ca2c52aSchristos bh = *rBh; 17406ca2c52aSchristos t1 = (unsigned64)al * (unsigned64)bl; 17416ca2c52aSchristos t2 = (unsigned64)ah * (unsigned64)bh; 17426ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t2, t1); 17436ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 17446ca2c52aSchristos 17456ca2c52aSchristos 17466ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words 17476ca2c52aSchristos signed32 al, ah, bl, bh; 17486ca2c52aSchristos signed64 t1, t2, tl, th; 17496ca2c52aSchristos int movl, movh, ovl, ovh; 17506ca2c52aSchristos al = *rA; 17516ca2c52aSchristos ah = *rAh; 17526ca2c52aSchristos bl = *rB; 17536ca2c52aSchristos bh = *rBh; 17546ca2c52aSchristos t1 = ev_multiply32_ssf(ah, bh, &movh); 17556ca2c52aSchristos t2 = ev_multiply32_ssf(al, bl, &movl); 17566ca2c52aSchristos th = EV_ACCHIGH + EV_SATURATE(movh, 0xffffffff, t1); 17576ca2c52aSchristos tl = EV_ACCLOW + EV_SATURATE(movl, 0xffffffff, t2); 17586ca2c52aSchristos ovh = EV_SAT_P_S32(th); 17596ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 17606ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 17616ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 17626ca2c52aSchristos EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); 17636ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 17646ca2c52aSchristos 17656ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words 17666ca2c52aSchristos signed32 al, ah, bl, bh; 17676ca2c52aSchristos signed64 t1, t2, tl, th; 17686ca2c52aSchristos int ovl, ovh; 17696ca2c52aSchristos al = *rA; 17706ca2c52aSchristos ah = *rAh; 17716ca2c52aSchristos bl = *rB; 17726ca2c52aSchristos bh = *rBh; 17736ca2c52aSchristos t1 = (signed64)ah * (signed64)bh; 17746ca2c52aSchristos t2 = (signed64)al * (signed64)bl; 17756ca2c52aSchristos th = EV_ACCHIGH + (t1 & 0xffffffff); 17766ca2c52aSchristos tl = EV_ACCLOW + (t2 & 0xffffffff); 17776ca2c52aSchristos ovh = EV_SAT_P_S32(th); 17786ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 17796ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 17806ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 17816ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 17826ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 17836ca2c52aSchristos 17846ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words 17856ca2c52aSchristos signed32 al, ah, bl, bh; 17866ca2c52aSchristos signed64 t1, t2; 17876ca2c52aSchristos int mov; 17886ca2c52aSchristos al = *rA; 17896ca2c52aSchristos ah = *rAh; 17906ca2c52aSchristos bl = *rB; 17916ca2c52aSchristos bh = *rBh; 17926ca2c52aSchristos t1 = ev_multiply32_smf(ah, bh, &mov); 17936ca2c52aSchristos t2 = ev_multiply32_smf(al, bl, &mov); 17946ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 17956ca2c52aSchristos EV_ACCLOW + (t2 & 0xffffffff)); 17966ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 17976ca2c52aSchristos 17986ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words 17996ca2c52aSchristos signed32 al, ah, bl, bh; 18006ca2c52aSchristos signed64 t1, t2; 18016ca2c52aSchristos al = *rA; 18026ca2c52aSchristos ah = *rAh; 18036ca2c52aSchristos bl = *rB; 18046ca2c52aSchristos bh = *rBh; 18056ca2c52aSchristos t1 = (signed64)ah * (signed64)bh; 18066ca2c52aSchristos t2 = (signed64)al * (signed64)bl; 18076ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 18086ca2c52aSchristos EV_ACCLOW + (t2 & 0xffffffff)); 18096ca2c52aSchristos //printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2); 18106ca2c52aSchristos //printf("evmwlsmiaaw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 18116ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 18126ca2c52aSchristos 18136ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words 18146ca2c52aSchristos unsigned32 al, ah, bl, bh; 18156ca2c52aSchristos unsigned64 t1, t2, tl, th; 18166ca2c52aSchristos int ovl, ovh; 18176ca2c52aSchristos al = *rA; 18186ca2c52aSchristos ah = *rAh; 18196ca2c52aSchristos bl = *rB; 18206ca2c52aSchristos bh = *rBh; 18216ca2c52aSchristos t1 = (unsigned64)ah * (unsigned64)bh; 18226ca2c52aSchristos t2 = (unsigned64)al * (unsigned64)bl; 18236ca2c52aSchristos th = EV_ACCHIGH + (t1 & 0xffffffff); 18246ca2c52aSchristos tl = EV_ACCLOW + (t2 & 0xffffffff); 18256ca2c52aSchristos ovh = (th >> 32); 18266ca2c52aSchristos ovl = (tl >> 32); 18276ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), 18286ca2c52aSchristos EV_SATURATE(ovl, 0xffffffff, tl)); 18296ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 18306ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 18316ca2c52aSchristos 18326ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words 18336ca2c52aSchristos unsigned32 al, ah, bl, bh; 18346ca2c52aSchristos unsigned64 t1, t2; 18356ca2c52aSchristos al = *rA; 18366ca2c52aSchristos ah = *rAh; 18376ca2c52aSchristos bl = *rB; 18386ca2c52aSchristos bh = *rBh; 18396ca2c52aSchristos t1 = (unsigned64)ah * (unsigned64)bh; 18406ca2c52aSchristos t2 = (unsigned64)al * (unsigned64)bl; 18416ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 18426ca2c52aSchristos EV_ACCLOW + (t2 & 0xffffffff)); 18436ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 18446ca2c52aSchristos 18456ca2c52aSchristos 18466ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words 18476ca2c52aSchristos signed32 al, ah, bl, bh; 18486ca2c52aSchristos signed64 t1, t2, tl, th; 18496ca2c52aSchristos int movl, movh, ovl, ovh; 18506ca2c52aSchristos al = *rA; 18516ca2c52aSchristos ah = *rAh; 18526ca2c52aSchristos bl = *rB; 18536ca2c52aSchristos bh = *rBh; 18546ca2c52aSchristos t1 = ev_multiply32_ssf(ah, bh, &movh); 18556ca2c52aSchristos t2 = ev_multiply32_ssf(al, bl, &movl); 18566ca2c52aSchristos th = EV_ACCHIGH - EV_SATURATE(movh, 0xffffffff, t1); 18576ca2c52aSchristos tl = EV_ACCLOW - EV_SATURATE(movl, 0xffffffff, t2); 18586ca2c52aSchristos ovh = EV_SAT_P_S32(th); 18596ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 18606ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 18616ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 18626ca2c52aSchristos EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); 18636ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 18646ca2c52aSchristos 18656ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1473:EVX:e500:evmwlssianw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate Negative in Words 18666ca2c52aSchristos signed32 al, ah, bl, bh; 18676ca2c52aSchristos signed64 t1, t2, tl, th; 18686ca2c52aSchristos int ovl, ovh; 18696ca2c52aSchristos al = *rA; 18706ca2c52aSchristos ah = *rAh; 18716ca2c52aSchristos bl = *rB; 18726ca2c52aSchristos bh = *rBh; 18736ca2c52aSchristos t1 = (signed64)ah * (signed64)bh; 18746ca2c52aSchristos t2 = (signed64)al * (signed64)bl; 18756ca2c52aSchristos th = EV_ACCHIGH - (t1 & 0xffffffff); 18766ca2c52aSchristos tl = EV_ACCLOW - (t2 & 0xffffffff); 18776ca2c52aSchristos ovh = EV_SAT_P_S32(th); 18786ca2c52aSchristos ovl = EV_SAT_P_S32(tl); 18796ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 18806ca2c52aSchristos EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 18816ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 18826ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 18836ca2c52aSchristos 18846ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1483:EVX:e500:evmwlsmfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate Negative in Words 18856ca2c52aSchristos signed32 al, ah, bl, bh; 18866ca2c52aSchristos signed64 t1, t2; 18876ca2c52aSchristos int mov; 18886ca2c52aSchristos al = *rA; 18896ca2c52aSchristos ah = *rAh; 18906ca2c52aSchristos bl = *rB; 18916ca2c52aSchristos bh = *rBh; 18926ca2c52aSchristos t1 = ev_multiply32_smf(ah, bh, &mov); 18936ca2c52aSchristos t2 = ev_multiply32_smf(al, bl, &mov); 18946ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 18956ca2c52aSchristos EV_ACCLOW - (t2 & 0xffffffff)); 18966ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 18976ca2c52aSchristos 18986ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1481:EVX:e500:evmwlsmianw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate Negative in Words 18996ca2c52aSchristos signed32 al, ah, bl, bh; 19006ca2c52aSchristos signed64 t1, t2; 19016ca2c52aSchristos al = *rA; 19026ca2c52aSchristos ah = *rAh; 19036ca2c52aSchristos bl = *rB; 19046ca2c52aSchristos bh = *rBh; 19056ca2c52aSchristos t1 = (signed64)ah * (signed64)bh; 19066ca2c52aSchristos t2 = (signed64)al * (signed64)bl; 19076ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 19086ca2c52aSchristos EV_ACCLOW - (t2 & 0xffffffff)); 19096ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 19106ca2c52aSchristos 19116ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1472:EVX:e500:evmwlusianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate Negative in Words 19126ca2c52aSchristos unsigned32 al, ah, bl, bh; 19136ca2c52aSchristos unsigned64 t1, t2, tl, th; 19146ca2c52aSchristos int ovl, ovh; 19156ca2c52aSchristos al = *rA; 19166ca2c52aSchristos ah = *rAh; 19176ca2c52aSchristos bl = *rB; 19186ca2c52aSchristos bh = *rBh; 19196ca2c52aSchristos t1 = (unsigned64)ah * (unsigned64)bh; 19206ca2c52aSchristos t2 = (unsigned64)al * (unsigned64)bl; 19216ca2c52aSchristos th = EV_ACCHIGH - (t1 & 0xffffffff); 19226ca2c52aSchristos tl = EV_ACCLOW - (t2 & 0xffffffff); 19236ca2c52aSchristos ovh = (th >> 32); 19246ca2c52aSchristos ovl = (tl >> 32); 19256ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), 19266ca2c52aSchristos EV_SATURATE(ovl, 0xffffffff, tl)); 19276ca2c52aSchristos //printf("evmwlusianw: ovl %d ovh %d al %d ah %d bl %d bh %d t1 %qd t2 %qd th %qd tl %qd\n", ovl, ovh, al, ah, al, bh, t1, t2, th, tl); 19286ca2c52aSchristos //printf("evmwlusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 19296ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 19306ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 19316ca2c52aSchristos 19326ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1480:EVX:e500:evmwlumianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words 19336ca2c52aSchristos unsigned32 al, ah, bl, bh; 19346ca2c52aSchristos unsigned64 t1, t2; 19356ca2c52aSchristos al = *rA; 19366ca2c52aSchristos ah = *rAh; 19376ca2c52aSchristos bl = *rB; 19386ca2c52aSchristos bh = *rBh; 19396ca2c52aSchristos t1 = (unsigned64)ah * (unsigned64)bh; 19406ca2c52aSchristos t2 = (unsigned64)al * (unsigned64)bl; 19416ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 19426ca2c52aSchristos EV_ACCLOW - (t2 & 0xffffffff)); 19436ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 19446ca2c52aSchristos 19456ca2c52aSchristos 19466ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1107:EVX:e500:evmwssf %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional 19476ca2c52aSchristos signed32 a, b; 19486ca2c52aSchristos signed64 t; 19496ca2c52aSchristos int movl; 19506ca2c52aSchristos a = *rA; 19516ca2c52aSchristos b = *rB; 19526ca2c52aSchristos t = ev_multiply32_ssf(a, b, &movl); 19536ca2c52aSchristos EV_SET_REG1(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); 19546ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, 0); 19556ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 19566ca2c52aSchristos 19576ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1139:EVX:e500:evmwssfa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate 19586ca2c52aSchristos signed32 a, b; 19596ca2c52aSchristos signed64 t; 19606ca2c52aSchristos int movl; 19616ca2c52aSchristos a = *rA; 19626ca2c52aSchristos b = *rB; 19636ca2c52aSchristos t = ev_multiply32_ssf(a, b, &movl); 19646ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); 19656ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, 0); 19666ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 19676ca2c52aSchristos 19686ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1115:EVX:e500:evmwsmf %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional 19696ca2c52aSchristos signed32 a, b; 19706ca2c52aSchristos signed64 t; 19716ca2c52aSchristos int movl; 19726ca2c52aSchristos a = *rA; 19736ca2c52aSchristos b = *rB; 19746ca2c52aSchristos t = ev_multiply32_smf(a, b, &movl); 19756ca2c52aSchristos EV_SET_REG1(*rSh, *rS, t); 19766ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 19776ca2c52aSchristos 19786ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1147:EVX:e500:evmwsmfa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate 19796ca2c52aSchristos signed32 a, b; 19806ca2c52aSchristos signed64 t; 19816ca2c52aSchristos int movl; 19826ca2c52aSchristos a = *rA; 19836ca2c52aSchristos b = *rB; 19846ca2c52aSchristos t = ev_multiply32_smf(a, b, &movl); 19856ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t); 19866ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 19876ca2c52aSchristos 19886ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1113:EVX:e500:evmwsmi %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer 19896ca2c52aSchristos signed32 a, b; 19906ca2c52aSchristos signed64 t; 19916ca2c52aSchristos int movl; 19926ca2c52aSchristos a = *rA; 19936ca2c52aSchristos b = *rB; 19946ca2c52aSchristos t = (signed64)a * (signed64)b; 19956ca2c52aSchristos EV_SET_REG1(*rSh, *rS, t); 19966ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 19976ca2c52aSchristos 19986ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1145:EVX:e500:evmwsmia %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate 19996ca2c52aSchristos signed32 a, b; 20006ca2c52aSchristos signed64 t; 20016ca2c52aSchristos int movl; 20026ca2c52aSchristos a = *rA; 20036ca2c52aSchristos b = *rB; 20046ca2c52aSchristos t = (signed64)a * (signed64)b; 20056ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t); 20066ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20076ca2c52aSchristos 20086ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1112:EVX:e500:evmwumi %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer 20096ca2c52aSchristos unsigned32 a, b; 20106ca2c52aSchristos unsigned64 t; 20116ca2c52aSchristos int movl; 20126ca2c52aSchristos a = *rA; 20136ca2c52aSchristos b = *rB; 20146ca2c52aSchristos t = (signed64)a * (signed64)b; 20156ca2c52aSchristos EV_SET_REG1(*rSh, *rS, t); 20166ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20176ca2c52aSchristos 20186ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1144:EVX:e500:evmwumia %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer and Accumulate 20196ca2c52aSchristos unsigned32 a, b; 20206ca2c52aSchristos unsigned64 t; 20216ca2c52aSchristos int movl; 20226ca2c52aSchristos a = *rA; 20236ca2c52aSchristos b = *rB; 20246ca2c52aSchristos t = (signed64)a * (signed64)b; 20256ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t); 20266ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20276ca2c52aSchristos 20286ca2c52aSchristos 20296ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1363:EVX:e500:evmwssfaa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional Add and Accumulate 20306ca2c52aSchristos signed64 t1, t2; 20316ca2c52aSchristos signed32 a, b; 20326ca2c52aSchristos int movl; 20336ca2c52aSchristos a = *rA; 20346ca2c52aSchristos b = *rB; 20356ca2c52aSchristos t1 = ev_multiply32_ssf(a, b, &movl); 20366ca2c52aSchristos t2 = ACC + EV_SATURATE(movl, 0x7fffffffffffffff, t1); 20376ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20386ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, 0); 20396ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 20406ca2c52aSchristos 20416ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1371:EVX:e500:evmwsmfaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional Add and Accumulate 20426ca2c52aSchristos signed64 t1, t2; 20436ca2c52aSchristos signed32 a, b; 20446ca2c52aSchristos int movl; 20456ca2c52aSchristos a = *rA; 20466ca2c52aSchristos b = *rB; 20476ca2c52aSchristos t1 = ev_multiply32_smf(a, b, &movl); 20486ca2c52aSchristos t2 = ACC + t1; 20496ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20506ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20516ca2c52aSchristos 20526ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1369:EVX:e500:evmwsmiaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer And and Accumulate 20536ca2c52aSchristos signed64 t1, t2; 20546ca2c52aSchristos signed32 a, b; 20556ca2c52aSchristos a = *rA; 20566ca2c52aSchristos b = *rB; 20576ca2c52aSchristos t1 = (signed64)a * (signed64)b; 20586ca2c52aSchristos t2 = ACC + t1; 20596ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20606ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20616ca2c52aSchristos 20626ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1368:EVX:e500:evmwumiaa %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer Add and Accumulate 20636ca2c52aSchristos unsigned64 t1, t2; 20646ca2c52aSchristos unsigned32 a, b; 20656ca2c52aSchristos a = *rA; 20666ca2c52aSchristos b = *rB; 20676ca2c52aSchristos t1 = (unsigned64)a * (unsigned64)b; 20686ca2c52aSchristos t2 = ACC + t1; 20696ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20706ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20716ca2c52aSchristos 20726ca2c52aSchristos 20736ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1491:EVX:e500:evmwssfan %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate Negative 20746ca2c52aSchristos signed64 t1, t2; 20756ca2c52aSchristos signed32 a, b; 20766ca2c52aSchristos int movl; 20776ca2c52aSchristos a = *rA; 20786ca2c52aSchristos b = *rB; 20796ca2c52aSchristos t1 = ev_multiply32_ssf(a, b, &movl); 20806ca2c52aSchristos t2 = ACC - EV_SATURATE(movl, 0x7fffffffffffffff, t1); 20816ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20826ca2c52aSchristos EV_SET_SPEFSCR_OV(movl, 0); 20836ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 20846ca2c52aSchristos 20856ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1499:EVX:e500:evmwsmfan %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate Negative 20866ca2c52aSchristos signed64 t1, t2; 20876ca2c52aSchristos signed32 a, b; 20886ca2c52aSchristos int movl; 20896ca2c52aSchristos a = *rA; 20906ca2c52aSchristos b = *rB; 20916ca2c52aSchristos t1 = ev_multiply32_smf(a, b, &movl); 20926ca2c52aSchristos t2 = ACC - t1; 20936ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 20946ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 20956ca2c52aSchristos 20966ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1497:EVX:e500:evmwsmian %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate Negative 20976ca2c52aSchristos signed64 t1, t2; 20986ca2c52aSchristos signed32 a, b; 20996ca2c52aSchristos a = *rA; 21006ca2c52aSchristos b = *rB; 21016ca2c52aSchristos t1 = (signed64)a * (signed64)b; 21026ca2c52aSchristos t2 = ACC - t1; 21036ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 21046ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 21056ca2c52aSchristos 21066ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1496:EVX:e500:evmwumian %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer and Accumulate Negative 21076ca2c52aSchristos unsigned64 t1, t2; 21086ca2c52aSchristos unsigned32 a, b; 21096ca2c52aSchristos a = *rA; 21106ca2c52aSchristos b = *rB; 21116ca2c52aSchristos t1 = (unsigned64)a * (unsigned64)b; 21126ca2c52aSchristos t2 = ACC - t1; 21136ca2c52aSchristos EV_SET_REG1_ACC(*rSh, *rS, t2); 21146ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 21156ca2c52aSchristos 21166ca2c52aSchristos 21176ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1217:EVX:e500:evaddssiaaw %RS,%RA:Vector Add Signed Saturate Integer to Accumulator Word 21186ca2c52aSchristos signed64 t1, t2; 21196ca2c52aSchristos signed32 al, ah; 21206ca2c52aSchristos int ovl, ovh; 21216ca2c52aSchristos al = *rA; 21226ca2c52aSchristos ah = *rAh; 21236ca2c52aSchristos t1 = (signed64)EV_ACCHIGH + (signed64)ah; 21246ca2c52aSchristos t2 = (signed64)EV_ACCLOW + (signed64)al; 21256ca2c52aSchristos ovh = EV_SAT_P_S32(t1); 21266ca2c52aSchristos ovl = EV_SAT_P_S32(t2); 21276ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t1), 21286ca2c52aSchristos EV_SATURATE_ACC(ovl, t2 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t2)); 21296ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 21306ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 21316ca2c52aSchristos 21326ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1225:EVX:e500:evaddsmiaaw %RS,%RA:Vector Add Signed Modulo Integer to Accumulator Word 21336ca2c52aSchristos signed64 t1, t2; 21346ca2c52aSchristos signed32 al, ah; 21356ca2c52aSchristos al = *rA; 21366ca2c52aSchristos ah = *rAh; 21376ca2c52aSchristos t1 = (signed64)EV_ACCHIGH + (signed64)ah; 21386ca2c52aSchristos t2 = (signed64)EV_ACCLOW + (signed64)al; 21396ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 21406ca2c52aSchristos //printf("evaddsmiaaw: al %d ah %d t1 %qd t2 %qd\n", al, ah, t1, t2); 21416ca2c52aSchristos //printf("evaddsmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 21426ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 21436ca2c52aSchristos 21446ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1216:EVX:e500:evaddusiaaw %RS,%RA:Vector Add Unsigned Saturate Integer to Accumulator Word 21456ca2c52aSchristos signed64 t1, t2; 21466ca2c52aSchristos unsigned32 al, ah; 21476ca2c52aSchristos int ovl, ovh; 21486ca2c52aSchristos al = *rA; 21496ca2c52aSchristos ah = *rAh; 21506ca2c52aSchristos t1 = (signed64)EV_ACCHIGH + (signed64)ah; 21516ca2c52aSchristos t2 = (signed64)EV_ACCLOW + (signed64)al; 21526ca2c52aSchristos ovh = EV_SAT_P_U32(t1); 21536ca2c52aSchristos ovl = EV_SAT_P_U32(t2); 21546ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, t1), 21556ca2c52aSchristos EV_SATURATE(ovl, 0xffffffff, t2)); 21566ca2c52aSchristos //printf("evaddusiaaw: ovl %d ovh %d al %d ah %d t1 %qd t2 %qd\n", ovl, ovh, al, ah, t1, t2); 21576ca2c52aSchristos //printf("evaddusiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 21586ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 21596ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 21606ca2c52aSchristos 21616ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1224:EVX:e500:evaddumiaaw %RS,%RA:Vector Add Unsigned Modulo Integer to Accumulator Word 21626ca2c52aSchristos unsigned64 t1, t2; 21636ca2c52aSchristos unsigned32 al, ah; 21646ca2c52aSchristos al = *rA; 21656ca2c52aSchristos ah = *rAh; 21666ca2c52aSchristos t1 = (unsigned64)EV_ACCHIGH + (unsigned64)ah; 21676ca2c52aSchristos t2 = EV_ACCLOW + al; 21686ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 21696ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 21706ca2c52aSchristos 21716ca2c52aSchristos 21726ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1219:EVX:e500:evsubfssiaaw %RS,%RA:Vector Subtract Signed Saturate Integer to Accumulator Word 21736ca2c52aSchristos signed64 t1, t2; 21746ca2c52aSchristos signed32 al, ah; 21756ca2c52aSchristos int ovl, ovh; 21766ca2c52aSchristos al = *rA; 21776ca2c52aSchristos ah = *rAh; 21786ca2c52aSchristos t1 = (signed64)EV_ACCHIGH - (signed64)ah; 21796ca2c52aSchristos t2 = (signed64)EV_ACCLOW - (signed64)al; 21806ca2c52aSchristos ovh = EV_SAT_P_S32(t1); 21816ca2c52aSchristos ovl = EV_SAT_P_S32(t2); 21826ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1, 0x80000000, 0x7fffffff, t1), 21836ca2c52aSchristos EV_SATURATE_ACC(ovl, t2, 0x80000000, 0x7fffffff, t2)); 21846ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 21856ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 21866ca2c52aSchristos 21876ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1227:EVX:e500:evsubfsmiaaw %RS,%RA:Vector Subtract Signed Modulo Integer to Accumulator Word 21886ca2c52aSchristos signed64 t1, t2; 21896ca2c52aSchristos signed32 al, ah; 21906ca2c52aSchristos al = *rA; 21916ca2c52aSchristos ah = *rAh; 21926ca2c52aSchristos t1 = (signed64)EV_ACCHIGH - (signed64)ah; 21936ca2c52aSchristos t2 = (signed64)EV_ACCLOW - (signed64)al; 21946ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 21956ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 21966ca2c52aSchristos 21976ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1218:EVX:e500:evsubfusiaaw %RS,%RA:Vector Subtract Unsigned Saturate Integer to Accumulator Word 21986ca2c52aSchristos signed64 t1, t2; 21996ca2c52aSchristos unsigned32 al, ah; 22006ca2c52aSchristos int ovl, ovh; 22016ca2c52aSchristos 22026ca2c52aSchristos al = *rA; 22036ca2c52aSchristos ah = *rAh; 22046ca2c52aSchristos t1 = (signed64)EV_ACCHIGH - (signed64)ah; 22056ca2c52aSchristos t2 = (signed64)EV_ACCLOW - (signed64)al; 22066ca2c52aSchristos ovh = EV_SAT_P_U32(t1); 22076ca2c52aSchristos ovl = EV_SAT_P_U32(t2); 22086ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0, t1), 22096ca2c52aSchristos EV_SATURATE(ovl, 0, t2)); 22106ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 22116ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 22126ca2c52aSchristos 22136ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1226:EVX:e500:evsubfumiaaw %RS,%RA:Vector Subtract Unsigned Modulo Integer to Accumulator Word 22146ca2c52aSchristos unsigned64 t1, t2; 22156ca2c52aSchristos unsigned32 al, ah; 22166ca2c52aSchristos al = *rA; 22176ca2c52aSchristos ah = *rAh; 22186ca2c52aSchristos t1 = (unsigned64)EV_ACCHIGH - (unsigned64)ah; 22196ca2c52aSchristos t2 = (unsigned64)EV_ACCLOW - (unsigned64)al; 22206ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 22216ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 22226ca2c52aSchristos 22236ca2c52aSchristos 22246ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.1220:EVX:e500:evmra %RS,%RA:Initialize Accumulator 22256ca2c52aSchristos EV_SET_REG2_ACC(*rSh, *rS, *rAh, *rA); 22266ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 22276ca2c52aSchristos 22286ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1222:EVX:e500:evdivws %RS,%RA,%RB:Vector Divide Word Signed 22296ca2c52aSchristos signed32 dividendh, dividendl, divisorh, divisorl; 22306ca2c52aSchristos signed32 w1, w2; 22316ca2c52aSchristos int ovh, ovl; 22326ca2c52aSchristos dividendh = *rAh; 22336ca2c52aSchristos dividendl = *rA; 22346ca2c52aSchristos divisorh = *rBh; 22356ca2c52aSchristos divisorl = *rB; 22366ca2c52aSchristos if (dividendh < 0 && divisorh == 0) { 22376ca2c52aSchristos w1 = 0x80000000; 22386ca2c52aSchristos ovh = 1; 22396ca2c52aSchristos } else if (dividendh > 0 && divisorh == 0) { 22406ca2c52aSchristos w1 = 0x7fffffff; 22416ca2c52aSchristos ovh = 1; 22426ca2c52aSchristos } else if (dividendh == 0x80000000 && divisorh == -1) { 22436ca2c52aSchristos w1 = 0x7fffffff; 22446ca2c52aSchristos ovh = 1; 22456ca2c52aSchristos } else { 22466ca2c52aSchristos w1 = dividendh / divisorh; 22476ca2c52aSchristos ovh = 0; 22486ca2c52aSchristos } 22496ca2c52aSchristos if (dividendl < 0 && divisorl == 0) { 22506ca2c52aSchristos w2 = 0x80000000; 22516ca2c52aSchristos ovl = 1; 22526ca2c52aSchristos } else if (dividendl > 0 && divisorl == 0) { 22536ca2c52aSchristos w2 = 0x7fffffff; 22546ca2c52aSchristos ovl = 1; 22556ca2c52aSchristos } else if (dividendl == 0x80000000 && divisorl == -1) { 22566ca2c52aSchristos w2 = 0x7fffffff; 22576ca2c52aSchristos ovl = 1; 22586ca2c52aSchristos } else { 22596ca2c52aSchristos w2 = dividendl / divisorl; 22606ca2c52aSchristos ovl = 0; 22616ca2c52aSchristos } 22626ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 22636ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 22646ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 22656ca2c52aSchristos 22666ca2c52aSchristos 22676ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.1223:EVX:e500:evdivwu %RS,%RA,%RB:Vector Divide Word Unsigned 22686ca2c52aSchristos unsigned32 dividendh, dividendl, divisorh, divisorl; 22696ca2c52aSchristos unsigned32 w1, w2; 22706ca2c52aSchristos int ovh, ovl; 22716ca2c52aSchristos dividendh = *rAh; 22726ca2c52aSchristos dividendl = *rA; 22736ca2c52aSchristos divisorh = *rBh; 22746ca2c52aSchristos divisorl = *rB; 22756ca2c52aSchristos if (divisorh == 0) { 22766ca2c52aSchristos w1 = 0xffffffff; 22776ca2c52aSchristos ovh = 1; 22786ca2c52aSchristos } else { 22796ca2c52aSchristos w1 = dividendh / divisorh; 22806ca2c52aSchristos ovh = 0; 22816ca2c52aSchristos } 22826ca2c52aSchristos if (divisorl == 0) { 22836ca2c52aSchristos w2 = 0xffffffff; 22846ca2c52aSchristos ovl = 1; 22856ca2c52aSchristos } else { 22866ca2c52aSchristos w2 = dividendl / divisorl; 22876ca2c52aSchristos ovl = 0; 22886ca2c52aSchristos } 22896ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 22906ca2c52aSchristos EV_SET_SPEFSCR_OV(ovl, ovh); 22916ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 22926ca2c52aSchristos 22936ca2c52aSchristos 22946ca2c52aSchristos# 22956ca2c52aSchristos# A.2.9 Floating Point SPE Instructions 22966ca2c52aSchristos# 22976ca2c52aSchristos 22986ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.644:EVX:e500:evfsabs %RS,%RA:Vector Floating-Point Absolute Value 22996ca2c52aSchristos unsigned32 w1, w2; 23006ca2c52aSchristos w1 = *rAh & 0x7fffffff; 23016ca2c52aSchristos w2 = *rA & 0x7fffffff; 23026ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23036ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 23046ca2c52aSchristos 23056ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.645:EVX:e500:evfsnabs %RS,%RA:Vector Floating-Point Negative Absolute Value 23066ca2c52aSchristos unsigned32 w1, w2; 23076ca2c52aSchristos w1 = *rAh | 0x80000000; 23086ca2c52aSchristos w2 = *rA | 0x80000000; 23096ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23106ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 23116ca2c52aSchristos 23126ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.646:EVX:e500:evfsneg %RS,%RA:Vector Floating-Point Negate 23136ca2c52aSchristos unsigned32 w1, w2; 23146ca2c52aSchristos w1 = *rAh; 23156ca2c52aSchristos w2 = *rA; 23166ca2c52aSchristos w1 = (w1 & 0x7fffffff) | ((~w1) & 0x80000000); 23176ca2c52aSchristos w2 = (w2 & 0x7fffffff) | ((~w2) & 0x80000000); 23186ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23196ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 23206ca2c52aSchristos 23216ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.640:EVX:e500:evfsadd %RS,%RA,%RB:Vector Floating-Point Add 23226ca2c52aSchristos unsigned32 w1, w2; 23236ca2c52aSchristos w1 = ev_fs_add (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 23246ca2c52aSchristos w2 = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 23256ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23266ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 23276ca2c52aSchristos 23286ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.641:EVX:e500:evfssub %RS,%RA,%RB:Vector Floating-Point Subtract 23296ca2c52aSchristos unsigned32 w1, w2; 23306ca2c52aSchristos w1 = ev_fs_sub (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 23316ca2c52aSchristos w2 = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 23326ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23336ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 23346ca2c52aSchristos 23356ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.648:EVX:e500:evfsmul %RS,%RA,%RB:Vector Floating-Point Multiply 23366ca2c52aSchristos unsigned32 w1, w2; 23376ca2c52aSchristos w1 = ev_fs_mul (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 23386ca2c52aSchristos w2 = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 23396ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23406ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 23416ca2c52aSchristos 23426ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.649:EVX:e500:evfsdiv %RS,%RA,%RB:Vector Floating-Point Divide 23436ca2c52aSchristos signed32 w1, w2; 23446ca2c52aSchristos w1 = ev_fs_div (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fdbzh, spefscr_fgh, spefscr_fxh, processor); 23456ca2c52aSchristos w2 = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); 23466ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 23476ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 23486ca2c52aSchristos 23496ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.652:EVX:e500:evfscmpgt %BF,%RA,%RB:Vector Floating-Point Compare Greater Than 23506ca2c52aSchristos sim_fpu al, ah, bl, bh; 23516ca2c52aSchristos int w, ch, cl; 23526ca2c52aSchristos sim_fpu_32to (&al, *rA); 23536ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 23546ca2c52aSchristos sim_fpu_32to (&bl, *rB); 23556ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 23566ca2c52aSchristos if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 23576ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 23586ca2c52aSchristos if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 23596ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finvh); 23606ca2c52aSchristos if (sim_fpu_is_gt(&ah, &bh)) 23616ca2c52aSchristos ch = 1; 23626ca2c52aSchristos else 23636ca2c52aSchristos ch = 0; 23646ca2c52aSchristos if (sim_fpu_is_gt(&al, &bl)) 23656ca2c52aSchristos cl = 1; 23666ca2c52aSchristos else 23676ca2c52aSchristos cl = 0; 23686ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 23696ca2c52aSchristos CR_SET(BF, w); 23706ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 23716ca2c52aSchristos 23726ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.653:EVX:e500:evfscmplt %BF,%RA,%RB:Vector Floating-Point Compare Less Than 23736ca2c52aSchristos sim_fpu al, ah, bl, bh; 23746ca2c52aSchristos int w, ch, cl; 23756ca2c52aSchristos sim_fpu_32to (&al, *rA); 23766ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 23776ca2c52aSchristos sim_fpu_32to (&bl, *rB); 23786ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 23796ca2c52aSchristos if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 23806ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 23816ca2c52aSchristos if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 23826ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finvh); 23836ca2c52aSchristos if (sim_fpu_is_lt(&ah, &bh)) 23846ca2c52aSchristos ch = 1; 23856ca2c52aSchristos else 23866ca2c52aSchristos ch = 0; 23876ca2c52aSchristos if (sim_fpu_is_lt(&al, &bl)) 23886ca2c52aSchristos cl = 1; 23896ca2c52aSchristos else 23906ca2c52aSchristos cl = 0; 23916ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 23926ca2c52aSchristos CR_SET(BF, w); 23936ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 23946ca2c52aSchristos 23956ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.654:EVX:e500:evfscmpeq %BF,%RA,%RB:Vector Floating-Point Compare Equal 23966ca2c52aSchristos sim_fpu al, ah, bl, bh; 23976ca2c52aSchristos int w, ch, cl; 23986ca2c52aSchristos sim_fpu_32to (&al, *rA); 23996ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 24006ca2c52aSchristos sim_fpu_32to (&bl, *rB); 24016ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 24026ca2c52aSchristos if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 24036ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 24046ca2c52aSchristos if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 24056ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finvh); 24066ca2c52aSchristos if (sim_fpu_is_eq(&ah, &bh)) 24076ca2c52aSchristos ch = 1; 24086ca2c52aSchristos else 24096ca2c52aSchristos ch = 0; 24106ca2c52aSchristos if (sim_fpu_is_eq(&al, &bl)) 24116ca2c52aSchristos cl = 1; 24126ca2c52aSchristos else 24136ca2c52aSchristos cl = 0; 24146ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 24156ca2c52aSchristos CR_SET(BF, w); 24166ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 24176ca2c52aSchristos 24186ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.668:EVX:e500:evfststgt %BF,%RA,%RB:Vector Floating-Point Test Greater Than 24196ca2c52aSchristos sim_fpu al, ah, bl, bh; 24206ca2c52aSchristos int w, ch, cl; 24216ca2c52aSchristos sim_fpu_32to (&al, *rA); 24226ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 24236ca2c52aSchristos sim_fpu_32to (&bl, *rB); 24246ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 24256ca2c52aSchristos if (sim_fpu_is_gt(&ah, &bh)) 24266ca2c52aSchristos ch = 1; 24276ca2c52aSchristos else 24286ca2c52aSchristos ch = 0; 24296ca2c52aSchristos if (sim_fpu_is_gt(&al, &bl)) 24306ca2c52aSchristos cl = 1; 24316ca2c52aSchristos else 24326ca2c52aSchristos cl = 0; 24336ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 24346ca2c52aSchristos CR_SET(BF, w); 24356ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 24366ca2c52aSchristos 24376ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.669:EVX:e500:evfststlt %BF,%RA,%RB:Vector Floating-Point Test Less Than 24386ca2c52aSchristos sim_fpu al, ah, bl, bh; 24396ca2c52aSchristos int w, ch, cl; 24406ca2c52aSchristos sim_fpu_32to (&al, *rA); 24416ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 24426ca2c52aSchristos sim_fpu_32to (&bl, *rB); 24436ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 24446ca2c52aSchristos if (sim_fpu_is_lt(&ah, &bh)) 24456ca2c52aSchristos ch = 1; 24466ca2c52aSchristos else 24476ca2c52aSchristos ch = 0; 24486ca2c52aSchristos if (sim_fpu_is_lt(&al, &bl)) 24496ca2c52aSchristos cl = 1; 24506ca2c52aSchristos else 24516ca2c52aSchristos cl = 0; 24526ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 24536ca2c52aSchristos CR_SET(BF, w); 24546ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 24556ca2c52aSchristos 24566ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.670:EVX:e500:evfststeq %BF,%RA,%RB:Vector Floating-Point Test Equal 24576ca2c52aSchristos sim_fpu al, ah, bl, bh; 24586ca2c52aSchristos int w, ch, cl; 24596ca2c52aSchristos sim_fpu_32to (&al, *rA); 24606ca2c52aSchristos sim_fpu_32to (&ah, *rAh); 24616ca2c52aSchristos sim_fpu_32to (&bl, *rB); 24626ca2c52aSchristos sim_fpu_32to (&bh, *rBh); 24636ca2c52aSchristos if (sim_fpu_is_eq(&ah, &bh)) 24646ca2c52aSchristos ch = 1; 24656ca2c52aSchristos else 24666ca2c52aSchristos ch = 0; 24676ca2c52aSchristos if (sim_fpu_is_eq(&al, &bl)) 24686ca2c52aSchristos cl = 1; 24696ca2c52aSchristos else 24706ca2c52aSchristos cl = 0; 24716ca2c52aSchristos w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 24726ca2c52aSchristos CR_SET(BF, w); 24736ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 24746ca2c52aSchristos 24756ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.656:EVX:e500:evfscfui %RS,%RB:Vector Convert Floating-Point from Unsigned Integer 24766ca2c52aSchristos unsigned32 f, w1, w2; 24776ca2c52aSchristos sim_fpu b; 24786ca2c52aSchristos 24796ca2c52aSchristos sim_fpu_u32to (&b, *rBh, sim_fpu_round_default); 24806ca2c52aSchristos sim_fpu_to32 (&w1, &b); 24816ca2c52aSchristos sim_fpu_u32to (&b, *rB, sim_fpu_round_default); 24826ca2c52aSchristos sim_fpu_to32 (&w2, &b); 24836ca2c52aSchristos 24846ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 24856ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 24866ca2c52aSchristos 24876ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.664:EVX:e500:evfsctuiz %RS,%RB:Vector Convert Floating-Point to Unsigned Integer with Round toward Zero 24886ca2c52aSchristos unsigned32 w1, w2; 24896ca2c52aSchristos sim_fpu b; 24906ca2c52aSchristos 24916ca2c52aSchristos sim_fpu_32to (&b, *rBh); 24926ca2c52aSchristos sim_fpu_to32u (&w1, &b, sim_fpu_round_zero); 24936ca2c52aSchristos sim_fpu_32to (&b, *rB); 24946ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); 24956ca2c52aSchristos 24966ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 24976ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 24986ca2c52aSchristos 24996ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.657:EVX:e500:evfscfsi %RS,%RB:Vector Convert Floating-Point from Signed Integer 25006ca2c52aSchristos signed32 w1, w2; 25016ca2c52aSchristos sim_fpu b, x, y; 25026ca2c52aSchristos 25036ca2c52aSchristos sim_fpu_i32to (&b, *rBh, sim_fpu_round_default); 25046ca2c52aSchristos sim_fpu_to32 (&w1, &b); 25056ca2c52aSchristos sim_fpu_i32to (&b, *rB, sim_fpu_round_default); 25066ca2c52aSchristos sim_fpu_to32 (&w2, &b); 25076ca2c52aSchristos 25086ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25096ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25106ca2c52aSchristos 25116ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.658:EVX:e500:evfscfuf %RS,%RB:Vector Convert Floating-Point from Unsigned Fraction 25126ca2c52aSchristos unsigned32 w1, w2, bh, bl; 25136ca2c52aSchristos sim_fpu b, x, y; 25146ca2c52aSchristos bh = *rBh; 25156ca2c52aSchristos if (bh == 0xffffffff) 25166ca2c52aSchristos sim_fpu_to32 (&w1, &sim_fpu_one); 25176ca2c52aSchristos else { 25186ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 25196ca2c52aSchristos sim_fpu_u32to (&y, bh, sim_fpu_round_default); 25206ca2c52aSchristos sim_fpu_div (&b, &y, &x); 25216ca2c52aSchristos sim_fpu_to32 (&w1, &b); 25226ca2c52aSchristos } 25236ca2c52aSchristos bl = *rB; 25246ca2c52aSchristos if (bl == 0xffffffff) 25256ca2c52aSchristos sim_fpu_to32 (&w2, &sim_fpu_one); 25266ca2c52aSchristos else { 25276ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 25286ca2c52aSchristos sim_fpu_u32to (&y, bl, sim_fpu_round_default); 25296ca2c52aSchristos sim_fpu_div (&b, &y, &x); 25306ca2c52aSchristos sim_fpu_to32 (&w2, &b); 25316ca2c52aSchristos } 25326ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25336ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25346ca2c52aSchristos 25356ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.659:EVX:e500:evfscfsf %RS,%RB:Vector Convert Floating-Point from Signed Fraction 25366ca2c52aSchristos unsigned32 w1, w2; 25376ca2c52aSchristos sim_fpu b, x, y; 25386ca2c52aSchristos 25396ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 25406ca2c52aSchristos sim_fpu_i32to (&y, *rBh, sim_fpu_round_default); 25416ca2c52aSchristos sim_fpu_div (&b, &y, &x); 25426ca2c52aSchristos sim_fpu_to32 (&w1, &b); 25436ca2c52aSchristos 25446ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 25456ca2c52aSchristos sim_fpu_i32to (&y, *rB, sim_fpu_round_default); 25466ca2c52aSchristos sim_fpu_div (&b, &y, &x); 25476ca2c52aSchristos sim_fpu_to32 (&w2, &b); 25486ca2c52aSchristos 25496ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25506ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25516ca2c52aSchristos 25526ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.660:EVX:e500:evfsctui %RS,%RB:Vector Convert Floating-Point to Unsigned Integer 25536ca2c52aSchristos unsigned32 w1, w2; 25546ca2c52aSchristos sim_fpu b; 25556ca2c52aSchristos 25566ca2c52aSchristos sim_fpu_32to (&b, *rBh); 25576ca2c52aSchristos sim_fpu_to32u (&w1, &b, sim_fpu_round_default); 25586ca2c52aSchristos sim_fpu_32to (&b, *rB); 25596ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 25606ca2c52aSchristos 25616ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25626ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25636ca2c52aSchristos 25646ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.661:EVX:e500:evfsctsi %RS,%RB:Vector Convert Floating-Point to Signed Integer 25656ca2c52aSchristos signed32 w1, w2; 25666ca2c52aSchristos sim_fpu b; 25676ca2c52aSchristos 25686ca2c52aSchristos sim_fpu_32to (&b, *rBh); 25696ca2c52aSchristos sim_fpu_to32i (&w1, &b, sim_fpu_round_default); 25706ca2c52aSchristos sim_fpu_32to (&b, *rB); 25716ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 25726ca2c52aSchristos 25736ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25746ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25756ca2c52aSchristos 25766ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.666:EVX:e500:evfsctsiz %RS,%RB:Vector Convert Floating-Point to Signed Integer with Round toward Zero 25776ca2c52aSchristos signed32 w1, w2; 25786ca2c52aSchristos sim_fpu b; 25796ca2c52aSchristos 25806ca2c52aSchristos sim_fpu_32to (&b, *rBh); 25816ca2c52aSchristos sim_fpu_to32i (&w1, &b, sim_fpu_round_zero); 25826ca2c52aSchristos sim_fpu_32to (&b, *rB); 25836ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); 25846ca2c52aSchristos 25856ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 25866ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 25876ca2c52aSchristos 25886ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.662:EVX:e500:evfsctuf %RS,%RB:Vector Convert Floating-Point to Unsigned Fraction 25896ca2c52aSchristos unsigned32 w1, w2; 25906ca2c52aSchristos sim_fpu b, x, y; 25916ca2c52aSchristos 25926ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 25936ca2c52aSchristos sim_fpu_32to (&y, *rBh); 25946ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 25956ca2c52aSchristos sim_fpu_to32u (&w1, &b, sim_fpu_round_default); 25966ca2c52aSchristos 25976ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 25986ca2c52aSchristos sim_fpu_32to (&y, *rB); 25996ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 26006ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 26016ca2c52aSchristos 26026ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 26036ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 26046ca2c52aSchristos 26056ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.663:EVX:e500:evfsctsf %RS,%RB:Vector Convert Floating-Point to Signed Fraction 26066ca2c52aSchristos signed32 w1, w2; 26076ca2c52aSchristos sim_fpu b, x, y; 26086ca2c52aSchristos 26096ca2c52aSchristos sim_fpu_32to (&y, *rBh); 26106ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 26116ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 26126ca2c52aSchristos sim_fpu_to32i (&w1, &b, sim_fpu_round_near); 26136ca2c52aSchristos 26146ca2c52aSchristos sim_fpu_32to (&y, *rB); 26156ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 26166ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 26176ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_near); 26186ca2c52aSchristos 26196ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 26206ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 26216ca2c52aSchristos 26226ca2c52aSchristos 26236ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.708:EVX:e500:efsabs %RS,%RA:Floating-Point Absolute Value 26246ca2c52aSchristos unsigned32 w1, w2; 26256ca2c52aSchristos w1 = *rSh; 26266ca2c52aSchristos w2 = *rA & 0x7fffffff; 26276ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 26286ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 26296ca2c52aSchristos 26306ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.709:EVX:e500:efsnabs %RS,%RA:Floating-Point Negative Absolute Value 26316ca2c52aSchristos unsigned32 w1, w2; 26326ca2c52aSchristos w1 = *rSh; 26336ca2c52aSchristos w2 = *rA | 0x80000000; 26346ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 26356ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 26366ca2c52aSchristos 26376ca2c52aSchristos0.4,6.RS,11.RA,16.0,21.710:EVX:e500:efsneg %RS,%RA:Floating-Point Negate 26386ca2c52aSchristos unsigned32 w1, w2; 26396ca2c52aSchristos w1 = *rSh; 26406ca2c52aSchristos w2 = (*rA & 0x7fffffff) | ((~*rA) & 0x80000000); 26416ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 26426ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 26436ca2c52aSchristos 26446ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.704:EVX:e500:efsadd %RS,%RA,%RB:Floating-Point Add 26456ca2c52aSchristos unsigned32 w; 26466ca2c52aSchristos w = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 26476ca2c52aSchristos EV_SET_REG(*rS, w); 26486ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 26496ca2c52aSchristos 26506ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.705:EVX:e500:efssub %RS,%RA,%RB:Floating-Point Subtract 26516ca2c52aSchristos unsigned32 w; 26526ca2c52aSchristos w = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 26536ca2c52aSchristos EV_SET_REG(*rS, w); 26546ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 26556ca2c52aSchristos 26566ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.712:EVX:e500:efsmul %RS,%RA,%RB:Floating-Point Multiply 26576ca2c52aSchristos unsigned32 w; 26586ca2c52aSchristos w = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 26596ca2c52aSchristos EV_SET_REG(*rS, w); 26606ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 26616ca2c52aSchristos 26626ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.713:EVX:e500:efsdiv %RS,%RA,%RB:Floating-Point Divide 26636ca2c52aSchristos unsigned32 w; 26646ca2c52aSchristos w = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); 26656ca2c52aSchristos EV_SET_REG(*rS, w); 26666ca2c52aSchristos PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 26676ca2c52aSchristos 26686ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.716:EVX:e500:efscmpgt %BF,%RA,%RB:Floating-Point Compare Greater Than 26696ca2c52aSchristos sim_fpu a, b; 26706ca2c52aSchristos int w, cl; 26716ca2c52aSchristos sim_fpu_32to (&a, *rA); 26726ca2c52aSchristos sim_fpu_32to (&b, *rB); 26736ca2c52aSchristos if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 26746ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 26756ca2c52aSchristos if (sim_fpu_is_gt(&a, &b)) 26766ca2c52aSchristos cl = 1; 26776ca2c52aSchristos else 26786ca2c52aSchristos cl = 0; 26796ca2c52aSchristos w = cl << 2 | cl << 1; 26806ca2c52aSchristos CR_SET(BF, w); 26816ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 26826ca2c52aSchristos 26836ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.717:EVX:e500:efscmplt %BF,%RA,%RB:Floating-Point Compare Less Than 26846ca2c52aSchristos sim_fpu al, bl; 26856ca2c52aSchristos int w, cl; 26866ca2c52aSchristos sim_fpu_32to (&al, *rA); 26876ca2c52aSchristos sim_fpu_32to (&bl, *rB); 26886ca2c52aSchristos if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 26896ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 26906ca2c52aSchristos if (sim_fpu_is_lt(&al, &bl)) 26916ca2c52aSchristos cl = 1; 26926ca2c52aSchristos else 26936ca2c52aSchristos cl = 0; 26946ca2c52aSchristos w = cl << 2 | cl << 1; 26956ca2c52aSchristos CR_SET(BF, w); 26966ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 26976ca2c52aSchristos 26986ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.718:EVX:e500:efscmpeq %BF,%RA,%RB:Floating-Point Compare Equal 26996ca2c52aSchristos sim_fpu al, bl; 27006ca2c52aSchristos int w, cl; 27016ca2c52aSchristos sim_fpu_32to (&al, *rA); 27026ca2c52aSchristos sim_fpu_32to (&bl, *rB); 27036ca2c52aSchristos if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 27046ca2c52aSchristos EV_SET_SPEFSCR_BITS(spefscr_finv); 27056ca2c52aSchristos if (sim_fpu_is_eq(&al, &bl)) 27066ca2c52aSchristos cl = 1; 27076ca2c52aSchristos else 27086ca2c52aSchristos cl = 0; 27096ca2c52aSchristos w = cl << 2 | cl << 1; 27106ca2c52aSchristos CR_SET(BF, w); 27116ca2c52aSchristos PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 27126ca2c52aSchristos 27136ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.732:EVX:e500:efststgt %BF,%RA,%RB:Floating-Point Test Greater Than 27146ca2c52aSchristos sim_fpu al, bl; 27156ca2c52aSchristos int w, cl; 27166ca2c52aSchristos sim_fpu_32to (&al, *rA); 27176ca2c52aSchristos sim_fpu_32to (&bl, *rB); 27186ca2c52aSchristos if (sim_fpu_is_gt(&al, &bl)) 27196ca2c52aSchristos cl = 1; 27206ca2c52aSchristos else 27216ca2c52aSchristos cl = 0; 27226ca2c52aSchristos w = cl << 2 | cl << 1; 27236ca2c52aSchristos CR_SET(BF, w); 27246ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 27256ca2c52aSchristos 27266ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.733:EVX:e500:efststlt %BF,%RA,%RB:Floating-Point Test Less Than 27276ca2c52aSchristos sim_fpu al, bl; 27286ca2c52aSchristos int w, cl; 27296ca2c52aSchristos sim_fpu_32to (&al, *rA); 27306ca2c52aSchristos sim_fpu_32to (&bl, *rB); 27316ca2c52aSchristos if (sim_fpu_is_lt(&al, &bl)) 27326ca2c52aSchristos cl = 1; 27336ca2c52aSchristos else 27346ca2c52aSchristos cl = 0; 27356ca2c52aSchristos w = cl << 2 | cl << 1; 27366ca2c52aSchristos CR_SET(BF, w); 27376ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 27386ca2c52aSchristos 27396ca2c52aSchristos0.4,6.BF,9./,11.RA,16.RB,21.734:EVX:e500:efststeq %BF,%RA,%RB:Floating-Point Test Equal 27406ca2c52aSchristos sim_fpu al, bl; 27416ca2c52aSchristos int w, cl; 27426ca2c52aSchristos sim_fpu_32to (&al, *rA); 27436ca2c52aSchristos sim_fpu_32to (&bl, *rB); 27446ca2c52aSchristos if (sim_fpu_is_eq(&al, &bl)) 27456ca2c52aSchristos cl = 1; 27466ca2c52aSchristos else 27476ca2c52aSchristos cl = 0; 27486ca2c52aSchristos w = cl << 2 | cl << 1; 27496ca2c52aSchristos CR_SET(BF, w); 27506ca2c52aSchristos PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 27516ca2c52aSchristos 27526ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.721:EVX:e500:efscfsi %RS,%RB:Convert Floating-Point from Signed Integer 27536ca2c52aSchristos signed32 f, w1, w2; 27546ca2c52aSchristos sim_fpu b; 27556ca2c52aSchristos w1 = *rSh; 27566ca2c52aSchristos sim_fpu_i32to (&b, *rB, sim_fpu_round_default); 27576ca2c52aSchristos sim_fpu_to32 (&w2, &b); 27586ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 27596ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 27606ca2c52aSchristos 27616ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.720:EVX:e500:efscfui %RS,%RB:Convert Floating-Point from Unsigned Integer 27626ca2c52aSchristos unsigned32 w1, w2; 27636ca2c52aSchristos sim_fpu b; 27646ca2c52aSchristos w1 = *rSh; 27656ca2c52aSchristos sim_fpu_u32to (&b, *rB, sim_fpu_round_default); 27666ca2c52aSchristos sim_fpu_to32 (&w2, &b); 27676ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 27686ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 27696ca2c52aSchristos 27706ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.723:EVX:e500:efscfsf %RS,%RB:Convert Floating-Point from Signed Fraction 27716ca2c52aSchristos unsigned32 w1, w2; 27726ca2c52aSchristos sim_fpu b, x, y; 27736ca2c52aSchristos w1 = *rSh; 27746ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 27756ca2c52aSchristos sim_fpu_i32to (&y, *rB, sim_fpu_round_default); 27766ca2c52aSchristos sim_fpu_div (&b, &y, &x); 27776ca2c52aSchristos sim_fpu_to32 (&w2, &b); 27786ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 27796ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 27806ca2c52aSchristos 27816ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.722:EVX:e500:efscfuf %RS,%RB:Convert Floating-Point from Unsigned Fraction 27826ca2c52aSchristos unsigned32 w1, w2, bl; 27836ca2c52aSchristos sim_fpu b, x, y; 27846ca2c52aSchristos w1 = *rSh; 27856ca2c52aSchristos bl = *rB; 27866ca2c52aSchristos if (bl == 0xffffffff) 27876ca2c52aSchristos sim_fpu_to32 (&w2, &sim_fpu_one); 27886ca2c52aSchristos else { 27896ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 27906ca2c52aSchristos sim_fpu_u32to (&y, bl, sim_fpu_round_default); 27916ca2c52aSchristos sim_fpu_div (&b, &y, &x); 27926ca2c52aSchristos sim_fpu_to32 (&w2, &b); 27936ca2c52aSchristos } 27946ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 27956ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 27966ca2c52aSchristos 27976ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.725:EVX:e500:efsctsi %RS,%RB:Convert Floating-Point to Signed Integer 27986ca2c52aSchristos signed64 temp; 27996ca2c52aSchristos signed32 w1, w2; 28006ca2c52aSchristos sim_fpu b; 28016ca2c52aSchristos w1 = *rSh; 28026ca2c52aSchristos sim_fpu_32to (&b, *rB); 28036ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 28046ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28056ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28066ca2c52aSchristos 28076ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.730:EVX:e500:efsctsiz %RS,%RB:Convert Floating-Point to Signed Integer with Round toward Zero 28086ca2c52aSchristos signed64 temp; 28096ca2c52aSchristos signed32 w1, w2; 28106ca2c52aSchristos sim_fpu b; 28116ca2c52aSchristos w1 = *rSh; 28126ca2c52aSchristos sim_fpu_32to (&b, *rB); 28136ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); 28146ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28156ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28166ca2c52aSchristos 28176ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.724:EVX:e500:efsctui %RS,%RB:Convert Floating-Point to Unsigned Integer 28186ca2c52aSchristos unsigned64 temp; 28196ca2c52aSchristos signed32 w1, w2; 28206ca2c52aSchristos sim_fpu b; 28216ca2c52aSchristos w1 = *rSh; 28226ca2c52aSchristos sim_fpu_32to (&b, *rB); 28236ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 28246ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28256ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28266ca2c52aSchristos 28276ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.728:EVX:e500:efsctuiz %RS,%RB:Convert Floating-Point to Unsigned Integer with Round toward Zero 28286ca2c52aSchristos unsigned64 temp; 28296ca2c52aSchristos signed32 w1, w2; 28306ca2c52aSchristos sim_fpu b; 28316ca2c52aSchristos w1 = *rSh; 28326ca2c52aSchristos sim_fpu_32to (&b, *rB); 28336ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); 28346ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28356ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28366ca2c52aSchristos 28376ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.727:EVX:e500:efsctsf %RS,%RB:Convert Floating-Point to Signed Fraction 28386ca2c52aSchristos unsigned32 w1, w2; 28396ca2c52aSchristos sim_fpu b, x, y; 28406ca2c52aSchristos w1 = *rSh; 28416ca2c52aSchristos sim_fpu_32to (&y, *rB); 28426ca2c52aSchristos sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 28436ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 28446ca2c52aSchristos sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 28456ca2c52aSchristos sim_fpu_to32 (&w2, &b); 28466ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28476ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28486ca2c52aSchristos 28496ca2c52aSchristos0.4,6.RS,11.0,16.RB,21.726:EVX:e500:efsctuf %RS,%RB:Convert Floating-Point to Unsigned Fraction 28506ca2c52aSchristos unsigned32 w1, w2; 28516ca2c52aSchristos sim_fpu b, x, y; 28526ca2c52aSchristos w1 = *rSh; 28536ca2c52aSchristos sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 28546ca2c52aSchristos sim_fpu_32to (&y, *rB); 28556ca2c52aSchristos sim_fpu_mul (&b, &y, &x); 28566ca2c52aSchristos sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 28576ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28586ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 28596ca2c52aSchristos 28606ca2c52aSchristos 28616ca2c52aSchristos# 28626ca2c52aSchristos# A.2.10 Vector Load/Store Instructions 28636ca2c52aSchristos# 28646ca2c52aSchristos 28656ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.769:EVX:e500:evldd %RS,%RA,%UIMM:Vector Load Double Word into Double Word 28666ca2c52aSchristos unsigned64 m; 28676ca2c52aSchristos unsigned_word b; 28686ca2c52aSchristos unsigned_word EA; 28696ca2c52aSchristos if (RA_is_0) b = 0; 28706ca2c52aSchristos else b = *rA; 28716ca2c52aSchristos EA = b + (UIMM << 3); 28726ca2c52aSchristos m = MEM(unsigned, EA, 8); 28736ca2c52aSchristos EV_SET_REG1(*rSh, *rS, m); 28746ca2c52aSchristos //printf("evldd(%d<-%d + %u): m %08x.%08x, *rSh %x *rS %x\n", RS, RA, UIMM, (int)(m >> 32), (int)m, *rSh, *rS); 28756ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 28766ca2c52aSchristos 28776ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.768:EVX:e500:evlddx %RS,%RA,%RB:Vector Load Double Word into Double Word Indexed 28786ca2c52aSchristos unsigned64 m; 28796ca2c52aSchristos unsigned_word b; 28806ca2c52aSchristos unsigned_word EA; 28816ca2c52aSchristos if (RA_is_0) b = 0; 28826ca2c52aSchristos else b = *rA; 28836ca2c52aSchristos EA = b + *rB; 28846ca2c52aSchristos m = MEM(unsigned, EA, 8); 28856ca2c52aSchristos EV_SET_REG1(*rSh, *rS, m); 28866ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 28876ca2c52aSchristos 28886ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.771:EVX:e500:evldw %RS,%RA,%UIMM:Vector Load Double into Two Words 28896ca2c52aSchristos unsigned_word b; 28906ca2c52aSchristos unsigned_word EA; 28916ca2c52aSchristos unsigned32 w1, w2; 28926ca2c52aSchristos if (RA_is_0) b = 0; 28936ca2c52aSchristos else b = *rA; 28946ca2c52aSchristos EA = b + (UIMM << 3); 28956ca2c52aSchristos w1 = MEM(unsigned, EA, 4); 28966ca2c52aSchristos w2 = MEM(unsigned, EA + 4, 4); 28976ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 28986ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 28996ca2c52aSchristos 29006ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.770:EVX:e500:evldwx %RS,%RA,%RB:Vector Load Double into Two Words Indexed 29016ca2c52aSchristos unsigned_word b; 29026ca2c52aSchristos unsigned_word EA; 29036ca2c52aSchristos unsigned32 w1, w2; 29046ca2c52aSchristos if (RA_is_0) b = 0; 29056ca2c52aSchristos else b = *rA; 29066ca2c52aSchristos EA = b + *rB; 29076ca2c52aSchristos w1 = MEM(unsigned, EA, 4); 29086ca2c52aSchristos w2 = MEM(unsigned, EA + 4, 4); 29096ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w2); 29106ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 29116ca2c52aSchristos 29126ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.773:EVX:e500:evldh %RS,%RA,%UIMM:Vector Load Double into 4 Half Words 29136ca2c52aSchristos unsigned_word b; 29146ca2c52aSchristos unsigned_word EA; 29156ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29166ca2c52aSchristos if (RA_is_0) b = 0; 29176ca2c52aSchristos else b = *rA; 29186ca2c52aSchristos EA = b + (UIMM << 3); 29196ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 29206ca2c52aSchristos h2 = MEM(unsigned, EA + 2, 2); 29216ca2c52aSchristos h3 = MEM(unsigned, EA + 4, 2); 29226ca2c52aSchristos h4 = MEM(unsigned, EA + 6, 2); 29236ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29246ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 29256ca2c52aSchristos 29266ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.772:EVX:e500:evldhx %RS,%RA,%RB:Vector Load Double into 4 Half Words Indexed 29276ca2c52aSchristos unsigned_word b; 29286ca2c52aSchristos unsigned_word EA; 29296ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29306ca2c52aSchristos if (RA_is_0) b = 0; 29316ca2c52aSchristos else b = *rA; 29326ca2c52aSchristos EA = b + *rB; 29336ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 29346ca2c52aSchristos h2 = MEM(unsigned, EA + 2, 2); 29356ca2c52aSchristos h3 = MEM(unsigned, EA + 4, 2); 29366ca2c52aSchristos h4 = MEM(unsigned, EA + 6, 2); 29376ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29386ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 29396ca2c52aSchristos 29406ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.785:EVX:e500:evlwhe %RS,%RA,%UIMM:Vector Load Word into Two Half Words Even 29416ca2c52aSchristos unsigned_word b; 29426ca2c52aSchristos unsigned_word EA; 29436ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29446ca2c52aSchristos if (RA_is_0) b = 0; 29456ca2c52aSchristos else b = *rA; 29466ca2c52aSchristos EA = b + (UIMM << 2); 29476ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 29486ca2c52aSchristos h2 = 0; 29496ca2c52aSchristos h3 = MEM(unsigned, EA + 2, 2); 29506ca2c52aSchristos h4 = 0; 29516ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29526ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 29536ca2c52aSchristos 29546ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.784:EVX:e500:evlwhex %RS,%RA,%RB:Vector Load Word into Two Half Words Even Indexed 29556ca2c52aSchristos unsigned_word b; 29566ca2c52aSchristos unsigned_word EA; 29576ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29586ca2c52aSchristos if (RA_is_0) b = 0; 29596ca2c52aSchristos else b = *rA; 29606ca2c52aSchristos EA = b + *rB; 29616ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 29626ca2c52aSchristos h2 = 0; 29636ca2c52aSchristos h3 = MEM(unsigned, EA + 2, 2); 29646ca2c52aSchristos h4 = 0; 29656ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29666ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 29676ca2c52aSchristos 29686ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.789:EVX:e500:evlwhou %RS,%RA,%UIMM:Vector Load Word into Two Half Words Odd Unsigned zero-extended 29696ca2c52aSchristos unsigned_word b; 29706ca2c52aSchristos unsigned_word EA; 29716ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29726ca2c52aSchristos if (RA_is_0) b = 0; 29736ca2c52aSchristos else b = *rA; 29746ca2c52aSchristos EA = b + (UIMM << 2); 29756ca2c52aSchristos h1 = 0; 29766ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 29776ca2c52aSchristos h3 = 0; 29786ca2c52aSchristos h4 = MEM(unsigned, EA + 2, 2); 29796ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29806ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 29816ca2c52aSchristos 29826ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.788:EVX:e500:evlwhoux %RS,%RA,%RB:Vector Load Word into Two Half Words Odd Unsigned Indexed zero-extended 29836ca2c52aSchristos unsigned_word b; 29846ca2c52aSchristos unsigned_word EA; 29856ca2c52aSchristos unsigned16 h1, h2, h3, h4; 29866ca2c52aSchristos if (RA_is_0) b = 0; 29876ca2c52aSchristos else b = *rA; 29886ca2c52aSchristos EA = b + *rB; 29896ca2c52aSchristos h1 = 0; 29906ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 29916ca2c52aSchristos h3 = 0; 29926ca2c52aSchristos h4 = MEM(unsigned, EA + 2, 2); 29936ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 29946ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 29956ca2c52aSchristos 29966ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.791:EVX:e500:evlwhos %RS,%RA,%UIMM:Vector Load Word into Half Words Odd Signed with sign extension 29976ca2c52aSchristos unsigned_word b; 29986ca2c52aSchristos unsigned_word EA; 29996ca2c52aSchristos unsigned16 h1, h2, h3, h4; 30006ca2c52aSchristos if (RA_is_0) b = 0; 30016ca2c52aSchristos else b = *rA; 30026ca2c52aSchristos EA = b + (UIMM << 2); 30036ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 30046ca2c52aSchristos if (h2 & 0x8000) 30056ca2c52aSchristos h1 = 0xffff; 30066ca2c52aSchristos else 30076ca2c52aSchristos h1 = 0; 30086ca2c52aSchristos h4 = MEM(unsigned, EA + 2, 2); 30096ca2c52aSchristos if (h4 & 0x8000) 30106ca2c52aSchristos h3 = 0xffff; 30116ca2c52aSchristos else 30126ca2c52aSchristos h3 = 0; 30136ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 30146ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 30156ca2c52aSchristos 30166ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.790:EVX:e500:evlwhosx %RS,%RA,%RB:Vector Load Word into Half Words Odd Signed Indexed with sign extension 30176ca2c52aSchristos unsigned_word b; 30186ca2c52aSchristos unsigned_word EA; 30196ca2c52aSchristos unsigned16 h1, h2, h3, h4; 30206ca2c52aSchristos if (RA_is_0) b = 0; 30216ca2c52aSchristos else b = *rA; 30226ca2c52aSchristos EA = b + *rB; 30236ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 30246ca2c52aSchristos if (h2 & 0x8000) 30256ca2c52aSchristos h1 = 0xffff; 30266ca2c52aSchristos else 30276ca2c52aSchristos h1 = 0; 30286ca2c52aSchristos h4 = MEM(unsigned, EA + 2, 2); 30296ca2c52aSchristos if (h4 & 0x8000) 30306ca2c52aSchristos h3 = 0xffff; 30316ca2c52aSchristos else 30326ca2c52aSchristos h3 = 0; 30336ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 30346ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 30356ca2c52aSchristos 30366ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.793:EVX:e500:evlwwsplat %RS,%RA,%UIMM:Vector Load Word into Word and Splat 30376ca2c52aSchristos unsigned_word b; 30386ca2c52aSchristos unsigned_word EA; 30396ca2c52aSchristos unsigned32 w1; 30406ca2c52aSchristos if (RA_is_0) b = 0; 30416ca2c52aSchristos else b = *rA; 30426ca2c52aSchristos EA = b + (UIMM << 2); 30436ca2c52aSchristos w1 = MEM(unsigned, EA, 4); 30446ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w1); 30456ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 30466ca2c52aSchristos 30476ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.792:EVX:e500:evlwwsplatx %RS,%RA,%RB:Vector Load Word into Word and Splat Indexed 30486ca2c52aSchristos unsigned_word b; 30496ca2c52aSchristos unsigned_word EA; 30506ca2c52aSchristos unsigned32 w1; 30516ca2c52aSchristos if (RA_is_0) b = 0; 30526ca2c52aSchristos else b = *rA; 30536ca2c52aSchristos EA = b + *rB; 30546ca2c52aSchristos w1 = MEM(unsigned, EA, 4); 30556ca2c52aSchristos EV_SET_REG2(*rSh, *rS, w1, w1); 30566ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 30576ca2c52aSchristos 30586ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.797:EVX:e500:evlwhsplat %RS,%RA,%UIMM:Vector Load Word into 2 Half Words and Splat 30596ca2c52aSchristos unsigned_word b; 30606ca2c52aSchristos unsigned_word EA; 30616ca2c52aSchristos unsigned16 h1, h2; 30626ca2c52aSchristos if (RA_is_0) b = 0; 30636ca2c52aSchristos else b = *rA; 30646ca2c52aSchristos EA = b + (UIMM << 2); 30656ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 30666ca2c52aSchristos h2 = MEM(unsigned, EA + 2, 2); 30676ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); 30686ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 30696ca2c52aSchristos 30706ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.796:EVX:e500:evlwhsplatx %RS,%RA,%RB:Vector Load Word into 2 Half Words and Splat Indexed 30716ca2c52aSchristos unsigned_word b; 30726ca2c52aSchristos unsigned_word EA; 30736ca2c52aSchristos unsigned16 h1, h2; 30746ca2c52aSchristos if (RA_is_0) b = 0; 30756ca2c52aSchristos else b = *rA; 30766ca2c52aSchristos EA = b + *rB; 30776ca2c52aSchristos h1 = MEM(unsigned, EA, 2); 30786ca2c52aSchristos h2 = MEM(unsigned, EA + 2, 2); 30796ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); 30806ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 30816ca2c52aSchristos 30826ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.777:EVX:e500:evlhhesplat %RS,%RA,%UIMM:Vector Load Half Word into Half Words Even and Splat 30836ca2c52aSchristos unsigned_word b; 30846ca2c52aSchristos unsigned_word EA; 30856ca2c52aSchristos unsigned16 h; 30866ca2c52aSchristos if (RA_is_0) b = 0; 30876ca2c52aSchristos else b = *rA; 30886ca2c52aSchristos EA = b + (UIMM << 1); 30896ca2c52aSchristos h = MEM(unsigned, EA, 2); 30906ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h, 0, h, 0); 30916ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 30926ca2c52aSchristos 30936ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.776:EVX:e500:evlhhesplatx %RS,%RA,%RB:Vector Load Half Word into Half Words Even and Splat Indexed 30946ca2c52aSchristos unsigned_word b; 30956ca2c52aSchristos unsigned_word EA; 30966ca2c52aSchristos unsigned16 h; 30976ca2c52aSchristos if (RA_is_0) b = 0; 30986ca2c52aSchristos else b = *rA; 30996ca2c52aSchristos EA = b + *rB; 31006ca2c52aSchristos h = MEM(unsigned, EA, 2); 31016ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h, 0, h, 0); 31026ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 31036ca2c52aSchristos 31046ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.781:EVX:e500:evlhhousplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Unsigned and Splat 31056ca2c52aSchristos unsigned_word b; 31066ca2c52aSchristos unsigned_word EA; 31076ca2c52aSchristos unsigned16 h; 31086ca2c52aSchristos if (RA_is_0) b = 0; 31096ca2c52aSchristos else b = *rA; 31106ca2c52aSchristos EA = b + (UIMM << 1); 31116ca2c52aSchristos h = MEM(unsigned, EA, 2); 31126ca2c52aSchristos EV_SET_REG4(*rSh, *rS, 0, h, 0, h); 31136ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 31146ca2c52aSchristos 31156ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.780:EVX:e500:evlhhousplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed 31166ca2c52aSchristos unsigned_word b; 31176ca2c52aSchristos unsigned_word EA; 31186ca2c52aSchristos unsigned16 h; 31196ca2c52aSchristos if (RA_is_0) b = 0; 31206ca2c52aSchristos else b = *rA; 31216ca2c52aSchristos EA = b + *rB; 31226ca2c52aSchristos h = MEM(unsigned, EA, 2); 31236ca2c52aSchristos EV_SET_REG4(*rSh, *rS, 0, h, 0, h); 31246ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 31256ca2c52aSchristos 31266ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.783:EVX:e500:evlhhossplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Signed and Splat 31276ca2c52aSchristos unsigned_word b; 31286ca2c52aSchristos unsigned_word EA; 31296ca2c52aSchristos unsigned16 h1, h2; 31306ca2c52aSchristos if (RA_is_0) b = 0; 31316ca2c52aSchristos else b = *rA; 31326ca2c52aSchristos EA = b + (UIMM << 1); 31336ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 31346ca2c52aSchristos if (h2 & 0x8000) 31356ca2c52aSchristos h1 = 0xffff; 31366ca2c52aSchristos else 31376ca2c52aSchristos h1 = 0; 31386ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); 31396ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 31406ca2c52aSchristos 31416ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.782:EVX:e500:evlhhossplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Signed and Splat Indexed 31426ca2c52aSchristos unsigned_word b; 31436ca2c52aSchristos unsigned_word EA; 31446ca2c52aSchristos unsigned16 h1, h2; 31456ca2c52aSchristos if (RA_is_0) b = 0; 31466ca2c52aSchristos else b = *rA; 31476ca2c52aSchristos EA = b + *rB; 31486ca2c52aSchristos h2 = MEM(unsigned, EA, 2); 31496ca2c52aSchristos if (h2 & 0x8000) 31506ca2c52aSchristos h1 = 0xffff; 31516ca2c52aSchristos else 31526ca2c52aSchristos h1 = 0; 31536ca2c52aSchristos EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); 31546ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 31556ca2c52aSchristos 31566ca2c52aSchristos 31576ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.801:EVX:e500:evstdd %RS,%RA,%UIMM:Vector Store Double of Double 31586ca2c52aSchristos unsigned_word b; 31596ca2c52aSchristos unsigned_word EA; 31606ca2c52aSchristos if (RA_is_0) b = 0; 31616ca2c52aSchristos else b = *rA; 31626ca2c52aSchristos EA = b + (UIMM << 3); 31636ca2c52aSchristos STORE(EA, 4, (*rSh)); 31646ca2c52aSchristos STORE(EA + 4, 4, (*rS)); 31656ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 31666ca2c52aSchristos 31676ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.800:EVX:e500:evstddx %RS,%RA,%RB:Vector Store Double of Double Indexed 31686ca2c52aSchristos unsigned_word b; 31696ca2c52aSchristos unsigned_word EA; 31706ca2c52aSchristos if (RA_is_0) b = 0; 31716ca2c52aSchristos else b = *rA; 31726ca2c52aSchristos EA = b + *rB; 31736ca2c52aSchristos STORE(EA, 4, (*rSh)); 31746ca2c52aSchristos STORE(EA + 4, 4, (*rS)); 31756ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 31766ca2c52aSchristos 31776ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.803:EVX:e500:evstdw %RS,%RA,%UIMM:Vector Store Double of Two Words 31786ca2c52aSchristos unsigned_word b; 31796ca2c52aSchristos unsigned_word EA; 31806ca2c52aSchristos unsigned32 w1, w2; 31816ca2c52aSchristos if (RA_is_0) b = 0; 31826ca2c52aSchristos else b = *rA; 31836ca2c52aSchristos EA = b + (UIMM << 3); 31846ca2c52aSchristos w1 = *rSh; 31856ca2c52aSchristos w2 = *rS; 31866ca2c52aSchristos STORE(EA + 0, 4, w1); 31876ca2c52aSchristos STORE(EA + 4, 4, w2); 31886ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 31896ca2c52aSchristos 31906ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.802:EVX:e500:evstdwx %RS,%RA,%RB:Vector Store Double of Two Words Indexed 31916ca2c52aSchristos unsigned_word b; 31926ca2c52aSchristos unsigned_word EA; 31936ca2c52aSchristos unsigned32 w1, w2; 31946ca2c52aSchristos if (RA_is_0) b = 0; 31956ca2c52aSchristos else b = *rA; 31966ca2c52aSchristos EA = b + *rB; 31976ca2c52aSchristos w1 = *rSh; 31986ca2c52aSchristos w2 = *rS; 31996ca2c52aSchristos STORE(EA + 0, 4, w1); 32006ca2c52aSchristos STORE(EA + 4, 4, w2); 32016ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 32026ca2c52aSchristos 32036ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.805:EVX:e500:evstdh %RS,%RA,%UIMM:Vector Store Double of Four Half Words 32046ca2c52aSchristos unsigned_word b; 32056ca2c52aSchristos unsigned_word EA; 32066ca2c52aSchristos unsigned16 h1, h2, h3, h4; 32076ca2c52aSchristos if (RA_is_0) b = 0; 32086ca2c52aSchristos else b = *rA; 32096ca2c52aSchristos EA = b + (UIMM << 3); 32106ca2c52aSchristos h1 = EV_HIHALF(*rSh); 32116ca2c52aSchristos h2 = EV_LOHALF(*rSh); 32126ca2c52aSchristos h3 = EV_HIHALF(*rS); 32136ca2c52aSchristos h4 = EV_LOHALF(*rS); 32146ca2c52aSchristos STORE(EA + 0, 2, h1); 32156ca2c52aSchristos STORE(EA + 2, 2, h2); 32166ca2c52aSchristos STORE(EA + 4, 2, h3); 32176ca2c52aSchristos STORE(EA + 6, 2, h4); 32186ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 32196ca2c52aSchristos 32206ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.804:EVX:e500:evstdhx %RS,%RA,%RB:Vector Store Double of Four Half Words Indexed 32216ca2c52aSchristos unsigned_word b; 32226ca2c52aSchristos unsigned_word EA; 32236ca2c52aSchristos unsigned16 h1, h2, h3, h4; 32246ca2c52aSchristos if (RA_is_0) b = 0; 32256ca2c52aSchristos else b = *rA; 32266ca2c52aSchristos EA = b + *rB; 32276ca2c52aSchristos h1 = EV_HIHALF(*rSh); 32286ca2c52aSchristos h2 = EV_LOHALF(*rSh); 32296ca2c52aSchristos h3 = EV_HIHALF(*rS); 32306ca2c52aSchristos h4 = EV_LOHALF(*rS); 32316ca2c52aSchristos STORE(EA + 0, 2, h1); 32326ca2c52aSchristos STORE(EA + 2, 2, h2); 32336ca2c52aSchristos STORE(EA + 4, 2, h3); 32346ca2c52aSchristos STORE(EA + 6, 2, h4); 32356ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 32366ca2c52aSchristos 32376ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.825:EVX:e500:evstwwe %RS,%RA,%UIMM:Vector Store Word of Word from Even 32386ca2c52aSchristos unsigned_word b; 32396ca2c52aSchristos unsigned_word EA; 32406ca2c52aSchristos unsigned32 w; 32416ca2c52aSchristos if (RA_is_0) b = 0; 32426ca2c52aSchristos else b = *rA; 32436ca2c52aSchristos EA = b + (UIMM << 3); 32446ca2c52aSchristos w = *rSh; 32456ca2c52aSchristos STORE(EA, 4, w); 32466ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 32476ca2c52aSchristos 32486ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.824:EVX:e500:evstwwex %RS,%RA,%RB:Vector Store Word of Word from Even Indexed 32496ca2c52aSchristos unsigned_word b; 32506ca2c52aSchristos unsigned_word EA; 32516ca2c52aSchristos unsigned32 w; 32526ca2c52aSchristos if (RA_is_0) b = 0; 32536ca2c52aSchristos else b = *rA; 32546ca2c52aSchristos EA = b + *rB; 32556ca2c52aSchristos w = *rSh; 32566ca2c52aSchristos STORE(EA, 4, w); 32576ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 32586ca2c52aSchristos 32596ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.829:EVX:e500:evstwwo %RS,%RA,%UIMM:Vector Store Word of Word from Odd 32606ca2c52aSchristos unsigned_word b; 32616ca2c52aSchristos unsigned_word EA; 32626ca2c52aSchristos unsigned32 w; 32636ca2c52aSchristos if (RA_is_0) b = 0; 32646ca2c52aSchristos else b = *rA; 32656ca2c52aSchristos EA = b + (UIMM << 3); 32666ca2c52aSchristos w = *rS; 32676ca2c52aSchristos STORE(EA, 4, w); 32686ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 32696ca2c52aSchristos 32706ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.828:EVX:e500:evstwwox %RS,%RA,%RB:Vector Store Word of Word from Odd Indexed 32716ca2c52aSchristos unsigned_word b; 32726ca2c52aSchristos unsigned_word EA; 32736ca2c52aSchristos unsigned32 w; 32746ca2c52aSchristos if (RA_is_0) b = 0; 32756ca2c52aSchristos else b = *rA; 32766ca2c52aSchristos EA = b + *rB; 32776ca2c52aSchristos w = *rS; 32786ca2c52aSchristos STORE(EA, 4, w); 32796ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 32806ca2c52aSchristos 32816ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.817:EVX:e500:evstwhe %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Even 32826ca2c52aSchristos unsigned_word b; 32836ca2c52aSchristos unsigned_word EA; 32846ca2c52aSchristos unsigned16 h1, h2; 32856ca2c52aSchristos if (RA_is_0) b = 0; 32866ca2c52aSchristos else b = *rA; 32876ca2c52aSchristos EA = b + (UIMM << 3); 32886ca2c52aSchristos h1 = EV_HIHALF(*rSh); 32896ca2c52aSchristos h2 = EV_HIHALF(*rS); 32906ca2c52aSchristos STORE(EA + 0, 2, h1); 32916ca2c52aSchristos STORE(EA + 2, 2, h2); 32926ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 32936ca2c52aSchristos 32946ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.816:EVX:e500:evstwhex %RS,%RA,%RB:Vector Store Word of Two Half Words from Even Indexed 32956ca2c52aSchristos unsigned_word b; 32966ca2c52aSchristos unsigned_word EA; 32976ca2c52aSchristos unsigned16 h1, h2; 32986ca2c52aSchristos if (RA_is_0) b = 0; 32996ca2c52aSchristos else b = *rA; 33006ca2c52aSchristos EA = b + *rB; 33016ca2c52aSchristos h1 = EV_HIHALF(*rSh); 33026ca2c52aSchristos h2 = EV_HIHALF(*rS); 33036ca2c52aSchristos STORE(EA + 0, 2, h1); 33046ca2c52aSchristos STORE(EA + 2, 2, h2); 33056ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 33066ca2c52aSchristos 33076ca2c52aSchristos0.4,6.RS,11.RA,16.UIMM,21.821:EVX:e500:evstwho %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Odd 33086ca2c52aSchristos unsigned_word b; 33096ca2c52aSchristos unsigned_word EA; 33106ca2c52aSchristos unsigned16 h1, h2; 33116ca2c52aSchristos if (RA_is_0) b = 0; 33126ca2c52aSchristos else b = *rA; 33136ca2c52aSchristos EA = b + (UIMM << 3); 33146ca2c52aSchristos h1 = EV_LOHALF(*rSh); 33156ca2c52aSchristos h2 = EV_LOHALF(*rS); 33166ca2c52aSchristos STORE(EA + 0, 2, h1); 33176ca2c52aSchristos STORE(EA + 2, 2, h2); 33186ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 33196ca2c52aSchristos 33206ca2c52aSchristos0.4,6.RS,11.RA,16.RB,21.820:EVX:e500:evstwhox %RS,%RA,%RB:Vector Store Word of Two Half Words from Odd Indexed 33216ca2c52aSchristos unsigned_word b; 33226ca2c52aSchristos unsigned_word EA; 33236ca2c52aSchristos unsigned16 h1, h2; 33246ca2c52aSchristos if (RA_is_0) b = 0; 33256ca2c52aSchristos else b = *rA; 33266ca2c52aSchristos EA = b + *rB; 33276ca2c52aSchristos h1 = EV_LOHALF(*rSh); 33286ca2c52aSchristos h2 = EV_LOHALF(*rS); 33296ca2c52aSchristos STORE(EA + 0, 2, h1); 33306ca2c52aSchristos STORE(EA + 2, 2, h2); 33316ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 33326ca2c52aSchristos 33336ca2c52aSchristos 33346ca2c52aSchristos# 33356ca2c52aSchristos# 4.5.1 Integer Select Instruction 33366ca2c52aSchristos# 33376ca2c52aSchristos 33386ca2c52aSchristos0.31,6.RS,11.RA,16.RB,21.CRB,26.30:X:e500:isel %RS,%RA,%RB,%CRB:Integer Select 33396ca2c52aSchristos if (CR & (1 << (31 - (unsigned)CRB))) 33406ca2c52aSchristos if (RA_is_0) 33416ca2c52aSchristos EV_SET_REG1(*rSh, *rS, 0); 33426ca2c52aSchristos else 33436ca2c52aSchristos EV_SET_REG2(*rSh, *rS, *rAh, *rA); 33446ca2c52aSchristos else 33456ca2c52aSchristos EV_SET_REG2(*rSh, *rS, *rBh, *rB); 33466ca2c52aSchristos PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 3347