1//Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp
2// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Constants and Defines
12//
13
14include(gen_int.inc)
15include(selfcheck.inc)
16include(std.inc)
17include(mmrs.inc)
18include(symtable.inc)
19
20#ifndef STACKSIZE
21#define STACKSIZE 0x10   // change for how much stack you need
22#endif
23#ifndef ITABLE
24#define ITABLE 0xF0000000
25#endif
26
27GEN_INT_INIT(ITABLE) // set location for interrupt table
28
29//
30// Reset/Bootstrap Code
31//   (Here we should set the processor operating modes, initialize registers,
32//    etc.)
33//
34
35BOOT:
36INIT_R_REGS(0);     // initialize general purpose regs
37
38INIT_P_REGS(0);     // initialize the pointers
39
40INIT_I_REGS(0);     // initialize the dsp address regs
41INIT_M_REGS(0);
42INIT_L_REGS(0);
43INIT_B_REGS(0);
44
45CLI R1;           // inhibit events during MMR writes
46
47LD32_LABEL(sp, USTACK);   // setup the user stack pointer
48USP = SP;
49
50LD32_LABEL(sp, KSTACK);   // setup the kernel stack pointer
51FP = SP;        // and frame pointer
52
53LD32(p0, EVT0);      // Setup Event Vectors and Handlers
54
55    P0 += 4;            // EVT0 not used (Emulation)
56
57    P0 += 4;            // EVT1 not used (Reset)
58
59LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
60    [ P0 ++ ] = R0;
61
62LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
63    [ P0 ++ ] = R0;
64
65    P0 += 4;            // EVT4 not used (Global Interrupt Enable)
66
67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68    [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
71    [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74    [ P0 ++ ] = R0;
75
76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77    [ P0 ++ ] = R0;
78
79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80    [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83    [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86    [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89    [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92    [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95    [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98    [ P0 ++ ] = R0;
99
100LD32(p0, EVT_OVERRIDE);
101    R0 = 0;
102    [ P0 ++ ] = R0;
103
104    R1 = -1;     // Change this to mask interrupts (*)
105CSYNC;       // wait for MMR writes to finish
106STI R1;      // sync and reenable events (implicit write to IMASK)
107
108DUMMY:
109
110    R0 = 0 (Z);
111
112LT0 = r0;       // set loop counters to something deterministic
113LB0 = r0;
114LC0 = r0;
115LT1 = r0;
116LB1 = r0;
117LC1 = r0;
118
119ASTAT = r0;     // reset other internal regs
120SYSCFG = r0;
121RETS = r0;      // prevent X's breaking LINK instruction
122
123// The following code sets up the test for running in USER mode
124
125LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
126                        // ReturnFromInterrupt (RTI)
127RETI = r0;      // We need to load the return address
128
129// Comment the following line for a USER Mode test
130
131JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
132
133RTI;
134
135STARTSUP:
136LD32_LABEL(p1, BEGIN);
137
138LD32(p0, EVT15);
139
140CLI R1;   // inhibit events during write to MMR
141    [ P0 ] = P1;  // IVG15 (General) handler (Int 15) load with start
142CSYNC;      // wait for it
143STI R1;     // reenable events with proper imask
144
145RAISE 15;       // after we RTI, INT 15 should be taken
146
147RTI;
148
149//
150// The Main Program
151//
152
153STARTUSER:
154
155LINK 0;     // change for how much stack frame space you need.
156
157JUMP BEGIN;
158
159//*********************************************************************
160
161BEGIN:
162
163                // COMMENT the following line for USER MODE tests
164    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
165
166                // **** YOUR CODE GOES HERE ****
167
168    // count of UI's will be in r5, which was initialized to 0 by header
169    .dw 0xC0E0 ;
170    .dw 0x2000 ;
171    .dw 0xC140 ;
172    .dw 0x2000 ;
173    .dw 0xC1A0 ;
174    .dw 0x2000 ;
175    .dw 0xC1C0 ;
176    .dw 0x2000 ;
177    .dw 0xC1E0 ;
178    .dw 0x2000 ;
179
180    .dw 0xC0E4 ;
181    .dw 0x0 ;
182    .dw 0xC144 ;
183    .dw 0x0 ;
184    .dw 0xC1A4 ;
185    .dw 0x0 ;
186    .dw 0xC1C4 ;
187    .dw 0x0 ;
188    .dw 0xC1E4 ;
189    .dw 0x0 ;
190
191    .dw 0xC0E4 ;
192    .dw 0x2000 ;
193    .dw 0xC144 ;
194    .dw 0x2000 ;
195    .dw 0xC1A4 ;
196    .dw 0x2000 ;
197    .dw 0xC1C4 ;
198    .dw 0x2000 ;
199    .dw 0xC1E4 ;
200    .dw 0x2000 ;
201
202CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
203                    // Xhandler counts all EXCAUSE = 0x21;
204CHECKREG(r5, 15); // count of all 16 bit UI's.
205
206END:
207dbg_pass;            // End the test
208
209//*********************************************************************
210
211//
212// Handlers for Events
213//
214
215NHANDLE:            // NMI Handler 2
216RTN;
217
218XHANDLE:            // Exception Handler 3
219                    // 32 bit illegal opcode handler - skips bad instruction
220
221    // handler MADE LEAN and destructive so test runs more quckly
222    //   se_undefinedinstruction1.dsp tests using a "nice" handler
223
224//    [--sp] = ASTAT; // save what we damage
225//    [--sp] = (r7 - r6);
226    R7 = SEQSTAT;
227    R7 <<= 26;
228    R7 >>= 26;      // only want EXCAUSE
229    R6 = 0x21;      // EXCAUSE 0x21 means I-Fetch Undefined Instruction
230CC = r7 == r6;
231IF !CC JUMP OUT;   // If EXCAUSE != 0x21 then leave
232
233UNDEFINEDINSTRUCTION:
234    R7 = RETX;      // Fix up return address
235
236    R7 += 4;        // skip offending 32 bit instruction
237
238RETX = r7;      // and put back in RETX
239
240    R5 += 1;        // Increment global counter
241
242OUT:
243//    (r7 - r6) = [sp++];
244//    ASTAT = [sp++];
245
246RTX;
247
248HWHANDLE:           // HW Error Handler 5
249RTI;
250
251THANDLE:            // Timer Handler 6
252RTI;
253
254I7HANDLE:           // IVG 7 Handler
255RTI;
256
257I8HANDLE:           // IVG 8 Handler
258RTI;
259
260I9HANDLE:           // IVG 9 Handler
261RTI;
262
263I10HANDLE:          // IVG 10 Handler
264RTI;
265
266I11HANDLE:          // IVG 11 Handler
267RTI;
268
269I12HANDLE:          // IVG 12 Handler
270RTI;
271
272I13HANDLE:          // IVG 13 Handler
273RTI;
274
275I14HANDLE:          // IVG 14 Handler
276RTI;
277
278I15HANDLE:          // IVG 15 Handler
279RTI;
280
281
282    // padding for the icache
283
284EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
285
286//
287// Data Segment
288//
289
290.data
291DATA:
292    .space (0x10);
293
294// Stack Segments (Both Kernel and User)
295
296    .space (STACKSIZE);
297KSTACK:
298
299    .space (STACKSIZE);
300USTACK:
301