1*48596154Schristos//Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp
2*48596154Schristos// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
3*48596154Schristos# mach: bfin
4*48596154Schristos# sim: --environment operating
5*48596154Schristos
6*48596154Schristos#include "test.h"
7*48596154Schristos.include "testutils.inc"
8*48596154Schristosstart
9*48596154Schristos
10*48596154Schristos//
11*48596154Schristos// Constants and Defines
12*48596154Schristos//
13*48596154Schristos
14*48596154Schristosinclude(gen_int.inc)
15*48596154Schristosinclude(selfcheck.inc)
16*48596154Schristosinclude(std.inc)
17*48596154Schristosinclude(mmrs.inc)
18*48596154Schristosinclude(symtable.inc)
19*48596154Schristos
20*48596154Schristos#ifndef STACKSIZE
21*48596154Schristos#define STACKSIZE 0x10   // change for how much stack you need
22*48596154Schristos#endif
23*48596154Schristos#ifndef ITABLE
24*48596154Schristos#define ITABLE 0xF0000000
25*48596154Schristos#endif
26*48596154Schristos
27*48596154SchristosGEN_INT_INIT(ITABLE) // set location for interrupt table
28*48596154Schristos
29*48596154Schristos//
30*48596154Schristos// Reset/Bootstrap Code
31*48596154Schristos//   (Here we should set the processor operating modes, initialize registers,
32*48596154Schristos//    etc.)
33*48596154Schristos//
34*48596154Schristos
35*48596154SchristosBOOT:
36*48596154SchristosINIT_R_REGS(0);     // initialize general purpose regs
37*48596154Schristos
38*48596154SchristosINIT_P_REGS(0);     // initialize the pointers
39*48596154Schristos
40*48596154SchristosINIT_I_REGS(0);     // initialize the dsp address regs
41*48596154SchristosINIT_M_REGS(0);
42*48596154SchristosINIT_L_REGS(0);
43*48596154SchristosINIT_B_REGS(0);
44*48596154Schristos
45*48596154SchristosCLI R1;           // inhibit events during MMR writes
46*48596154Schristos
47*48596154SchristosLD32_LABEL(sp, USTACK);   // setup the user stack pointer
48*48596154SchristosUSP = SP;
49*48596154Schristos
50*48596154SchristosLD32_LABEL(sp, KSTACK);   // setup the kernel stack pointer
51*48596154SchristosFP = SP;        // and frame pointer
52*48596154Schristos
53*48596154SchristosLD32(p0, EVT0);      // Setup Event Vectors and Handlers
54*48596154Schristos
55*48596154Schristos    P0 += 4;            // EVT0 not used (Emulation)
56*48596154Schristos
57*48596154Schristos    P0 += 4;            // EVT1 not used (Reset)
58*48596154Schristos
59*48596154SchristosLD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
60*48596154Schristos    [ P0 ++ ] = R0;
61*48596154Schristos
62*48596154SchristosLD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
63*48596154Schristos    [ P0 ++ ] = R0;
64*48596154Schristos
65*48596154Schristos    P0 += 4;            // EVT4 not used (Global Interrupt Enable)
66*48596154Schristos
67*48596154SchristosLD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68*48596154Schristos    [ P0 ++ ] = R0;
69*48596154Schristos
70*48596154SchristosLD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
71*48596154Schristos    [ P0 ++ ] = R0;
72*48596154Schristos
73*48596154SchristosLD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74*48596154Schristos    [ P0 ++ ] = R0;
75*48596154Schristos
76*48596154SchristosLD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77*48596154Schristos    [ P0 ++ ] = R0;
78*48596154Schristos
79*48596154SchristosLD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80*48596154Schristos    [ P0 ++ ] = R0;
81*48596154Schristos
82*48596154SchristosLD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83*48596154Schristos    [ P0 ++ ] = R0;
84*48596154Schristos
85*48596154SchristosLD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86*48596154Schristos    [ P0 ++ ] = R0;
87*48596154Schristos
88*48596154SchristosLD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89*48596154Schristos    [ P0 ++ ] = R0;
90*48596154Schristos
91*48596154SchristosLD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92*48596154Schristos    [ P0 ++ ] = R0;
93*48596154Schristos
94*48596154SchristosLD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95*48596154Schristos    [ P0 ++ ] = R0;
96*48596154Schristos
97*48596154SchristosLD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98*48596154Schristos    [ P0 ++ ] = R0;
99*48596154Schristos
100*48596154SchristosLD32(p0, EVT_OVERRIDE);
101*48596154Schristos    R0 = 0;
102*48596154Schristos    [ P0 ++ ] = R0;
103*48596154Schristos
104*48596154Schristos    R1 = -1;     // Change this to mask interrupts (*)
105*48596154SchristosCSYNC;       // wait for MMR writes to finish
106*48596154SchristosSTI R1;      // sync and reenable events (implicit write to IMASK)
107*48596154Schristos
108*48596154SchristosDUMMY:
109*48596154Schristos
110*48596154Schristos    R0 = 0 (Z);
111*48596154Schristos
112*48596154SchristosLT0 = r0;       // set loop counters to something deterministic
113*48596154SchristosLB0 = r0;
114*48596154SchristosLC0 = r0;
115*48596154SchristosLT1 = r0;
116*48596154SchristosLB1 = r0;
117*48596154SchristosLC1 = r0;
118*48596154Schristos
119*48596154SchristosASTAT = r0;     // reset other internal regs
120*48596154SchristosSYSCFG = r0;
121*48596154SchristosRETS = r0;      // prevent X's breaking LINK instruction
122*48596154Schristos
123*48596154Schristos// The following code sets up the test for running in USER mode
124*48596154Schristos
125*48596154SchristosLD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
126*48596154Schristos                        // ReturnFromInterrupt (RTI)
127*48596154SchristosRETI = r0;      // We need to load the return address
128*48596154Schristos
129*48596154Schristos// Comment the following line for a USER Mode test
130*48596154Schristos
131*48596154SchristosJUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
132*48596154Schristos
133*48596154SchristosRTI;
134*48596154Schristos
135*48596154SchristosSTARTSUP:
136*48596154SchristosLD32_LABEL(p1, BEGIN);
137*48596154Schristos
138*48596154SchristosLD32(p0, EVT15);
139*48596154Schristos
140*48596154SchristosCLI R1;   // inhibit events during write to MMR
141*48596154Schristos    [ P0 ] = P1;  // IVG15 (General) handler (Int 15) load with start
142*48596154SchristosCSYNC;      // wait for it
143*48596154SchristosSTI R1;     // reenable events with proper imask
144*48596154Schristos
145*48596154SchristosRAISE 15;       // after we RTI, INT 15 should be taken
146*48596154Schristos
147*48596154SchristosRTI;
148*48596154Schristos
149*48596154Schristos//
150*48596154Schristos// The Main Program
151*48596154Schristos//
152*48596154Schristos
153*48596154SchristosSTARTUSER:
154*48596154Schristos
155*48596154SchristosLINK 0;     // change for how much stack frame space you need.
156*48596154Schristos
157*48596154SchristosJUMP BEGIN;
158*48596154Schristos
159*48596154Schristos//*********************************************************************
160*48596154Schristos
161*48596154SchristosBEGIN:
162*48596154Schristos
163*48596154Schristos                // COMMENT the following line for USER MODE tests
164*48596154Schristos    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
165*48596154Schristos
166*48596154Schristos                // **** YOUR CODE GOES HERE ****
167*48596154Schristos
168*48596154Schristos    // count of UI's will be in r5, which was initialized to 0 by header
169*48596154Schristos
170*48596154Schristos    .dw 0x41FD ;
171*48596154Schristos    .dw 0x41FE ;
172*48596154Schristos    .dw 0x41FF ;
173*48596154Schristos    .dw 0x9040 ;
174*48596154Schristos    .dw 0x9049 ;
175*48596154Schristos    .dw 0x9052 ;
176*48596154Schristos    .dw 0x905B ;
177*48596154Schristos    .dw 0x9064 ;
178*48596154Schristos    .dw 0x906D ;
179*48596154Schristos    .dw 0x9076 ;
180*48596154Schristos    .dw 0x907F ;
181*48596154Schristos    .dw 0x90C0 ;
182*48596154Schristos    .dw 0x90C9 ;
183*48596154Schristos    .dw 0x90D2 ;
184*48596154Schristos    .dw 0x90DB ;
185*48596154Schristos    .dw 0x90E4 ;
186*48596154Schristos    .dw 0x90ED ;
187*48596154Schristos    .dw 0x90F6 ;
188*48596154Schristos    .dw 0x90FF ;
189*48596154Schristos    .dw 0x9180 ;
190*48596154Schristos
191*48596154Schristos
192*48596154SchristosCHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
193*48596154Schristos                    // Xhandler counts all EXCAUSE = 0x21;
194*48596154SchristosCHECKREG(r5, 20); // count of all 16 bit UI's.
195*48596154Schristos
196*48596154SchristosEND:
197*48596154Schristosdbg_pass;            // End the test
198*48596154Schristos
199*48596154Schristos//*********************************************************************
200*48596154Schristos
201*48596154Schristos//
202*48596154Schristos// Handlers for Events
203*48596154Schristos//
204*48596154Schristos
205*48596154SchristosNHANDLE:            // NMI Handler 2
206*48596154SchristosRTN;
207*48596154Schristos
208*48596154SchristosXHANDLE:            // Exception Handler 3
209*48596154Schristos                    // 16 bit illegal opcode handler - skips bad instruction
210*48596154Schristos
211*48596154Schristos    // handler MADE LEAN and destructive so test runs more quckly
212*48596154Schristos    //   se_undefinedinstruction1.dsp tests using a "nice" handler
213*48596154Schristos
214*48596154Schristos//    [--sp] = ASTAT; // save what we damage
215*48596154Schristos//    [--sp] = (r7 - r6);
216*48596154Schristos    R7 = SEQSTAT;
217*48596154Schristos    R7 <<= 26;
218*48596154Schristos    R7 >>= 26;      // only want EXCAUSE
219*48596154Schristos    R6 = 0x21;      // EXCAUSE 0x21 means I-Fetch Undefined Instruction
220*48596154SchristosCC = r7 == r6;
221*48596154SchristosIF CC JUMP UNDEFINEDINSTRUCTION;   // If EXCAUSE != 0x21 then leave
222*48596154Schristos
223*48596154Schristos    R6 = 0x22;      // Also accept illegal insn combo
224*48596154SchristosCC = r7 == r6;
225*48596154SchristosIF CC JUMP UNDEFINEDINSTRUCTION;   // If EXCAUSE != 0x21 then leave
226*48596154Schristos
227*48596154Schristosdbg_fail;
228*48596154Schristos
229*48596154SchristosUNDEFINEDINSTRUCTION:
230*48596154Schristos    R7 = RETX;      // Fix up return address
231*48596154Schristos
232*48596154Schristos    R7 += 2;        // skip offending 16 bit instruction
233*48596154Schristos
234*48596154SchristosRETX = r7;      // and put back in RETX
235*48596154Schristos
236*48596154Schristos    R5 += 1;        // Increment global counter
237*48596154Schristos
238*48596154SchristosOUT:
239*48596154Schristos//    (r7 - r6) = [sp++];
240*48596154Schristos//    ASTAT = [sp++];
241*48596154Schristos
242*48596154SchristosRTX;
243*48596154Schristos
244*48596154SchristosHWHANDLE:           // HW Error Handler 5
245*48596154SchristosRTI;
246*48596154Schristos
247*48596154SchristosTHANDLE:            // Timer Handler 6
248*48596154SchristosRTI;
249*48596154Schristos
250*48596154SchristosI7HANDLE:           // IVG 7 Handler
251*48596154SchristosRTI;
252*48596154Schristos
253*48596154SchristosI8HANDLE:           // IVG 8 Handler
254*48596154SchristosRTI;
255*48596154Schristos
256*48596154SchristosI9HANDLE:           // IVG 9 Handler
257*48596154SchristosRTI;
258*48596154Schristos
259*48596154SchristosI10HANDLE:          // IVG 10 Handler
260*48596154SchristosRTI;
261*48596154Schristos
262*48596154SchristosI11HANDLE:          // IVG 11 Handler
263*48596154SchristosRTI;
264*48596154Schristos
265*48596154SchristosI12HANDLE:          // IVG 12 Handler
266*48596154SchristosRTI;
267*48596154Schristos
268*48596154SchristosI13HANDLE:          // IVG 13 Handler
269*48596154SchristosRTI;
270*48596154Schristos
271*48596154SchristosI14HANDLE:          // IVG 14 Handler
272*48596154SchristosRTI;
273*48596154Schristos
274*48596154SchristosI15HANDLE:          // IVG 15 Handler
275*48596154SchristosRTI;
276*48596154Schristos
277*48596154Schristos
278*48596154Schristos    // padding for the icache
279*48596154Schristos
280*48596154SchristosEXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
281*48596154Schristos
282*48596154Schristos//
283*48596154Schristos// Data Segment
284*48596154Schristos//
285*48596154Schristos
286*48596154Schristos.data
287*48596154SchristosDATA:
288*48596154Schristos    .space (0x10);
289*48596154Schristos
290*48596154Schristos// Stack Segments (Both Kernel and User)
291*48596154Schristos
292*48596154Schristos    .space (STACKSIZE);
293*48596154SchristosKSTACK:
294*48596154Schristos
295*48596154Schristos    .space (STACKSIZE);
296*48596154SchristosUSTACK:
297