1*99307961Smatt.\" $NetBSD: arm_sync_icache.2,v 1.6 2014/01/16 21:48:41 matt Exp $ 298de4ab7Sthorpej.\" 398de4ab7Sthorpej.\" Copyright (c) 1996 Mark Brinicombe 498de4ab7Sthorpej.\" All rights reserved. 598de4ab7Sthorpej.\" 698de4ab7Sthorpej.\" Redistribution and use in source and binary forms, with or without 798de4ab7Sthorpej.\" modification, are permitted provided that the following conditions 898de4ab7Sthorpej.\" are met: 998de4ab7Sthorpej.\" 1. Redistributions of source code must retain the above copyright 1098de4ab7Sthorpej.\" notice, this list of conditions and the following disclaimer. 1198de4ab7Sthorpej.\" 2. Redistributions in binary form must reproduce the above copyright 1298de4ab7Sthorpej.\" notice, this list of conditions and the following disclaimer in the 1398de4ab7Sthorpej.\" documentation and/or other materials provided with the distribution. 1498de4ab7Sthorpej.\" 3. All advertising materials mentioning features or use of this software 1598de4ab7Sthorpej.\" must display the following acknowledgement: 1698de4ab7Sthorpej.\" This product includes software developed by Mark Brinicombe 1798de4ab7Sthorpej.\" 4. Neither the name of the University nor the names of its contributors 1898de4ab7Sthorpej.\" may be used to endorse or promote products derived from this software 1998de4ab7Sthorpej.\" without specific prior written permission. 2098de4ab7Sthorpej.\" 2198de4ab7Sthorpej.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2298de4ab7Sthorpej.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2398de4ab7Sthorpej.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2498de4ab7Sthorpej.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2598de4ab7Sthorpej.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2698de4ab7Sthorpej.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2798de4ab7Sthorpej.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2898de4ab7Sthorpej.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2998de4ab7Sthorpej.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3098de4ab7Sthorpej.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3198de4ab7Sthorpej.\" SUCH DAMAGE. 3298de4ab7Sthorpej.\" 33*99307961Smatt.Dd January 17, 2014 3498de4ab7Sthorpej.Dt ARM_SYNC_ICACHE 2 arm 3598de4ab7Sthorpej.Os 3698de4ab7Sthorpej.Sh NAME 3798de4ab7Sthorpej.Nm arm_sync_icache 380568bf74Swiz.Nd clean the CPU data cache and flush the CPU instruction cache 3998de4ab7Sthorpej.Sh LIBRARY 4098de4ab7Sthorpej.Lb libarm 4198de4ab7Sthorpej.Sh SYNOPSIS 42472351e1Swiz.In machine/sysarch.h 4398de4ab7Sthorpej.Ft int 44*99307961Smatt.Fn arm_sync_icache "uintptr_t addr" "size_t len" 4598de4ab7Sthorpej.Sh DESCRIPTION 4698de4ab7Sthorpej.Fn arm_sync_icache 4798de4ab7Sthorpejwill make sure that all the entries in the processor instruction cache 481022a63fSwizare synchronized with main memory and that any data in a write back cache 4998de4ab7Sthorpejhas been cleaned. 50de0b517cSwizSome ARM processors (e.g. SA110) have separate instruction and data 5198de4ab7Sthorpejcaches thus any dynamically generated or modified code needs to be 5298de4ab7Sthorpejwritten back from any data caches to main memory and the instruction 531022a63fSwizcache needs to be synchronized with main memory. 5498de4ab7Sthorpej.Pp 5598de4ab7SthorpejOn such processors 5698de4ab7Sthorpej.Fn arm_sync_icache 5798de4ab7Sthorpejwill clean the data cache and invalidate the processor instruction cache 58de0b517cSwizto force reloading from main memory. 59de0b517cSwizOn processors that have a shared instruction and data cache and have a 60de0b517cSwizwrite through cache (e.g. ARM6) no action needs to be taken. 6198de4ab7Sthorpej.Pp 6298de4ab7SthorpejThe routine takes a start address 6398de4ab7Sthorpej.Fa addr 6498de4ab7Sthorpejand a length 6598de4ab7Sthorpej.Fa len 661022a63fSwizto describe the area of memory that needs to be cleaned and synchronized. 6798de4ab7Sthorpej.Sh ERRORS 6898de4ab7Sthorpej.Fn arm_sync_icache 6998de4ab7Sthorpejwill never fail so will always return 0. 7098de4ab7Sthorpej.Sh REFERENCES 7198de4ab7SthorpejStrongARM Data Sheet 72