1.\" $NetBSD: arm_sync_icache.2,v 1.5 2004/02/13 09:56:47 wiz Exp $ 2.\" 3.\" Copyright (c) 1996 Mark Brinicombe 4.\" All rights reserved. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 3. All advertising materials mentioning features or use of this software 15.\" must display the following acknowledgement: 16.\" This product includes software developed by Mark Brinicombe 17.\" 4. Neither the name of the University nor the names of its contributors 18.\" may be used to endorse or promote products derived from this software 19.\" without specific prior written permission. 20.\" 21.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31.\" SUCH DAMAGE. 32.\" 33.Dd March 29, 2002 34.Dt ARM_SYNC_ICACHE 2 arm 35.Os 36.Sh NAME 37.Nm arm_sync_icache 38.Nd clean the CPU data cache and flush the CPU instruction cache 39.Sh LIBRARY 40.Lb libarm 41.Sh SYNOPSIS 42.In machine/sysarch.h 43.Ft int 44.Fn arm_sync_icache "u_int addr" "int len" 45.Sh DESCRIPTION 46.Fn arm_sync_icache 47will make sure that all the entries in the processor instruction cache 48are synchronized with main memory and that any data in a write back cache 49has been cleaned. 50Some ARM processors (e.g. SA110) have separate instruction and data 51caches thus any dynamically generated or modified code needs to be 52written back from any data caches to main memory and the instruction 53cache needs to be synchronized with main memory. 54.Pp 55On such processors 56.Fn arm_sync_icache 57will clean the data cache and invalidate the processor instruction cache 58to force reloading from main memory. 59On processors that have a shared instruction and data cache and have a 60write through cache (e.g. ARM6) no action needs to be taken. 61.Pp 62The routine takes a start address 63.Fa addr 64and a length 65.Fa len 66to describe the area of memory that needs to be cleaned and synchronized. 67.Sh ERRORS 68.Fn arm_sync_icache 69will never fail so will always return 0. 70.Sh REFERENCES 71StrongARM Data Sheet 72