1.\" $NetBSD: epgpio.4,v 1.3 2009/03/09 19:24:29 joerg Exp $ 2.\" 3.\" Copyright (c) 2009 Ken Hornstein. 4.\" All rights reserved 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.Dd February 22, 2009 28.Dt EPGPIO 4 29.Os 30.Sh NAME 31.Nm epgpio 32.Nd General Purpose I/O support for Cirrus EP93xx ARM processors 33.Sh SYNOPSIS 34.Cd "epgpio0 at epsoc? addr 0x80840000 size 0xcc intr 59" 35.Cd "gpio* at epgpio?" 36.Pp 37.Cd options EPGPIO_PORT_A_MASK=0xXX 38.Cd options EPGPIO_PORT_B_MASK=0xXX 39.Cd options EPGPIO_PORT_C_MASK=0xXX 40.Cd options EPGPIO_PORT_D_MASK=0xXX 41.Cd options EPGPIO_PORT_E_MASK=0xXX 42.Cd options EPGPIO_PORT_F_MASK=0xXX 43.Cd options EPGPIO_PORT_G_MASK=0xXX 44.Cd options EPGPIO_PORT_H_MASK=0xXX 45.Sh DESCRIPTION 46The 47.Nm 48driver provides support for the on-board General Purpose I/O (GPIO) pins on 49the Cirrus Logic EP93xx series of processors. 50There are 8 GPIO ports (Ports 51A though H) each having 8 GPIO pins available (note: early revisions of 52some EP9301 processors have some ports with less than eight pins available 53on each port; check the documentation for your specific processor). 54.Pp 55The 56.Nm 57driver provides a 58.Xr gpio 4 59controller interface and will attach each port as a separate 60.Xr gpio 4 61device with 8 pins available. 62All pins are bidirectional; when used 63as inputs they should not be driven beyond TTL voltage levels, but 64for exact details on the electrical interface the documentation for 65the specific evbarm board should be consulted. 66.Ss Kernel options 67The following kernel options are available to configure the behavior of the 68.Nm 69driver. 70.Pp 71.Bl -tag -width "options" -compact 72.It Cd options EPGPIO_PORT_A_MASK=0xXX 73.It Cd options EPGPIO_PORT_B_MASK=0xXX 74.It Cd options EPGPIO_PORT_C_MASK=0xXX 75.It Cd options EPGPIO_PORT_D_MASK=0xXX 76.It Cd options EPGPIO_PORT_E_MASK=0xXX 77.It Cd options EPGPIO_PORT_F_MASK=0xXX 78.It Cd options EPGPIO_PORT_G_MASK=0xXX 79.It Cd options EPGPIO_PORT_H_MASK=0xXX 80.El 81.Pp 82Each of these options is a bitmask specifying the pins available to the 83.Xr gpio 4 84controller for the corresponding port. 85Pins should be disabled if they 86are not available or are being used by the hardware for other purposes. 87The default mask is 88.Dq 0xff 89for all ports. 90.Sh IMPLEMENTATION NOTES 91When a port bitmask configures less than 8 pins available, the remaining 92pins will appear as sequentially numbered pins to the 93.Xr gpio 4 94interface. 95For example, if 96.Dv EPGPIO_PORT_A_MASK 97is set to 98.Dq 0x2c , 99Port A pins 1, 3, and 5 will appear as 100.Xr gpio 4 101pins 0, 1, and 2 respectively. 102.Sh SEE ALSO 103.Xr gpio 4 104