1.\" $NetBSD: stpcide.4,v 1.8 2009/10/21 00:30:43 snj Exp $ 2.\" 3.\" Copyright (c) 2003 Tohru Nishimura. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22.\" INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24.\" 25.Dd October 31, 2003 26.Dt STPCIDE 4 27.Os 28.Sh NAME 29.Nm stpcide 30.Nd STMicroelectronics STPC IDE disk controllers driver 31.Sh SYNOPSIS 32.Cd "stpcide* at pci? dev ? function ? flags 0x0000" 33.Sh DESCRIPTION 34The 35.Nm 36driver supports the STMicroelectronics STPC x86 SoC internal IDE controllers, 37and provides the interface with the hardware for the 38.Xr ata 4 39driver. 40The driver features DMA mode 2 and PIO mode 4 transfer speeds. 41.Pp 42The 0x0002 flag forces the 43.Nm 44driver to disable DMA on chipsets for which DMA would normally be 45enabled. 46This can be used as a debugging aid, or to work around 47problems where the IDE controller is wired up to the system incorrectly. 48.Sh SEE ALSO 49.Xr ata 4 , 50.Xr atapi 4 , 51.Xr intro 4 , 52.Xr pci 4 , 53.Xr pciide 4 , 54.Xr wd 4 , 55.Xr wdc 4 56.Sh BUGS 57The timings used for the DMA and PIO modes are for STPC Atlas and 58its siblings with their PCI clock configured at 33 MHz. 59Other speeds including the STPC Vega Ultra-IDE controller will need 60adjustments. 61