1.\" $NetBSD: pci_configure_bus.9,v 1.8 2002/02/25 00:40:19 kleink Exp $ 2.\" 3.\" Copyright 2001 Wasabi Systems, Inc. 4.\" All rights reserved. 5.\" 6.\" Written by Allen Briggs for Wasabi Systems, Inc. 7.\" 8.\" Redistribution and use in source and binary forms, with or without 9.\" modification, are permitted provided that the following conditions 10.\" are met: 11.\" 1. Redistributions of source code must retain the above copyright 12.\" notice, this list of conditions and the following disclaimer. 13.\" 2. Redistributions in binary form must reproduce the above copyright 14.\" notice, this list of conditions and the following disclaimer in the 15.\" documentation and/or other materials provided with the distribution. 16.\" 3. All advertising materials mentioning features or use of this software 17.\" must display the following acknowledgement: 18.\" This product includes software developed for the NetBSD Project by 19.\" Wasabi Systems, Inc. 20.\" 4. The name of Wasabi Systems, Inc. may not be used to endorse 21.\" or promote products derived from this software without specific prior 22.\" written permission. 23.\" 24.\" THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 25.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34.\" POSSIBILITY OF SUCH DAMAGE. 35.\" 36.Dd February 25, 2002 37.Dt PCI_CONFIGURE_BUS 9 38.Os 39.Sh NAME 40.Nm pci_configure_bus , 41.Nm pci_conf_hook , 42.Nm pci_conf_interrupt 43.Nd perform PCI bus configuration 44.Sh SYNOPSIS 45.Fd #include \*[Lt]dev/pci/pciconf.h\*[Gt] 46.Ft int 47.Fo pci_configure_bus 48.Fa "pci_chipset_tag_t pc" 49.Fa "struct extent *ioext" 50.Fa "struct extent *memext" 51.Fa "struct extent *pmemext" 52.Fa "int firstbus" 53.Fa "int cacheline_size" 54.Fc 55.Sh DESCRIPTION 56The 57.Fn pci_configure_bus 58function configures a PCI bus for use. This involves: 59.Bl -bullet 60.It 61Defining bus numbers for all busses on the system, 62.It 63Setting the Base Address Registers for all devices, 64.It 65Setting up the interrupt line register for all devices, 66.It 67Configuring bus latency timers for all devices, and 68.It 69Configuring cacheline sizes for all devices. 70.El 71.Pp 72In traditional PCs and Alpha systems, the BIOS or firmware takes care 73of this task, but that is not the case for all systems. 74.Fn pci_configure_bus 75should be called prior to the auto-configuration of the bus. 76.Pp 77The 78.Fa pc 79argument is a machine-dependent tag used to specify the PCI chipset to the 80system. This should be the same value used with 81.Fn pci_make_tag . 82The extent arguments 83define memory extents from which the address space for the cards will be 84taken. These addresses should be in the PCI address space. The 85.Fa ioext 86extent is for PCI I/O accesses. The 87.Fa memext 88extent is for PCI memory accesses that might have side effects. I.e., 89that can not be cached. The 90.Fa pmemext 91extent is for PCI memory accesses that can be cached. The 92.Fa pmemext 93extent will be used for any ROMs and any memory regions that are marked as 94.Dq prefetchable 95in their BAR. If an implementation does not distinguish between 96prefetchable and non-prefetchable memory, it may pass NULL for 97.Fa pmemext . 98In this case, prefetchable memory allocations will be made from the 99non-prefetchable region. The 100.Fa firstbus 101argument indicates the number of the first bus to be configured. The 102.Fa cacheline_size 103argument is used to configure the PCI Cache Line Size Register; it 104should be the size, in bytes, of the largest D-cache line on the system. 105.Pp 106An implementation may choose to not have full configuration performed 107by 108.Fn pci_configure_bus 109on certain PCI devices, such as PCI host bridges or PCI bus analyzers 110which are instantiated as devices on the bus. In order for this to 111take place, the header 112.Aq Pa machine/pci_machdep.h 113must define the 114.Dv __HAVE_PCI_CONF_HOOK 115symbol (without a value), and a machine-dependent function 116.Fn pci_conf_hook 117(declared in the same header) 118must be defined. The prototype for this function is 119.Pp 120.Fn "int pci_conf_hook" "pci_chipset_tag_t pc" "int bus" \ 121 "int device" "int function" "pcireg_t id" 122.Pp 123In this function, 124.Fa bus , 125.Fa device , 126and 127.Fa function 128uniquely identify the item being configured; 129in addition to this, the value of the device's PCI identification 130register is passed in 131.Fa id . 132For each device 133.Fn pci_conf_hook 134can then decide upon the amount of configuration to be performed by 135returning a bitwise inclusive-or of the following flags: 136.Bl -tag -width PCI_CONF_ENABLE_MEM -offset indent 137.It Dv PCI_CONF_MAP_IO 138Configure Base Address Registers that map I/O space 139.It Dv PCI_CONF_MAP_MEM 140Configure Base Address Registers that map memory space 141.It Dv PCI_CONF_MAP_ROM 142Configure Expansion ROM Base Address register 143.It Dv PCI_CONF_ENABLE_IO 144Enable I/O space accesses 145.It Dv PCI_CONF_ENABLE_MEM 146Enable memory space accesses 147.It Dv PCI_CONF_ENABLE_BM 148Enable bus mastering 149.El 150.Pp 151In addition, 152.Dv PCI_CONF_ALL 153specifies all of the above. 154.Pp 155One of the functions of 156.Fn pci_configure_bus 157is to configure interrupt 158.Dq line 159information. This must be done on a machine-dependent basis, so a 160machine-dependent function 161.Fn pci_conf_interrupt 162must be defined. The prototype for this function is 163.Pp 164.Fn "void pci_conf_interrupt" "pci_chipset_tag_t pc" "int bus" \ 165 "int device" "int function" "int swiz" "int *iline" 166.Pp 167In this function, 168.Fa bus , 169.Fa device , 170and 171.Fa function , 172uniquely identify the item being configured. The 173.Fa swiz 174argument is a 175.Dq swizzle , 176a sum of the device numbers of the primary interface of the bridges between 177the host bridge and the current device. The function is responsible for 178setting the value of 179.Fa iline . 180See chapter 9 of the 181.Dq PCI-to-PCI Bridge Architecture Specification 182for more information on swizzling (also known as interrupt routing). 183.Sh RETURN VALUES 184If successful 185.Fn pci_configure_bus 186returns 0. A non-zero return value means that the bus was not completely 187configured for some reason. A description of the failure will be displayed 188on the console. 189.Sh ENVIRONMENT 190The 191.Fn pci_configure_bus 192function is only included in the kernel if the kernel is compiled with 193the 194.Dv PCI_NETBSD_CONFIGURE 195option enabled. 196.Sh EXAMPLES 197The 198.Fn pci_conf_hook 199function in the walnut implementation looks like: 200.Pp 201.Bd -literal -compact 202int 203pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 204 pcireg_t id) 205{ 206 207 if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && 208 PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) || 209 (PCI_VENDOR(id) == PCI_VENDOR_INTEL && 210 PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) { 211 /* Don't configure the bridge and PCI probe. */ 212 return 0; 213 } 214 return (PCI_CONF_ALL & ~PCI_CONF_MAP_ROM); 215} 216.Ed 217.Pp 218The 219.Fn pci_conf_interrupt 220function in the sandpoint implementation looks like: 221.Pp 222.Bd -literal -compact 223void 224pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 225 int swiz, int *iline) 226{ 227 if (bus == 0) { 228 *iline = dev; 229 } else { 230 *iline = 13 + ((swiz + dev + 3) \*[Am] 3); 231 } 232} 233.Ed 234.Pp 235The BeBox has nearly 1GB of PCI I/O memory starting at processor address 2360x81000000 (PCI I/O address 0x01000000), and nearly 1GB of PCI memory 237starting at 0xC0000000 (PCI memory address 0x00000000). 238The 239.Fn pci_configure_bus 240function might be called as follows: 241.Pp 242.Bd -literal -compact 243 struct extent *ioext, *memext; 244 ... 245 ioext = extent_create("pciio", 0x01000000, 0x0fffffff, M_DEVBUF, 246 NULL, 0, EX_NOWAIT); 247 memext = extent_create("pcimem", 0x00000000, 0x0fffffff, M_DEVBUF, 248 NULL, 0, EX_NOWAIT); 249 ... 250 pci_configure_bus(0, ioext, memext, NULL); 251 ... 252 extent_destroy(ioext); 253 extent_destroy(memext); 254 ... 255.Ed 256.Pp 257Note that this must be called before the PCI bus is attached during 258autoconfiguration. 259.Sh SEE ALSO 260.Xr pci 4 , 261.Xr extent 9 262.Sh HISTORY 263.Fn pci_configure_bus 264was added in 265.Nx 1.6 . 266