1.\" $NetBSD: tc.9,v 1.11 2010/12/02 12:54:13 wiz Exp $ 2.\" 3.\" Copyright (c) 2001 The NetBSD Foundation, Inc. 4.\" All rights reserved. 5.\" 6.\" This code is derived from software contributed to The NetBSD Foundation 7.\" by Gregory McGarry. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28.\" POSSIBILITY OF SUCH DAMAGE. 29.\" 30.Dd October 7, 2001 31.Dt TC 9 32.Os 33.Sh NAME 34.Nm TC , 35.Nm tc_intr_establish , 36.Nm tc_intr_disestablish , 37.Nm tc_intr_evcnt . 38.Nm tc_mb , 39.Nm tc_wmb , 40.Nm tc_syncbus , 41.Nm tc_badaddr , 42.Nm TC_DENSE_TO_SPARSE , 43.Nm TC_PHYS_TO_UNCACHED 44.Nd TURBOchannel bus 45.Sh SYNOPSIS 46.In machine/bus.h 47.In dev/tc/tcvar.h 48.In dev/tc/tcdevs.h 49.Ft void 50.Fn tc_intr_establish "struct device *dev" "void *cookie" \ 51"int level" "int (*handler)(void *)" "void *arg" 52.Ft void 53.Fn tc_intr_disestablish "struct device *dev" "void *cookie" 54.Ft const struct evcnt * 55.Fn tc_intr_evcnt "struct device *dev" "void *cookie" 56.Ft void 57.Fn tc_mb "" 58.Ft void 59.Fn tc_wmb "" 60.Ft void 61.Fn tc_syncbus "" 62.Ft int 63.Fn tc_badaddr "tc_addr_t tcaddr" 64.Ft tc_addr_t 65.Fn TC_DENSE_TO_SPARSE "tc_addr_t addr" 66.Ft tc_addr_t 67.Fn TC_PHYS_TO_UNCACHED "tc_addr_t addr" 68.Sh DESCRIPTION 69The 70.Nm 71device provides support for the DEC TURBOchannel bus found on all DEC 72TURBOchannel machines with MIPS (DECstation 5000 series, excluding the 735000/200) and Alpha (3000-series) systems. 74TURBOchannel is a 32-bit wide synchronous DMA-capable bus, running 75at 25 MHz on higher-end machines and at 12.5 MHz on lower-end machines. 76.Sh DATA TYPES 77Drivers for devices attached to the TURBOchannel bus will make use of 78the following data types: 79.Bl -tag -width compact 80.It Fa struct tc_attach_args 81A structure use to inform the driver of TURBOchannel bus properties. 82It contains the following members: 83.Bd -literal 84 bus_space_tag_t ta_memt; 85 bus_dma_tag_t ta_dmat; 86 char ta_modname[TC_ROM_LLEN+1]; 87 u_int ta_slot; 88 tc_offset_t ta_offset; 89 tc_addr_t ta_addr; 90 void *ta_cookie; 91 u_int ta_busspeed; 92.Ed 93.Pp 94The 95.Em ta_busspeed 96member specifies the TURBOchannel bus speed and is useful for 97time-related functions. 98Values values are 99.Em TC_SPEED_12_5_MHZ 100for the 12.5 MHz bus and 101.Em TC_SPEED_25_MHZ 102for the 50 MHz bus. 103.El 104.Sh FUNCTIONS 105.Bl -tag -width compact 106.It Fn tc_intr_establish "dev" "cookie" "level" "handler" "arg" 107Establish an interrupt handler with device 108.Fa dev 109for the interrupt described completely by 110.Fa cookie , 111the value passed to the driver in the 112.Em ta_cookie 113member of the 114.Em tc_attach_args 115structure. 116The priority of the interrupt is specified by 117.Fa level . 118When the interrupt occurs the function 119.Fa handler 120is called with argument 121.Fa arg . 122.It Fn tc_intr_disestablish "dev" "cookie" 123Dis-establish the interrupt handler with device 124.Fa dev 125for the interrupt described completely 126.Fa cookie . 127.It Fn tc_intr_evcnt "dev" "cookie" 128Do interrupt event counting with device 129.Fa dev 130for the event described completely by 131.Fa cookie . 132.It Fn tc_mb "" 133A read/write memory barrier. 134Any CPU-to-memory reads/writes before the barrier must complete before 135any CPU-to-memory reads/writes after it. 136.It Fn tc_wmb "" 137A write memory barrier. 138Any CPU-to-memory writes before the barrier must complete 139before any CPU-to-memory writes after it. 140.It Fn tc_syncbus "" 141Synchronise writes on the TURBOchannel bus by ensuring CPU writes are 142propagated across the TURBOchannel bus. 143.It Fn tc_badaddr "tcaddr" 144Returns non-zero if the given address 145.Fa tcaddr 146is invalid. 147.It Fn TC_DENSE_TO_SPARSE "addr" 148Convert the given physical address 149.Fa addr 150in TURBOchannel dense space to the corresponding address in 151TURBOchannel sparse space. 152.It Fn TC_PHYS_TO_UNCACHED "addr" 153Convert the given system memory physical address 154.Fa addr 155to the physical address of the corresponding region that is not 156cached. 157.El 158.Sh AUTOCONFIGURATION 159The TURBOchannel bus is a direct-connection bus. 160During autoconfiguration, the parent specifies the name of the found 161TURBOchannel module into the 162.Fa ta_modname 163member of the 164.Em tc_attach_args 165structure. 166Drivers should match on this name. 167.Sh DMA SUPPORT 168The TURBOchannel bus supports 32-bit, bidirectional DMA transfers. 169Support is provided by the standard 170.Xr bus_dma 9 171interface. 172.Sh CODE REFERENCES 173The TURBOchannel subsystem itself is implemented within the file 174.Pa sys/dev/tc/tc_subr.c . 175Machine-dependent portions can be found in 176.Pa sys/arch/\*[Lt]arch\*[Gt]/tc/tcbus.c . 177.Sh SEE ALSO 178.Xr tc 4 , 179.Xr autoconf 9 , 180.Xr bus_dma 9 , 181.Xr bus_space 9 , 182.Xr driver 9 183