xref: /netbsd/sys/arch/acorn32/podulebus/ascreg.h (revision 6550d01e)
1 /* $NetBSD: ascreg.h,v 1.6 2006/08/20 19:26:52 bjh21 Exp $ */
2 
3 /*
4  * Copyright (c) 1982, 1990 The Regents of the University of California.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of the University nor the names of its contributors
16  *    may be used to endorse or promote products derived from this software
17  *    without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  *	from:ahscreg.h,v 1.2 1994/10/26 02:02:46
32  */
33 
34 /*
35  * Copyright (c) 1996 Mark Brinicombe
36  * Copyright (c) 1994 Christian E. Hopps
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions
40  * are met:
41  * 1. Redistributions of source code must retain the above copyright
42  *    notice, this list of conditions and the following disclaimer.
43  * 2. Redistributions in binary form must reproduce the above copyright
44  *    notice, this list of conditions and the following disclaimer in the
45  *    documentation and/or other materials provided with the distribution.
46  * 3. All advertising materials mentioning features or use of this software
47  *    must display the following acknowledgement:
48  *	This product includes software developed by the University of
49  *	California, Berkeley and its contributors.
50  * 4. Neither the name of the University nor the names of its contributors
51  *    may be used to endorse or promote products derived from this software
52  *    without specific prior written permission.
53  *
54  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
55  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
57  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
58  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
59  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
60  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
61  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
62  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
63  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64  * SUCH DAMAGE.
65  *
66  *	from:ahscreg.h,v 1.2 1994/10/26 02:02:46
67  */
68 
69 #ifndef _ASCREG_H_
70 #define _ASCREG_H_
71 
72 #define v_char		volatile char
73 #define	v_int		volatile int
74 #define vu_char		volatile u_char
75 #define vu_short	volatile u_short
76 #define vu_int		volatile u_int
77 
78 /* Addresses relative to podule base */
79 
80 #define ASC_INTSTATUS	0x2000
81 #define ASC_CLRINT	0x2000
82 #define ASC_PAGEREG	0x3000
83 
84 /* Addresses relative to module base */
85 
86 #define ASC_DMAC		0x3000
87 #define ASC_SBIC		0x2000
88 #define ASC_SRAM		0x0000
89 
90 #define ASC_SBIC_SPACE		8
91 
92 #define ASC_SRAM_BLKSIZE	0x1000
93 
94 #define IS_IRQREQ		0x01
95 #define IS_DMAC_IRQ		0x02
96 #define IS_SBIC_IRQ		0x08
97 
98 #if 0
99 
100 /* SBIC status codes */
101 
102 #define SBIC_ResetOk	0x00
103 #define SBIC_ResetAFOk	0x01
104 
105 /* DMAC constants */
106 
107 #define DMAC_Bits		0x01
108 #define DMAC_Ctrl1		0x60
109 #define DMAC_Ctrl2		0x01
110 #define DMAC_CLEAR_MASK		0x0E
111 #define DMAC_SET_MASK		0x0F
112 #define DMAC_DMA_RD_MODE	0x04
113 #define DMAC_DMA_WR_MODE	0x08
114 
115 /* DMAC registers */
116 
117 #define DMAC_INITIALISE	0x0000	/* WO ---- ---- ---- ---- ---- ----  16B  RES */
118 #define DMAC_CHANNEL	0x0200	/* R  ---- ---- ---- BASE SEL3 SEL2 SEL1 SEL0 */
119 				/* W  ---- ---- ---- ---- ---- BASE *SELECT** */
120 #define DMAC_TXCNTLO	0x0004	/* RW   C7   C6   C5   C4   C3   C2   C1   C0 */
121 #define DMAC_TXCNTHI	0x0204	/* RW  C15  C14  C13  C12  C11  C10   C9   C8 */
122 #define DMAC_TXADRLO	0x0008	/* RW   A7   A6   A5   A4   A3   A2   A1   A0 */
123 #define DMAC_TXADRMD	0x0208	/* RW  A15  A14  A13  A12  A11  A10   A9   A8 */
124 #define DMAC_TXADRHI	0x000C	/* RW  A23  A22  A21  A20  A19  A18  A17  A16 */
125 #define DMAC_DEVCON1	0x0010	/* RW  AKL  RQL  EXW  ROT  CMP DDMA AHLD  MTM */
126 #define DMAC_DEVCON2	0x0210	/* RW ---- ---- ---- ---- ---- ----  WEV BHLD */
127 #define DMAC_MODECON	0x0014	/* RW **TMODE** ADIR AUTI **TDIR*** ---- WORD */
128 #define DMAC_STATUS	0x0214	/* RO  RQ3  RQ2  RQ1  RQ0  TC3  TC2  TC1  TC0 */
129 #if 0
130 templo  = dmac + 0x0018;/*    RO   T7   T6   T5   T4   T3   T2   T1   T0 */
131 temphi  = dmac + 0x0218;/*    RO  T15  T14  T13  T12  T11  T10   T9   T8 */
132 #endif
133 #define DMAC_REQREG	0x001C	/* RW ---- ---- ---- ---- SRQ3 SRQ2 SRQ1 SRQ0 */
134 #define DMAC_MASKREG	0x021C	/* RW ---- ---- ---- ----   M3   M2   M1   M0 */
135 
136 #endif
137 #endif /* _ASCREG_H_ */
138