1 /* $NetBSD: algor_p4032reg.h,v 1.2 2001/06/22 05:57:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Memory map and register definitions for the Algorithmics P-4032. 41 */ 42 43 #define P4032_MEMORY 0x00000000UL /* onbord DRAM memory */ 44 /* 256 MB */ 45 #define P4032_ISAMEM 0x10000000UL /* ISA window of PCI memory */ 46 /* 8MB */ 47 #define P4032_PCIMEM 0x11000000UL /* PCI memory window */ 48 /* 112MB */ 49 #define P4032_PCIIO 0x1ed00000UL /* PCI I/O window */ 50 /* 1MB */ 51 #define P4032_PCICFG 0x1ee00000UL /* PCI config space */ 52 /* 1MB */ 53 #define P4032_V962PBC 0x1ef00000UL /* V962PBC PCI controller */ 54 /* 64KB */ 55 #define P4032_CFGBOOT_W 0x1fc00000UL /* configured bootstrap (W) */ 56 /* 1MB or 512KB */ 57 #define P4032_SOCKET_W 0x1fd00000UL /* socket EPROM (W) */ 58 /* 512KB */ 59 #define P4032_FLASH_W 0x1fe00000UL /* flash (W) */ 60 /* 1MB */ 61 #define P4032_RTC 0x1ff00000UL /* RTC */ 62 #define P4032_PCKBC 0x1ff10000UL /* keyboard controller */ 63 #define P4032_LED 0x1ff20010UL /* LED display (4reg) */ 64 #define P4032_LCD 0x1ff30000UL /* LCD display */ 65 #define P4032_GPIO 0x1ff40000UL /* General purpose I/O */ 66 #define P4032_FDC 0x1ff807c0UL /* floppy controller */ 67 #define P4032_GAME 0x1ff80800UL /* game port (unused) */ 68 #define P4032_COM2 0x1ff80be0UL /* COM2 */ 69 #define P4032_LPT 0x1ff80de0UL /* parallel port */ 70 #define P4032_COM1 0x1ff80fe0UL /* COM1 */ 71 #define P4032_IRR0 0x1ff90000UL /* interrupt req. 0 */ 72 #define P4032_IRR1 0x1ff90004UL /* interrupt req. 1 */ 73 #define P4032_IRR2 0x1ff90008UL /* interrupt req. 2 */ 74 #define P4032_XBAR0 0x1ff9000cUL /* interrupt crossbar 0 */ 75 #define P4032_XBAR1 0x1ff90010UL /* interrupt crossbar 1 */ 76 #define P4032_XBAR2 0x1ff90014UL /* interrupt crossbar 2 */ 77 #define P4032_VERSION 0x1ff9001cUL /* board version */ 78 #define P4032_FLOPPY_DMA_ACK 0x1ffa0fd4UL /* floppy "DMA ACK" */ 79 #define P4032_BOARD_CONFIG 0x1ffb0000UL /* board configuration */ 80 #define P4032_DRAM_CONFIG 0x1ffc0000UL /* DRAM configuration */ 81 #define P4032_OPTION 0x1ffd0000UL /* option register */ 82 #define P4032_PCIMEM_HI 0x20000000UL /* PCI memory high window */ 83 /* 3.5GB */ 84 85 /* IRR0 (8-bit devices) */ 86 #define IRR0_PCICTLR 0x01 /* PCI controller */ 87 #define IRR0_FLOPPY 0x02 /* floppy controller */ 88 #define IRR0_PCKBC 0x04 /* keyboard controller */ 89 #define IRR0_COM1 0x08 /* COM1 */ 90 #define IRR0_COM2 0x10 /* COM2 */ 91 #define IRR0_LPT 0x20 /* centronics */ 92 #define IRR0_GPIO 0x40 /* general purpose I/O */ 93 #define IRR0_RTC 0x80 /* real-time clock */ 94 95 /* IRR1 (error/clear) */ 96 #define IRR1_DEBUG 0x01 /* debug switch */ 97 #define IRR1_POWERFAIL 0x02 /* power fail */ 98 #define IRR1_BUSERR 0x04 /* bus error */ 99 #define IRR1_LPT_ACK 0x20 /* centronics interrupt ack. */ 100 101 /* IRR2 (PCI) */ 102 #define IRR2_FLOPPY_DMA 0x08 /* floppy DMA request */ 103 #define IRR2_PCIIRQ0 0x10 /* PCIIRQ 0 */ 104 #define IRR2_PCIIRQ1 0x20 /* PCIIRQ 1 */ 105 #define IRR2_PCIIRQ2 0x40 /* PCIIRQ 2 */ 106 #define IRR2_PCIIRQ3 0x80 /* PCIIRQ 3 */ 107 108 /* 109 * The Algorithmics PMON initializes two DMA windows: 110 * 111 * PCI 8000.0000 -> Phys 0000.0000 (256MB) 112 * PCI c000.0000 -> Phys 0000.0000 (256MB) 113 * 114 * The latter has prefetching enabled, the former disabled, on 115 * V962 < rev B2, which have broken DMA FIFOs. The latter is 116 * given to the on-board Ethernet. 117 */ 118 #define P4032_DMA_PCI_PCIBASE 0x80000000UL 119 #define P4032_DMA_PCI_PF_PCIBASE 0xc0000000UL 120 #define P4032_DMA_PCI_PHYSBASE 0x00000000UL 121 #define P4032_DMA_PCI_SIZE (256 * 1024 * 1024) 122