xref: /netbsd/sys/arch/alpha/include/pte.h (revision c4a72b64)
1 /* $NetBSD: pte.h,v 1.27 2002/10/14 05:11:23 chs Exp $ */
2 
3 /*-
4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by the NetBSD
22  *	Foundation, Inc. and its contributors.
23  * 4. Neither the name of The NetBSD Foundation nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*
41  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
42  * All rights reserved.
43  *
44  * Author: Chris G. Demetriou
45  *
46  * Permission to use, copy, modify and distribute this software and
47  * its documentation is hereby granted, provided that both the copyright
48  * notice and this permission notice appear in all copies of the
49  * software, derivative works or modified versions, and any portions
50  * thereof, and that both notices appear in supporting documentation.
51  *
52  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
53  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
54  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
55  *
56  * Carnegie Mellon requests users of this software to return to
57  *
58  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
59  *  School of Computer Science
60  *  Carnegie Mellon University
61  *  Pittsburgh PA 15213-3890
62  *
63  * any improvements or extensions that they make and grant Carnegie the
64  * rights to redistribute these changes.
65  */
66 
67 #ifndef _ALPHA_PTE_H_
68 #define	_ALPHA_PTE_H_
69 
70 /*
71  * Alpha page table entry.
72  * Things which are in the VMS PALcode but not in the OSF PALcode
73  * are marked with "(VMS)".
74  *
75  * This information derived from pp. (II) 3-3 - (II) 3-6 and
76  * (III) 3-3 - (III) 3-5 of the "Alpha Architecture Reference Manual" by
77  * Richard L. Sites.
78  */
79 
80 /*
81  * Alpha Page Table Entry
82  */
83 
84 #include <machine/alpha_cpu.h>
85 
86 typedef	alpha_pt_entry_t	pt_entry_t;
87 
88 #define	PTESHIFT	3			/* pte size == 1 << PTESHIFT */
89 
90 #define	PG_V		ALPHA_PTE_VALID
91 #define	PG_NV		0
92 #define	PG_FOR		ALPHA_PTE_FAULT_ON_READ
93 #define	PG_FOW		ALPHA_PTE_FAULT_ON_WRITE
94 #define	PG_FOE		ALPHA_PTE_FAULT_ON_EXECUTE
95 #define	PG_ASM		ALPHA_PTE_ASM
96 #define	PG_GH		ALPHA_PTE_GRANULARITY
97 #define	PG_KRE		ALPHA_PTE_KR
98 #define	PG_URE		ALPHA_PTE_UR
99 #define	PG_KWE		ALPHA_PTE_KW
100 #define	PG_UWE		ALPHA_PTE_UW
101 #define	PG_PROT		ALPHA_PTE_PROT
102 #define	PG_RSVD		0x000000000000cc80	/* Reserved for hardware */
103 #define	PG_WIRED	0x0000000000010000	/* Wired. [SOFTWARE] */
104 #define	PG_PVLIST	0x0000000000020000	/* on pv list [SOFTWARE] */
105 #define	PG_EXEC		0x0000000000040000	/* execute perms [SOFTWARE] */
106 #define	PG_FRAME	ALPHA_PTE_RAME
107 #define	PG_SHIFT	32
108 #define	PG_PFNUM(x)	ALPHA_PTE_TO_PFN(x)
109 
110 /*
111  * These are the PALcode PTE bits that we care about when checking to see
112  * if a PTE has changed in such a way as to require a TBI.
113  */
114 #define	PG_PALCODE(x)	((x) & ALPHA_PTE_PALCODE)
115 
116 #if defined(_KERNEL) || defined(__KVM_ALPHA_PRIVATE)
117 #define	NPTEPG_SHIFT	(PAGE_SHIFT - PTESHIFT)
118 #define	NPTEPG		(1L << NPTEPG_SHIFT)
119 
120 #define	PTEMASK		(NPTEPG - 1)
121 
122 #define	l3pte_index(va)	\
123 	(((vaddr_t)(va) >> PAGE_SHIFT) & PTEMASK)
124 
125 #define	l2pte_index(va)	\
126 	(((vaddr_t)(va) >> (PAGE_SHIFT + NPTEPG_SHIFT)) & PTEMASK)
127 
128 #define	l1pte_index(va) \
129 	(((vaddr_t)(va) >> (PAGE_SHIFT + 2 * NPTEPG_SHIFT)) & PTEMASK)
130 
131 #define	VPT_INDEX(va)	\
132 	(((vaddr_t)(va) >> PAGE_SHIFT) & ((1 << 3 * NPTEPG_SHIFT) - 1))
133 
134 /* Space mapped by one level 1 PTE */
135 #define	ALPHA_L1SEG_SIZE	(1L << ((2 * NPTEPG_SHIFT) + PAGE_SHIFT))
136 
137 /* Space mapped by one level 2 PTE */
138 #define	ALPHA_L2SEG_SIZE	(1L << (NPTEPG_SHIFT + PAGE_SHIFT))
139 
140 #define	alpha_trunc_l1seg(x)	(((u_long)(x)) & ~(ALPHA_L1SEG_SIZE-1))
141 #define	alpha_trunc_l2seg(x)	(((u_long)(x)) & ~(ALPHA_L2SEG_SIZE-1))
142 #endif /* _KERNEL || __KVM_ALPHA_PRIVATE */
143 
144 #ifdef _KERNEL
145 extern	pt_entry_t *kernel_lev1map;	/* kernel level 1 page table */
146 #endif /* _KERNEL */
147 
148 #endif /* ! _ALPHA_PTE_H_ */
149