xref: /netbsd/sys/arch/alpha/include/tc_machdep.h (revision bf9ec67e)
1 /* $NetBSD: tc_machdep.h,v 1.4 2000/06/01 00:04:50 cgd Exp $ */
2 
3 /*
4  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
5  * All rights reserved.
6  *
7  * Author: Chris G. Demetriou
8  *
9  * Permission to use, copy, modify and distribute this software and
10  * its documentation is hereby granted, provided that both the copyright
11  * notice and this permission notice appear in all copies of the
12  * software, derivative works or modified versions, and any portions
13  * thereof, and that both notices appear in supporting documentation.
14  *
15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18  *
19  * Carnegie Mellon requests users of this software to return to
20  *
21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22  *  School of Computer Science
23  *  Carnegie Mellon University
24  *  Pittsburgh PA 15213-3890
25  *
26  * any improvements or extensions that they make and grant Carnegie the
27  * rights to redistribute these changes.
28  */
29 
30 /*
31  * Machine-specific definitions for TurboChannel support.
32  *
33  * This file must typedef the following types:
34  *
35  *	tc_addr_t	TurboChannel bus address
36  *	tc_offset_t	TurboChannel bus address difference (offset)
37  *
38  * This file must prototype or define the following functions
39  * or macros (one or more of which may be no-ops):
40  *
41  *	tc_mb()		read/write memory barrier (any CPU<->memory
42  *			reads/writes before must complete before any
43  *			CPU<->memory reads/writes after).
44  *	tc_wmb()	write memory barrier (any CPU<->memory writes
45  *			before must complete before any CPU<->memory
46  *			writes after).
47  *	tc_syncbus()	sync TC bus; make sure CPU writes are
48  *			propagated across the TurboChannel bus.
49  *	tc_badaddr()	return non-zero if the given address is invalid.
50  *	TC_DENSE_TO_SPARSE()
51  *			convert the given physical address in
52  *			TurboChannel dense space to the corresponding
53  *			address in TurboChannel sparse space.
54  *	TC_PHYS_TO_UNCACHED()
55  *			convert the given system memory physical address
56  *			to the physical address of the corresponding
57  *			region that is not cached.
58  */
59 
60 typedef u_int64_t	tc_addr_t;
61 typedef int32_t		tc_offset_t;
62 
63 #define	tc_mb()		alpha_mb()
64 #define	tc_wmb()	alpha_wmb()
65 
66 /*
67  * A junk address to read from, to make sure writes are complete.  See
68  * System Programmer's Manual, section 9.3 (p. 9-4), and sacrifice a
69  * chicken.
70  */
71 #define	tc_syncbus()							\
72     do {								\
73 	volatile u_int32_t no_optimize;					\
74 	no_optimize =	 						\
75 	    *(volatile u_int32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \
76     } while (0)
77 
78 #define	tc_badaddr(tcaddr)						\
79     badaddr((void *)(tcaddr), sizeof (u_int32_t))
80 
81 #define	TC_SPACE_IND		0xffffffffe0000003
82 #define	TC_SPACE_DENSE		0x0000000000000000
83 #define TC_SPACE_DENSE_OFFSET	0x0000000007fffffc
84 #define	TC_SPACE_SPARSE		0x0000000010000000
85 #define	TC_SPACE_SPARSE_OFFSET	0x000000000ffffff8
86 
87 #define	TC_DENSE_TO_SPARSE(addr)					\
88     (((addr) & TC_SPACE_IND) | TC_SPACE_SPARSE |			\
89 	(((addr) & TC_SPACE_DENSE_OFFSET) << 1))
90 
91 #define	TC_PHYS_TO_UNCACHED(addr)					\
92     (addr)
93 
94 /*
95  * These functions are private, and may not be called by
96  * machine-independent code.
97  */
98 bus_space_tag_t tc_bus_mem_init(void *memv);
99 void tc_dma_init(void);
100 
101 /*
102  * Address of scatter/gather SRAM on the 3000/500-series.
103  *
104  * There is room for 32K entries, yielding 256M of sgva space.
105  * The page table is readable in both dense and sparse space.
106  * The page table is writable only in sparse space.
107  *
108  * In sparse space, the 32-bit PTEs are followed by 32-bits
109  * of pad.
110  */
111 #define	TC_SGSRAM_DENSE		0x0000001c2800000UL
112 #define	TC_SGSRAM_SPARSE	0x0000001d5000000UL
113