1 /* $NetBSD: apecs_bus_mem.c,v 1.10 2010/12/15 01:27:18 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(1, "$NetBSD: apecs_bus_mem.c,v 1.10 2010/12/15 01:27:18 matt Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/syslog.h> 38 #include <sys/device.h> 39 40 #include <machine/bus.h> 41 42 #include <alpha/pci/apecsreg.h> 43 #include <alpha/pci/apecsvar.h> 44 45 #define CHIP apecs 46 47 #define CHIP_EX_MALLOC_SAFE(v) (((struct apecs_config *)(v))->ac_mallocsafe) 48 #define CHIP_D_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_d_mem_ex) 49 #define CHIP_S_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_s_mem_ex) 50 51 /* Dense region 1 */ 52 #define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL 53 #define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL 54 #define CHIP_D_MEM_W1_SYS_START(v) APECS_PCI_DENSE 55 #define CHIP_D_MEM_W1_SYS_END(v) (APECS_PCI_DENSE + 0xffffffffUL) 56 57 /* Sparse region 1 */ 58 #define CHIP_S_MEM_W1_BUS_START(v) 0x00000000UL 59 #define CHIP_S_MEM_W1_BUS_END(v) 0x00ffffffUL 60 #define CHIP_S_MEM_W1_SYS_START(v) APECS_PCI_SPARSE 61 #define CHIP_S_MEM_W1_SYS_END(v) \ 62 (APECS_PCI_SPARSE + (0x01000000UL << 5) - 1) 63 64 /* Sparse region 2 */ 65 #define CHIP_S_MEM_W2_BUS_START(v) \ 66 ((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \ 67 0x01000000UL) 68 #define CHIP_S_MEM_W2_BUS_END(v) \ 69 ((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \ 70 0x07ffffffUL) 71 #define CHIP_S_MEM_W2_SYS_START(v) \ 72 (APECS_PCI_SPARSE + (0x01000000UL << 5)) 73 #define CHIP_S_MEM_W2_SYS_END(v) \ 74 (APECS_PCI_SPARSE + (0x08000000UL << 5) - 1) 75 76 #include <alpha/pci/pci_swiz_bus_mem_chipdep.c> 77