1*b627dca8Smatt /* $NetBSD: apecsreg.h,v 1.8 2012/02/06 02:14:14 matt Exp $ */ 2549f126fScgd 3549f126fScgd /* 460d53ca3Scgd * Copyright (c) 1995 Carnegie-Mellon University. 5549f126fScgd * All rights reserved. 6549f126fScgd * 7549f126fScgd * Author: Chris G. Demetriou 8549f126fScgd * 9549f126fScgd * Permission to use, copy, modify and distribute this software and 10549f126fScgd * its documentation is hereby granted, provided that both the copyright 11549f126fScgd * notice and this permission notice appear in all copies of the 12549f126fScgd * software, derivative works or modified versions, and any portions 13549f126fScgd * thereof, and that both notices appear in supporting documentation. 14549f126fScgd * 15549f126fScgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16549f126fScgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17549f126fScgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18549f126fScgd * 19549f126fScgd * Carnegie Mellon requests users of this software to return to 20549f126fScgd * 21549f126fScgd * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22549f126fScgd * School of Computer Science 23549f126fScgd * Carnegie Mellon University 24549f126fScgd * Pittsburgh PA 15213-3890 25549f126fScgd * 26549f126fScgd * any improvements or extensions that they make and grant Carnegie the 27549f126fScgd * rights to redistribute these changes. 28549f126fScgd */ 29549f126fScgd 30549f126fScgd /* 31549f126fScgd * APECS Chipset registers and constants. 32549f126fScgd * 33549f126fScgd * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data 34549f126fScgd * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38. 35549f126fScgd */ 36549f126fScgd 37079e0c6bScgd #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) 38deb4082fScgd 39549f126fScgd /* 40549f126fScgd * Base addresses 41549f126fScgd */ 42549f126fScgd #define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */ 43549f126fScgd #define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */ 44549f126fScgd #define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */ 45549f126fScgd #define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ 46549f126fScgd #define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ 47549f126fScgd #define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ 48549f126fScgd #define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */ 49549f126fScgd 50549f126fScgd 51549f126fScgd /* 52549f126fScgd * 21071-CA Registers 53549f126fScgd */ 54549f126fScgd 55549f126fScgd /* 56549f126fScgd * 21071-CA General Registers 57549f126fScgd */ 58549f126fScgd #define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */ 59549f126fScgd #define COMANCHE_GCR_RSVD 0xc009 60549f126fScgd #define COMANCHE_GCR_SYSARB 0x0006 61549f126fScgd #define COMANCHE_GCR_WIDEMEM 0x0010 62549f126fScgd #define COMANCHE_GCR_BC_EN 0x0020 63549f126fScgd #define COMANCHE_GCR_BC_NOALLOC 0x0040 64549f126fScgd #define COMANCHE_GCR_BC_LONGWR 0x0080 65549f126fScgd #define COMANCHE_GCR_BC_IGNTAG 0x0100 66549f126fScgd #define COMANCHE_GCR_BC_FRCTAG 0x0200 67549f126fScgd #define COMANCHE_GCR_BC_FRCD 0x0400 68549f126fScgd #define COMANCHE_GCR_BC_FRCV 0x0800 69549f126fScgd #define COMANCHE_GCR_BC_FRCP 0x1000 70549f126fScgd #define COMANCHE_GCR_BC_BADAP 0x2000 71549f126fScgd 72549f126fScgd #define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */ 73549f126fScgd 74549f126fScgd #define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */ 75549f126fScgd #define COMANCHE_ED_LOSTERR 0x0001 76549f126fScgd #define COMANCHE_ED_BC_TAPERR 0x0002 77549f126fScgd #define COMANCHE_ED_BC_TCPERR 0x0004 78549f126fScgd #define COMANCHE_ED_NXMERR 0x0008 79549f126fScgd #define COMANCHE_ED_DMACAUSE 0x0010 80549f126fScgd #define COMANCHE_ED_VICCAUSE 0x0020 81549f126fScgd #define COMANCHE_ED_CREQCAUSE 0x01c0 82549f126fScgd #define COMANCHE_ED_RSVD 0x1e00 83549f126fScgd #define COMANCHE_ED_PASS2 0x2000 84549f126fScgd #define COMANCHE_ED_IDXLLOCK 0x4000 85549f126fScgd #define COMANCHE_ED_WRPEND 0x8000 86549f126fScgd 87549f126fScgd #define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */ 88549f126fScgd #define COMANCHE_TAGENB_RSVD 0x0001 89549f126fScgd 90549f126fScgd #define COMANCHE_TAGENB_C_4G 0x0000 91549f126fScgd #define COMANCHE_TAGENB_C_2G 0x8000 92549f126fScgd #define COMANCHE_TAGENB_C_1G 0xc000 93549f126fScgd #define COMANCHE_TAGENB_C_512M 0xe000 94549f126fScgd #define COMANCHE_TAGENB_C_256M 0xf000 95549f126fScgd #define COMANCHE_TAGENB_C_128M 0xf800 96549f126fScgd #define COMANCHE_TAGENB_C_64M 0xfc00 97549f126fScgd #define COMANCHE_TAGENB_C_32M 0xfe00 98549f126fScgd #define COMANCHE_TAGENB_C_16M 0xff00 99549f126fScgd #define COMANCHE_TAGENB_C_8M 0xff80 100549f126fScgd #define COMANCHE_TAGENB_C_4M 0xffc0 101549f126fScgd #define COMANCHE_TAGENB_C_2M 0xffe0 102549f126fScgd #define COMANCHE_TAGENB_C_1M 0xfff0 103549f126fScgd #define COMANCHE_TAGENB_C_512K 0xfff8 104549f126fScgd #define COMANCHE_TAGENB_C_256K 0xfffc 105549f126fScgd #define COMANCHE_TAGENB_C_128K 0xfffe 106549f126fScgd 107549f126fScgd #define COMANCHE_TAGENB_M_4G 0xffff 108549f126fScgd #define COMANCHE_TAGENB_M_2G 0x7fff 109549f126fScgd #define COMANCHE_TAGENB_M_1G 0x3fff 110549f126fScgd #define COMANCHE_TAGENB_M_512M 0x1fff 111549f126fScgd #define COMANCHE_TAGENB_M_256M 0x0fff 112549f126fScgd #define COMANCHE_TAGENB_M_128M 0x07ff 113549f126fScgd #define COMANCHE_TAGENB_M_64M 0x03ff 114549f126fScgd #define COMANCHE_TAGENB_M_32M 0x01ff 115549f126fScgd #define COMANCHE_TAGENB_M_16M 0x00ff 116549f126fScgd #define COMANCHE_TAGENB_M_8M 0x007f 117549f126fScgd #define COMANCHE_TAGENB_M_4M 0x003f 118549f126fScgd #define COMANCHE_TAGENB_M_2M 0x001f 119549f126fScgd #define COMANCHE_TAGENB_M_1M 0x000e 120549f126fScgd #define COMANCHE_TAGENB_M_512K 0x0006 121549f126fScgd #define COMANCHE_TAGENB_M_256K 0x0002 122549f126fScgd #define COMANCHE_TAGENB_M_128K 0x0000 123549f126fScgd 124549f126fScgd #define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */ 125549f126fScgd 126549f126fScgd #define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */ 127549f126fScgd #define COMANCHE_ERR_HI_RSVD 0xe000 128549f126fScgd 129549f126fScgd #define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */ 130549f126fScgd 131549f126fScgd #define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */ 132549f126fScgd #define COMANCHE_LOCK_HI_RSVD 0xe000 133549f126fScgd 134549f126fScgd /* 135549f126fScgd * 21071-CA Memory Registers 136549f126fScgd */ 137549f126fScgd #define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */ 138549f126fScgd #define COMANCHE_LOCK_HI_RSVD 0xe000 139549f126fScgd 140549f126fScgd #define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */ 141549f126fScgd 142549f126fScgd #define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */ 143549f126fScgd #define COMANCHE_VFP_COL 0x001f 144549f126fScgd #define COMANCHE_VFP_ROW 0x3fe0 145549f126fScgd #define COMANCHE_VFP_SUBBANK 0x4000 146549f126fScgd #define COMANCHE_VFP_RSVD 0x8000 147549f126fScgd 148549f126fScgd #define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */ 149549f126fScgd 150549f126fScgd #define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */ 151549f126fScgd 152549f126fScgd /* 153549f126fScgd * 21071-CA Memory banks' Base Address Register format 154549f126fScgd */ 155549f126fScgd #define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */ 156549f126fScgd #define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */ 157549f126fScgd #define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */ 158549f126fScgd #define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */ 159549f126fScgd #define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */ 160549f126fScgd #define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */ 161549f126fScgd #define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */ 162549f126fScgd #define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */ 163549f126fScgd #define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */ 164549f126fScgd #define COMANCHE_BAR_RSVD 0x001f 165549f126fScgd 166549f126fScgd /* 167549f126fScgd * 21071-CA Memory banks' Configuration Register format 168549f126fScgd */ 169549f126fScgd #define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */ 170549f126fScgd #define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */ 171549f126fScgd #define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */ 172549f126fScgd #define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */ 173549f126fScgd #define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */ 174549f126fScgd #define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */ 175549f126fScgd #define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */ 176549f126fScgd #define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */ 177549f126fScgd #define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */ 178549f126fScgd #define COMANCHE_CR_VALID 0x0001 179549f126fScgd #define COMANCHE_CR_SIZE 0x001e 180549f126fScgd #define COMANCHE_CR_SUBENA 0x0020 181549f126fScgd #define COMANCHE_CR_COLSEL 0x01c0 182549f126fScgd #define COMANCHE_CR_S0_RSVD 0xfe00 183549f126fScgd #define COMANCHE_CR_S8_CHECK 0x0200 184549f126fScgd #define COMANCHE_CR_S8_RSVD 0xfc00 185549f126fScgd 186549f126fScgd /* 187549f126fScgd * 21071-CA Memory banks' Timing Register A format 188549f126fScgd */ 189549f126fScgd #define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */ 190549f126fScgd #define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */ 191549f126fScgd #define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */ 192549f126fScgd #define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */ 193549f126fScgd #define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */ 194549f126fScgd #define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */ 195549f126fScgd #define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */ 196549f126fScgd #define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */ 197549f126fScgd #define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */ 198549f126fScgd #define COMANCHE_TRA_ROWSETUP 0x0003 199549f126fScgd #define COMANCHE_TRA_ROWHOLD 0x000c 200549f126fScgd #define COMANCHE_TRA_COLSETUP 0x0070 201549f126fScgd #define COMANCHE_TRA_COLHOLD 0x0180 202549f126fScgd #define COMANCHE_TRA_RDLYROW 0x0e00 203549f126fScgd #define COMANCHE_TRA_RDLYCOL 0x7000 204549f126fScgd #define COMANCHE_TRA_RSVD 0x8000 205549f126fScgd 206549f126fScgd /* 207549f126fScgd * 21071-CA Memory banks' Timing Register B format 208549f126fScgd */ 209549f126fScgd #define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */ 210549f126fScgd #define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */ 211549f126fScgd #define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */ 212549f126fScgd #define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */ 213549f126fScgd #define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */ 214549f126fScgd #define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */ 215549f126fScgd #define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */ 216549f126fScgd #define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */ 217549f126fScgd #define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */ 218549f126fScgd #define COMANCHE_TRB_RTCAS 0x0007 219549f126fScgd #define COMANCHE_TRB_WTCAS 0x0038 220549f126fScgd #define COMANCHE_TRB_TCP 0x00c0 221549f126fScgd #define COMANCHE_TRB_WHOLD0ROW 0x0700 222549f126fScgd #define COMANCHE_TRB_WHOLD0COL 0x3800 223549f126fScgd #define COMANCHE_TRB_RSVD 0xc000 224549f126fScgd 225549f126fScgd 226549f126fScgd /* 227549f126fScgd * 21071-DA Registers 228549f126fScgd */ 229549f126fScgd #define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */ 230549f126fScgd #define EPIC_DCSR_TENB 0x00000001 231549f126fScgd #define EPIC_DCSR_RSVD 0x7fc00082 232549f126fScgd #define EPIC_DCSR_PENB 0x00000004 233549f126fScgd #define EPIC_DCSR_DCEI 0x00000008 234549f126fScgd #define EPIC_DCSR_DPEC 0x00000010 235549f126fScgd #define EPIC_DCSR_IORT 0x00000020 236549f126fScgd #define EPIC_DCSR_LOST 0x00000040 237549f126fScgd #define EPIC_DCSR_DDPE 0x00000100 238549f126fScgd #define EPIC_DCSR_IOPE 0x00000200 239549f126fScgd #define EPIC_DCSR_TABT 0x00000400 240549f126fScgd #define EPIC_DCSR_NDEV 0x00000800 241549f126fScgd #define EPIC_DCSR_CMRD 0x00001000 242549f126fScgd #define EPIC_DCSR_UMRD 0x00002000 243549f126fScgd #define EPIC_DCSR_IPTL 0x00004000 244549f126fScgd #define EPIC_DCSR_MERR 0x00008000 245549f126fScgd #define EPIC_DCSR_DBYP 0x00030000 246549f126fScgd #define EPIC_DCSR_PCMD 0x003c0000 247549f126fScgd #define EPIC_DCSR_PASS2 0x80000000 248549f126fScgd 249549f126fScgd #define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */ 250549f126fScgd 251549f126fScgd #define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */ 252549f126fScgd #define EPIC_SEAR_RSVD 0x0000000f 253549f126fScgd #define EPIC_SEAR_SYS_ERR 0xfffffff0 254549f126fScgd 255549f126fScgd #define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */ 256549f126fScgd #define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */ 257549f126fScgd #define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */ 258549f126fScgd 259549f126fScgd #define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */ 260549f126fScgd #define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */ 261549f126fScgd #define EPIC_TBASE_RSVD 0x000001ff 262549f126fScgd #define EPIC_TBASE_T_BASE 0xfffffe00 26346b89d77Sthorpej #define EPIC_TBASE_SHIFT 1 264549f126fScgd 265549f126fScgd #define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */ 266549f126fScgd #define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */ 267549f126fScgd #define EPIC_PCI_BASE_RSVD 0x0003ffff 268549f126fScgd #define EPIC_PCI_BASE_SGEN 0x00040000 269549f126fScgd #define EPIC_PCI_BASE_WENB 0x00080000 270549f126fScgd #define EPIC_PCI_BASE_PCI_BASE 0xfff00000 271549f126fScgd 272549f126fScgd #define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */ 27346b89d77Sthorpej #define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */ 274549f126fScgd #define EPIC_PCI_MASK_RSVD 0x000fffff 275549f126fScgd #define EPIC_PCI_MASK_PCI_MASK 0xfff00000 27646b89d77Sthorpej #define EPIC_PCI_MASK_1M 0x00000000 27746b89d77Sthorpej #define EPIC_PCI_MASK_2M 0x00100000 27846b89d77Sthorpej #define EPIC_PCI_MASK_4M 0x00300000 27946b89d77Sthorpej #define EPIC_PCI_MASK_8M 0x00700000 28046b89d77Sthorpej #define EPIC_PCI_MASK_16M 0x00f00000 28146b89d77Sthorpej #define EPIC_PCI_MASK_32M 0x01f00000 28246b89d77Sthorpej #define EPIC_PCI_MASK_64M 0x03f00000 28346b89d77Sthorpej #define EPIC_PCI_MASK_128M 0x07f00000 28446b89d77Sthorpej #define EPIC_PCI_MASK_256M 0x0ff00000 28546b89d77Sthorpej #define EPIC_PCI_MASK_512M 0x1ff00000 28646b89d77Sthorpej #define EPIC_PCI_MASK_1G 0x3ff00000 28746b89d77Sthorpej #define EPIC_PCI_MASK_2G 0x7ff00000 28846b89d77Sthorpej #define EPIC_PCI_MASK_4G 0xfff00000 289549f126fScgd 290549f126fScgd #define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */ 291549f126fScgd 292549f126fScgd #define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */ 293549f126fScgd #define EPIC_HAXR1_RSVD 0x07ffffff 294549f126fScgd #define EPIC_HAXR1_EADDR 0xf8000000 295549f126fScgd 296549f126fScgd #define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */ 297deb4082fScgd #define EPIC_HAXR2_CONF_TYPE 0x00000003 298deb4082fScgd #define EPIC_HAXR2_CONF_TYPO0 0x00000000 299deb4082fScgd #define EPIC_HAXR2_CONF_TYPE1 0x00000001 300549f126fScgd #define EPIC_HAXR2_RSVD 0x00fffffc 301549f126fScgd #define EPIC_HAXR2_EADDR 0xff000000 302549f126fScgd 303549f126fScgd #define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */ 304549f126fScgd #define EPIC_PMLT_PMLC 0x000000ff 305549f126fScgd #define EPIC_PMLT_RSVD 0xffffff00 306549f126fScgd 307549f126fScgd #define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */ 308549f126fScgd #define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */ 309549f126fScgd #define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */ 310549f126fScgd #define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */ 311549f126fScgd #define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */ 312549f126fScgd #define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */ 313549f126fScgd #define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */ 314549f126fScgd #define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */ 315549f126fScgd #define EPIC_TLB_TAG_RSVD 0x00000fff 316549f126fScgd #define EPIC_TLB_TAG_EVAL 0x00001000 317549f126fScgd #define EPIC_TLB_TAG_PCI_PAGE 0xffffe000 318549f126fScgd 319549f126fScgd #define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */ 320549f126fScgd #define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */ 321549f126fScgd #define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */ 322549f126fScgd #define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */ 323549f126fScgd #define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */ 324549f126fScgd #define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */ 325549f126fScgd #define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */ 326549f126fScgd #define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */ 327549f126fScgd #define EPIC_TLB_DATA_RSVD 0xffe00001 328549f126fScgd #define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe 329549f126fScgd 330549f126fScgd #define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */ 331549f126fScgd 332549f126fScgd /* 333549f126fScgd * EPIC Scatter-Gather Map Entries 334549f126fScgd */ 335549f126fScgd 336549f126fScgd struct sgmapent { 337*b627dca8Smatt uint64_t val; 338549f126fScgd }; 339549f126fScgd #define SGMAPENT_EVAL 0x0000000000000001L 340549f126fScgd #define SGMAPENT_PFN 0x00000000001ffffeL 341549f126fScgd #define SGMAPENT_RSVD 0xffffffffffe00000L 342549f126fScgd 343549f126fScgd #define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1)) 344