xref: /netbsd/sys/arch/alpha/pci/cia_swiz_bus_io.c (revision 6550d01e)
1 /* $NetBSD: cia_swiz_bus_io.c,v 1.16 2010/12/15 01:27:18 matt Exp $ */
2 
3 /*
4  * Copyright (c) 1996 Carnegie-Mellon University.
5  * All rights reserved.
6  *
7  * Author: Chris G. Demetriou
8  *
9  * Permission to use, copy, modify and distribute this software and
10  * its documentation is hereby granted, provided that both the copyright
11  * notice and this permission notice appear in all copies of the
12  * software, derivative works or modified versions, and any portions
13  * thereof, and that both notices appear in supporting documentation.
14  *
15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18  *
19  * Carnegie Mellon requests users of this software to return to
20  *
21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22  *  School of Computer Science
23  *  Carnegie Mellon University
24  *  Pittsburgh PA 15213-3890
25  *
26  * any improvements or extensions that they make and grant Carnegie the
27  * rights to redistribute these changes.
28  */
29 
30 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
31 
32 __KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_io.c,v 1.16 2010/12/15 01:27:18 matt Exp $");
33 
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/syslog.h>
38 #include <sys/device.h>
39 
40 #include <machine/bus.h>
41 
42 #include <alpha/pci/ciareg.h>
43 #include <alpha/pci/ciavar.h>
44 
45 #define	CHIP		cia_swiz
46 
47 #define	CHIP_EX_MALLOC_SAFE(v)	(((struct cia_config *)(v))->cc_mallocsafe)
48 #define	CHIP_IO_EXTENT(v)	(((struct cia_config *)(v))->cc_io_ex)
49 
50 /* IO region 1 */
51 #define CHIP_IO_W1_BUS_START(v)						\
52 	    HAE_IO_REG1_START(((struct cia_config *)(v))->cc_hae_io)
53 #define CHIP_IO_W1_BUS_END(v)						\
54 	    (CHIP_IO_W1_BUS_START(v) + HAE_IO_REG1_MASK)
55 #define CHIP_IO_W1_SYS_START(v)						\
56 	    CIA_PCI_SIO1
57 #define CHIP_IO_W1_SYS_END(v)						\
58 	    (CIA_PCI_SIO1 + ((HAE_IO_REG1_MASK + 1) << 5) - 1)
59 
60 /* IO region 2 */
61 #define CHIP_IO_W2_BUS_START(v)						\
62 	    HAE_IO_REG2_START(((struct cia_config *)(v))->cc_hae_io)
63 #define CHIP_IO_W2_BUS_END(v)						\
64 	    (CHIP_IO_W2_BUS_START(v) + HAE_IO_REG2_MASK)
65 #define CHIP_IO_W2_SYS_START(v)						\
66 	    CIA_PCI_SIO2
67 #define CHIP_IO_W2_SYS_END(v)						\
68 	    (CIA_PCI_SIO2 + ((HAE_IO_REG2_MASK + 1) << 5) - 1)
69 
70 #include <alpha/pci/pci_swiz_bus_io_chipdep.c>
71