1 /* $NetBSD: dwlpx.c,v 1.26 2002/10/02 04:06:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.26 2002/10/02 04:06:39 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <alpha/tlsb/tlsbreg.h> 50 #include <alpha/tlsb/kftxxvar.h> 51 #include <alpha/tlsb/kftxxreg.h> 52 #include <alpha/pci/dwlpxreg.h> 53 #include <alpha/pci/dwlpxvar.h> 54 #include <alpha/pci/pci_kn8ae.h> 55 56 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 57 #define DWLPX_SYSBASE(sc) \ 58 ((((unsigned long)((sc)->dwlpx_node - 4)) << 36) | \ 59 (((unsigned long) (sc)->dwlpx_hosenum) << 34) | \ 60 (1LL << 39)) 61 62 63 static int dwlpxmatch __P((struct device *, struct cfdata *, void *)); 64 static void dwlpxattach __P((struct device *, struct device *, void *)); 65 CFATTACH_DECL(dwlpx, sizeof(struct dwlpx_softc), 66 dwlpxmatch, dwlpxattach, NULL, NULL); 67 68 extern struct cfdriver dwlpx_cd; 69 70 static int dwlpxprint __P((void *, const char *)); 71 72 void dwlpx_errintr(void *, u_long vec); 73 74 static int 75 dwlpxprint(aux, pnp) 76 void *aux; 77 const char *pnp; 78 { 79 register struct pcibus_attach_args *pba = aux; 80 /* only PCIs can attach to DWLPX's; easy. */ 81 if (pnp) 82 printf("%s at %s", pba->pba_busname, pnp); 83 printf(" bus %d", pba->pba_bus); 84 return (UNCONF); 85 } 86 87 static int 88 dwlpxmatch(parent, cf, aux) 89 struct device *parent; 90 struct cfdata *cf; 91 void *aux; 92 { 93 struct kft_dev_attach_args *ka = aux; 94 95 if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0) 96 return (0); 97 return (1); 98 } 99 100 static void 101 dwlpxattach(parent, self, aux) 102 struct device *parent; 103 struct device *self; 104 void *aux; 105 { 106 static int once = 0; 107 struct dwlpx_softc *sc = (struct dwlpx_softc *)self; 108 struct dwlpx_config *ccp = &sc->dwlpx_cc; 109 struct kft_dev_attach_args *ka = aux; 110 struct pcibus_attach_args pba; 111 u_int32_t pcia_present; 112 113 sc->dwlpx_node = ka->ka_node; 114 sc->dwlpx_dtype = ka->ka_dtype; 115 sc->dwlpx_hosenum = ka->ka_hosenum; 116 117 dwlpx_init(sc); 118 dwlpx_dma_init(ccp); 119 120 pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 121 printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n", 122 (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK, 123 (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "", 124 sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32); 125 126 #if 0 127 { 128 int hpc, slot, slotval; 129 const char *str; 130 for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) { 131 for (slot = 0; slot < 4; slot++) { 132 slotval = (pcia_present >> 133 PCIA_PRESENT_SLOTSHIFT(hpc, slot)) & 134 PCIA_PRESENT_SLOT_MASK; 135 if (slotval == PCIA_PRESENT_SLOT_NONE) 136 continue; 137 switch (slotval) { 138 case PCIA_PRESENT_SLOT_25W: 139 str = "25"; 140 break; 141 case PCIA_PRESENT_SLOT_15W: 142 str = "15"; 143 break; 144 case PCIA_PRESENT_SLOW_7W: 145 default: /* XXX gcc */ 146 str = "7.5"; 147 break; 148 } 149 printf("%s: hpc %d slot %d: %s watt module\n", 150 sc->dwlpx_dev.dv_xname, hpc, slot, str); 151 } 152 } 153 } 154 #endif 155 156 if (once == 0) { 157 /* 158 * Set up interrupts 159 */ 160 pci_kn8ae_pickintr(&sc->dwlpx_cc, 1); 161 once++; 162 } else { 163 pci_kn8ae_pickintr(&sc->dwlpx_cc, 0); 164 } 165 166 /* 167 * Attach PCI bus 168 */ 169 pba.pba_busname = "pci"; 170 pba.pba_iot = &sc->dwlpx_cc.cc_iot; 171 pba.pba_memt = &sc->dwlpx_cc.cc_memt; 172 pba.pba_dmat = /* start with direct, may change... */ 173 alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI); 174 pba.pba_pc = &sc->dwlpx_cc.cc_pc; 175 pba.pba_bus = 0; 176 pba.pba_bridgetag = NULL; 177 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 178 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 179 config_found(self, &pba, dwlpxprint); 180 } 181 182 void 183 dwlpx_init(sc) 184 struct dwlpx_softc *sc; 185 { 186 u_int32_t ctl; 187 struct dwlpx_config *ccp = &sc->dwlpx_cc; 188 unsigned long vec, ls = DWLPX_SYSBASE(sc); 189 int i; 190 191 if (ccp->cc_initted == 0) { 192 /* 193 * On reads, you get a fault if you read a nonexisted HPC. 194 * We know the internal KFTIA hose (hose 0) has only 2 HPCs, 195 * but we can also actually probe for HPCs. 196 * Assume at least one. 197 */ 198 for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC; 199 sc->dwlpx_nhpc++) { 200 if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls), 201 sizeof (ctl)) != 0) { 202 break; 203 } 204 } 205 if (sc->dwlpx_nhpc != NHPC) { 206 /* clear (potential) Illegal CSR Address Error */ 207 REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) = 208 PCIA_ERR_ALLERR; 209 } 210 211 dwlpx_bus_io_init(&ccp->cc_iot, ccp); 212 dwlpx_bus_mem_init(&ccp->cc_memt, ccp); 213 } 214 dwlpx_pci_init(&ccp->cc_pc, ccp); 215 ccp->cc_sc = sc; 216 217 /* 218 * Establish a precalculated base for convenience's sake. 219 */ 220 ccp->cc_sysbase = ls; 221 222 /* 223 * If there are only 2 HPCs, then the 'present' register is not 224 * implemented, so there will only ever be 32K SG entries. Otherwise 225 * any revision greater than zero will have 128K entries. 226 */ 227 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 228 if (sc->dwlpx_nhpc == 2) { 229 sc->dwlpx_sgmapsz = DWLPX_SG32K; 230 #if 0 231 /* 232 * As of 2/25/98- When I enable SG128K, and then have to flip 233 * TBIT below, I get bad SGRAM errors. We'll fix this later 234 * if this gets important. 235 */ 236 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) { 237 sc->dwlpx_sgmapsz = DWLPX_SG128K; 238 #endif 239 } else { 240 sc->dwlpx_sgmapsz = DWLPX_SG32K; 241 } 242 243 /* 244 * Set up interrupt stuff for this DWLPX. 245 * 246 * Note that all PCI interrupt pins are disabled at this time. 247 * 248 * Do this even for all HPCs- even for the nonexistent 249 * one on hose zero of a KFTIA. 250 */ 251 vec = scb_alloc(dwlpx_errintr, sc); 252 if (vec == SCB_ALLOC_FAILED) 253 panic("%s: unable to allocate error vector", 254 sc->dwlpx_dev.dv_xname); 255 printf("%s: error interrupt at vector 0x%lx\n", 256 sc->dwlpx_dev.dv_xname, vec); 257 for (i = 0; i < NHPC; i++) { 258 REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT; 259 REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec; 260 } 261 262 /* 263 * Establish HAE values, as well as make sure of sanity elsewhere. 264 */ 265 for (i = 0; i < sc->dwlpx_nhpc; i++) { 266 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase); 267 ctl &= 0x0fffffff; 268 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f)); 269 /* 270 * I originally also had it or'ing in 3, which makes no sense. 271 */ 272 273 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB; 274 275 /* 276 * Only valid if we're attached to a KFTIA or a KTHA. 277 */ 278 ctl |= PCIA_CTL_3UP; 279 280 ctl |= PCIA_CTL_CUTENA; 281 282 /* 283 * Fit in appropriate S/G Map Ram size. 284 */ 285 if (sc->dwlpx_sgmapsz == DWLPX_SG32K) 286 ctl |= PCIA_CTL_SG32K; 287 else if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 288 ctl |= PCIA_CTL_SG128K; 289 else 290 ctl |= PCIA_CTL_SG32K; 291 292 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl; 293 } 294 /* 295 * Enable TBIT if required 296 */ 297 if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 298 REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1; 299 alpha_mb(); 300 ccp->cc_initted = 1; 301 } 302 303 void 304 dwlpx_errintr(arg, vec) 305 void *arg; 306 unsigned long vec; 307 { 308 struct dwlpx_softc *sc = arg; 309 struct dwlpx_config *ccp = &sc->dwlpx_cc; 310 int i; 311 struct { 312 u_int32_t err; 313 u_int32_t addr; 314 } hpcs[NHPC]; 315 316 for (i = 0; i < sc->dwlpx_nhpc; i++) { 317 hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase); 318 hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase); 319 } 320 printf("%s: node %d hose %d error interrupt\n", 321 sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum); 322 323 for (i = 0; i < sc->dwlpx_nhpc; i++) { 324 if ((hpcs[i].err & PCIA_ERR_ERROR) == 0) 325 continue; 326 printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, " 327 "Failing Address 0x%x\n", 328 i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" : 329 "read from", hpcs[i].addr & ~3); 330 if (hpcs[i].err & PCIA_ERR_SERR_L) 331 printf("\t PCI device asserted SERR_L\n"); 332 if (hpcs[i].err & PCIA_ERR_ILAT) 333 printf("\t Incremental Latency Exceeded\n"); 334 if (hpcs[i].err & PCIA_ERR_SGPRTY) 335 printf("\t CPU access of SG RAM Parity Error\n"); 336 if (hpcs[i].err & PCIA_ERR_ILLCSR) 337 printf("\t Illegal CSR Address Error\n"); 338 if (hpcs[i].err & PCIA_ERR_PCINXM) 339 printf("\t Nonexistent PCI Address Error\n"); 340 if (hpcs[i].err & PCIA_ERR_DSCERR) 341 printf("\t PCI Target Disconnect Error\n"); 342 if (hpcs[i].err & PCIA_ERR_ABRT) 343 printf("\t PCI Target Abort Error\n"); 344 if (hpcs[i].err & PCIA_ERR_WPRTY) 345 printf("\t PCI Write Parity Error\n"); 346 if (hpcs[i].err & PCIA_ERR_DPERR) 347 printf("\t PCI Data Parity Error\n"); 348 if (hpcs[i].err & PCIA_ERR_APERR) 349 printf("\t PCI Address Parity Error\n"); 350 if (hpcs[i].err & PCIA_ERR_DFLT) 351 printf("\t SG Map RAM Invalid Entry Error\n"); 352 if (hpcs[i].err & PCIA_ERR_DPRTY) 353 printf("\t DMA access of SG RAM Parity Error\n"); 354 if (hpcs[i].err & PCIA_ERR_DRPERR) 355 printf("\t DMA Read Return Parity Error\n"); 356 if (hpcs[i].err & PCIA_ERR_MABRT) 357 printf("\t PCI Master Abort Error\n"); 358 if (hpcs[i].err & PCIA_ERR_CPRTY) 359 printf("\t CSR Parity Error\n"); 360 if (hpcs[i].err & PCIA_ERR_COVR) 361 printf("\t CSR Overrun Error\n"); 362 if (hpcs[i].err & PCIA_ERR_MBPERR) 363 printf("\t Mailbox Parity Error\n"); 364 if (hpcs[i].err & PCIA_ERR_MBILI) 365 printf("\t Mailbox Illegal Length Error\n"); 366 REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err; 367 } 368 } 369